i386.c revision 52294
1/* Subroutines for insn-output.c for Intel X86. 2 Copyright (C) 1988, 92, 94-98, 1999 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21/* $FreeBSD: head/contrib/gcc/config/i386/i386.c 52294 1999-10-16 08:08:21Z obrien $ */ 22 23#include <setjmp.h> 24#include "config.h" 25#include "system.h" 26#include "rtl.h" 27#include "regs.h" 28#include "hard-reg-set.h" 29#include "real.h" 30#include "insn-config.h" 31#include "conditions.h" 32#include "insn-flags.h" 33#include "output.h" 34#include "insn-attr.h" 35#include "tree.h" 36#include "flags.h" 37#include "except.h" 38#include "function.h" 39#include "recog.h" 40#include "expr.h" 41#include "toplev.h" 42 43#ifdef EXTRA_CONSTRAINT 44/* If EXTRA_CONSTRAINT is defined, then the 'S' 45 constraint in REG_CLASS_FROM_LETTER will no longer work, and various 46 asm statements that need 'S' for class SIREG will break. */ 47 error EXTRA_CONSTRAINT conflicts with S constraint letter 48/* The previous line used to be #error, but some compilers barf 49 even if the conditional was untrue. */ 50#endif 51 52#ifndef CHECK_STACK_LIMIT 53#define CHECK_STACK_LIMIT -1 54#endif 55 56#define PIC_REG_USED \ 57 (flag_pic && (current_function_uses_pic_offset_table \ 58 || current_function_uses_const_pool \ 59 || profile_flag || profile_block_flag)) 60 61/* Type of an operand for ix86_{binary,unary}_operator_ok */ 62enum reg_mem 63{ 64 reg_p, 65 mem_p, 66 imm_p 67}; 68 69/* Processor costs (relative to an add) */ 70struct processor_costs i386_cost = { /* 386 specific costs */ 71 1, /* cost of an add instruction */ 72 1, /* cost of a lea instruction */ 73 3, /* variable shift costs */ 74 2, /* constant shift costs */ 75 6, /* cost of starting a multiply */ 76 1, /* cost of multiply per each bit set */ 77 23 /* cost of a divide/mod */ 78}; 79 80struct processor_costs i486_cost = { /* 486 specific costs */ 81 1, /* cost of an add instruction */ 82 1, /* cost of a lea instruction */ 83 3, /* variable shift costs */ 84 2, /* constant shift costs */ 85 12, /* cost of starting a multiply */ 86 1, /* cost of multiply per each bit set */ 87 40 /* cost of a divide/mod */ 88}; 89 90struct processor_costs pentium_cost = { 91 1, /* cost of an add instruction */ 92 1, /* cost of a lea instruction */ 93 4, /* variable shift costs */ 94 1, /* constant shift costs */ 95 11, /* cost of starting a multiply */ 96 0, /* cost of multiply per each bit set */ 97 25 /* cost of a divide/mod */ 98}; 99 100struct processor_costs pentiumpro_cost = { 101 1, /* cost of an add instruction */ 102 1, /* cost of a lea instruction */ 103 3, /* variable shift costs */ 104 1, /* constant shift costs */ 105 4, /* cost of starting a multiply */ 106 0, /* cost of multiply per each bit set */ 107 17 /* cost of a divide/mod */ 108}; 109 110/* We use decoding time together with execution time. 111 To get correct vale add 1 for short decodable, 2 for long decodable 112 and 4 for vector decodable instruction to execution time and divide 113 by two (because CPU is able to do two insns at a time). */ 114 115struct processor_costs k6_cost = { 116 1, /* cost of an add instruction */ 117 1, /* cost of a lea instruction */ 118 1, /* variable shift costs */ 119 1, /* constant shift costs */ 120 3, /* cost of starting a multiply */ 121 0, /* cost of multiply per each bit set */ 122 20 /* cost of a divide/mod */ 123}; 124 125struct processor_costs *ix86_cost = &pentium_cost; 126 127/* Processor feature/optimization bitmasks. */ 128#define m_386 (1<<PROCESSOR_I386) 129#define m_486 (1<<PROCESSOR_I486) 130#define m_PENT (1<<PROCESSOR_PENTIUM) 131#define m_PPRO (1<<PROCESSOR_PENTIUMPRO) 132#define m_K6 (1<<PROCESSOR_K6) 133 134const int x86_use_leave = m_386 | m_K6; 135const int x86_push_memory = m_386 | m_K6; 136const int x86_zero_extend_with_and = m_486 | m_PENT; 137const int x86_movx = m_386 | m_PPRO | m_K6; 138const int x86_double_with_add = ~(m_386 | m_PENT | m_PPRO); 139const int x86_use_bit_test = m_386; 140const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO; 141const int x86_use_q_reg = m_PENT | m_PPRO | m_K6; 142const int x86_use_any_reg = m_486; 143const int x86_cmove = m_PPRO; 144const int x86_deep_branch = m_PPRO| m_K6; 145 146#define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx)) 147 148extern FILE *asm_out_file; 149extern char *strcat (); 150 151static void ix86_epilogue PROTO((int)); 152static void ix86_prologue PROTO((int)); 153 154char *singlemove_string (); 155char *output_move_const_single (); 156char *output_fp_cc0_set (); 157 158char *hi_reg_name[] = HI_REGISTER_NAMES; 159char *qi_reg_name[] = QI_REGISTER_NAMES; 160char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; 161 162/* Array of the smallest class containing reg number REGNO, indexed by 163 REGNO. Used by REGNO_REG_CLASS in i386.h. */ 164 165enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = 166{ 167 /* ax, dx, cx, bx */ 168 AREG, DREG, CREG, BREG, 169 /* si, di, bp, sp */ 170 SIREG, DIREG, INDEX_REGS, GENERAL_REGS, 171 /* FP registers */ 172 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, 173 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, 174 /* arg pointer */ 175 INDEX_REGS 176}; 177 178/* Test and compare insns in i386.md store the information needed to 179 generate branch and scc insns here. */ 180 181struct rtx_def *i386_compare_op0 = NULL_RTX; 182struct rtx_def *i386_compare_op1 = NULL_RTX; 183struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); 184 185/* which cpu are we scheduling for */ 186enum processor_type ix86_cpu; 187 188/* which instruction set architecture to use. */ 189int ix86_arch; 190 191/* Strings to hold which cpu and instruction set architecture to use. */ 192char *ix86_cpu_string; /* for -mcpu=<xxx> */ 193char *ix86_arch_string; /* for -march=<xxx> */ 194 195/* Register allocation order */ 196char *i386_reg_alloc_order; 197static char regs_allocated[FIRST_PSEUDO_REGISTER]; 198 199/* # of registers to use to pass arguments. */ 200char *i386_regparm_string; 201 202/* i386_regparm_string as a number */ 203int i386_regparm; 204 205/* Alignment to use for loops and jumps: */ 206 207/* Power of two alignment for loops. */ 208char *i386_align_loops_string; 209 210/* Power of two alignment for non-loop jumps. */ 211char *i386_align_jumps_string; 212 213/* Power of two alignment for stack boundary in bytes. */ 214char *i386_preferred_stack_boundary_string; 215 216/* Preferred alignment for stack boundary in bits. */ 217int i386_preferred_stack_boundary; 218 219/* Values 1-5: see jump.c */ 220int i386_branch_cost; 221char *i386_branch_cost_string; 222 223/* Power of two alignment for functions. */ 224int i386_align_funcs; 225char *i386_align_funcs_string; 226 227/* Power of two alignment for loops. */ 228int i386_align_loops; 229 230/* Power of two alignment for non-loop jumps. */ 231int i386_align_jumps; 232 233/* Sometimes certain combinations of command options do not make 234 sense on a particular target machine. You can define a macro 235 `OVERRIDE_OPTIONS' to take account of this. This macro, if 236 defined, is executed once just after all the command options have 237 been parsed. 238 239 Don't use this macro to turn on various extra optimizations for 240 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 241 242void 243override_options () 244{ 245 int ch, i, j; 246 int def_align; 247 248 static struct ptt 249 { 250 char *name; /* Canonical processor name. */ 251 enum processor_type processor; /* Processor type enum value. */ 252 struct processor_costs *cost; /* Processor costs */ 253 int target_enable; /* Target flags to enable. */ 254 int target_disable; /* Target flags to disable. */ 255 } processor_target_table[] = { 256 {PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0}, 257 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0}, 258 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0}, 259 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0}, 260 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost, 0, 0}, 261 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO, 262 &pentiumpro_cost, 0, 0}, 263 {PROCESSOR_K6_STRING, PROCESSOR_K6, &k6_cost, 0, 0} 264 }; 265 266 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); 267 268#ifdef SUBTARGET_OVERRIDE_OPTIONS 269 SUBTARGET_OVERRIDE_OPTIONS; 270#endif 271 272 /* Validate registers in register allocation order. */ 273 if (i386_reg_alloc_order) 274 { 275 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) 276 { 277 int regno = 0; 278 279 switch (ch) 280 { 281 case 'a': regno = 0; break; 282 case 'd': regno = 1; break; 283 case 'c': regno = 2; break; 284 case 'b': regno = 3; break; 285 case 'S': regno = 4; break; 286 case 'D': regno = 5; break; 287 case 'B': regno = 6; break; 288 289 default: fatal ("Register '%c' is unknown", ch); 290 } 291 292 if (regs_allocated[regno]) 293 fatal ("Register '%c' already specified in allocation order", ch); 294 295 regs_allocated[regno] = 1; 296 } 297 } 298 299 if (ix86_arch_string == 0) 300 { 301 ix86_arch_string = PROCESSOR_PENTIUM_STRING; 302 if (ix86_cpu_string == 0) 303 ix86_cpu_string = PROCESSOR_DEFAULT_STRING; 304 } 305 306 for (i = 0; i < ptt_size; i++) 307 if (! strcmp (ix86_arch_string, processor_target_table[i].name)) 308 { 309 ix86_arch = processor_target_table[i].processor; 310 if (ix86_cpu_string == 0) 311 ix86_cpu_string = processor_target_table[i].name; 312 break; 313 } 314 315 if (i == ptt_size) 316 { 317 error ("bad value (%s) for -march= switch", ix86_arch_string); 318 ix86_arch_string = PROCESSOR_PENTIUM_STRING; 319 ix86_arch = PROCESSOR_DEFAULT; 320 } 321 322 if (ix86_cpu_string == 0) 323 ix86_cpu_string = PROCESSOR_DEFAULT_STRING; 324 325 for (j = 0; j < ptt_size; j++) 326 if (! strcmp (ix86_cpu_string, processor_target_table[j].name)) 327 { 328 ix86_cpu = processor_target_table[j].processor; 329 ix86_cost = processor_target_table[j].cost; 330 if (i > j && (int) ix86_arch >= (int) PROCESSOR_K6) 331 error ("-mcpu=%s does not support -march=%s", 332 ix86_cpu_string, ix86_arch_string); 333 334 target_flags |= processor_target_table[j].target_enable; 335 target_flags &= ~processor_target_table[j].target_disable; 336 break; 337 } 338 339 if (j == ptt_size) 340 { 341 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string); 342 ix86_cpu_string = PROCESSOR_DEFAULT_STRING; 343 ix86_cpu = PROCESSOR_DEFAULT; 344 } 345 346 /* Validate -mregparm= value. */ 347 if (i386_regparm_string) 348 { 349 i386_regparm = atoi (i386_regparm_string); 350 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX) 351 fatal ("-mregparm=%d is not between 0 and %d", 352 i386_regparm, REGPARM_MAX); 353 } 354 355 /* The 486 suffers more from non-aligned cache line fills, and the 356 larger code size results in a larger cache foot-print and more misses. 357 The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte 358 cache line. */ 359 def_align = (TARGET_486) ? 4 : 2; 360 361 /* Validate -malign-loops= value, or provide default. */ 362#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN 363 i386_align_loops = 4; 364#else 365 i386_align_loops = 2; 366#endif 367 if (i386_align_loops_string) 368 { 369 i386_align_loops = atoi (i386_align_loops_string); 370 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN) 371 fatal ("-malign-loops=%d is not between 0 and %d", 372 i386_align_loops, MAX_CODE_ALIGN); 373 } 374 375 /* Validate -malign-jumps= value, or provide default. */ 376#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN 377 i386_align_jumps = 4; 378#else 379 i386_align_jumps = def_align; 380#endif 381 if (i386_align_jumps_string) 382 { 383 i386_align_jumps = atoi (i386_align_jumps_string); 384 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN) 385 fatal ("-malign-jumps=%d is not between 0 and %d", 386 i386_align_jumps, MAX_CODE_ALIGN); 387 } 388 389 /* Validate -malign-functions= value, or provide default. */ 390 i386_align_funcs = def_align; 391 if (i386_align_funcs_string) 392 { 393 i386_align_funcs = atoi (i386_align_funcs_string); 394 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN) 395 fatal ("-malign-functions=%d is not between 0 and %d", 396 i386_align_funcs, MAX_CODE_ALIGN); 397 } 398 399 /* Validate -mpreferred_stack_boundary= value, or provide default. 400 The default of 128 bits is for Pentium III's SSE __m128. */ 401 i386_preferred_stack_boundary = 128; 402 if (i386_preferred_stack_boundary_string) 403 { 404 i = atoi (i386_preferred_stack_boundary_string); 405 if (i < 2 || i > 31) 406 fatal ("-mpreferred_stack_boundary=%d is not between 2 and 31", i); 407 i386_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT; 408 } 409 410 /* Validate -mbranch-cost= value, or provide default. */ 411 i386_branch_cost = 1; 412 if (i386_branch_cost_string) 413 { 414 i386_branch_cost = atoi (i386_branch_cost_string); 415 if (i386_branch_cost < 0 || i386_branch_cost > 5) 416 fatal ("-mbranch-cost=%d is not between 0 and 5", i386_branch_cost); 417 } 418 419 /* Keep nonleaf frame pointers. */ 420 if (TARGET_OMIT_LEAF_FRAME_POINTER) 421 flag_omit_frame_pointer = 1; 422} 423 424/* A C statement (sans semicolon) to choose the order in which to 425 allocate hard registers for pseudo-registers local to a basic 426 block. 427 428 Store the desired register order in the array `reg_alloc_order'. 429 Element 0 should be the register to allocate first; element 1, the 430 next register; and so on. 431 432 The macro body should not assume anything about the contents of 433 `reg_alloc_order' before execution of the macro. 434 435 On most machines, it is not necessary to define this macro. */ 436 437void 438order_regs_for_local_alloc () 439{ 440 int i, ch, order; 441 442 /* User specified the register allocation order. */ 443 444 if (i386_reg_alloc_order) 445 { 446 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) 447 { 448 int regno = 0; 449 450 switch (ch) 451 { 452 case 'a': regno = 0; break; 453 case 'd': regno = 1; break; 454 case 'c': regno = 2; break; 455 case 'b': regno = 3; break; 456 case 'S': regno = 4; break; 457 case 'D': regno = 5; break; 458 case 'B': regno = 6; break; 459 } 460 461 reg_alloc_order[order++] = regno; 462 } 463 464 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 465 { 466 if (! regs_allocated[i]) 467 reg_alloc_order[order++] = i; 468 } 469 } 470 471 /* If user did not specify a register allocation order, use natural order. */ 472 else 473 { 474 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 475 reg_alloc_order[i] = i; 476 } 477} 478 479void 480optimization_options (level, size) 481 int level; 482 int size ATTRIBUTE_UNUSED; 483{ 484 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to 485 make the problem with not enough registers even worse. */ 486#ifdef INSN_SCHEDULING 487 if (level > 1) 488 flag_schedule_insns = 0; 489#endif 490} 491 492/* Sign-extend a 16-bit constant */ 493 494struct rtx_def * 495i386_sext16_if_const (op) 496 struct rtx_def *op; 497{ 498 if (GET_CODE (op) == CONST_INT) 499 { 500 HOST_WIDE_INT val = INTVAL (op); 501 HOST_WIDE_INT sext_val; 502 if (val & 0x8000) 503 sext_val = val | ~0xffff; 504 else 505 sext_val = val & 0xffff; 506 if (sext_val != val) 507 op = GEN_INT (sext_val); 508 } 509 return op; 510} 511 512/* Return nonzero if the rtx is aligned */ 513 514static int 515i386_aligned_reg_p (regno) 516 int regno; 517{ 518 return (regno == STACK_POINTER_REGNUM 519 || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM)); 520} 521 522int 523i386_aligned_p (op) 524 rtx op; 525{ 526 /* Registers and immediate operands are always "aligned". */ 527 if (GET_CODE (op) != MEM) 528 return 1; 529 530 /* Don't even try to do any aligned optimizations with volatiles. */ 531 if (MEM_VOLATILE_P (op)) 532 return 0; 533 534 /* Get address of memory operand. */ 535 op = XEXP (op, 0); 536 537 switch (GET_CODE (op)) 538 { 539 case CONST_INT: 540 if (INTVAL (op) & 3) 541 break; 542 return 1; 543 544 /* Match "reg + offset" */ 545 case PLUS: 546 if (GET_CODE (XEXP (op, 1)) != CONST_INT) 547 break; 548 if (INTVAL (XEXP (op, 1)) & 3) 549 break; 550 551 op = XEXP (op, 0); 552 if (GET_CODE (op) != REG) 553 break; 554 555 /* ... fall through ... */ 556 557 case REG: 558 return i386_aligned_reg_p (REGNO (op)); 559 560 default: 561 break; 562 } 563 564 return 0; 565} 566 567/* Return nonzero if INSN looks like it won't compute useful cc bits 568 as a side effect. This information is only a hint. */ 569 570int 571i386_cc_probably_useless_p (insn) 572 rtx insn; 573{ 574 return ! next_cc0_user (insn); 575} 576 577/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific 578 attribute for DECL. The attributes in ATTRIBUTES have previously been 579 assigned to DECL. */ 580 581int 582i386_valid_decl_attribute_p (decl, attributes, identifier, args) 583 tree decl ATTRIBUTE_UNUSED; 584 tree attributes ATTRIBUTE_UNUSED; 585 tree identifier ATTRIBUTE_UNUSED; 586 tree args ATTRIBUTE_UNUSED; 587{ 588 return 0; 589} 590 591/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific 592 attribute for TYPE. The attributes in ATTRIBUTES have previously been 593 assigned to TYPE. */ 594 595int 596i386_valid_type_attribute_p (type, attributes, identifier, args) 597 tree type; 598 tree attributes ATTRIBUTE_UNUSED; 599 tree identifier; 600 tree args; 601{ 602 if (TREE_CODE (type) != FUNCTION_TYPE 603 && TREE_CODE (type) != METHOD_TYPE 604 && TREE_CODE (type) != FIELD_DECL 605 && TREE_CODE (type) != TYPE_DECL) 606 return 0; 607 608 /* Stdcall attribute says callee is responsible for popping arguments 609 if they are not variable. */ 610 if (is_attribute_p ("stdcall", identifier)) 611 return (args == NULL_TREE); 612 613 /* Cdecl attribute says the callee is a normal C declaration. */ 614 if (is_attribute_p ("cdecl", identifier)) 615 return (args == NULL_TREE); 616 617 /* Regparm attribute specifies how many integer arguments are to be 618 passed in registers. */ 619 if (is_attribute_p ("regparm", identifier)) 620 { 621 tree cst; 622 623 if (! args || TREE_CODE (args) != TREE_LIST 624 || TREE_CHAIN (args) != NULL_TREE 625 || TREE_VALUE (args) == NULL_TREE) 626 return 0; 627 628 cst = TREE_VALUE (args); 629 if (TREE_CODE (cst) != INTEGER_CST) 630 return 0; 631 632 if (TREE_INT_CST_HIGH (cst) != 0 633 || TREE_INT_CST_LOW (cst) < 0 634 || TREE_INT_CST_LOW (cst) > REGPARM_MAX) 635 return 0; 636 637 return 1; 638 } 639 640 return 0; 641} 642 643/* Return 0 if the attributes for two types are incompatible, 1 if they 644 are compatible, and 2 if they are nearly compatible (which causes a 645 warning to be generated). */ 646 647int 648i386_comp_type_attributes (type1, type2) 649 tree type1; 650 tree type2; 651{ 652 /* Check for mismatch of non-default calling convention. */ 653 char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall"; 654 655 if (TREE_CODE (type1) != FUNCTION_TYPE) 656 return 1; 657 658 /* Check for mismatched return types (cdecl vs stdcall). */ 659 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1)) 660 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2))) 661 return 0; 662 return 1; 663} 664 665 666/* Value is the number of bytes of arguments automatically 667 popped when returning from a subroutine call. 668 FUNDECL is the declaration node of the function (as a tree), 669 FUNTYPE is the data type of the function (as a tree), 670 or for a library call it is an identifier node for the subroutine name. 671 SIZE is the number of bytes of arguments passed on the stack. 672 673 On the 80386, the RTD insn may be used to pop them if the number 674 of args is fixed, but if the number is variable then the caller 675 must pop them all. RTD can't be used for library calls now 676 because the library is compiled with the Unix compiler. 677 Use of RTD is a selectable option, since it is incompatible with 678 standard Unix calling sequences. If the option is not selected, 679 the caller must always pop the args. 680 681 The attribute stdcall is equivalent to RTD on a per module basis. */ 682 683int 684i386_return_pops_args (fundecl, funtype, size) 685 tree fundecl; 686 tree funtype; 687 int size; 688{ 689 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE); 690 691 /* Cdecl functions override -mrtd, and never pop the stack. */ 692 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) { 693 694 /* Stdcall functions will pop the stack if not variable args. */ 695 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))) 696 rtd = 1; 697 698 if (rtd 699 && (TYPE_ARG_TYPES (funtype) == NULL_TREE 700 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) 701 == void_type_node))) 702 return size; 703 } 704 705 /* Lose any fake structure return argument. */ 706 if (aggregate_value_p (TREE_TYPE (funtype))) 707 return GET_MODE_SIZE (Pmode); 708 709 return 0; 710} 711 712 713/* Argument support functions. */ 714 715/* Initialize a variable CUM of type CUMULATIVE_ARGS 716 for a call to a function whose data type is FNTYPE. 717 For a library call, FNTYPE is 0. */ 718 719void 720init_cumulative_args (cum, fntype, libname) 721 CUMULATIVE_ARGS *cum; /* Argument info to initialize */ 722 tree fntype; /* tree ptr for function decl */ 723 rtx libname; /* SYMBOL_REF of library name or 0 */ 724{ 725 static CUMULATIVE_ARGS zero_cum; 726 tree param, next_param; 727 728 if (TARGET_DEBUG_ARG) 729 { 730 fprintf (stderr, "\ninit_cumulative_args ("); 731 if (fntype) 732 fprintf (stderr, "fntype code = %s, ret code = %s", 733 tree_code_name[(int) TREE_CODE (fntype)], 734 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]); 735 else 736 fprintf (stderr, "no fntype"); 737 738 if (libname) 739 fprintf (stderr, ", libname = %s", XSTR (libname, 0)); 740 } 741 742 *cum = zero_cum; 743 744 /* Set up the number of registers to use for passing arguments. */ 745 cum->nregs = i386_regparm; 746 if (fntype) 747 { 748 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype)); 749 750 if (attr) 751 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr))); 752 } 753 754 /* Determine if this function has variable arguments. This is 755 indicated by the last argument being 'void_type_mode' if there 756 are no variable arguments. If there are variable arguments, then 757 we won't pass anything in registers */ 758 759 if (cum->nregs) 760 { 761 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0; 762 param != 0; param = next_param) 763 { 764 next_param = TREE_CHAIN (param); 765 if (next_param == 0 && TREE_VALUE (param) != void_type_node) 766 cum->nregs = 0; 767 } 768 } 769 770 if (TARGET_DEBUG_ARG) 771 fprintf (stderr, ", nregs=%d )\n", cum->nregs); 772 773 return; 774} 775 776/* Update the data in CUM to advance over an argument 777 of mode MODE and data type TYPE. 778 (TYPE is null for libcalls where that information may not be available.) */ 779 780void 781function_arg_advance (cum, mode, type, named) 782 CUMULATIVE_ARGS *cum; /* current arg information */ 783 enum machine_mode mode; /* current arg mode */ 784 tree type; /* type of the argument or 0 if lib support */ 785 int named; /* whether or not the argument was named */ 786{ 787 int bytes 788 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 789 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 790 791 if (TARGET_DEBUG_ARG) 792 fprintf (stderr, 793 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n", 794 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); 795 796 cum->words += words; 797 cum->nregs -= words; 798 cum->regno += words; 799 800 if (cum->nregs <= 0) 801 { 802 cum->nregs = 0; 803 cum->regno = 0; 804 } 805 806 return; 807} 808 809/* Define where to put the arguments to a function. 810 Value is zero to push the argument on the stack, 811 or a hard register in which to store the argument. 812 813 MODE is the argument's machine mode. 814 TYPE is the data type of the argument (as a tree). 815 This is null for libcalls where that information may 816 not be available. 817 CUM is a variable of type CUMULATIVE_ARGS which gives info about 818 the preceding args and about the function being called. 819 NAMED is nonzero if this argument is a named parameter 820 (otherwise it is an extra parameter matching an ellipsis). */ 821 822struct rtx_def * 823function_arg (cum, mode, type, named) 824 CUMULATIVE_ARGS *cum; /* current arg information */ 825 enum machine_mode mode; /* current arg mode */ 826 tree type; /* type of the argument or 0 if lib support */ 827 int named; /* != 0 for normal args, == 0 for ... args */ 828{ 829 rtx ret = NULL_RTX; 830 int bytes 831 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 832 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 833 834 switch (mode) 835 { 836 /* For now, pass fp/complex values on the stack. */ 837 default: 838 break; 839 840 case BLKmode: 841 case DImode: 842 case SImode: 843 case HImode: 844 case QImode: 845 if (words <= cum->nregs) 846 ret = gen_rtx_REG (mode, cum->regno); 847 break; 848 } 849 850 if (TARGET_DEBUG_ARG) 851 { 852 fprintf (stderr, 853 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d", 854 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); 855 856 if (ret) 857 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]); 858 else 859 fprintf (stderr, ", stack"); 860 861 fprintf (stderr, " )\n"); 862 } 863 864 return ret; 865} 866 867/* For an arg passed partly in registers and partly in memory, 868 this is the number of registers used. 869 For args passed entirely in registers or entirely in memory, zero. */ 870 871int 872function_arg_partial_nregs (cum, mode, type, named) 873 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; /* current arg information */ 874 enum machine_mode mode ATTRIBUTE_UNUSED; /* current arg mode */ 875 tree type ATTRIBUTE_UNUSED; /* type of the argument or 0 if lib support */ 876 int named ATTRIBUTE_UNUSED; /* != 0 for normal args, == 0 for ... args */ 877{ 878 return 0; 879} 880 881char * 882singlemove_string (operands) 883 rtx *operands; 884{ 885 rtx x; 886 if (GET_CODE (operands[0]) == MEM 887 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC) 888 { 889 if (XEXP (x, 0) != stack_pointer_rtx) 890 abort (); 891 return "push%L1 %1"; 892 } 893 else if (GET_CODE (operands[1]) == CONST_DOUBLE) 894 return output_move_const_single (operands); 895 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) 896 return AS2 (mov%L0,%1,%0); 897 else if (CONSTANT_P (operands[1])) 898 return AS2 (mov%L0,%1,%0); 899 else 900 { 901 output_asm_insn ("push%L1 %1", operands); 902 return "pop%L0 %0"; 903 } 904} 905 906/* Output an insn to add the constant N to the register X. */ 907 908static void 909asm_add (n, x) 910 int n; 911 rtx x; 912{ 913 rtx xops[2]; 914 xops[0] = x; 915 916 if (n == -1) 917 output_asm_insn (AS1 (dec%L0,%0), xops); 918 else if (n == 1) 919 output_asm_insn (AS1 (inc%L0,%0), xops); 920 else if (n < 0 || n == 128) 921 { 922 xops[1] = GEN_INT (-n); 923 output_asm_insn (AS2 (sub%L0,%1,%0), xops); 924 } 925 else if (n > 0) 926 { 927 xops[1] = GEN_INT (n); 928 output_asm_insn (AS2 (add%L0,%1,%0), xops); 929 } 930} 931 932/* Output assembler code to perform a doubleword move insn 933 with operands OPERANDS. */ 934 935char * 936output_move_double (operands) 937 rtx *operands; 938{ 939 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; 940 rtx latehalf[2]; 941 rtx middlehalf[2]; 942 rtx xops[2]; 943 int dest_overlapped_low = 0; 944 int size = GET_MODE_SIZE (GET_MODE (operands[0])); 945 946 middlehalf[0] = 0; 947 middlehalf[1] = 0; 948 949 /* First classify both operands. */ 950 951 if (REG_P (operands[0])) 952 optype0 = REGOP; 953 else if (offsettable_memref_p (operands[0])) 954 optype0 = OFFSOP; 955 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 956 optype0 = POPOP; 957 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 958 optype0 = PUSHOP; 959 else if (GET_CODE (operands[0]) == MEM) 960 optype0 = MEMOP; 961 else 962 optype0 = RNDOP; 963 964 if (REG_P (operands[1])) 965 optype1 = REGOP; 966 else if (CONSTANT_P (operands[1])) 967 optype1 = CNSTOP; 968 else if (offsettable_memref_p (operands[1])) 969 optype1 = OFFSOP; 970 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) 971 optype1 = POPOP; 972 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) 973 optype1 = PUSHOP; 974 else if (GET_CODE (operands[1]) == MEM) 975 optype1 = MEMOP; 976 else 977 optype1 = RNDOP; 978 979 /* Check for the cases that are not supposed to happen 980 either due to the operand constraints or the fact 981 that all memory operands on the x86 are offsettable. 982 Abort if we get one, because generating code for these 983 cases is painful. */ 984 985 if (optype0 == RNDOP || optype1 == RNDOP 986 || optype0 == MEMOP || optype1 == MEMOP) 987 abort (); 988 989 /* If one operand is decrementing and one is incrementing 990 decrement the former register explicitly 991 and change that operand into ordinary indexing. */ 992 993 if (optype0 == PUSHOP && optype1 == POPOP) 994 { 995 /* ??? Can this ever happen on i386? */ 996 operands[0] = XEXP (XEXP (operands[0], 0), 0); 997 asm_add (-size, operands[0]); 998 if (GET_MODE (operands[1]) == XFmode) 999 operands[0] = gen_rtx_MEM (XFmode, operands[0]); 1000 else if (GET_MODE (operands[0]) == DFmode) 1001 operands[0] = gen_rtx_MEM (DFmode, operands[0]); 1002 else 1003 operands[0] = gen_rtx_MEM (DImode, operands[0]); 1004 optype0 = OFFSOP; 1005 } 1006 1007 if (optype0 == POPOP && optype1 == PUSHOP) 1008 { 1009 /* ??? Can this ever happen on i386? */ 1010 operands[1] = XEXP (XEXP (operands[1], 0), 0); 1011 asm_add (-size, operands[1]); 1012 if (GET_MODE (operands[1]) == XFmode) 1013 operands[1] = gen_rtx_MEM (XFmode, operands[1]); 1014 else if (GET_MODE (operands[1]) == DFmode) 1015 operands[1] = gen_rtx_MEM (DFmode, operands[1]); 1016 else 1017 operands[1] = gen_rtx_MEM (DImode, operands[1]); 1018 optype1 = OFFSOP; 1019 } 1020 1021 /* Ok, we can do one word at a time. 1022 Normally we do the low-numbered word first, 1023 but if either operand is autodecrementing then we 1024 do the high-numbered word first. 1025 1026 In either case, set up in LATEHALF the operands to use 1027 for the high-numbered word and in some cases alter the 1028 operands in OPERANDS to be suitable for the low-numbered word. */ 1029 1030 if (size == 12) 1031 { 1032 if (optype0 == REGOP) 1033 { 1034 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1035 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); 1036 } 1037 else if (optype0 == OFFSOP) 1038 { 1039 middlehalf[0] = adj_offsettable_operand (operands[0], 4); 1040 latehalf[0] = adj_offsettable_operand (operands[0], 8); 1041 } 1042 else 1043 { 1044 middlehalf[0] = operands[0]; 1045 latehalf[0] = operands[0]; 1046 } 1047 1048 if (optype1 == REGOP) 1049 { 1050 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1051 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); 1052 } 1053 else if (optype1 == OFFSOP) 1054 { 1055 middlehalf[1] = adj_offsettable_operand (operands[1], 4); 1056 latehalf[1] = adj_offsettable_operand (operands[1], 8); 1057 } 1058 else if (optype1 == CNSTOP) 1059 { 1060 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1061 { 1062 REAL_VALUE_TYPE r; long l[3]; 1063 1064 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1065 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); 1066 operands[1] = GEN_INT (l[0]); 1067 middlehalf[1] = GEN_INT (l[1]); 1068 latehalf[1] = GEN_INT (l[2]); 1069 } 1070 else if (CONSTANT_P (operands[1])) 1071 /* No non-CONST_DOUBLE constant should ever appear here. */ 1072 abort (); 1073 } 1074 else 1075 { 1076 middlehalf[1] = operands[1]; 1077 latehalf[1] = operands[1]; 1078 } 1079 } 1080 1081 else 1082 { 1083 /* Size is not 12. */ 1084 1085 if (optype0 == REGOP) 1086 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1087 else if (optype0 == OFFSOP) 1088 latehalf[0] = adj_offsettable_operand (operands[0], 4); 1089 else 1090 latehalf[0] = operands[0]; 1091 1092 if (optype1 == REGOP) 1093 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1094 else if (optype1 == OFFSOP) 1095 latehalf[1] = adj_offsettable_operand (operands[1], 4); 1096 else if (optype1 == CNSTOP) 1097 split_double (operands[1], &operands[1], &latehalf[1]); 1098 else 1099 latehalf[1] = operands[1]; 1100 } 1101 1102 /* If insn is effectively movd N (sp),-(sp) then we will do the 1103 high word first. We should use the adjusted operand 1 1104 (which is N+4 (sp) or N+8 (sp)) 1105 for the low word and middle word as well, 1106 to compensate for the first decrement of sp. */ 1107 if (optype0 == PUSHOP 1108 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM 1109 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) 1110 middlehalf[1] = operands[1] = latehalf[1]; 1111 1112 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), 1113 if the upper part of reg N does not appear in the MEM, arrange to 1114 emit the move late-half first. Otherwise, compute the MEM address 1115 into the upper part of N and use that as a pointer to the memory 1116 operand. */ 1117 if (optype0 == REGOP && optype1 == OFFSOP) 1118 { 1119 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) 1120 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) 1121 { 1122 /* If both halves of dest are used in the src memory address, 1123 compute the address into latehalf of dest. */ 1124 compadr: 1125 xops[0] = latehalf[0]; 1126 xops[1] = XEXP (operands[1], 0); 1127 output_asm_insn (AS2 (lea%L0,%a1,%0), xops); 1128 if (GET_MODE (operands[1]) == XFmode) 1129 { 1130 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); 1131 middlehalf[1] = adj_offsettable_operand (operands[1], size-8); 1132 latehalf[1] = adj_offsettable_operand (operands[1], size-4); 1133 } 1134 else 1135 { 1136 operands[1] = gen_rtx_MEM (DImode, latehalf[0]); 1137 latehalf[1] = adj_offsettable_operand (operands[1], size-4); 1138 } 1139 } 1140 1141 else if (size == 12 1142 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0))) 1143 { 1144 /* Check for two regs used by both source and dest. */ 1145 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) 1146 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) 1147 goto compadr; 1148 1149 /* Only the middle reg conflicts; simply put it last. */ 1150 output_asm_insn (singlemove_string (operands), operands); 1151 output_asm_insn (singlemove_string (latehalf), latehalf); 1152 output_asm_insn (singlemove_string (middlehalf), middlehalf); 1153 return ""; 1154 } 1155 1156 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))) 1157 /* If the low half of dest is mentioned in the source memory 1158 address, the arrange to emit the move late half first. */ 1159 dest_overlapped_low = 1; 1160 } 1161 1162 /* If one or both operands autodecrementing, 1163 do the two words, high-numbered first. */ 1164 1165 /* Likewise, the first move would clobber the source of the second one, 1166 do them in the other order. This happens only for registers; 1167 such overlap can't happen in memory unless the user explicitly 1168 sets it up, and that is an undefined circumstance. */ 1169 1170#if 0 1171 if (optype0 == PUSHOP || optype1 == PUSHOP 1172 || (optype0 == REGOP && optype1 == REGOP 1173 && REGNO (operands[0]) == REGNO (latehalf[1])) 1174 || dest_overlapped_low) 1175#endif 1176 1177 if (optype0 == PUSHOP || optype1 == PUSHOP 1178 || (optype0 == REGOP && optype1 == REGOP 1179 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) 1180 || REGNO (operands[0]) == REGNO (latehalf[1]))) 1181 || dest_overlapped_low) 1182 { 1183 /* Do the high-numbered word. */ 1184 output_asm_insn (singlemove_string (latehalf), latehalf); 1185 1186 if (size == 12) 1187 output_asm_insn (singlemove_string (middlehalf), middlehalf); 1188 1189 /* Do low-numbered word. */ 1190 return singlemove_string (operands); 1191 } 1192 1193 /* Normal case: do the two words, low-numbered first. */ 1194 1195 output_asm_insn (singlemove_string (operands), operands); 1196 1197 /* Do the middle one of the three words for long double */ 1198 if (size == 12) 1199 output_asm_insn (singlemove_string (middlehalf), middlehalf); 1200 1201 /* Do the high-numbered word. */ 1202 output_asm_insn (singlemove_string (latehalf), latehalf); 1203 1204 return ""; 1205} 1206 1207#define MAX_TMPS 2 /* max temporary registers used */ 1208 1209/* Output the appropriate code to move push memory on the stack */ 1210 1211char * 1212output_move_pushmem (operands, insn, length, tmp_start, n_operands) 1213 rtx operands[]; 1214 rtx insn; 1215 int length; 1216 int tmp_start; 1217 int n_operands; 1218{ 1219 struct 1220 { 1221 char *load; 1222 char *push; 1223 rtx xops[2]; 1224 } tmp_info[MAX_TMPS]; 1225 1226 rtx src = operands[1]; 1227 int max_tmps = 0; 1228 int offset = 0; 1229 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src); 1230 int stack_offset = 0; 1231 int i, num_tmps; 1232 rtx xops[1]; 1233 1234 if (! offsettable_memref_p (src)) 1235 fatal_insn ("Source is not offsettable", insn); 1236 1237 if ((length & 3) != 0) 1238 fatal_insn ("Pushing non-word aligned size", insn); 1239 1240 /* Figure out which temporary registers we have available */ 1241 for (i = tmp_start; i < n_operands; i++) 1242 { 1243 if (GET_CODE (operands[i]) == REG) 1244 { 1245 if (reg_overlap_mentioned_p (operands[i], src)) 1246 continue; 1247 1248 tmp_info[ max_tmps++ ].xops[1] = operands[i]; 1249 if (max_tmps == MAX_TMPS) 1250 break; 1251 } 1252 } 1253 1254 if (max_tmps == 0) 1255 for (offset = length - 4; offset >= 0; offset -= 4) 1256 { 1257 xops[0] = adj_offsettable_operand (src, offset + stack_offset); 1258 output_asm_insn (AS1(push%L0,%0), xops); 1259 if (stack_p) 1260 stack_offset += 4; 1261 } 1262 1263 else 1264 for (offset = length - 4; offset >= 0; ) 1265 { 1266 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++) 1267 { 1268 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1); 1269 tmp_info[num_tmps].push = AS1(push%L0,%1); 1270 tmp_info[num_tmps].xops[0] 1271 = adj_offsettable_operand (src, offset + stack_offset); 1272 offset -= 4; 1273 } 1274 1275 for (i = 0; i < num_tmps; i++) 1276 output_asm_insn (tmp_info[i].load, tmp_info[i].xops); 1277 1278 for (i = 0; i < num_tmps; i++) 1279 output_asm_insn (tmp_info[i].push, tmp_info[i].xops); 1280 1281 if (stack_p) 1282 stack_offset += 4*num_tmps; 1283 } 1284 1285 return ""; 1286} 1287 1288int 1289standard_80387_constant_p (x) 1290 rtx x; 1291{ 1292#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) 1293 REAL_VALUE_TYPE d; 1294 jmp_buf handler; 1295 int is0, is1; 1296 1297 if (setjmp (handler)) 1298 return 0; 1299 1300 set_float_handler (handler); 1301 REAL_VALUE_FROM_CONST_DOUBLE (d, x); 1302 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d); 1303 is1 = REAL_VALUES_EQUAL (d, dconst1); 1304 set_float_handler (NULL_PTR); 1305 1306 if (is0) 1307 return 1; 1308 1309 if (is1) 1310 return 2; 1311 1312 /* Note that on the 80387, other constants, such as pi, 1313 are much slower to load as standard constants 1314 than to load from doubles in memory! */ 1315 /* ??? Not true on K6: all constants are equal cost. */ 1316#endif 1317 1318 return 0; 1319} 1320 1321char * 1322output_move_const_single (operands) 1323 rtx *operands; 1324{ 1325 if (FP_REG_P (operands[0])) 1326 { 1327 int conval = standard_80387_constant_p (operands[1]); 1328 1329 if (conval == 1) 1330 return "fldz"; 1331 1332 if (conval == 2) 1333 return "fld1"; 1334 } 1335 1336 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1337 { 1338 REAL_VALUE_TYPE r; long l; 1339 1340 if (GET_MODE (operands[1]) == XFmode) 1341 abort (); 1342 1343 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1344 REAL_VALUE_TO_TARGET_SINGLE (r, l); 1345 operands[1] = GEN_INT (l); 1346 } 1347 1348 return singlemove_string (operands); 1349} 1350 1351/* Returns 1 if OP is either a symbol reference or a sum of a symbol 1352 reference and a constant. */ 1353 1354int 1355symbolic_operand (op, mode) 1356 register rtx op; 1357 enum machine_mode mode ATTRIBUTE_UNUSED; 1358{ 1359 switch (GET_CODE (op)) 1360 { 1361 case SYMBOL_REF: 1362 case LABEL_REF: 1363 return 1; 1364 1365 case CONST: 1366 op = XEXP (op, 0); 1367 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 1368 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 1369 && GET_CODE (XEXP (op, 1)) == CONST_INT); 1370 1371 default: 1372 return 0; 1373 } 1374} 1375 1376/* Return nonzero if OP is a constant shift count small enough to 1377 encode into an lea instruction. */ 1378 1379int 1380small_shift_operand (op, mode) 1381 rtx op; 1382 enum machine_mode mode ATTRIBUTE_UNUSED; 1383{ 1384 return (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 && INTVAL (op) < 4); 1385} 1386 1387/* Test for a valid operand for a call instruction. 1388 Don't allow the arg pointer register or virtual regs 1389 since they may change into reg + const, which the patterns 1390 can't handle yet. */ 1391 1392int 1393call_insn_operand (op, mode) 1394 rtx op; 1395 enum machine_mode mode ATTRIBUTE_UNUSED; 1396{ 1397 if (GET_CODE (op) == MEM 1398 && ((CONSTANT_ADDRESS_P (XEXP (op, 0)) 1399 /* This makes a difference for PIC. */ 1400 && general_operand (XEXP (op, 0), Pmode)) 1401 || (GET_CODE (XEXP (op, 0)) == REG 1402 && XEXP (op, 0) != arg_pointer_rtx 1403 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER 1404 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) 1405 return 1; 1406 1407 return 0; 1408} 1409 1410/* Like call_insn_operand but allow (mem (symbol_ref ...)) 1411 even if pic. */ 1412 1413int 1414expander_call_insn_operand (op, mode) 1415 rtx op; 1416 enum machine_mode mode ATTRIBUTE_UNUSED; 1417{ 1418 if (GET_CODE (op) == MEM 1419 && (CONSTANT_ADDRESS_P (XEXP (op, 0)) 1420 || (GET_CODE (XEXP (op, 0)) == REG 1421 && XEXP (op, 0) != arg_pointer_rtx 1422 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER 1423 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) 1424 return 1; 1425 1426 return 0; 1427} 1428 1429/* Return 1 if OP is a comparison operator that can use the condition code 1430 generated by an arithmetic operation. */ 1431 1432int 1433arithmetic_comparison_operator (op, mode) 1434 register rtx op; 1435 enum machine_mode mode; 1436{ 1437 enum rtx_code code; 1438 1439 if (mode != VOIDmode && mode != GET_MODE (op)) 1440 return 0; 1441 1442 code = GET_CODE (op); 1443 if (GET_RTX_CLASS (code) != '<') 1444 return 0; 1445 1446 return (code != GT && code != LE); 1447} 1448 1449int 1450ix86_logical_operator (op, mode) 1451 register rtx op; 1452 enum machine_mode mode ATTRIBUTE_UNUSED; 1453{ 1454 return GET_CODE (op) == AND || GET_CODE (op) == IOR || GET_CODE (op) == XOR; 1455} 1456 1457 1458/* Returns 1 if OP contains a symbol reference */ 1459 1460int 1461symbolic_reference_mentioned_p (op) 1462 rtx op; 1463{ 1464 register char *fmt; 1465 register int i; 1466 1467 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) 1468 return 1; 1469 1470 fmt = GET_RTX_FORMAT (GET_CODE (op)); 1471 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) 1472 { 1473 if (fmt[i] == 'E') 1474 { 1475 register int j; 1476 1477 for (j = XVECLEN (op, i) - 1; j >= 0; j--) 1478 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) 1479 return 1; 1480 } 1481 1482 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) 1483 return 1; 1484 } 1485 1486 return 0; 1487} 1488 1489/* Attempt to expand a binary operator. Make the expansion closer to the 1490 actual machine, then just general_operand, which will allow 3 separate 1491 memory references (one output, two input) in a single insn. Return 1492 whether the insn fails, or succeeds. */ 1493 1494int 1495ix86_expand_binary_operator (code, mode, operands) 1496 enum rtx_code code; 1497 enum machine_mode mode; 1498 rtx operands[]; 1499{ 1500 int modified; 1501 1502 /* Recognize <var1> = <value> <op> <var1> for commutative operators */ 1503 if (GET_RTX_CLASS (code) == 'c' 1504 && (rtx_equal_p (operands[0], operands[2]) 1505 || immediate_operand (operands[1], mode))) 1506 { 1507 rtx temp = operands[1]; 1508 operands[1] = operands[2]; 1509 operands[2] = temp; 1510 } 1511 1512 /* If optimizing, copy to regs to improve CSE */ 1513 if (TARGET_PSEUDO && optimize 1514 && ((reload_in_progress | reload_completed) == 0)) 1515 { 1516 if (GET_CODE (operands[1]) == MEM 1517 && ! rtx_equal_p (operands[0], operands[1])) 1518 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1519 1520 if (GET_CODE (operands[2]) == MEM) 1521 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 1522 1523 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS) 1524 { 1525 rtx temp = gen_reg_rtx (GET_MODE (operands[0])); 1526 1527 emit_move_insn (temp, operands[1]); 1528 operands[1] = temp; 1529 return TRUE; 1530 } 1531 } 1532 1533 if (!ix86_binary_operator_ok (code, mode, operands)) 1534 { 1535 /* If not optimizing, try to make a valid insn (optimize code 1536 previously did this above to improve chances of CSE) */ 1537 1538 if ((! TARGET_PSEUDO || !optimize) 1539 && ((reload_in_progress | reload_completed) == 0) 1540 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)) 1541 { 1542 modified = FALSE; 1543 if (GET_CODE (operands[1]) == MEM 1544 && ! rtx_equal_p (operands[0], operands[1])) 1545 { 1546 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1547 modified = TRUE; 1548 } 1549 1550 if (GET_CODE (operands[2]) == MEM) 1551 { 1552 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 1553 modified = TRUE; 1554 } 1555 1556 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS) 1557 { 1558 rtx temp = gen_reg_rtx (GET_MODE (operands[0])); 1559 1560 emit_move_insn (temp, operands[1]); 1561 operands[1] = temp; 1562 return TRUE; 1563 } 1564 1565 if (modified && ! ix86_binary_operator_ok (code, mode, operands)) 1566 return FALSE; 1567 } 1568 else 1569 return FALSE; 1570 } 1571 1572 return TRUE; 1573} 1574 1575/* Return TRUE or FALSE depending on whether the binary operator meets the 1576 appropriate constraints. */ 1577 1578int 1579ix86_binary_operator_ok (code, mode, operands) 1580 enum rtx_code code; 1581 enum machine_mode mode ATTRIBUTE_UNUSED; 1582 rtx operands[3]; 1583{ 1584 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) 1585 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c'); 1586} 1587 1588/* Attempt to expand a unary operator. Make the expansion closer to the 1589 actual machine, then just general_operand, which will allow 2 separate 1590 memory references (one output, one input) in a single insn. Return 1591 whether the insn fails, or succeeds. */ 1592 1593int 1594ix86_expand_unary_operator (code, mode, operands) 1595 enum rtx_code code; 1596 enum machine_mode mode; 1597 rtx operands[]; 1598{ 1599 /* If optimizing, copy to regs to improve CSE */ 1600 if (TARGET_PSEUDO 1601 && optimize 1602 && ((reload_in_progress | reload_completed) == 0) 1603 && GET_CODE (operands[1]) == MEM) 1604 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1605 1606 if (! ix86_unary_operator_ok (code, mode, operands)) 1607 { 1608 if ((! TARGET_PSEUDO || optimize == 0) 1609 && ((reload_in_progress | reload_completed) == 0) 1610 && GET_CODE (operands[1]) == MEM) 1611 { 1612 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 1613 if (! ix86_unary_operator_ok (code, mode, operands)) 1614 return FALSE; 1615 } 1616 else 1617 return FALSE; 1618 } 1619 1620 return TRUE; 1621} 1622 1623/* Return TRUE or FALSE depending on whether the unary operator meets the 1624 appropriate constraints. */ 1625 1626int 1627ix86_unary_operator_ok (code, mode, operands) 1628 enum rtx_code code ATTRIBUTE_UNUSED; 1629 enum machine_mode mode ATTRIBUTE_UNUSED; 1630 rtx operands[2] ATTRIBUTE_UNUSED; 1631{ 1632 return TRUE; 1633} 1634 1635static rtx pic_label_rtx; 1636static char pic_label_name [256]; 1637static int pic_label_no = 0; 1638 1639/* This function generates code for -fpic that loads %ebx with 1640 the return address of the caller and then returns. */ 1641 1642void 1643asm_output_function_prefix (file, name) 1644 FILE *file; 1645 char *name ATTRIBUTE_UNUSED; 1646{ 1647 rtx xops[2]; 1648 xops[0] = pic_offset_table_rtx; 1649 xops[1] = stack_pointer_rtx; 1650 1651 /* Deep branch prediction favors having a return for every call. */ 1652 if (PIC_REG_USED && TARGET_DEEP_BRANCH_PREDICTION) 1653 { 1654 tree prologue_node; 1655 1656 if (pic_label_rtx == 0) 1657 { 1658 pic_label_rtx = gen_label_rtx (); 1659 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++); 1660 LABEL_NAME (pic_label_rtx) = pic_label_name; 1661 } 1662 1663 prologue_node = make_node (FUNCTION_DECL); 1664 DECL_RESULT (prologue_node) = 0; 1665 1666 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an 1667 internal (non-global) label that's being emitted, it didn't make 1668 sense to have .type information for local labels. This caused 1669 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving 1670 me debug info for a label that you're declaring non-global?) this 1671 was changed to call ASM_OUTPUT_LABEL() instead. */ 1672 1673 1674 ASM_OUTPUT_LABEL (file, pic_label_name); 1675 output_asm_insn ("movl (%1),%0", xops); 1676 output_asm_insn ("ret", xops); 1677 } 1678} 1679 1680/* Generate the assembly code for function entry. 1681 FILE is an stdio stream to output the code to. 1682 SIZE is an int: how many units of temporary storage to allocate. */ 1683 1684void 1685function_prologue (file, size) 1686 FILE *file ATTRIBUTE_UNUSED; 1687 int size ATTRIBUTE_UNUSED; 1688{ 1689 if (TARGET_SCHEDULE_PROLOGUE) 1690 { 1691 pic_label_rtx = 0; 1692 return; 1693 } 1694 1695 ix86_prologue (0); 1696} 1697 1698/* Expand the prologue into a bunch of separate insns. */ 1699 1700void 1701ix86_expand_prologue () 1702{ 1703 if (! TARGET_SCHEDULE_PROLOGUE) 1704 return; 1705 1706 ix86_prologue (1); 1707} 1708 1709void 1710load_pic_register (do_rtl) 1711 int do_rtl; 1712{ 1713 rtx xops[4]; 1714 1715 if (TARGET_DEEP_BRANCH_PREDICTION) 1716 { 1717 xops[0] = pic_offset_table_rtx; 1718 if (pic_label_rtx == 0) 1719 { 1720 pic_label_rtx = gen_label_rtx (); 1721 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++); 1722 LABEL_NAME (pic_label_rtx) = pic_label_name; 1723 } 1724 1725 xops[1] = gen_rtx_MEM (QImode, 1726 gen_rtx (SYMBOL_REF, Pmode, 1727 LABEL_NAME (pic_label_rtx))); 1728 1729 if (do_rtl) 1730 { 1731 emit_insn (gen_prologue_get_pc (xops[0], xops[1])); 1732 emit_insn (gen_prologue_set_got (xops[0], 1733#ifdef YES_UNDERSCORES 1734 gen_rtx_SYMBOL_REF (Pmode, 1735 "$__GLOBAL_OFFSET_TABLE_"), 1736#else 1737 gen_rtx_SYMBOL_REF (Pmode, 1738 "$_GLOBAL_OFFSET_TABLE_"), 1739#endif 1740 xops[1])); 1741 } 1742 else 1743 { 1744 output_asm_insn (AS1 (call,%X1), xops); 1745 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_,%0", xops); 1746 pic_label_rtx = 0; 1747 } 1748 } 1749 1750 else 1751 { 1752 xops[0] = pic_offset_table_rtx; 1753 xops[1] = gen_label_rtx (); 1754 1755 if (do_rtl) 1756 { 1757 /* We can't put a raw CODE_LABEL into the RTL, and we can't emit 1758 a new CODE_LABEL after reload, so we need a single pattern to 1759 emit the 3 necessary instructions. */ 1760 emit_insn (gen_prologue_get_pc_and_set_got (xops[0])); 1761 } 1762 else 1763 { 1764 output_asm_insn (AS1 (call,%P1), xops); 1765 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 1766 CODE_LABEL_NUMBER (xops[1])); 1767 output_asm_insn (AS1 (pop%L0,%0), xops); 1768 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops); 1769 } 1770 } 1771 1772 /* When -fpic, we must emit a scheduling barrier, so that the instruction 1773 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get 1774 moved before any instruction which implicitly uses the got. */ 1775 1776 if (do_rtl) 1777 emit_insn (gen_blockage ()); 1778} 1779 1780/* Compute the size of local storage taking into consideration the 1781 desired stack alignment which is to be maintained. Also determine 1782 the number of registers saved below the local storage. */ 1783 1784HOST_WIDE_INT 1785ix86_compute_frame_size (size, nregs_on_stack) 1786 HOST_WIDE_INT size; 1787 int *nregs_on_stack; 1788{ 1789 int limit; 1790 int nregs; 1791 int regno; 1792 int padding; 1793 int pic_reg_used = PIC_REG_USED; 1794 HOST_WIDE_INT total_size; 1795 1796 limit = frame_pointer_needed 1797 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM; 1798 1799 nregs = 0; 1800 1801 for (regno = limit - 1; regno >= 0; regno--) 1802 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 1803 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 1804 nregs++; 1805 1806 padding = 0; 1807 total_size = size + (nregs * UNITS_PER_WORD); 1808 1809#ifdef PREFERRED_STACK_BOUNDARY 1810 { 1811 int offset; 1812 int preferred_alignment = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT; 1813 1814 offset = 4; 1815 if (frame_pointer_needed) 1816 offset += UNITS_PER_WORD; 1817 1818 total_size += offset; 1819 1820 padding = ((total_size + preferred_alignment - 1) 1821 & -preferred_alignment) - total_size; 1822 1823 if (padding < (((offset + preferred_alignment - 1) 1824 & -preferred_alignment) - offset)) 1825 padding += preferred_alignment; 1826 1827 /* Don't bother aligning the stack of a leaf function 1828 which doesn't allocate any stack slots. */ 1829 if (size == 0 && current_function_is_leaf) 1830 padding = 0; 1831 } 1832#endif 1833 1834 if (nregs_on_stack) 1835 *nregs_on_stack = nregs; 1836 1837 return size + padding; 1838} 1839 1840static void 1841ix86_prologue (do_rtl) 1842 int do_rtl; 1843{ 1844 register int regno; 1845 int limit; 1846 rtx xops[4]; 1847 int pic_reg_used = PIC_REG_USED; 1848 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), (int *)0); 1849 rtx insn; 1850 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset; 1851 1852 xops[0] = stack_pointer_rtx; 1853 xops[1] = frame_pointer_rtx; 1854 xops[2] = GEN_INT (tsize); 1855 1856 if (frame_pointer_needed) 1857 { 1858 if (do_rtl) 1859 { 1860 insn = emit_insn (gen_rtx (SET, VOIDmode, 1861 gen_rtx_MEM (SImode, 1862 gen_rtx (PRE_DEC, SImode, 1863 stack_pointer_rtx)), 1864 frame_pointer_rtx)); 1865 1866 RTX_FRAME_RELATED_P (insn) = 1; 1867 insn = emit_move_insn (xops[1], xops[0]); 1868 RTX_FRAME_RELATED_P (insn) = 1; 1869 } 1870 1871 else 1872 { 1873 output_asm_insn ("push%L1 %1", xops); 1874#ifdef INCOMING_RETURN_ADDR_RTX 1875 if (dwarf2out_do_frame ()) 1876 { 1877 char *l = dwarf2out_cfi_label (); 1878 1879 cfa_store_offset += 4; 1880 cfa_offset = cfa_store_offset; 1881 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); 1882 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset); 1883 } 1884#endif 1885 1886 output_asm_insn (AS2 (mov%L0,%0,%1), xops); 1887#ifdef INCOMING_RETURN_ADDR_RTX 1888 if (dwarf2out_do_frame ()) 1889 dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset); 1890#endif 1891 } 1892 } 1893 1894 if (tsize == 0) 1895 ; 1896 else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT) 1897 { 1898 if (do_rtl) 1899 { 1900 insn = emit_insn (gen_prologue_set_stack_ptr (xops[2])); 1901 RTX_FRAME_RELATED_P (insn) = 1; 1902 } 1903 else 1904 { 1905 output_asm_insn (AS2 (sub%L0,%2,%0), xops); 1906#ifdef INCOMING_RETURN_ADDR_RTX 1907 if (dwarf2out_do_frame ()) 1908 { 1909 cfa_store_offset += tsize; 1910 if (! frame_pointer_needed) 1911 { 1912 cfa_offset = cfa_store_offset; 1913 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset); 1914 } 1915 } 1916#endif 1917 } 1918 } 1919 else 1920 { 1921 xops[3] = gen_rtx_REG (SImode, 0); 1922 if (do_rtl) 1923 emit_move_insn (xops[3], xops[2]); 1924 else 1925 output_asm_insn (AS2 (mov%L0,%2,%3), xops); 1926 1927 xops[3] = gen_rtx_MEM (FUNCTION_MODE, 1928 gen_rtx (SYMBOL_REF, Pmode, "_alloca")); 1929 1930 if (do_rtl) 1931 emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx)); 1932 else 1933 output_asm_insn (AS1 (call,%P3), xops); 1934 } 1935 1936 /* Note If use enter it is NOT reversed args. 1937 This one is not reversed from intel!! 1938 I think enter is slower. Also sdb doesn't like it. 1939 But if you want it the code is: 1940 { 1941 xops[3] = const0_rtx; 1942 output_asm_insn ("enter %2,%3", xops); 1943 } 1944 */ 1945 1946 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); 1947 for (regno = limit - 1; regno >= 0; regno--) 1948 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 1949 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 1950 { 1951 xops[0] = gen_rtx_REG (SImode, regno); 1952 if (do_rtl) 1953 { 1954 insn = emit_insn (gen_rtx (SET, VOIDmode, 1955 gen_rtx_MEM (SImode, 1956 gen_rtx (PRE_DEC, SImode, 1957 stack_pointer_rtx)), 1958 xops[0])); 1959 1960 RTX_FRAME_RELATED_P (insn) = 1; 1961 } 1962 else 1963 { 1964 output_asm_insn ("push%L0 %0", xops); 1965#ifdef INCOMING_RETURN_ADDR_RTX 1966 if (dwarf2out_do_frame ()) 1967 { 1968 char *l = dwarf2out_cfi_label (); 1969 1970 cfa_store_offset += 4; 1971 if (! frame_pointer_needed) 1972 { 1973 cfa_offset = cfa_store_offset; 1974 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset); 1975 } 1976 1977 dwarf2out_reg_save (l, regno, - cfa_store_offset); 1978 } 1979#endif 1980 } 1981 } 1982 1983#ifdef SUBTARGET_PROLOGUE 1984 SUBTARGET_PROLOGUE; 1985#endif 1986 1987 if (pic_reg_used) 1988 load_pic_register (do_rtl); 1989 1990 /* If we are profiling, make sure no instructions are scheduled before 1991 the call to mcount. However, if -fpic, the above call will have 1992 done that. */ 1993 if ((profile_flag || profile_block_flag) 1994 && ! pic_reg_used && do_rtl) 1995 emit_insn (gen_blockage ()); 1996} 1997 1998/* Return 1 if it is appropriate to emit `ret' instructions in the 1999 body of a function. Do this only if the epilogue is simple, needing a 2000 couple of insns. Prior to reloading, we can't tell how many registers 2001 must be saved, so return 0 then. Return 0 if there is no frame 2002 marker to de-allocate. 2003 2004 If NON_SAVING_SETJMP is defined and true, then it is not possible 2005 for the epilogue to be simple, so return 0. This is a special case 2006 since NON_SAVING_SETJMP will not cause regs_ever_live to change 2007 until final, but jump_optimize may need to know sooner if a 2008 `return' is OK. */ 2009 2010int 2011ix86_can_use_return_insn_p () 2012{ 2013 int regno; 2014 int nregs = 0; 2015 int reglimit = (frame_pointer_needed 2016 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); 2017 2018#ifdef NON_SAVING_SETJMP 2019 if (NON_SAVING_SETJMP && current_function_calls_setjmp) 2020 return 0; 2021#endif 2022 2023 if (! reload_completed) 2024 return 0; 2025 2026 for (regno = reglimit - 1; regno >= 0; regno--) 2027 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 2028 || (regno == PIC_OFFSET_TABLE_REGNUM && PIC_REG_USED)) 2029 nregs++; 2030 2031 return nregs == 0 || ! frame_pointer_needed; 2032} 2033 2034/* This function generates the assembly code for function exit. 2035 FILE is an stdio stream to output the code to. 2036 SIZE is an int: how many units of temporary storage to deallocate. */ 2037 2038void 2039function_epilogue (file, size) 2040 FILE *file ATTRIBUTE_UNUSED; 2041 int size ATTRIBUTE_UNUSED; 2042{ 2043 return; 2044} 2045 2046/* Restore function stack, frame, and registers. */ 2047 2048void 2049ix86_expand_epilogue () 2050{ 2051 ix86_epilogue (1); 2052} 2053 2054static void 2055ix86_epilogue (do_rtl) 2056 int do_rtl; 2057{ 2058 register int regno; 2059 register int limit; 2060 int nregs; 2061 rtx xops[3]; 2062 int pic_reg_used = PIC_REG_USED; 2063 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging; 2064 HOST_WIDE_INT offset; 2065 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), &nregs); 2066 2067 /* sp is often unreliable so we may have to go off the frame pointer. */ 2068 2069 offset = -(tsize + nregs * UNITS_PER_WORD); 2070 2071 xops[2] = stack_pointer_rtx; 2072 2073 /* When -fpic, we must emit a scheduling barrier, so that the instruction 2074 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get 2075 moved before any instruction which implicitly uses the got. This 2076 includes any instruction which uses a SYMBOL_REF or a LABEL_REF. 2077 2078 Alternatively, this could be fixed by making the dependence on the 2079 PIC_OFFSET_TABLE_REGNUM explicit in the RTL. */ 2080 2081 if (flag_pic || profile_flag || profile_block_flag) 2082 emit_insn (gen_blockage ()); 2083 2084 /* If we're only restoring one register and sp is not valid then 2085 using a move instruction to restore the register since it's 2086 less work than reloading sp and popping the register. Otherwise, 2087 restore sp (if necessary) and pop the registers. */ 2088 2089 limit = frame_pointer_needed 2090 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM; 2091 2092 if (nregs > 1 || sp_valid) 2093 { 2094 if ( !sp_valid ) 2095 { 2096 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset); 2097 if (do_rtl) 2098 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0))); 2099 else 2100 output_asm_insn (AS2 (lea%L2,%0,%2), xops); 2101 } 2102 2103 for (regno = 0; regno < limit; regno++) 2104 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 2105 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 2106 { 2107 xops[0] = gen_rtx_REG (SImode, regno); 2108 2109 if (do_rtl) 2110 emit_insn (gen_pop (xops[0])); 2111 else 2112 output_asm_insn ("pop%L0 %0", xops); 2113 } 2114 } 2115 2116 else 2117 for (regno = 0; regno < limit; regno++) 2118 if ((regs_ever_live[regno] && ! call_used_regs[regno]) 2119 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 2120 { 2121 xops[0] = gen_rtx_REG (SImode, regno); 2122 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset); 2123 2124 if (do_rtl) 2125 emit_move_insn (xops[0], xops[1]); 2126 else 2127 output_asm_insn (AS2 (mov%L0,%1,%0), xops); 2128 2129 offset += 4; 2130 } 2131 2132 if (frame_pointer_needed) 2133 { 2134 /* If not an i386, mov & pop is faster than "leave". */ 2135 2136 if (TARGET_USE_LEAVE) 2137 { 2138 if (do_rtl) 2139 emit_insn (gen_leave()); 2140 else 2141 output_asm_insn ("leave", xops); 2142 } 2143 else 2144 { 2145 xops[0] = frame_pointer_rtx; 2146 xops[1] = stack_pointer_rtx; 2147 2148 if (do_rtl) 2149 { 2150 emit_insn (gen_epilogue_set_stack_ptr()); 2151 emit_insn (gen_pop (xops[0])); 2152 } 2153 else 2154 { 2155 output_asm_insn (AS2 (mov%L2,%0,%2), xops); 2156 output_asm_insn ("pop%L0 %0", xops); 2157 } 2158 } 2159 } 2160 2161 else if (tsize) 2162 { 2163 /* Intel's docs say that for 4 or 8 bytes of stack frame one should 2164 use `pop' and not `add'. */ 2165 int use_pop = tsize == 4; 2166 2167 /* Use two pops only for the Pentium processors. */ 2168 if (tsize == 8 && !TARGET_386 && !TARGET_486) 2169 { 2170 rtx retval = current_function_return_rtx; 2171 2172 xops[1] = gen_rtx_REG (SImode, 1); /* %edx */ 2173 2174 /* This case is a bit more complex. Since we cannot pop into 2175 %ecx twice we need a second register. But this is only 2176 available if the return value is not of DImode in which 2177 case the %edx register is not available. */ 2178 use_pop = (retval == NULL 2179 || ! reg_overlap_mentioned_p (xops[1], retval)); 2180 } 2181 2182 if (use_pop) 2183 { 2184 xops[0] = gen_rtx_REG (SImode, 2); /* %ecx */ 2185 2186 if (do_rtl) 2187 { 2188 /* We have to prevent the two pops here from being scheduled. 2189 GCC otherwise would try in some situation to put other 2190 instructions in between them which has a bad effect. */ 2191 emit_insn (gen_blockage ()); 2192 emit_insn (gen_pop (xops[0])); 2193 if (tsize == 8) 2194 emit_insn (gen_pop (xops[1])); 2195 } 2196 else 2197 { 2198 output_asm_insn ("pop%L0 %0", xops); 2199 if (tsize == 8) 2200 output_asm_insn ("pop%L1 %1", xops); 2201 } 2202 } 2203 else 2204 { 2205 /* If there is no frame pointer, we must still release the frame. */ 2206 xops[0] = GEN_INT (tsize); 2207 2208 if (do_rtl) 2209 emit_insn (gen_rtx (SET, VOIDmode, xops[2], 2210 gen_rtx (PLUS, SImode, xops[2], xops[0]))); 2211 else 2212 output_asm_insn (AS2 (add%L2,%0,%2), xops); 2213 } 2214 } 2215 2216#ifdef FUNCTION_BLOCK_PROFILER_EXIT 2217 if (profile_block_flag == 2) 2218 { 2219 FUNCTION_BLOCK_PROFILER_EXIT(file); 2220 } 2221#endif 2222 2223 if (current_function_pops_args && current_function_args_size) 2224 { 2225 xops[1] = GEN_INT (current_function_pops_args); 2226 2227 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If 2228 asked to pop more, pop return address, do explicit add, and jump 2229 indirectly to the caller. */ 2230 2231 if (current_function_pops_args >= 32768) 2232 { 2233 /* ??? Which register to use here? */ 2234 xops[0] = gen_rtx_REG (SImode, 2); 2235 2236 if (do_rtl) 2237 { 2238 emit_insn (gen_pop (xops[0])); 2239 emit_insn (gen_rtx (SET, VOIDmode, xops[2], 2240 gen_rtx (PLUS, SImode, xops[1], xops[2]))); 2241 emit_jump_insn (xops[0]); 2242 } 2243 else 2244 { 2245 output_asm_insn ("pop%L0 %0", xops); 2246 output_asm_insn (AS2 (add%L2,%1,%2), xops); 2247 output_asm_insn ("jmp %*%0", xops); 2248 } 2249 } 2250 else 2251 { 2252 if (do_rtl) 2253 emit_jump_insn (gen_return_pop_internal (xops[1])); 2254 else 2255 output_asm_insn ("ret %1", xops); 2256 } 2257 } 2258 else 2259 { 2260 if (do_rtl) 2261 emit_jump_insn (gen_return_internal ()); 2262 else 2263 output_asm_insn ("ret", xops); 2264 } 2265} 2266 2267/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2268 that is a valid memory address for an instruction. 2269 The MODE argument is the machine mode for the MEM expression 2270 that wants to use this address. 2271 2272 On x86, legitimate addresses are: 2273 base movl (base),reg 2274 displacement movl disp,reg 2275 base + displacement movl disp(base),reg 2276 index + base movl (base,index),reg 2277 (index + base) + displacement movl disp(base,index),reg 2278 index*scale movl (,index,scale),reg 2279 index*scale + disp movl disp(,index,scale),reg 2280 index*scale + base movl (base,index,scale),reg 2281 (index*scale + base) + disp movl disp(base,index,scale),reg 2282 2283 In each case, scale can be 1, 2, 4, 8. */ 2284 2285/* This is exactly the same as print_operand_addr, except that 2286 it recognizes addresses instead of printing them. 2287 2288 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should 2289 convert common non-canonical forms to canonical form so that they will 2290 be recognized. */ 2291 2292#define ADDR_INVALID(msg,insn) \ 2293do { \ 2294 if (TARGET_DEBUG_ADDR) \ 2295 { \ 2296 fprintf (stderr, msg); \ 2297 debug_rtx (insn); \ 2298 } \ 2299} while (0) 2300 2301int 2302legitimate_pic_address_disp_p (disp) 2303 register rtx disp; 2304{ 2305 if (GET_CODE (disp) != CONST) 2306 return 0; 2307 disp = XEXP (disp, 0); 2308 2309 if (GET_CODE (disp) == PLUS) 2310 { 2311 if (GET_CODE (XEXP (disp, 1)) != CONST_INT) 2312 return 0; 2313 disp = XEXP (disp, 0); 2314 } 2315 2316 if (GET_CODE (disp) != UNSPEC 2317 || XVECLEN (disp, 0) != 1) 2318 return 0; 2319 2320 /* Must be @GOT or @GOTOFF. */ 2321 if (XINT (disp, 1) != 6 2322 && XINT (disp, 1) != 7) 2323 return 0; 2324 2325 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF 2326 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF) 2327 return 0; 2328 2329 return 1; 2330} 2331 2332int 2333legitimate_address_p (mode, addr, strict) 2334 enum machine_mode mode; 2335 register rtx addr; 2336 int strict; 2337{ 2338 rtx base = NULL_RTX; 2339 rtx indx = NULL_RTX; 2340 rtx scale = NULL_RTX; 2341 rtx disp = NULL_RTX; 2342 2343 if (TARGET_DEBUG_ADDR) 2344 { 2345 fprintf (stderr, 2346 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n", 2347 GET_MODE_NAME (mode), strict); 2348 2349 debug_rtx (addr); 2350 } 2351 2352 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG) 2353 base = addr; 2354 2355 else if (GET_CODE (addr) == PLUS) 2356 { 2357 rtx op0 = XEXP (addr, 0); 2358 rtx op1 = XEXP (addr, 1); 2359 enum rtx_code code0 = GET_CODE (op0); 2360 enum rtx_code code1 = GET_CODE (op1); 2361 2362 if (code0 == REG || code0 == SUBREG) 2363 { 2364 if (code1 == REG || code1 == SUBREG) 2365 { 2366 indx = op0; /* index + base */ 2367 base = op1; 2368 } 2369 2370 else 2371 { 2372 base = op0; /* base + displacement */ 2373 disp = op1; 2374 } 2375 } 2376 2377 else if (code0 == MULT) 2378 { 2379 indx = XEXP (op0, 0); 2380 scale = XEXP (op0, 1); 2381 2382 if (code1 == REG || code1 == SUBREG) 2383 base = op1; /* index*scale + base */ 2384 2385 else 2386 disp = op1; /* index*scale + disp */ 2387 } 2388 2389 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) 2390 { 2391 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */ 2392 scale = XEXP (XEXP (op0, 0), 1); 2393 base = XEXP (op0, 1); 2394 disp = op1; 2395 } 2396 2397 else if (code0 == PLUS) 2398 { 2399 indx = XEXP (op0, 0); /* index + base + disp */ 2400 base = XEXP (op0, 1); 2401 disp = op1; 2402 } 2403 2404 else 2405 { 2406 ADDR_INVALID ("PLUS subcode is not valid.\n", op0); 2407 return FALSE; 2408 } 2409 } 2410 2411 else if (GET_CODE (addr) == MULT) 2412 { 2413 indx = XEXP (addr, 0); /* index*scale */ 2414 scale = XEXP (addr, 1); 2415 } 2416 2417 else 2418 disp = addr; /* displacement */ 2419 2420 /* Allow arg pointer and stack pointer as index if there is not scaling */ 2421 if (base && indx && !scale 2422 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx)) 2423 { 2424 rtx tmp = base; 2425 base = indx; 2426 indx = tmp; 2427 } 2428 2429 /* Validate base register: 2430 2431 Don't allow SUBREG's here, it can lead to spill failures when the base 2432 is one word out of a two word structure, which is represented internally 2433 as a DImode int. */ 2434 2435 if (base) 2436 { 2437 if (GET_CODE (base) != REG) 2438 { 2439 ADDR_INVALID ("Base is not a register.\n", base); 2440 return FALSE; 2441 } 2442 2443 if (GET_MODE (base) != Pmode) 2444 { 2445 ADDR_INVALID ("Base is not in Pmode.\n", base); 2446 return FALSE; 2447 } 2448 2449 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base)) 2450 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base))) 2451 { 2452 ADDR_INVALID ("Base is not valid.\n", base); 2453 return FALSE; 2454 } 2455 } 2456 2457 /* Validate index register: 2458 2459 Don't allow SUBREG's here, it can lead to spill failures when the index 2460 is one word out of a two word structure, which is represented internally 2461 as a DImode int. */ 2462 if (indx) 2463 { 2464 if (GET_CODE (indx) != REG) 2465 { 2466 ADDR_INVALID ("Index is not a register.\n", indx); 2467 return FALSE; 2468 } 2469 2470 if (GET_MODE (indx) != Pmode) 2471 { 2472 ADDR_INVALID ("Index is not in Pmode.\n", indx); 2473 return FALSE; 2474 } 2475 2476 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx)) 2477 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx))) 2478 { 2479 ADDR_INVALID ("Index is not valid.\n", indx); 2480 return FALSE; 2481 } 2482 } 2483 else if (scale) 2484 abort (); /* scale w/o index invalid */ 2485 2486 /* Validate scale factor: */ 2487 if (scale) 2488 { 2489 HOST_WIDE_INT value; 2490 2491 if (GET_CODE (scale) != CONST_INT) 2492 { 2493 ADDR_INVALID ("Scale is not valid.\n", scale); 2494 return FALSE; 2495 } 2496 2497 value = INTVAL (scale); 2498 if (value != 1 && value != 2 && value != 4 && value != 8) 2499 { 2500 ADDR_INVALID ("Scale is not a good multiplier.\n", scale); 2501 return FALSE; 2502 } 2503 } 2504 2505 /* Validate displacement. */ 2506 if (disp) 2507 { 2508 if (!CONSTANT_ADDRESS_P (disp)) 2509 { 2510 ADDR_INVALID ("Displacement is not valid.\n", disp); 2511 return FALSE; 2512 } 2513 2514 else if (GET_CODE (disp) == CONST_DOUBLE) 2515 { 2516 ADDR_INVALID ("Displacement is a const_double.\n", disp); 2517 return FALSE; 2518 } 2519 2520 if (flag_pic && SYMBOLIC_CONST (disp)) 2521 { 2522 if (! legitimate_pic_address_disp_p (disp)) 2523 { 2524 ADDR_INVALID ("Displacement is an invalid PIC construct.\n", 2525 disp); 2526 return FALSE; 2527 } 2528 2529 if (base != pic_offset_table_rtx 2530 && (indx != pic_offset_table_rtx || scale != NULL_RTX)) 2531 { 2532 ADDR_INVALID ("PIC displacement against invalid base.\n", disp); 2533 return FALSE; 2534 } 2535 } 2536 2537 else if (HALF_PIC_P ()) 2538 { 2539 if (! HALF_PIC_ADDRESS_P (disp) 2540 || (base != NULL_RTX || indx != NULL_RTX)) 2541 { 2542 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", 2543 disp); 2544 return FALSE; 2545 } 2546 } 2547 } 2548 2549 if (TARGET_DEBUG_ADDR) 2550 fprintf (stderr, "Address is valid.\n"); 2551 2552 /* Everything looks valid, return true */ 2553 return TRUE; 2554} 2555 2556/* Return a legitimate reference for ORIG (an address) using the 2557 register REG. If REG is 0, a new pseudo is generated. 2558 2559 There are two types of references that must be handled: 2560 2561 1. Global data references must load the address from the GOT, via 2562 the PIC reg. An insn is emitted to do this load, and the reg is 2563 returned. 2564 2565 2. Static data references, constant pool addresses, and code labels 2566 compute the address as an offset from the GOT, whose base is in 2567 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to 2568 differentiate them from global data objects. The returned 2569 address is the PIC reg + an unspec constant. 2570 2571 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC 2572 reg also appears in the address. */ 2573 2574rtx 2575legitimize_pic_address (orig, reg) 2576 rtx orig; 2577 rtx reg; 2578{ 2579 rtx addr = orig; 2580 rtx new = orig; 2581 rtx base; 2582 2583 if (GET_CODE (addr) == LABEL_REF 2584 || (GET_CODE (addr) == SYMBOL_REF 2585 && (CONSTANT_POOL_ADDRESS_P (addr) 2586 || SYMBOL_REF_FLAG (addr)))) 2587 { 2588 /* This symbol may be referenced via a displacement from the PIC 2589 base address (@GOTOFF). */ 2590 2591 current_function_uses_pic_offset_table = 1; 2592 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7); 2593 new = gen_rtx_CONST (VOIDmode, new); 2594 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 2595 2596 if (reg != 0) 2597 { 2598 emit_move_insn (reg, new); 2599 new = reg; 2600 } 2601 } 2602 else if (GET_CODE (addr) == SYMBOL_REF) 2603 { 2604 /* This symbol must be referenced via a load from the 2605 Global Offset Table (@GOT). */ 2606 2607 current_function_uses_pic_offset_table = 1; 2608 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6); 2609 new = gen_rtx_CONST (VOIDmode, new); 2610 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 2611 new = gen_rtx_MEM (Pmode, new); 2612 RTX_UNCHANGING_P (new) = 1; 2613 2614 if (reg == 0) 2615 reg = gen_reg_rtx (Pmode); 2616 emit_move_insn (reg, new); 2617 new = reg; 2618 } 2619 else 2620 { 2621 if (GET_CODE (addr) == CONST) 2622 { 2623 addr = XEXP (addr, 0); 2624 if (GET_CODE (addr) == UNSPEC) 2625 { 2626 /* Check that the unspec is one of the ones we generate? */ 2627 } 2628 else if (GET_CODE (addr) != PLUS) 2629 abort(); 2630 } 2631 if (GET_CODE (addr) == PLUS) 2632 { 2633 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1); 2634 2635 /* Check first to see if this is a constant offset from a @GOTOFF 2636 symbol reference. */ 2637 if ((GET_CODE (op0) == LABEL_REF 2638 || (GET_CODE (op0) == SYMBOL_REF 2639 && (CONSTANT_POOL_ADDRESS_P (op0) 2640 || SYMBOL_REF_FLAG (op0)))) 2641 && GET_CODE (op1) == CONST_INT) 2642 { 2643 current_function_uses_pic_offset_table = 1; 2644 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7); 2645 new = gen_rtx_PLUS (VOIDmode, new, op1); 2646 new = gen_rtx_CONST (VOIDmode, new); 2647 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); 2648 2649 if (reg != 0) 2650 { 2651 emit_move_insn (reg, new); 2652 new = reg; 2653 } 2654 } 2655 else 2656 { 2657 base = legitimize_pic_address (XEXP (addr, 0), reg); 2658 new = legitimize_pic_address (XEXP (addr, 1), 2659 base == reg ? NULL_RTX : reg); 2660 2661 if (GET_CODE (new) == CONST_INT) 2662 new = plus_constant (base, INTVAL (new)); 2663 else 2664 { 2665 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1))) 2666 { 2667 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0)); 2668 new = XEXP (new, 1); 2669 } 2670 new = gen_rtx_PLUS (Pmode, base, new); 2671 } 2672 } 2673 } 2674 } 2675 return new; 2676} 2677 2678/* Emit insns to move operands[1] into operands[0]. */ 2679 2680void 2681emit_pic_move (operands, mode) 2682 rtx *operands; 2683 enum machine_mode mode ATTRIBUTE_UNUSED; 2684{ 2685 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 2686 2687 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) 2688 operands[1] = force_reg (Pmode, operands[1]); 2689 else 2690 operands[1] = legitimize_pic_address (operands[1], temp); 2691} 2692 2693/* Try machine-dependent ways of modifying an illegitimate address 2694 to be legitimate. If we find one, return the new, valid address. 2695 This macro is used in only one place: `memory_address' in explow.c. 2696 2697 OLDX is the address as it was before break_out_memory_refs was called. 2698 In some cases it is useful to look at this to decide what needs to be done. 2699 2700 MODE and WIN are passed so that this macro can use 2701 GO_IF_LEGITIMATE_ADDRESS. 2702 2703 It is always safe for this macro to do nothing. It exists to recognize 2704 opportunities to optimize the output. 2705 2706 For the 80386, we handle X+REG by loading X into a register R and 2707 using R+REG. R will go in a general reg and indexing will be used. 2708 However, if REG is a broken-out memory address or multiplication, 2709 nothing needs to be done because REG can certainly go in a general reg. 2710 2711 When -fpic is used, special handling is needed for symbolic references. 2712 See comments by legitimize_pic_address in i386.c for details. */ 2713 2714rtx 2715legitimize_address (x, oldx, mode) 2716 register rtx x; 2717 register rtx oldx ATTRIBUTE_UNUSED; 2718 enum machine_mode mode; 2719{ 2720 int changed = 0; 2721 unsigned log; 2722 2723 if (TARGET_DEBUG_ADDR) 2724 { 2725 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", 2726 GET_MODE_NAME (mode)); 2727 debug_rtx (x); 2728 } 2729 2730 if (flag_pic && SYMBOLIC_CONST (x)) 2731 return legitimize_pic_address (x, 0); 2732 2733 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ 2734 if (GET_CODE (x) == ASHIFT 2735 && GET_CODE (XEXP (x, 1)) == CONST_INT 2736 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4) 2737 { 2738 changed = 1; 2739 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)), 2740 GEN_INT (1 << log)); 2741 } 2742 2743 if (GET_CODE (x) == PLUS) 2744 { 2745 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */ 2746 2747 if (GET_CODE (XEXP (x, 0)) == ASHIFT 2748 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2749 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4) 2750 { 2751 changed = 1; 2752 XEXP (x, 0) = gen_rtx (MULT, Pmode, 2753 force_reg (Pmode, XEXP (XEXP (x, 0), 0)), 2754 GEN_INT (1 << log)); 2755 } 2756 2757 if (GET_CODE (XEXP (x, 1)) == ASHIFT 2758 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 2759 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4) 2760 { 2761 changed = 1; 2762 XEXP (x, 1) = gen_rtx (MULT, Pmode, 2763 force_reg (Pmode, XEXP (XEXP (x, 1), 0)), 2764 GEN_INT (1 << log)); 2765 } 2766 2767 /* Put multiply first if it isn't already. */ 2768 if (GET_CODE (XEXP (x, 1)) == MULT) 2769 { 2770 rtx tmp = XEXP (x, 0); 2771 XEXP (x, 0) = XEXP (x, 1); 2772 XEXP (x, 1) = tmp; 2773 changed = 1; 2774 } 2775 2776 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) 2777 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be 2778 created by virtual register instantiation, register elimination, and 2779 similar optimizations. */ 2780 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS) 2781 { 2782 changed = 1; 2783 x = gen_rtx (PLUS, Pmode, 2784 gen_rtx (PLUS, Pmode, XEXP (x, 0), 2785 XEXP (XEXP (x, 1), 0)), 2786 XEXP (XEXP (x, 1), 1)); 2787 } 2788 2789 /* Canonicalize 2790 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) 2791 into (plus (plus (mult (reg) (const)) (reg)) (const)). */ 2792 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS 2793 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT 2794 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS 2795 && CONSTANT_P (XEXP (x, 1))) 2796 { 2797 rtx constant; 2798 rtx other = NULL_RTX; 2799 2800 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2801 { 2802 constant = XEXP (x, 1); 2803 other = XEXP (XEXP (XEXP (x, 0), 1), 1); 2804 } 2805 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) 2806 { 2807 constant = XEXP (XEXP (XEXP (x, 0), 1), 1); 2808 other = XEXP (x, 1); 2809 } 2810 else 2811 constant = 0; 2812 2813 if (constant) 2814 { 2815 changed = 1; 2816 x = gen_rtx (PLUS, Pmode, 2817 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), 2818 XEXP (XEXP (XEXP (x, 0), 1), 0)), 2819 plus_constant (other, INTVAL (constant))); 2820 } 2821 } 2822 2823 if (changed && legitimate_address_p (mode, x, FALSE)) 2824 return x; 2825 2826 if (GET_CODE (XEXP (x, 0)) == MULT) 2827 { 2828 changed = 1; 2829 XEXP (x, 0) = force_operand (XEXP (x, 0), 0); 2830 } 2831 2832 if (GET_CODE (XEXP (x, 1)) == MULT) 2833 { 2834 changed = 1; 2835 XEXP (x, 1) = force_operand (XEXP (x, 1), 0); 2836 } 2837 2838 if (changed 2839 && GET_CODE (XEXP (x, 1)) == REG 2840 && GET_CODE (XEXP (x, 0)) == REG) 2841 return x; 2842 2843 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1))) 2844 { 2845 changed = 1; 2846 x = legitimize_pic_address (x, 0); 2847 } 2848 2849 if (changed && legitimate_address_p (mode, x, FALSE)) 2850 return x; 2851 2852 if (GET_CODE (XEXP (x, 0)) == REG) 2853 { 2854 register rtx temp = gen_reg_rtx (Pmode); 2855 register rtx val = force_operand (XEXP (x, 1), temp); 2856 if (val != temp) 2857 emit_move_insn (temp, val); 2858 2859 XEXP (x, 1) = temp; 2860 return x; 2861 } 2862 2863 else if (GET_CODE (XEXP (x, 1)) == REG) 2864 { 2865 register rtx temp = gen_reg_rtx (Pmode); 2866 register rtx val = force_operand (XEXP (x, 0), temp); 2867 if (val != temp) 2868 emit_move_insn (temp, val); 2869 2870 XEXP (x, 0) = temp; 2871 return x; 2872 } 2873 } 2874 2875 return x; 2876} 2877 2878/* Print an integer constant expression in assembler syntax. Addition 2879 and subtraction are the only arithmetic that may appear in these 2880 expressions. FILE is the stdio stream to write to, X is the rtx, and 2881 CODE is the operand print code from the output string. */ 2882 2883static void 2884output_pic_addr_const (file, x, code) 2885 FILE *file; 2886 rtx x; 2887 int code; 2888{ 2889 char buf[256]; 2890 2891 switch (GET_CODE (x)) 2892 { 2893 case PC: 2894 if (flag_pic) 2895 putc ('.', file); 2896 else 2897 abort (); 2898 break; 2899 2900 case SYMBOL_REF: 2901 assemble_name (file, XSTR (x, 0)); 2902 if (code == 'P' && ! SYMBOL_REF_FLAG (x)) 2903 fputs ("@PLT", file); 2904 break; 2905 2906 case LABEL_REF: 2907 x = XEXP (x, 0); 2908 /* FALLTHRU */ 2909 case CODE_LABEL: 2910 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); 2911 assemble_name (asm_out_file, buf); 2912 break; 2913 2914 case CONST_INT: 2915 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); 2916 break; 2917 2918 case CONST: 2919 /* This used to output parentheses around the expression, 2920 but that does not work on the 386 (either ATT or BSD assembler). */ 2921 output_pic_addr_const (file, XEXP (x, 0), code); 2922 break; 2923 2924 case CONST_DOUBLE: 2925 if (GET_MODE (x) == VOIDmode) 2926 { 2927 /* We can use %d if the number is <32 bits and positive. */ 2928 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) 2929 fprintf (file, "0x%lx%08lx", 2930 (unsigned long) CONST_DOUBLE_HIGH (x), 2931 (unsigned long) CONST_DOUBLE_LOW (x)); 2932 else 2933 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x)); 2934 } 2935 else 2936 /* We can't handle floating point constants; 2937 PRINT_OPERAND must handle them. */ 2938 output_operand_lossage ("floating constant misused"); 2939 break; 2940 2941 case PLUS: 2942 /* Some assemblers need integer constants to appear first. */ 2943 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 2944 { 2945 output_pic_addr_const (file, XEXP (x, 0), code); 2946 fprintf (file, "+"); 2947 output_pic_addr_const (file, XEXP (x, 1), code); 2948 } 2949 else if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2950 { 2951 output_pic_addr_const (file, XEXP (x, 1), code); 2952 fprintf (file, "+"); 2953 output_pic_addr_const (file, XEXP (x, 0), code); 2954 } 2955 else 2956 abort (); 2957 break; 2958 2959 case MINUS: 2960 output_pic_addr_const (file, XEXP (x, 0), code); 2961 fprintf (file, "-"); 2962 output_pic_addr_const (file, XEXP (x, 1), code); 2963 break; 2964 2965 case UNSPEC: 2966 if (XVECLEN (x, 0) != 1) 2967 abort (); 2968 output_pic_addr_const (file, XVECEXP (x, 0, 0), code); 2969 switch (XINT (x, 1)) 2970 { 2971 case 6: 2972 fputs ("@GOT", file); 2973 break; 2974 case 7: 2975 fputs ("@GOTOFF", file); 2976 break; 2977 case 8: 2978 fputs ("@PLT", file); 2979 break; 2980 default: 2981 output_operand_lossage ("invalid UNSPEC as operand"); 2982 break; 2983 } 2984 break; 2985 2986 default: 2987 output_operand_lossage ("invalid expression as operand"); 2988 } 2989} 2990 2991static void 2992put_jump_code (code, reverse, file) 2993 enum rtx_code code; 2994 int reverse; 2995 FILE *file; 2996{ 2997 int flags = cc_prev_status.flags; 2998 int ieee = (TARGET_IEEE_FP && (flags & CC_IN_80387) 2999 && !(cc_prev_status.flags & CC_FCOMI)); 3000 const char *suffix; 3001 3002 if (flags & CC_Z_IN_NOT_C) 3003 switch (code) 3004 { 3005 case EQ: 3006 fputs (reverse ? "c" : "nc", file); 3007 return; 3008 3009 case NE: 3010 fputs (reverse ? "nc" : "c", file); 3011 return; 3012 3013 default: 3014 abort (); 3015 } 3016 if (ieee) 3017 { 3018 switch (code) 3019 { 3020 case LE: 3021 suffix = reverse ? "ae" : "b"; 3022 break; 3023 case GT: 3024 case LT: 3025 case GE: 3026 suffix = reverse ? "ne" : "e"; 3027 break; 3028 case EQ: 3029 suffix = reverse ? "ne" : "e"; 3030 break; 3031 case NE: 3032 suffix = reverse ? "e" : "ne"; 3033 break; 3034 default: 3035 abort (); 3036 } 3037 fputs (suffix, file); 3038 return; 3039 } 3040 if (flags & CC_TEST_AX) 3041 abort(); 3042 if ((flags & CC_NO_OVERFLOW) && (code == LE || code == GT)) 3043 abort (); 3044 if (reverse) 3045 code = reverse_condition (code); 3046 switch (code) 3047 { 3048 case EQ: 3049 suffix = "e"; 3050 break; 3051 3052 case NE: 3053 suffix = "ne"; 3054 break; 3055 3056 case GT: 3057 suffix = flags & CC_IN_80387 ? "a" : "g"; 3058 break; 3059 3060 case GTU: 3061 suffix = "a"; 3062 break; 3063 3064 case LT: 3065 if (flags & CC_NO_OVERFLOW) 3066 suffix = "s"; 3067 else 3068 suffix = flags & CC_IN_80387 ? "b" : "l"; 3069 break; 3070 3071 case LTU: 3072 suffix = "b"; 3073 break; 3074 3075 case GE: 3076 if (flags & CC_NO_OVERFLOW) 3077 suffix = "ns"; 3078 else 3079 suffix = flags & CC_IN_80387 ? "ae" : "ge"; 3080 break; 3081 3082 case GEU: 3083 suffix = "ae"; 3084 break; 3085 3086 case LE: 3087 suffix = flags & CC_IN_80387 ? "be" : "le"; 3088 break; 3089 3090 case LEU: 3091 suffix = "be"; 3092 break; 3093 3094 default: 3095 abort (); 3096 } 3097 fputs (suffix, file); 3098} 3099 3100/* Append the correct conditional move suffix which corresponds to CODE. */ 3101 3102static void 3103put_condition_code (code, reverse_cc, mode, file) 3104 enum rtx_code code; 3105 int reverse_cc; 3106 enum mode_class mode; 3107 FILE * file; 3108{ 3109 int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387) 3110 && ! (cc_prev_status.flags & CC_FCOMI)); 3111 if (reverse_cc && ! ieee) 3112 code = reverse_condition (code); 3113 3114 if (mode == MODE_INT) 3115 switch (code) 3116 { 3117 case NE: 3118 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 3119 fputs ("b", file); 3120 else 3121 fputs ("ne", file); 3122 return; 3123 3124 case EQ: 3125 if (cc_prev_status.flags & CC_Z_IN_NOT_C) 3126 fputs ("ae", file); 3127 else 3128 fputs ("e", file); 3129 return; 3130 3131 case GE: 3132 if (cc_prev_status.flags & CC_NO_OVERFLOW) 3133 fputs ("ns", file); 3134 else 3135 fputs ("ge", file); 3136 return; 3137 3138 case GT: 3139 fputs ("g", file); 3140 return; 3141 3142 case LE: 3143 fputs ("le", file); 3144 return; 3145 3146 case LT: 3147 if (cc_prev_status.flags & CC_NO_OVERFLOW) 3148 fputs ("s", file); 3149 else 3150 fputs ("l", file); 3151 return; 3152 3153 case GEU: 3154 fputs ("ae", file); 3155 return; 3156 3157 case GTU: 3158 fputs ("a", file); 3159 return; 3160 3161 case LEU: 3162 fputs ("be", file); 3163 return; 3164 3165 case LTU: 3166 fputs ("b", file); 3167 return; 3168 3169 default: 3170 output_operand_lossage ("Invalid %%C operand"); 3171 } 3172 3173 else if (mode == MODE_FLOAT) 3174 switch (code) 3175 { 3176 case NE: 3177 fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file); 3178 return; 3179 case EQ: 3180 fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file); 3181 return; 3182 case GE: 3183 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file); 3184 return; 3185 case GT: 3186 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file); 3187 return; 3188 case LE: 3189 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file); 3190 return; 3191 case LT: 3192 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file); 3193 return; 3194 case GEU: 3195 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file); 3196 return; 3197 case GTU: 3198 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file); 3199 return; 3200 case LEU: 3201 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file); 3202 return; 3203 case LTU: 3204 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file); 3205 return; 3206 default: 3207 output_operand_lossage ("Invalid %%C operand"); 3208 } 3209} 3210 3211/* Meaning of CODE: 3212 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. 3213 C -- print opcode suffix for set/cmov insn. 3214 c -- like C, but print reversed condition 3215 F -- print opcode suffix for fcmov insn. 3216 f -- like F, but print reversed condition 3217 D -- print the opcode suffix for a jump 3218 d -- like D, but print reversed condition 3219 R -- print the prefix for register names. 3220 z -- print the opcode suffix for the size of the current operand. 3221 * -- print a star (in certain assembler syntax) 3222 w -- print the operand as if it's a "word" (HImode) even if it isn't. 3223 J -- print the appropriate jump operand. 3224 s -- print a shift double count, followed by the assemblers argument 3225 delimiter. 3226 b -- print the QImode name of the register for the indicated operand. 3227 %b0 would print %al if operands[0] is reg 0. 3228 w -- likewise, print the HImode name of the register. 3229 k -- likewise, print the SImode name of the register. 3230 h -- print the QImode name for a "high" register, either ah, bh, ch or dh. 3231 y -- print "st(0)" instead of "st" as a register. 3232 P -- print as a PIC constant 3233 _ -- output "_" if YES_UNDERSCORES */ 3234 3235void 3236print_operand (file, x, code) 3237 FILE *file; 3238 rtx x; 3239 int code; 3240{ 3241 if (code) 3242 { 3243 switch (code) 3244 { 3245 case '*': 3246 if (USE_STAR) 3247 putc ('*', file); 3248 return; 3249 3250 case '_': 3251#ifdef YES_UNDERSCORES 3252 putc ('_', file); 3253#endif 3254 return; 3255 3256 case 'L': 3257 PUT_OP_SIZE (code, 'l', file); 3258 return; 3259 3260 case 'W': 3261 PUT_OP_SIZE (code, 'w', file); 3262 return; 3263 3264 case 'B': 3265 PUT_OP_SIZE (code, 'b', file); 3266 return; 3267 3268 case 'Q': 3269 PUT_OP_SIZE (code, 'l', file); 3270 return; 3271 3272 case 'S': 3273 PUT_OP_SIZE (code, 's', file); 3274 return; 3275 3276 case 'T': 3277 PUT_OP_SIZE (code, 't', file); 3278 return; 3279 3280 case 'z': 3281 /* 387 opcodes don't get size suffixes if the operands are 3282 registers. */ 3283 3284 if (STACK_REG_P (x)) 3285 return; 3286 3287 /* this is the size of op from size of operand */ 3288 switch (GET_MODE_SIZE (GET_MODE (x))) 3289 { 3290 case 2: 3291#ifdef HAVE_GAS_FILDS_FISTS 3292 PUT_OP_SIZE ('W', 's', file); 3293#endif 3294 return; 3295 3296 case 4: 3297 if (GET_MODE (x) == SFmode) 3298 { 3299 PUT_OP_SIZE ('S', 's', file); 3300 return; 3301 } 3302 else 3303 PUT_OP_SIZE ('L', 'l', file); 3304 return; 3305 3306 case 12: 3307 PUT_OP_SIZE ('T', 't', file); 3308 return; 3309 3310 case 8: 3311 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) 3312 { 3313#ifdef GAS_MNEMONICS 3314 PUT_OP_SIZE ('Q', 'q', file); 3315 return; 3316#else 3317 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ 3318#endif 3319 } 3320 3321 PUT_OP_SIZE ('Q', 'l', file); 3322 return; 3323 3324 default: 3325 abort (); 3326 } 3327 3328 case 'b': 3329 case 'w': 3330 case 'k': 3331 case 'h': 3332 case 'y': 3333 case 'P': 3334 case 'X': 3335 break; 3336 3337 case 'J': 3338 switch (GET_CODE (x)) 3339 { 3340 /* These conditions are appropriate for testing the result 3341 of an arithmetic operation, not for a compare operation. 3342 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume 3343 CC_Z_IN_NOT_C false and not floating point. */ 3344 case NE: fputs ("jne", file); return; 3345 case EQ: fputs ("je", file); return; 3346 case GE: fputs ("jns", file); return; 3347 case LT: fputs ("js", file); return; 3348 case GEU: fputs ("jmp", file); return; 3349 case GTU: fputs ("jne", file); return; 3350 case LEU: fputs ("je", file); return; 3351 case LTU: fputs ("#branch never", file); return; 3352 3353 /* no matching branches for GT nor LE */ 3354 3355 default: 3356 abort (); 3357 } 3358 3359 case 's': 3360 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT) 3361 { 3362 PRINT_OPERAND (file, x, 0); 3363 fputs (AS2C (,) + 1, file); 3364 } 3365 3366 return; 3367 3368 case 'D': 3369 put_jump_code (GET_CODE (x), 0, file); 3370 return; 3371 3372 case 'd': 3373 put_jump_code (GET_CODE (x), 1, file); 3374 return; 3375 3376 /* This is used by the conditional move instructions. */ 3377 case 'C': 3378 put_condition_code (GET_CODE (x), 0, MODE_INT, file); 3379 return; 3380 3381 /* Like above, but reverse condition */ 3382 case 'c': 3383 put_condition_code (GET_CODE (x), 1, MODE_INT, file); return; 3384 3385 case 'F': 3386 put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file); 3387 return; 3388 3389 /* Like above, but reverse condition */ 3390 case 'f': 3391 put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file); 3392 return; 3393 3394 default: 3395 { 3396 char str[50]; 3397 3398 sprintf (str, "invalid operand code `%c'", code); 3399 output_operand_lossage (str); 3400 } 3401 } 3402 } 3403 3404 if (GET_CODE (x) == REG) 3405 { 3406 PRINT_REG (x, code, file); 3407 } 3408 3409 else if (GET_CODE (x) == MEM) 3410 { 3411 PRINT_PTR (x, file); 3412 if (CONSTANT_ADDRESS_P (XEXP (x, 0))) 3413 { 3414 if (flag_pic) 3415 output_pic_addr_const (file, XEXP (x, 0), code); 3416 else 3417 output_addr_const (file, XEXP (x, 0)); 3418 } 3419 else 3420 output_address (XEXP (x, 0)); 3421 } 3422 3423 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) 3424 { 3425 REAL_VALUE_TYPE r; 3426 long l; 3427 3428 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 3429 REAL_VALUE_TO_TARGET_SINGLE (r, l); 3430 PRINT_IMMED_PREFIX (file); 3431 fprintf (file, "0x%lx", l); 3432 } 3433 3434 /* These float cases don't actually occur as immediate operands. */ 3435 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) 3436 { 3437 REAL_VALUE_TYPE r; 3438 char dstr[30]; 3439 3440 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 3441 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); 3442 fprintf (file, "%s", dstr); 3443 } 3444 3445 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) 3446 { 3447 REAL_VALUE_TYPE r; 3448 char dstr[30]; 3449 3450 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 3451 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); 3452 fprintf (file, "%s", dstr); 3453 } 3454 else 3455 { 3456 if (code != 'P') 3457 { 3458 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) 3459 PRINT_IMMED_PREFIX (file); 3460 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF 3461 || GET_CODE (x) == LABEL_REF) 3462 PRINT_OFFSET_PREFIX (file); 3463 } 3464 if (flag_pic) 3465 output_pic_addr_const (file, x, code); 3466 else 3467 output_addr_const (file, x); 3468 } 3469} 3470 3471/* Print a memory operand whose address is ADDR. */ 3472 3473void 3474print_operand_address (file, addr) 3475 FILE *file; 3476 register rtx addr; 3477{ 3478 register rtx reg1, reg2, breg, ireg; 3479 rtx offset; 3480 3481 switch (GET_CODE (addr)) 3482 { 3483 case REG: 3484 /* ESI addressing makes instruction vector decoded on the K6. We can 3485 avoid this by ESI+0 addressing. */ 3486 if (REGNO_REG_CLASS (REGNO (addr)) == SIREG 3487 && ix86_cpu == PROCESSOR_K6 && !optimize_size) 3488 output_addr_const (file, const0_rtx); 3489 ADDR_BEG (file); 3490 fprintf (file, "%se", RP); 3491 fputs (hi_reg_name[REGNO (addr)], file); 3492 ADDR_END (file); 3493 break; 3494 3495 case PLUS: 3496 reg1 = 0; 3497 reg2 = 0; 3498 ireg = 0; 3499 breg = 0; 3500 offset = 0; 3501 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) 3502 { 3503 offset = XEXP (addr, 0); 3504 addr = XEXP (addr, 1); 3505 } 3506 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) 3507 { 3508 offset = XEXP (addr, 1); 3509 addr = XEXP (addr, 0); 3510 } 3511 3512 if (GET_CODE (addr) != PLUS) 3513 ; 3514 else if (GET_CODE (XEXP (addr, 0)) == MULT) 3515 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1); 3516 else if (GET_CODE (XEXP (addr, 1)) == MULT) 3517 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0); 3518 else if (GET_CODE (XEXP (addr, 0)) == REG) 3519 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1); 3520 else if (GET_CODE (XEXP (addr, 1)) == REG) 3521 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0); 3522 3523 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) 3524 { 3525 if (reg1 == 0) 3526 reg1 = addr; 3527 else 3528 reg2 = addr; 3529 3530 addr = 0; 3531 } 3532 3533 if (offset != 0) 3534 { 3535 if (addr != 0) 3536 abort (); 3537 addr = offset; 3538 } 3539 3540 if ((reg1 && GET_CODE (reg1) == MULT) 3541 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) 3542 { 3543 breg = reg2; 3544 ireg = reg1; 3545 } 3546 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) 3547 { 3548 breg = reg1; 3549 ireg = reg2; 3550 } 3551 3552 if (ireg != 0 || breg != 0) 3553 { 3554 int scale = 1; 3555 3556 if (addr != 0) 3557 { 3558 if (flag_pic) 3559 output_pic_addr_const (file, addr, 0); 3560 else if (GET_CODE (addr) == LABEL_REF) 3561 output_asm_label (addr); 3562 else 3563 output_addr_const (file, addr); 3564 } 3565 3566 if (ireg != 0 && GET_CODE (ireg) == MULT) 3567 { 3568 scale = INTVAL (XEXP (ireg, 1)); 3569 ireg = XEXP (ireg, 0); 3570 } 3571 3572 /* The stack pointer can only appear as a base register, 3573 never an index register, so exchange the regs if it is wrong. */ 3574 3575 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) 3576 { 3577 rtx tmp; 3578 3579 tmp = breg; 3580 breg = ireg; 3581 ireg = tmp; 3582 } 3583 3584 /* output breg+ireg*scale */ 3585 PRINT_B_I_S (breg, ireg, scale, file); 3586 break; 3587 } 3588 3589 case MULT: 3590 { 3591 int scale; 3592 3593 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) 3594 { 3595 scale = INTVAL (XEXP (addr, 0)); 3596 ireg = XEXP (addr, 1); 3597 } 3598 else 3599 { 3600 scale = INTVAL (XEXP (addr, 1)); 3601 ireg = XEXP (addr, 0); 3602 } 3603 3604 /* (reg,reg,) is shorter than (,reg,2). */ 3605 if (scale == 2) 3606 { 3607 PRINT_B_I_S (ireg, ireg, 1, file); 3608 } 3609 else 3610 { 3611 output_addr_const (file, const0_rtx); 3612 PRINT_B_I_S (NULL_RTX, ireg, scale, file); 3613 } 3614 } 3615 break; 3616 3617 default: 3618 if (GET_CODE (addr) == CONST_INT 3619 && INTVAL (addr) < 0x8000 3620 && INTVAL (addr) >= -0x8000) 3621 fprintf (file, "%d", (int) INTVAL (addr)); 3622 else 3623 { 3624 if (flag_pic) 3625 output_pic_addr_const (file, addr, 0); 3626 else 3627 output_addr_const (file, addr); 3628 } 3629 } 3630} 3631 3632/* Set the cc_status for the results of an insn whose pattern is EXP. 3633 On the 80386, we assume that only test and compare insns, as well 3634 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT, 3635 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. 3636 Also, we assume that jumps, moves and sCOND don't affect the condition 3637 codes. All else clobbers the condition codes, by assumption. 3638 3639 We assume that ALL integer add, minus, etc. instructions effect the 3640 condition codes. This MUST be consistent with i386.md. 3641 3642 We don't record any float test or compare - the redundant test & 3643 compare check in final.c does not handle stack-like regs correctly. */ 3644 3645void 3646notice_update_cc (exp) 3647 rtx exp; 3648{ 3649 if (GET_CODE (exp) == SET) 3650 { 3651 /* Jumps do not alter the cc's. */ 3652 if (SET_DEST (exp) == pc_rtx) 3653 return; 3654 3655 /* Moving register or memory into a register: 3656 it doesn't alter the cc's, but it might invalidate 3657 the RTX's which we remember the cc's came from. 3658 (Note that moving a constant 0 or 1 MAY set the cc's). */ 3659 if (REG_P (SET_DEST (exp)) 3660 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM 3661 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<' 3662 || GET_CODE (SET_SRC (exp)) == IF_THEN_ELSE)) 3663 { 3664 if (cc_status.value1 3665 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) 3666 cc_status.value1 = 0; 3667 3668 if (cc_status.value2 3669 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) 3670 cc_status.value2 = 0; 3671 3672 return; 3673 } 3674 3675 /* Moving register into memory doesn't alter the cc's. 3676 It may invalidate the RTX's which we remember the cc's came from. */ 3677 if (GET_CODE (SET_DEST (exp)) == MEM 3678 && (REG_P (SET_SRC (exp)) 3679 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) 3680 { 3681 if (cc_status.value1 3682 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) 3683 cc_status.value1 = 0; 3684 if (cc_status.value2 3685 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) 3686 cc_status.value2 = 0; 3687 3688 return; 3689 } 3690 3691 /* Function calls clobber the cc's. */ 3692 else if (GET_CODE (SET_SRC (exp)) == CALL) 3693 { 3694 CC_STATUS_INIT; 3695 return; 3696 } 3697 3698 /* Tests and compares set the cc's in predictable ways. */ 3699 else if (SET_DEST (exp) == cc0_rtx) 3700 { 3701 CC_STATUS_INIT; 3702 cc_status.value1 = SET_SRC (exp); 3703 return; 3704 } 3705 3706 /* Certain instructions effect the condition codes. */ 3707 else if (GET_MODE (SET_SRC (exp)) == SImode 3708 || GET_MODE (SET_SRC (exp)) == HImode 3709 || GET_MODE (SET_SRC (exp)) == QImode) 3710 switch (GET_CODE (SET_SRC (exp))) 3711 { 3712 case ASHIFTRT: case LSHIFTRT: case ASHIFT: 3713 /* Shifts on the 386 don't set the condition codes if the 3714 shift count is zero. */ 3715 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) 3716 { 3717 CC_STATUS_INIT; 3718 break; 3719 } 3720 3721 /* We assume that the CONST_INT is non-zero (this rtx would 3722 have been deleted if it were zero. */ 3723 3724 case PLUS: case MINUS: case NEG: 3725 case AND: case IOR: case XOR: 3726 cc_status.flags = CC_NO_OVERFLOW; 3727 cc_status.value1 = SET_SRC (exp); 3728 cc_status.value2 = SET_DEST (exp); 3729 break; 3730 3731 /* This is the bsf pattern used by ffs. */ 3732 case UNSPEC: 3733 if (XINT (SET_SRC (exp), 1) == 5) 3734 { 3735 /* Only the Z flag is defined after bsf. */ 3736 cc_status.flags 3737 = CC_NOT_POSITIVE | CC_NOT_NEGATIVE | CC_NO_OVERFLOW; 3738 cc_status.value1 = XVECEXP (SET_SRC (exp), 0, 0); 3739 cc_status.value2 = 0; 3740 break; 3741 } 3742 /* FALLTHRU */ 3743 3744 default: 3745 CC_STATUS_INIT; 3746 } 3747 else 3748 { 3749 CC_STATUS_INIT; 3750 } 3751 } 3752 else if (GET_CODE (exp) == PARALLEL 3753 && GET_CODE (XVECEXP (exp, 0, 0)) == SET) 3754 { 3755 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) 3756 return; 3757 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) 3758 3759 { 3760 CC_STATUS_INIT; 3761 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) 3762 { 3763 cc_status.flags |= CC_IN_80387; 3764 if (TARGET_CMOVE && stack_regs_mentioned_p 3765 (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1))) 3766 cc_status.flags |= CC_FCOMI; 3767 } 3768 else 3769 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); 3770 return; 3771 } 3772 3773 CC_STATUS_INIT; 3774 } 3775 else 3776 { 3777 CC_STATUS_INIT; 3778 } 3779} 3780 3781/* Split one or more DImode RTL references into pairs of SImode 3782 references. The RTL can be REG, offsettable MEM, integer constant, or 3783 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to 3784 split and "num" is its length. lo_half and hi_half are output arrays 3785 that parallel "operands". */ 3786 3787void 3788split_di (operands, num, lo_half, hi_half) 3789 rtx operands[]; 3790 int num; 3791 rtx lo_half[], hi_half[]; 3792{ 3793 while (num--) 3794 { 3795 rtx op = operands[num]; 3796 if (! reload_completed) 3797 { 3798 lo_half[num] = gen_lowpart (SImode, op); 3799 hi_half[num] = gen_highpart (SImode, op); 3800 } 3801 else if (GET_CODE (op) == REG) 3802 { 3803 lo_half[num] = gen_rtx_REG (SImode, REGNO (op)); 3804 hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1); 3805 } 3806 else if (CONSTANT_P (op)) 3807 split_double (op, &lo_half[num], &hi_half[num]); 3808 else if (offsettable_memref_p (op)) 3809 { 3810 rtx lo_addr = XEXP (op, 0); 3811 rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0); 3812 lo_half[num] = change_address (op, SImode, lo_addr); 3813 hi_half[num] = change_address (op, SImode, hi_addr); 3814 } 3815 else 3816 abort(); 3817 } 3818} 3819 3820/* Return 1 if this is a valid binary operation on a 387. 3821 OP is the expression matched, and MODE is its mode. */ 3822 3823int 3824binary_387_op (op, mode) 3825 register rtx op; 3826 enum machine_mode mode; 3827{ 3828 if (mode != VOIDmode && mode != GET_MODE (op)) 3829 return 0; 3830 3831 switch (GET_CODE (op)) 3832 { 3833 case PLUS: 3834 case MINUS: 3835 case MULT: 3836 case DIV: 3837 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; 3838 3839 default: 3840 return 0; 3841 } 3842} 3843 3844/* Return 1 if this is a valid shift or rotate operation on a 386. 3845 OP is the expression matched, and MODE is its mode. */ 3846 3847int 3848shift_op (op, mode) 3849 register rtx op; 3850 enum machine_mode mode; 3851{ 3852 rtx operand = XEXP (op, 0); 3853 3854 if (mode != VOIDmode && mode != GET_MODE (op)) 3855 return 0; 3856 3857 if (GET_MODE (operand) != GET_MODE (op) 3858 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) 3859 return 0; 3860 3861 return (GET_CODE (op) == ASHIFT 3862 || GET_CODE (op) == ASHIFTRT 3863 || GET_CODE (op) == LSHIFTRT 3864 || GET_CODE (op) == ROTATE 3865 || GET_CODE (op) == ROTATERT); 3866} 3867 3868/* Return 1 if OP is COMPARE rtx with mode VOIDmode. 3869 MODE is not used. */ 3870 3871int 3872VOIDmode_compare_op (op, mode) 3873 register rtx op; 3874 enum machine_mode mode ATTRIBUTE_UNUSED; 3875{ 3876 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; 3877} 3878 3879/* Output code to perform a 387 binary operation in INSN, one of PLUS, 3880 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] 3881 is the expression of the binary operation. The output may either be 3882 emitted here, or returned to the caller, like all output_* functions. 3883 3884 There is no guarantee that the operands are the same mode, as they 3885 might be within FLOAT or FLOAT_EXTEND expressions. */ 3886 3887char * 3888output_387_binary_op (insn, operands) 3889 rtx insn; 3890 rtx *operands; 3891{ 3892 rtx temp; 3893 char *base_op; 3894 static char buf[100]; 3895 3896 switch (GET_CODE (operands[3])) 3897 { 3898 case PLUS: 3899 base_op = "fadd"; 3900 break; 3901 3902 case MINUS: 3903 base_op = "fsub"; 3904 break; 3905 3906 case MULT: 3907 base_op = "fmul"; 3908 break; 3909 3910 case DIV: 3911 base_op = "fdiv"; 3912 break; 3913 3914 default: 3915 abort (); 3916 } 3917 3918 strcpy (buf, base_op); 3919 3920 switch (GET_CODE (operands[3])) 3921 { 3922 case MULT: 3923 case PLUS: 3924 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) 3925 { 3926 temp = operands[2]; 3927 operands[2] = operands[1]; 3928 operands[1] = temp; 3929 } 3930 3931 if (GET_CODE (operands[2]) == MEM) 3932 return strcat (buf, AS1 (%z2,%2)); 3933 3934 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) 3935 abort (); 3936 3937 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) 3938 { 3939 if (STACK_TOP_P (operands[0])) 3940 return strcat (buf, AS2 (p,%0,%2)); 3941 else 3942 return strcat (buf, AS2 (p,%2,%0)); 3943 } 3944 3945 if (STACK_TOP_P (operands[0])) 3946 return strcat (buf, AS2C (%y2,%0)); 3947 else 3948 return strcat (buf, AS2C (%2,%0)); 3949 3950 case MINUS: 3951 case DIV: 3952 if (GET_CODE (operands[1]) == MEM) 3953 return strcat (buf, AS1 (r%z1,%1)); 3954 3955 if (GET_CODE (operands[2]) == MEM) 3956 return strcat (buf, AS1 (%z2,%2)); 3957 3958 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) 3959 abort (); 3960 3961 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) 3962 { 3963 if (STACK_TOP_P (operands[0])) 3964 return strcat (buf, AS2 (p,%0,%2)); 3965 else 3966 return strcat (buf, AS2 (rp,%2,%0)); 3967 } 3968 3969 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 3970 { 3971 if (STACK_TOP_P (operands[0])) 3972 return strcat (buf, AS2 (rp,%0,%1)); 3973 else 3974 return strcat (buf, AS2 (p,%1,%0)); 3975 } 3976 3977 if (STACK_TOP_P (operands[0])) 3978 { 3979 if (STACK_TOP_P (operands[1])) 3980 return strcat (buf, AS2C (%y2,%0)); 3981 else 3982 return strcat (buf, AS2 (r,%y1,%0)); 3983 } 3984 else if (STACK_TOP_P (operands[1])) 3985 return strcat (buf, AS2C (%1,%0)); 3986 else 3987 return strcat (buf, AS2 (r,%2,%0)); 3988 3989 default: 3990 abort (); 3991 } 3992} 3993 3994/* Output code for INSN to convert a float to a signed int. OPERANDS 3995 are the insn operands. The input may be SFmode, DFmode, or XFmode 3996 and the output operand may be SImode or DImode. As a special case, 3997 make sure that the 387 stack top dies if the output mode is DImode, 3998 because the hardware requires this. */ 3999 4000char * 4001output_fix_trunc (insn, operands) 4002 rtx insn; 4003 rtx *operands; 4004{ 4005 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 4006 rtx xops[2]; 4007 4008 if (! STACK_TOP_P (operands[1])) 4009 abort (); 4010 4011 if (GET_MODE (operands[0]) == DImode && ! stack_top_dies) 4012 abort (); 4013 4014 xops[0] = GEN_INT (0x0c00); 4015 xops[1] = operands[5]; 4016 4017 output_asm_insn (AS1 (fnstc%W2,%2), operands); 4018 output_asm_insn (AS2 (mov%W5,%2,%w5), operands); 4019 output_asm_insn (AS2 (or%W1,%0,%w1), xops); 4020 output_asm_insn (AS2 (mov%W3,%w5,%3), operands); 4021 output_asm_insn (AS1 (fldc%W3,%3), operands); 4022 4023 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[4] : operands[0]; 4024 4025 if (stack_top_dies) 4026 output_asm_insn (AS1 (fistp%z0,%y0), xops); 4027 else 4028 output_asm_insn (AS1 (fist%z0,%y0), xops); 4029 4030 if (NON_STACK_REG_P (operands[0])) 4031 { 4032 if (GET_MODE (operands[0]) == SImode) 4033 output_asm_insn (AS2 (mov%L0,%4,%0), operands); 4034 else 4035 { 4036 xops[0] = operands[0]; 4037 xops[1] = operands[4]; 4038 output_asm_insn (output_move_double (xops), xops); 4039 } 4040 } 4041 4042 return AS1 (fldc%W2,%2); 4043} 4044 4045/* Output code for INSN to extend a float. OPERANDS are the insn 4046 operands. The output may be DFmode or XFmode and the input operand 4047 may be SFmode or DFmode. Operands 2 and 3 are scratch memory and 4048 are only necessary if operands 0 or 1 are non-stack registers. */ 4049 4050void 4051output_float_extend (insn, operands) 4052 rtx insn; 4053 rtx *operands; 4054{ 4055 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 4056 rtx xops[2]; 4057 4058 if (! STACK_TOP_P (operands[0]) && ! STACK_TOP_P (operands[1])) 4059 abort (); 4060 4061 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]) && stack_top_dies) 4062 return; 4063 4064 if (STACK_TOP_P (operands[0]) ) 4065 { 4066 if (NON_STACK_REG_P (operands[1])) 4067 { 4068 if (GET_MODE (operands[1]) == SFmode) 4069 output_asm_insn (AS2 (mov%L0,%1,%2), operands); 4070 else 4071 { 4072 xops[0] = operands[2]; 4073 xops[1] = operands[1]; 4074 output_asm_insn (output_move_double (xops), xops); 4075 } 4076 } 4077 4078 xops[0] = NON_STACK_REG_P (operands[1]) ? operands[2] : operands[1]; 4079 4080 output_asm_insn (AS1 (fld%z0,%y0), xops); 4081 } 4082 else 4083 { 4084 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[3] : operands[0]; 4085 4086 if (stack_top_dies 4087 || (GET_CODE (xops[0]) == MEM && GET_MODE (xops[0]) == XFmode)) 4088 { 4089 output_asm_insn (AS1 (fstp%z0,%y0), xops); 4090 if (! stack_top_dies) 4091 output_asm_insn (AS1 (fld%z0,%y0), xops); 4092 } 4093 else 4094 output_asm_insn (AS1 (fst%z0,%y0), xops); 4095 4096 if (NON_STACK_REG_P (operands[0])) 4097 { 4098 xops[0] = operands[0]; 4099 xops[1] = operands[3]; 4100 output_asm_insn (output_move_double (xops), xops); 4101 } 4102 } 4103} 4104 4105/* Output code for INSN to compare OPERANDS. The two operands might 4106 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND 4107 expression. If the compare is in mode CCFPEQmode, use an opcode that 4108 will not fault if a qNaN is present. */ 4109 4110char * 4111output_float_compare (insn, operands) 4112 rtx insn; 4113 rtx *operands; 4114{ 4115 int stack_top_dies; 4116 rtx body = XVECEXP (PATTERN (insn), 0, 0); 4117 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; 4118 rtx tmp; 4119 int cc0_set = 1; 4120 int i; 4121 4122 if (TARGET_CMOVE && STACK_REG_P (operands[1]) 4123 && STACK_REG_P (operands[0])) 4124 { 4125 cc_status.flags |= CC_FCOMI; 4126 cc_prev_status.flags &= ~CC_TEST_AX; 4127 } 4128 4129 if (! STACK_TOP_P (operands[0])) 4130 { 4131 tmp = operands[0]; 4132 operands[0] = operands[1]; 4133 operands[1] = tmp; 4134 cc_status.flags |= CC_REVERSED; 4135 } 4136 4137 if (! STACK_TOP_P (operands[0])) 4138 abort (); 4139 4140 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; 4141 4142 if (STACK_REG_P (operands[1]) 4143 && stack_top_dies 4144 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 4145 && REGNO (operands[1]) == FIRST_STACK_REG + 1) 4146 { 4147 /* If both the top of the 387 stack dies, and the other operand 4148 is also a stack register that dies, then this must be a 4149 `fcompp' float compare */ 4150 4151 if (unordered_compare) 4152 { 4153 if (cc_status.flags & CC_FCOMI) 4154 { 4155 output_asm_insn (AS2 (fucomip,%y1,%0), operands); 4156 output_asm_insn (AS1 (fstp, %y0), operands); 4157 if (!TARGET_IEEE_FP) 4158 cc0_set = 0; 4159 } 4160 else 4161 output_asm_insn ("fucompp", operands); 4162 } 4163 else 4164 { 4165 if (cc_status.flags & CC_FCOMI) 4166 { 4167 output_asm_insn (AS2 (fcomip, %y1,%0), operands); 4168 output_asm_insn (AS1 (fstp, %y0), operands); 4169 if (!TARGET_IEEE_FP) 4170 cc0_set = 0; 4171 } 4172 else 4173 output_asm_insn ("fcompp", operands); 4174 } 4175 } 4176 else 4177 { 4178 static char buf[100]; 4179 4180 /* Decide if this is a float compare or an unordered float compare. */ 4181 4182 if (unordered_compare) 4183 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom"); 4184 else 4185 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom"); 4186 4187 /* Modify the opcode if the 387 stack is to be popped. */ 4188 4189 if (stack_top_dies) 4190 strcat (buf, "p"); 4191 4192 if (cc_status.flags & CC_FCOMI) 4193 { 4194 output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands); 4195 if (!TARGET_IEEE_FP) 4196 cc0_set = 0; 4197 } 4198 else 4199 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); 4200 } 4201 4202 /* Now retrieve the condition code. */ 4203 if (cc0_set) 4204 { 4205 char *r = output_fp_cc0_set (insn); 4206 if (r[0]) output_asm_insn (r, operands); 4207 } 4208 4209 4210 /* We emit fstp instruction after integer comparsions to improve 4211 scheduling. */ 4212 for (i = 0; i < 2 ; i++) 4213 { 4214 if (STACK_REG_P (operands[i]) 4215 && find_regno_note (insn, REG_DEAD, REGNO (operands[i])) 4216 && REGNO (operands[i]) != FIRST_STACK_REG 4217 && (!stack_top_dies || REGNO (operands[i]) != FIRST_STACK_REG + 1)) 4218 { 4219 rtx xexp[2]; 4220 xexp[0] = gen_rtx_REG (DFmode, 4221 REGNO (operands[i]) - (stack_top_dies != 0)); 4222 output_asm_insn (AS1 (fstp, %y0), xexp); 4223 } 4224 } 4225 4226 return ""; 4227 4228 4229} 4230 4231/* Output opcodes to transfer the results of FP compare or test INSN 4232 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the 4233 result of the compare or test is unordered, no comparison operator 4234 succeeds except NE. Return an output template, if any. */ 4235 4236char * 4237output_fp_cc0_set (insn) 4238 rtx insn; 4239{ 4240 rtx xops[3]; 4241 rtx next; 4242 enum rtx_code code; 4243 4244 if (!(cc_status.flags & CC_FCOMI)) 4245 { 4246 xops[0] = gen_rtx_REG (HImode, 0); 4247 output_asm_insn (AS1 (fnsts%W0,%0), xops); 4248 } 4249 4250 if (! TARGET_IEEE_FP) 4251 { 4252 if (!(cc_status.flags & CC_REVERSED)) 4253 { 4254 next = next_cc0_user (insn); 4255 4256 if (GET_CODE (PATTERN (next)) == SET 4257 && SET_DEST (PATTERN (next)) == pc_rtx 4258 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) 4259 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); 4260 else if (GET_CODE (PATTERN (next)) == SET) 4261 code = GET_CODE (SET_SRC (PATTERN (next))); 4262 else 4263 return "sahf"; 4264 4265 if (code == GT || code == LT || code == EQ || code == NE 4266 || code == LE || code == GE) 4267 { 4268 /* We will test eax directly. */ 4269 cc_status.flags |= CC_TEST_AX; 4270 return ""; 4271 } 4272 } 4273 4274 return "sahf"; 4275 } 4276 4277 next = next_cc0_user (insn); 4278 if (next == NULL_RTX) 4279 abort (); 4280 4281 if (GET_CODE (PATTERN (next)) == SET 4282 && SET_DEST (PATTERN (next)) == pc_rtx 4283 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) 4284 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); 4285 else if (GET_CODE (PATTERN (next)) == SET) 4286 { 4287 if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) 4288 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); 4289 else 4290 code = GET_CODE (SET_SRC (PATTERN (next))); 4291 } 4292 4293 else if (GET_CODE (PATTERN (next)) == PARALLEL 4294 && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET) 4295 { 4296 if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE) 4297 code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0)); 4298 else 4299 code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))); 4300 } 4301 else 4302 abort (); 4303 4304 if (cc_status.flags & CC_FCOMI) 4305 { 4306 /* It is very tricky. We have to do it right. */ 4307 4308 xops [0] = gen_rtx_REG (QImode, 0); 4309 4310 switch (code) 4311 { 4312 case GT: 4313 case GE: 4314 break; 4315 4316 case LT: 4317 output_asm_insn (AS1 (setb,%b0), xops); 4318 output_asm_insn (AS1 (setp,%h0), xops); 4319 output_asm_insn (AS2 (cmp%B0,%b0,%h0), xops); 4320 break; 4321 4322 case LE: 4323 output_asm_insn (AS1 (setbe,%b0), xops); 4324 output_asm_insn (AS1 (setnp,%h0), xops); 4325 output_asm_insn (AS2 (xor%B0,%b0,%h0), xops); 4326 break; 4327 4328 case EQ: 4329 case NE: 4330 output_asm_insn (AS1 (setne,%b0), xops); 4331 output_asm_insn (AS1 (setp,%h0), xops); 4332 output_asm_insn (AS2 (or%B0,%b0,%h0), xops); 4333 break; 4334 4335 case GTU: 4336 case LTU: 4337 case GEU: 4338 case LEU: 4339 default: 4340 abort (); 4341 } 4342 } 4343 else 4344 { 4345 xops[0] = gen_rtx_REG (QImode, 0); 4346 4347 switch (code) 4348 { 4349 case GT: 4350 xops[1] = GEN_INT (0x45); 4351 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4352 /* je label */ 4353 break; 4354 4355 case LT: 4356 xops[1] = GEN_INT (0x45); 4357 xops[2] = GEN_INT (0x01); 4358 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4359 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); 4360 /* je label */ 4361 break; 4362 4363 case GE: 4364 xops[1] = GEN_INT (0x05); 4365 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4366 /* je label */ 4367 break; 4368 4369 case LE: 4370 xops[1] = GEN_INT (0x45); 4371 xops[2] = GEN_INT (0x40); 4372 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4373 output_asm_insn (AS1 (dec%B0,%h0), xops); 4374 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); 4375 /* jb label */ 4376 break; 4377 4378 case EQ: 4379 xops[1] = GEN_INT (0x45); 4380 xops[2] = GEN_INT (0x40); 4381 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4382 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); 4383 /* je label */ 4384 break; 4385 4386 case NE: 4387 xops[1] = GEN_INT (0x44); 4388 xops[2] = GEN_INT (0x40); 4389 output_asm_insn (AS2 (and%B0,%1,%h0), xops); 4390 output_asm_insn (AS2 (xor%B0,%2,%h0), xops); 4391 /* jne label */ 4392 break; 4393 4394 case GTU: 4395 case LTU: 4396 case GEU: 4397 case LEU: 4398 default: 4399 abort (); 4400 } 4401 } 4402 4403 return ""; 4404} 4405 4406#define MAX_386_STACK_LOCALS 2 4407 4408static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; 4409 4410/* Define the structure for the machine field in struct function. */ 4411struct machine_function 4412{ 4413 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; 4414 rtx pic_label_rtx; 4415 char pic_label_name[256]; 4416}; 4417 4418/* Functions to save and restore i386_stack_locals. 4419 These will be called, via pointer variables, 4420 from push_function_context and pop_function_context. */ 4421 4422void 4423save_386_machine_status (p) 4424 struct function *p; 4425{ 4426 p->machine 4427 = (struct machine_function *) xmalloc (sizeof (struct machine_function)); 4428 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals, 4429 sizeof i386_stack_locals); 4430 p->machine->pic_label_rtx = pic_label_rtx; 4431 bcopy (pic_label_name, p->machine->pic_label_name, 256); 4432} 4433 4434void 4435restore_386_machine_status (p) 4436 struct function *p; 4437{ 4438 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals, 4439 sizeof i386_stack_locals); 4440 pic_label_rtx = p->machine->pic_label_rtx; 4441 bcopy (p->machine->pic_label_name, pic_label_name, 256); 4442 free (p->machine); 4443 p->machine = NULL; 4444} 4445 4446/* Clear stack slot assignments remembered from previous functions. 4447 This is called from INIT_EXPANDERS once before RTL is emitted for each 4448 function. */ 4449 4450void 4451clear_386_stack_locals () 4452{ 4453 enum machine_mode mode; 4454 int n; 4455 4456 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; 4457 mode = (enum machine_mode) ((int) mode + 1)) 4458 for (n = 0; n < MAX_386_STACK_LOCALS; n++) 4459 i386_stack_locals[(int) mode][n] = NULL_RTX; 4460 4461 pic_label_rtx = NULL_RTX; 4462 bzero (pic_label_name, 256); 4463 /* Arrange to save and restore i386_stack_locals around nested functions. */ 4464 save_machine_status = save_386_machine_status; 4465 restore_machine_status = restore_386_machine_status; 4466} 4467 4468/* Return a MEM corresponding to a stack slot with mode MODE. 4469 Allocate a new slot if necessary. 4470 4471 The RTL for a function can have several slots available: N is 4472 which slot to use. */ 4473 4474rtx 4475assign_386_stack_local (mode, n) 4476 enum machine_mode mode; 4477 int n; 4478{ 4479 if (n < 0 || n >= MAX_386_STACK_LOCALS) 4480 abort (); 4481 4482 if (i386_stack_locals[(int) mode][n] == NULL_RTX) 4483 i386_stack_locals[(int) mode][n] 4484 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); 4485 4486 return i386_stack_locals[(int) mode][n]; 4487} 4488 4489int is_mul(op,mode) 4490 register rtx op; 4491 enum machine_mode mode ATTRIBUTE_UNUSED; 4492{ 4493 return (GET_CODE (op) == MULT); 4494} 4495 4496int is_div(op,mode) 4497 register rtx op; 4498 enum machine_mode mode ATTRIBUTE_UNUSED; 4499{ 4500 return (GET_CODE (op) == DIV); 4501} 4502 4503#ifdef NOTYET 4504/* Create a new copy of an rtx. 4505 Recursively copies the operands of the rtx, 4506 except for those few rtx codes that are sharable. 4507 Doesn't share CONST */ 4508 4509rtx 4510copy_all_rtx (orig) 4511 register rtx orig; 4512{ 4513 register rtx copy; 4514 register int i, j; 4515 register RTX_CODE code; 4516 register char *format_ptr; 4517 4518 code = GET_CODE (orig); 4519 4520 switch (code) 4521 { 4522 case REG: 4523 case QUEUED: 4524 case CONST_INT: 4525 case CONST_DOUBLE: 4526 case SYMBOL_REF: 4527 case CODE_LABEL: 4528 case PC: 4529 case CC0: 4530 case SCRATCH: 4531 /* SCRATCH must be shared because they represent distinct values. */ 4532 return orig; 4533 4534#if 0 4535 case CONST: 4536 /* CONST can be shared if it contains a SYMBOL_REF. If it contains 4537 a LABEL_REF, it isn't sharable. */ 4538 if (GET_CODE (XEXP (orig, 0)) == PLUS 4539 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF 4540 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) 4541 return orig; 4542 break; 4543#endif 4544 /* A MEM with a constant address is not sharable. The problem is that 4545 the constant address may need to be reloaded. If the mem is shared, 4546 then reloading one copy of this mem will cause all copies to appear 4547 to have been reloaded. */ 4548 } 4549 4550 copy = rtx_alloc (code); 4551 PUT_MODE (copy, GET_MODE (orig)); 4552 copy->in_struct = orig->in_struct; 4553 copy->volatil = orig->volatil; 4554 copy->unchanging = orig->unchanging; 4555 copy->integrated = orig->integrated; 4556 /* intel1 */ 4557 copy->is_spill_rtx = orig->is_spill_rtx; 4558 4559 format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); 4560 4561 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) 4562 { 4563 switch (*format_ptr++) 4564 { 4565 case 'e': 4566 XEXP (copy, i) = XEXP (orig, i); 4567 if (XEXP (orig, i) != NULL) 4568 XEXP (copy, i) = copy_rtx (XEXP (orig, i)); 4569 break; 4570 4571 case '0': 4572 case 'u': 4573 XEXP (copy, i) = XEXP (orig, i); 4574 break; 4575 4576 case 'E': 4577 case 'V': 4578 XVEC (copy, i) = XVEC (orig, i); 4579 if (XVEC (orig, i) != NULL) 4580 { 4581 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); 4582 for (j = 0; j < XVECLEN (copy, i); j++) 4583 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j)); 4584 } 4585 break; 4586 4587 case 'w': 4588 XWINT (copy, i) = XWINT (orig, i); 4589 break; 4590 4591 case 'i': 4592 XINT (copy, i) = XINT (orig, i); 4593 break; 4594 4595 case 's': 4596 case 'S': 4597 XSTR (copy, i) = XSTR (orig, i); 4598 break; 4599 4600 default: 4601 abort (); 4602 } 4603 } 4604 return copy; 4605} 4606 4607 4608/* Try to rewrite a memory address to make it valid */ 4609 4610void 4611rewrite_address (mem_rtx) 4612 rtx mem_rtx; 4613{ 4614 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx; 4615 int scale = 1; 4616 int offset_adjust = 0; 4617 int was_only_offset = 0; 4618 rtx mem_addr = XEXP (mem_rtx, 0); 4619 char *storage = oballoc (0); 4620 int in_struct = 0; 4621 int is_spill_rtx = 0; 4622 4623 in_struct = MEM_IN_STRUCT_P (mem_rtx); 4624 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx); 4625 4626 if (GET_CODE (mem_addr) == PLUS 4627 && GET_CODE (XEXP (mem_addr, 1)) == PLUS 4628 && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG) 4629 { 4630 /* This part is utilized by the combiner. */ 4631 ret_rtx 4632 = gen_rtx (PLUS, GET_MODE (mem_addr), 4633 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)), 4634 XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)), 4635 XEXP (XEXP (mem_addr, 1), 1)); 4636 4637 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx)) 4638 { 4639 XEXP (mem_rtx, 0) = ret_rtx; 4640 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx; 4641 return; 4642 } 4643 4644 obfree (storage); 4645 } 4646 4647 /* This part is utilized by loop.c. 4648 If the address contains PLUS (reg,const) and this pattern is invalid 4649 in this case - try to rewrite the address to make it valid. */ 4650 storage = oballoc (0); 4651 index_rtx = base_rtx = offset_rtx = NULL; 4652 4653 /* Find the base index and offset elements of the memory address. */ 4654 if (GET_CODE (mem_addr) == PLUS) 4655 { 4656 if (GET_CODE (XEXP (mem_addr, 0)) == REG) 4657 { 4658 if (GET_CODE (XEXP (mem_addr, 1)) == REG) 4659 base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0); 4660 else 4661 base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1); 4662 } 4663 4664 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT) 4665 { 4666 index_rtx = XEXP (mem_addr, 0); 4667 if (GET_CODE (XEXP (mem_addr, 1)) == REG) 4668 base_rtx = XEXP (mem_addr, 1); 4669 else 4670 offset_rtx = XEXP (mem_addr, 1); 4671 } 4672 4673 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS) 4674 { 4675 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS 4676 && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT 4677 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0)) 4678 == REG) 4679 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1)) 4680 == CONST_INT) 4681 && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) 4682 == CONST_INT) 4683 && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG 4684 && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF) 4685 { 4686 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0); 4687 offset_rtx = XEXP (mem_addr, 1); 4688 base_rtx = XEXP (XEXP (mem_addr, 0), 1); 4689 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)); 4690 } 4691 else 4692 { 4693 offset_rtx = XEXP (mem_addr, 1); 4694 index_rtx = XEXP (XEXP (mem_addr, 0), 0); 4695 base_rtx = XEXP (XEXP (mem_addr, 0), 1); 4696 } 4697 } 4698 4699 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT) 4700 { 4701 was_only_offset = 1; 4702 index_rtx = NULL; 4703 base_rtx = NULL; 4704 offset_rtx = XEXP (mem_addr, 1); 4705 offset_adjust = INTVAL (XEXP (mem_addr, 0)); 4706 if (offset_adjust == 0) 4707 { 4708 XEXP (mem_rtx, 0) = offset_rtx; 4709 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; 4710 return; 4711 } 4712 } 4713 else 4714 { 4715 obfree (storage); 4716 return; 4717 } 4718 } 4719 else if (GET_CODE (mem_addr) == MULT) 4720 index_rtx = mem_addr; 4721 else 4722 { 4723 obfree (storage); 4724 return; 4725 } 4726 4727 if (index_rtx != 0 && GET_CODE (index_rtx) == MULT) 4728 { 4729 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT) 4730 { 4731 obfree (storage); 4732 return; 4733 } 4734 4735 scale_rtx = XEXP (index_rtx, 1); 4736 scale = INTVAL (scale_rtx); 4737 index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); 4738 } 4739 4740 /* Now find which of the elements are invalid and try to fix them. */ 4741 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL) 4742 { 4743 offset_adjust = INTVAL (index_rtx) * scale; 4744 4745 if (offset_rtx != 0 && CONSTANT_P (offset_rtx)) 4746 offset_rtx = plus_constant (offset_rtx, offset_adjust); 4747 else if (offset_rtx == 0) 4748 offset_rtx = const0_rtx; 4749 4750 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; 4751 XEXP (mem_rtx, 0) = offset_rtx; 4752 return; 4753 } 4754 4755 if (base_rtx && GET_CODE (base_rtx) == PLUS 4756 && GET_CODE (XEXP (base_rtx, 0)) == REG 4757 && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT) 4758 { 4759 offset_adjust += INTVAL (XEXP (base_rtx, 1)); 4760 base_rtx = copy_all_rtx (XEXP (base_rtx, 0)); 4761 } 4762 4763 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT) 4764 { 4765 offset_adjust += INTVAL (base_rtx); 4766 base_rtx = NULL; 4767 } 4768 4769 if (index_rtx && GET_CODE (index_rtx) == PLUS 4770 && GET_CODE (XEXP (index_rtx, 0)) == REG 4771 && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT) 4772 { 4773 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale; 4774 index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); 4775 } 4776 4777 if (index_rtx) 4778 { 4779 if (! LEGITIMATE_INDEX_P (index_rtx) 4780 && ! (index_rtx == stack_pointer_rtx && scale == 1 4781 && base_rtx == NULL)) 4782 { 4783 obfree (storage); 4784 return; 4785 } 4786 } 4787 4788 if (base_rtx) 4789 { 4790 if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG) 4791 { 4792 obfree (storage); 4793 return; 4794 } 4795 } 4796 4797 if (offset_adjust != 0) 4798 { 4799 if (offset_rtx != 0 && CONSTANT_P (offset_rtx)) 4800 offset_rtx = plus_constant (offset_rtx, offset_adjust); 4801 else 4802 offset_rtx = const0_rtx; 4803 4804 if (index_rtx) 4805 { 4806 if (base_rtx) 4807 { 4808 if (scale != 1) 4809 { 4810 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), 4811 gen_rtx (MULT, GET_MODE (index_rtx), 4812 index_rtx, scale_rtx), 4813 base_rtx); 4814 4815 if (GET_CODE (offset_rtx) != CONST_INT 4816 || INTVAL (offset_rtx) != 0) 4817 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx), 4818 ret_rtx, offset_rtx); 4819 } 4820 else 4821 { 4822 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), 4823 index_rtx, base_rtx); 4824 4825 if (GET_CODE (offset_rtx) != CONST_INT 4826 || INTVAL (offset_rtx) != 0) 4827 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx), 4828 ret_rtx, offset_rtx); 4829 } 4830 } 4831 else 4832 { 4833 if (scale != 1) 4834 { 4835 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx), 4836 index_rtx, scale_rtx); 4837 4838 if (GET_CODE (offset_rtx) != CONST_INT 4839 || INTVAL (offset_rtx) != 0) 4840 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx), 4841 ret_rtx, offset_rtx); 4842 } 4843 else 4844 { 4845 if (GET_CODE (offset_rtx) == CONST_INT 4846 && INTVAL (offset_rtx) == 0) 4847 ret_rtx = index_rtx; 4848 else 4849 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), 4850 index_rtx, offset_rtx); 4851 } 4852 } 4853 } 4854 else 4855 { 4856 if (base_rtx) 4857 { 4858 if (GET_CODE (offset_rtx) == CONST_INT 4859 && INTVAL (offset_rtx) == 0) 4860 ret_rtx = base_rtx; 4861 else 4862 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx, 4863 offset_rtx); 4864 } 4865 else if (was_only_offset) 4866 ret_rtx = offset_rtx; 4867 else 4868 { 4869 obfree (storage); 4870 return; 4871 } 4872 } 4873 4874 XEXP (mem_rtx, 0) = ret_rtx; 4875 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; 4876 return; 4877 } 4878 else 4879 { 4880 obfree (storage); 4881 return; 4882 } 4883} 4884#endif /* NOTYET */ 4885 4886/* Return 1 if the first insn to set cc before INSN also sets the register 4887 REG_RTX; otherwise return 0. */ 4888int 4889last_to_set_cc (reg_rtx, insn) 4890 rtx reg_rtx, insn; 4891{ 4892 rtx prev_insn = PREV_INSN (insn); 4893 4894 while (prev_insn) 4895 { 4896 if (GET_CODE (prev_insn) == NOTE) 4897 ; 4898 4899 else if (GET_CODE (prev_insn) == INSN) 4900 { 4901 if (GET_CODE (PATTERN (prev_insn)) != SET) 4902 return (0); 4903 4904 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx)) 4905 { 4906 if (sets_condition_code (SET_SRC (PATTERN (prev_insn)))) 4907 return (1); 4908 4909 return (0); 4910 } 4911 4912 else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn)))) 4913 return (0); 4914 } 4915 4916 else 4917 return (0); 4918 4919 prev_insn = PREV_INSN (prev_insn); 4920 } 4921 4922 return (0); 4923} 4924 4925int 4926doesnt_set_condition_code (pat) 4927 rtx pat; 4928{ 4929 switch (GET_CODE (pat)) 4930 { 4931 case MEM: 4932 case REG: 4933 return 1; 4934 4935 default: 4936 return 0; 4937 4938 } 4939} 4940 4941int 4942sets_condition_code (pat) 4943 rtx pat; 4944{ 4945 switch (GET_CODE (pat)) 4946 { 4947 case PLUS: 4948 case MINUS: 4949 case AND: 4950 case IOR: 4951 case XOR: 4952 case NOT: 4953 case NEG: 4954 case MULT: 4955 case DIV: 4956 case MOD: 4957 case UDIV: 4958 case UMOD: 4959 return 1; 4960 4961 default: 4962 return (0); 4963 } 4964} 4965 4966int 4967str_immediate_operand (op, mode) 4968 register rtx op; 4969 enum machine_mode mode ATTRIBUTE_UNUSED; 4970{ 4971 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0) 4972 return 1; 4973 4974 return 0; 4975} 4976 4977int 4978is_fp_insn (insn) 4979 rtx insn; 4980{ 4981 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 4982 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode 4983 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode 4984 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)) 4985 return 1; 4986 4987 return 0; 4988} 4989 4990/* Return 1 if the mode of the SET_DEST of insn is floating point 4991 and it is not an fld or a move from memory to memory. 4992 Otherwise return 0 */ 4993 4994int 4995is_fp_dest (insn) 4996 rtx insn; 4997{ 4998 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 4999 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode 5000 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode 5001 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode) 5002 && GET_CODE (SET_DEST (PATTERN (insn))) == REG 5003 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG 5004 && GET_CODE (SET_SRC (PATTERN (insn))) != MEM) 5005 return 1; 5006 5007 return 0; 5008} 5009 5010/* Return 1 if the mode of the SET_DEST of INSN is floating point and is 5011 memory and the source is a register. */ 5012 5013int 5014is_fp_store (insn) 5015 rtx insn; 5016{ 5017 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 5018 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode 5019 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode 5020 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode) 5021 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM 5022 && GET_CODE (SET_SRC (PATTERN (insn))) == REG) 5023 return 1; 5024 5025 return 0; 5026} 5027 5028/* Return 1 if DEP_INSN sets a register which INSN uses as a base 5029 or index to reference memory. 5030 otherwise return 0 */ 5031 5032int 5033agi_dependent (insn, dep_insn) 5034 rtx insn, dep_insn; 5035{ 5036 int push = 0, push_dep = 0; 5037 if (GET_CODE (dep_insn) == INSN 5038 && GET_CODE (PATTERN (dep_insn)) == SET 5039 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG 5040 && reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn)) 5041 return 1; 5042 5043 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 5044 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM 5045 && push_operand (SET_DEST (PATTERN (insn)), 5046 GET_MODE (SET_DEST (PATTERN (insn))))) 5047 push = 1; 5048 5049 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET 5050 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM 5051 && push_operand (SET_DEST (PATTERN (dep_insn)), 5052 GET_MODE (SET_DEST (PATTERN (dep_insn))))) 5053 push_dep = 1; 5054 5055 /* CPUs contain special hardware to allow two pushes. */ 5056 if (push && push_dep) 5057 return 0; 5058 5059 /* Push operation implicitly change stack pointer causing AGI stalls. */ 5060 if (push_dep && reg_mentioned_in_mem (stack_pointer_rtx, insn)) 5061 return 1; 5062 5063 /* Push also implicitly read stack pointer. */ 5064 if (push && modified_in_p (stack_pointer_rtx, dep_insn)) 5065 return 1; 5066 5067 return 0; 5068} 5069 5070/* Return 1 if reg is used in rtl as a base or index for a memory ref 5071 otherwise return 0. */ 5072 5073int 5074reg_mentioned_in_mem (reg, rtl) 5075 rtx reg, rtl; 5076{ 5077 register char *fmt; 5078 register int i, j; 5079 register enum rtx_code code; 5080 5081 if (rtl == NULL) 5082 return 0; 5083 5084 code = GET_CODE (rtl); 5085 5086 switch (code) 5087 { 5088 case HIGH: 5089 case CONST_INT: 5090 case CONST: 5091 case CONST_DOUBLE: 5092 case SYMBOL_REF: 5093 case LABEL_REF: 5094 case PC: 5095 case CC0: 5096 case SUBREG: 5097 return 0; 5098 default: 5099 break; 5100 } 5101 5102 if (code == MEM && reg_mentioned_p (reg, rtl)) 5103 return 1; 5104 5105 fmt = GET_RTX_FORMAT (code); 5106 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5107 { 5108 if (fmt[i] == 'E') 5109 { 5110 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--) 5111 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j))) 5112 return 1; 5113 } 5114 5115 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i))) 5116 return 1; 5117 } 5118 5119 return 0; 5120} 5121 5122/* Output the appropriate insns for doing strlen if not just doing repnz; scasb 5123 5124 operands[0] = result, initialized with the startaddress 5125 operands[1] = alignment of the address. 5126 operands[2] = scratch register, initialized with the startaddress when 5127 not aligned, otherwise undefined 5128 5129 This is just the body. It needs the initialisations mentioned above and 5130 some address computing at the end. These things are done in i386.md. */ 5131 5132char * 5133output_strlen_unroll (operands) 5134 rtx operands[]; 5135{ 5136 rtx xops[18]; 5137 5138 xops[0] = operands[0]; /* Result */ 5139 /* operands[1]; * Alignment */ 5140 xops[1] = operands[2]; /* Scratch */ 5141 xops[2] = GEN_INT (0); 5142 xops[3] = GEN_INT (2); 5143 xops[4] = GEN_INT (3); 5144 xops[5] = GEN_INT (4); 5145 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */ 5146 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */ 5147 xops[8] = gen_label_rtx (); /* label of main loop */ 5148 5149 if (TARGET_USE_Q_REG && QI_REG_P (xops[1])) 5150 xops[9] = gen_label_rtx (); /* pentium optimisation */ 5151 5152 xops[10] = gen_label_rtx (); /* end label 2 */ 5153 xops[11] = gen_label_rtx (); /* end label 1 */ 5154 xops[12] = gen_label_rtx (); /* end label */ 5155 /* xops[13] * Temporary used */ 5156 xops[14] = GEN_INT (0xff); 5157 xops[15] = GEN_INT (0xff00); 5158 xops[16] = GEN_INT (0xff0000); 5159 xops[17] = GEN_INT (0xff000000); 5160 5161 /* Loop to check 1..3 bytes for null to get an aligned pointer. */ 5162 5163 /* Is there a known alignment and is it less than 4? */ 5164 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4) 5165 { 5166 /* Is there a known alignment and is it not 2? */ 5167 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2) 5168 { 5169 xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */ 5170 xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */ 5171 5172 /* Leave just the 3 lower bits. 5173 If this is a q-register, then the high part is used later 5174 therefore use andl rather than andb. */ 5175 output_asm_insn (AS2 (and%L1,%4,%1), xops); 5176 5177 /* Is aligned to 4-byte address when zero */ 5178 output_asm_insn (AS1 (je,%l8), xops); 5179 5180 /* Side-effect even Parity when %eax == 3 */ 5181 output_asm_insn (AS1 (jp,%6), xops); 5182 5183 /* Is it aligned to 2 bytes ? */ 5184 if (QI_REG_P (xops[1])) 5185 output_asm_insn (AS2 (cmp%L1,%3,%1), xops); 5186 else 5187 output_asm_insn (AS2 (cmp%L1,%3,%1), xops); 5188 5189 output_asm_insn (AS1 (je,%7), xops); 5190 } 5191 else 5192 { 5193 /* Since the alignment is 2, we have to check 2 or 0 bytes; 5194 check if is aligned to 4 - byte. */ 5195 output_asm_insn (AS2 (and%L1,%3,%1), xops); 5196 5197 /* Is aligned to 4-byte address when zero */ 5198 output_asm_insn (AS1 (je,%l8), xops); 5199 } 5200 5201 xops[13] = gen_rtx_MEM (QImode, xops[0]); 5202 5203 /* Now compare the bytes; compare with the high part of a q-reg 5204 gives shorter code. */ 5205 if (QI_REG_P (xops[1])) 5206 { 5207 /* Compare the first n unaligned byte on a byte per byte basis. */ 5208 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops); 5209 5210 /* When zero we reached the end. */ 5211 output_asm_insn (AS1 (je,%l12), xops); 5212 5213 /* Increment the address. */ 5214 output_asm_insn (AS1 (inc%L0,%0), xops); 5215 5216 /* Not needed with an alignment of 2 */ 5217 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2) 5218 { 5219 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5220 CODE_LABEL_NUMBER (xops[7])); 5221 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops); 5222 output_asm_insn (AS1 (je,%l12), xops); 5223 output_asm_insn (AS1 (inc%L0,%0), xops); 5224 5225 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5226 CODE_LABEL_NUMBER (xops[6])); 5227 } 5228 5229 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops); 5230 } 5231 else 5232 { 5233 output_asm_insn (AS2 (cmp%B13,%2,%13), xops); 5234 output_asm_insn (AS1 (je,%l12), xops); 5235 output_asm_insn (AS1 (inc%L0,%0), xops); 5236 5237 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5238 CODE_LABEL_NUMBER (xops[7])); 5239 output_asm_insn (AS2 (cmp%B13,%2,%13), xops); 5240 output_asm_insn (AS1 (je,%l12), xops); 5241 output_asm_insn (AS1 (inc%L0,%0), xops); 5242 5243 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5244 CODE_LABEL_NUMBER (xops[6])); 5245 output_asm_insn (AS2 (cmp%B13,%2,%13), xops); 5246 } 5247 5248 output_asm_insn (AS1 (je,%l12), xops); 5249 output_asm_insn (AS1 (inc%L0,%0), xops); 5250 } 5251 5252 /* Generate loop to check 4 bytes at a time. It is not a good idea to 5253 align this loop. It gives only huge programs, but does not help to 5254 speed up. */ 5255 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8])); 5256 5257 xops[13] = gen_rtx_MEM (SImode, xops[0]); 5258 output_asm_insn (AS2 (mov%L1,%13,%1), xops); 5259 5260 if (QI_REG_P (xops[1])) 5261 { 5262 /* On i586 it is faster to combine the hi- and lo- part as 5263 a kind of lookahead. If anding both yields zero, then one 5264 of both *could* be zero, otherwise none of both is zero; 5265 this saves one instruction, on i486 this is slower 5266 tested with P-90, i486DX2-66, AMD486DX2-66 */ 5267 if (TARGET_PENTIUM) 5268 { 5269 output_asm_insn (AS2 (test%B1,%h1,%b1), xops); 5270 output_asm_insn (AS1 (jne,%l9), xops); 5271 } 5272 5273 /* Check first byte. */ 5274 output_asm_insn (AS2 (test%B1,%b1,%b1), xops); 5275 output_asm_insn (AS1 (je,%l12), xops); 5276 5277 /* Check second byte. */ 5278 output_asm_insn (AS2 (test%B1,%h1,%h1), xops); 5279 output_asm_insn (AS1 (je,%l11), xops); 5280 5281 if (TARGET_PENTIUM) 5282 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", 5283 CODE_LABEL_NUMBER (xops[9])); 5284 } 5285 5286 else 5287 { 5288 /* Check first byte. */ 5289 output_asm_insn (AS2 (test%L1,%14,%1), xops); 5290 output_asm_insn (AS1 (je,%l12), xops); 5291 5292 /* Check second byte. */ 5293 output_asm_insn (AS2 (test%L1,%15,%1), xops); 5294 output_asm_insn (AS1 (je,%l11), xops); 5295 } 5296 5297 /* Check third byte. */ 5298 output_asm_insn (AS2 (test%L1,%16,%1), xops); 5299 output_asm_insn (AS1 (je,%l10), xops); 5300 5301 /* Check fourth byte and increment address. */ 5302 output_asm_insn (AS2 (add%L0,%5,%0), xops); 5303 output_asm_insn (AS2 (test%L1,%17,%1), xops); 5304 output_asm_insn (AS1 (jne,%l8), xops); 5305 5306 /* Now generate fixups when the compare stops within a 4-byte word. */ 5307 output_asm_insn (AS2 (sub%L0,%4,%0), xops); 5308 5309 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10])); 5310 output_asm_insn (AS1 (inc%L0,%0), xops); 5311 5312 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11])); 5313 output_asm_insn (AS1 (inc%L0,%0), xops); 5314 5315 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12])); 5316 5317 return ""; 5318} 5319 5320char * 5321output_fp_conditional_move (which_alternative, operands) 5322 int which_alternative; 5323 rtx operands[]; 5324{ 5325 enum rtx_code code = GET_CODE (operands[1]); 5326 5327 /* This should never happen. */ 5328 if (!(cc_prev_status.flags & CC_IN_80387) 5329 && (code == GT || code == LE || code == GE || code == LT)) 5330 abort (); 5331 5332 switch (which_alternative) 5333 { 5334 case 0: 5335 /* r <- cond ? arg : r */ 5336 output_asm_insn (AS2 (fcmov%F1,%2,%0), operands); 5337 break; 5338 5339 case 1: 5340 /* r <- cond ? r : arg */ 5341 output_asm_insn (AS2 (fcmov%f1,%3,%0), operands); 5342 break; 5343 5344 default: 5345 abort (); 5346 } 5347 5348 return ""; 5349} 5350 5351char * 5352output_int_conditional_move (which_alternative, operands) 5353 int which_alternative; 5354 rtx operands[]; 5355{ 5356 enum rtx_code code = GET_CODE (operands[1]); 5357 5358 /* This is very tricky. We have to do it right. For a code segement 5359 like: 5360 5361 int foo, bar; 5362 .... 5363 foo = foo - x; 5364 if (foo >= 0) 5365 bar = y; 5366 5367 final_scan_insn () may delete the insn which sets CC. We have to 5368 tell final_scan_insn () if it should be reinserted. When CODE is 5369 GT or LE, we have to check the CC_NO_OVERFLOW bit and return 5370 NULL_PTR to tell final to reinsert the test insn because the 5371 conditional move cannot be handled properly without it. */ 5372 if ((code == GT || code == LE) 5373 && (cc_prev_status.flags & CC_NO_OVERFLOW)) 5374 return NULL_PTR; 5375 5376 switch (which_alternative) 5377 { 5378 case 0: 5379 /* r <- cond ? arg : r */ 5380 output_asm_insn (AS2 (cmov%C1,%2,%0), operands); 5381 break; 5382 5383 case 1: 5384 /* r <- cond ? r : arg */ 5385 output_asm_insn (AS2 (cmov%c1,%3,%0), operands); 5386 break; 5387 5388 default: 5389 abort (); 5390 } 5391 5392 return ""; 5393} 5394 5395int 5396x86_adjust_cost (insn, link, dep_insn, cost) 5397 rtx insn, link, dep_insn; 5398 int cost; 5399{ 5400 rtx next_inst; 5401 5402 if (GET_CODE (dep_insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) 5403 return 0; 5404 5405 if (GET_CODE (dep_insn) == INSN 5406 && GET_CODE (PATTERN (dep_insn)) == SET 5407 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG 5408 && GET_CODE (insn) == INSN 5409 && GET_CODE (PATTERN (insn)) == SET 5410 && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)), 5411 SET_SRC (PATTERN (insn)))) 5412 return 0; /* ??? */ 5413 5414 5415 switch (ix86_cpu) 5416 { 5417 case PROCESSOR_PENTIUM: 5418 if (cost != 0 && is_fp_insn (insn) && is_fp_insn (dep_insn) 5419 && !is_fp_dest (dep_insn)) 5420 return 0; 5421 5422 if (agi_dependent (insn, dep_insn)) 5423 return cost ? cost + 1 : 2; 5424 5425 if (GET_CODE (insn) == INSN 5426 && GET_CODE (PATTERN (insn)) == SET 5427 && SET_DEST (PATTERN (insn)) == cc0_rtx 5428 && (next_inst = next_nonnote_insn (insn)) 5429 && GET_CODE (next_inst) == JUMP_INSN) 5430 /* compare probably paired with jump */ 5431 return 0; 5432 5433 /* Stores stalls one cycle longer than other insns. */ 5434 if (is_fp_insn (insn) && cost && is_fp_store (dep_insn)) 5435 cost++; 5436 break; 5437 case PROCESSOR_K6: 5438 default: 5439 if (!is_fp_dest (dep_insn)) 5440 { 5441 if(!agi_dependent (insn, dep_insn)) 5442 return 0; 5443 if (TARGET_486) 5444 return 2; 5445 } 5446 else 5447 if (is_fp_store (insn) && is_fp_insn (dep_insn) 5448 && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn)) 5449 && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))) 5450 && (GET_CODE (NEXT_INSN (insn)) == INSN) 5451 && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN) 5452 && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE) 5453 && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) 5454 == NOTE_INSN_LOOP_END)) 5455 return 3; 5456 break; 5457 } 5458 5459 return cost; 5460} 5461 5462/* Output assembly code for a left shift. 5463 5464 Always use "sal" when shifting a memory operand or for a non constant 5465 shift count. 5466 5467 When optimizing for size, we know that src == dest, and we should always 5468 use "sal". If src != dest, then copy src to dest and use "sal". 5469 5470 Pentium and PPro (speed): 5471 5472 When src == dest, use "add" for a shift counts of one, else use 5473 "sal". If we modeled Pentium AGI stalls and U/V pipelining better we 5474 would want to generate lea for some shifts on the Pentium. 5475 5476 When src != dest, use "lea" for small shift counts. Otherwise, 5477 copy src to dest and use the normal shifting code. Exception for 5478 TARGET_DOUBLE_WITH_ADD. */ 5479 5480char * 5481output_ashl (insn, operands) 5482 rtx insn, *operands; 5483{ 5484 /* Handle case where srcreg != dstreg. */ 5485 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) 5486 { 5487 if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1) 5488 switch (GET_MODE (operands[0])) 5489 { 5490 case SImode: 5491 output_asm_insn (AS2 (mov%L0,%1,%0), operands); 5492 return AS2 (add%L0,%1,%0); 5493 case HImode: 5494 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands); 5495 if (i386_cc_probably_useless_p (insn)) 5496 { 5497 CC_STATUS_INIT; 5498 return AS2 (add%L0,%k1,%k0); 5499 } 5500 return AS2 (add%W0,%k1,%k0); 5501 case QImode: 5502 output_asm_insn (AS2 (mov%B0,%1,%0), operands); 5503 return AS2 (add%B0,%1,%0); 5504 default: 5505 abort (); 5506 } 5507 else 5508 { 5509 CC_STATUS_INIT; 5510 5511 /* This should be extremely rare (impossible?). We can not encode a 5512 shift of the stack pointer using an lea instruction. So copy the 5513 stack pointer into the destination register and use an lea. */ 5514 if (operands[1] == stack_pointer_rtx) 5515 { 5516 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands); 5517 operands[1] = operands[0]; 5518 } 5519 5520 /* For shifts up to and including 3 bits, use lea. */ 5521 operands[1] = gen_rtx_MULT (SImode, 5522 gen_rtx_REG (SImode, REGNO (operands[1])), 5523 GEN_INT (1 << INTVAL (operands[2]))); 5524 return AS2 (lea%L0,%a1,%k0); 5525 } 5526 } 5527 5528 /* Source and destination match. */ 5529 5530 /* Handle variable shift. */ 5531 if (REG_P (operands[2])) 5532 switch (GET_MODE (operands[0])) 5533 { 5534 case SImode: 5535 return AS2 (sal%L0,%b2,%0); 5536 case HImode: 5537 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn)) 5538 { 5539 CC_STATUS_INIT; 5540 return AS2 (sal%L0,%b2,%k0); 5541 } 5542 else 5543 return AS2 (sal%W0,%b2,%0); 5544 case QImode: 5545 return AS2 (sal%B0,%b2,%0); 5546 default: 5547 abort (); 5548 } 5549 5550 /* Always perform shift by 1 using an add instruction. */ 5551 if (REG_P (operands[0]) && operands[2] == const1_rtx) 5552 switch (GET_MODE (operands[0])) 5553 { 5554 case SImode: 5555 return AS2 (add%L0,%0,%0); 5556 case HImode: 5557 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn)) 5558 { 5559 CC_STATUS_INIT; 5560 return AS2 (add%L0,%k0,%k0); 5561 } 5562 else 5563 return AS2 (add%W0,%0,%0); 5564 case QImode: 5565 return AS2 (add%B0,%0,%0); 5566 default: 5567 abort (); 5568 } 5569 5570#if 0 5571 /* ??? Currently disabled. Because our model of Pentium is far from being 5572 exact, this change will need some benchmarking. */ 5573 /* Shift reg by 2 or 3 use an lea instruction for Pentium if this is 5574 insn is expected to issue into the V pipe (the insn's mode will be 5575 TImode for a U pipe, and !TImode for a V pipe instruction). */ 5576 if (! optimize_size 5577 && REG_P (operands[0]) 5578 && GET_CODE (operands[2]) == CONST_INT 5579 && INTVAL (operands[2]) <= 3 5580 && (int)ix86_cpu == (int)PROCESSOR_PENTIUM 5581 && GET_MODE (insn) != TImode) 5582 { 5583 CC_STATUS_INIT; 5584 operands[1] = gen_rtx_MULT (SImode, gen_rtx_REG (SImode, REGNO (operands[1])), 5585 GEN_INT (1 << INTVAL (operands[2]))); 5586 return AS2 (lea%L0,%a1,%0); 5587 } 5588#endif 5589 5590 /* Otherwise use a shift instruction. */ 5591 switch (GET_MODE (operands[0])) 5592 { 5593 case SImode: 5594 return AS2 (sal%L0,%2,%0); 5595 case HImode: 5596 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn)) 5597 { 5598 CC_STATUS_INIT; 5599 return AS2 (sal%L0,%2,%k0); 5600 } 5601 else 5602 return AS2 (sal%W0,%2,%0); 5603 case QImode: 5604 return AS2 (sal%B0,%2,%0); 5605 default: 5606 abort (); 5607 } 5608} 5609 5610/* Given the memory address ADDR, calculate the length of the address or 5611 the length of just the displacement (controlled by DISP_LENGTH). 5612 5613 The length returned does not include the one-byte modrm, opcode, 5614 or prefix. */ 5615 5616int 5617memory_address_info (addr, disp_length) 5618 rtx addr; 5619 int disp_length; 5620{ 5621 rtx base, index, disp, scale; 5622 rtx op0, op1; 5623 int len; 5624 5625 if (GET_CODE (addr) == PRE_DEC 5626 || GET_CODE (addr) == POST_INC) 5627 return 0; 5628 5629 /* Register Indirect. */ 5630 if (register_operand (addr, Pmode)) 5631 { 5632 /* Special cases: ebp and esp need the two-byte modrm form. 5633 5634 We change [ESI] to [ESI+0] on the K6 when not optimizing 5635 for size. */ 5636 if (addr == stack_pointer_rtx 5637 || addr == arg_pointer_rtx 5638 || addr == frame_pointer_rtx 5639 || (REGNO_REG_CLASS (REGNO (addr)) == SIREG 5640 && ix86_cpu == PROCESSOR_K6 && !optimize_size)) 5641 return 1; 5642 else 5643 return 0; 5644 } 5645 5646 /* Direct Addressing. */ 5647 if (CONSTANT_P (addr)) 5648 return 4; 5649 5650 index = base = disp = scale = NULL_RTX; 5651 op0 = XEXP (addr, 0); 5652 op1 = XEXP (addr, 1); 5653 5654 if (GET_CODE (addr) == PLUS) 5655 { 5656 if (register_operand (op0, Pmode)) 5657 { 5658 if (register_operand (op1, Pmode)) 5659 index = op0, base = op1; 5660 else 5661 base = op0, disp = op1; 5662 } 5663 else if (GET_CODE (op0) == MULT) 5664 { 5665 index = XEXP (op0, 0); 5666 scale = XEXP (op0, 1); 5667 if (register_operand (op1, Pmode)) 5668 base = op1; 5669 else 5670 disp = op1; 5671 } 5672 else if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) 5673 { 5674 index = XEXP (XEXP (op0, 0), 0); 5675 scale = XEXP (XEXP (op0, 0), 1); 5676 base = XEXP (op0, 1); 5677 disp = op1; 5678 } 5679 else if (GET_CODE (op0) == PLUS) 5680 { 5681 index = XEXP (op0, 0); 5682 base = XEXP (op0, 1); 5683 disp = op1; 5684 } 5685 else 5686 abort (); 5687 } 5688 else if (GET_CODE (addr) == MULT 5689 /* We're called for lea too, which implements ashift on occasion. */ 5690 || GET_CODE (addr) == ASHIFT) 5691 { 5692 index = XEXP (addr, 0); 5693 scale = XEXP (addr, 1); 5694 } 5695 else 5696 abort (); 5697 5698 /* Allow arg pointer and stack pointer as index if there is not scaling */ 5699 if (base && index && !scale 5700 && (index == stack_pointer_rtx 5701 || index == arg_pointer_rtx 5702 || index == frame_pointer_rtx)) 5703 { 5704 rtx tmp = base; 5705 base = index; 5706 index = tmp; 5707 } 5708 5709 /* Special case: ebp cannot be encoded as a base without a displacement. */ 5710 if (base == frame_pointer_rtx && !disp) 5711 disp = const0_rtx; 5712 5713 /* Scaling can not be encoded without base or displacement. 5714 Except for scale == 1 where we can encode reg + reg instead of reg * 2. */ 5715 if (!base && index 5716 && (!scale || GET_CODE (scale) != CONST_INT || (INTVAL (scale) != 1))) 5717 disp = const0_rtx; 5718 5719 /* Find the length of the displacement constant. */ 5720 len = 0; 5721 if (disp) 5722 { 5723 if (GET_CODE (disp) == CONST_INT 5724 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K')) 5725 len = 1; 5726 else 5727 len = 4; 5728 } 5729 5730 /* An index requires the two-byte modrm form. Not important 5731 if we are computing just length of the displacement. */ 5732 if (index && ! disp_length) 5733 len += 1; 5734 5735 return len; 5736} 5737