ChangeLog.gcc43 revision 260140
12007-08-08 Andrew Haley <aph@redhat.com> (r128087) 2 3 * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New. 4 * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New. 5 * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New. 6 72007-07-12 Geoffrey Keating <geoffk@apple.com> (r126588) 8 9 * builtins.c (get_pointer_alignment): Honor DECL_ALIGN on a 10 FUNCTION_DECL. 11 * tree.c (build_decl_stat): Move code from here... 12 (make_node_stat): ... to here. Don't uselessly clear DECL_USER_ALIGN. 13 (expr_align): Honor DECL_ALIGN on a FUNCTION_DECL. Add comment 14 about using DECL_ALIGN of LABEL_DECL and CONST_DECL. 15 * tree.h (DECL_USER_ALIGN): Fix misplaced comment. 16 * varasm.c (assemble_start_function): Use DECL_ALIGN instead of 17 FUNCTION_BOUNDARY. 18 192007-07-09 Geoffrey Keating <geoffk@apple.com> (r126529) 20 21 PR 32617 22 * c-common.c (c_alignof_expr): Look at DECL_ALIGN of 23 FUNCTION_DECLs. 24 (handle_aligned_attribute): Allow use on FUNCTION_DECLs. 25 * varasm.c (assemble_start_function): Honor DECL_ALIGN 26 for FUNCTION_DECLs. Don't use align_functions_log if 27 DECL_USER_ALIGN. 28 * print-tree.c (print_node): Print DECL_ALIGN and DECL_USER_ALIGN 29 even for FUNCTION_DECLs. 30 * c-decl.c (merge_decls): Propagate DECL_ALIGN even for 31 FUNCTION_DECLs. 32 * tree.h (DECL_ALIGN): Update for new location of 'align'. 33 (DECL_FUNCTION_CODE): Update for new location and name of 34 'function_code'. 35 (DECL_OFFSET_ALIGN): Update for new location of 'off_align'. 36 (struct tree_decl_common): Move 'align' and 'off_align' out 37 of union, ensure they're still on a 32-bit boundary. Remove 38 other fields in union 'u1'. 39 (struct tree_function_decl): Add field 'function_code' replacing 40 'u1.f' in tree_decl_common. 41 * tree.c (build_decl_stat): Set initial value of DECL_ALIGN. 42 * doc/extend.texi (Function Attributes): Add 'aligned' attribute. 43 (Variable Attributes): Cross-reference 'aligned' attribute 44 to Function Attributes. 45 * flags.h (force_align_functions_log): Delete. 46 * toplev.c (force_align_functions_log): Delete. 47 482007-07-06 Josh Conner <jconner@apple.com> (r126422) 49 50 PR middle-end/32602 51 PR middle-end/32603 52 * calls.c (store_one_arg): Handle arguments which are partially 53 on the stack when detecting argument overlap. 54 552007-07-03 Eric Christopher <echristo@apple.com> (r126278) 56 57 * doc/cppopts.texi: Add conflicting option note to -dM. 58 * doc/invoke.texi: Add note about possible conflicts with 59 -E for -dCHARS and note that -dM will not produce 60 any results if there is no machine dependent reorg. 61 622007-06-28 Geoffrey Keating <geoffk@apple.com> (r126088) 63 64 * doc/invoke.texi (C++ Dialect Options): Document 65 fvisibility-ms-compat. 66 * c.opt (fvisibility-ms-compat): New. 67 682007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346) 69 70 PR preprocessor/23479 71 * doc/extend.texi: Document the 0b-prefixed binary integer 72 constant extension. 73 742007-05-31 Daniel Berlin <dberlin@dberlin.org> (r125239) 75 76 * c-typeck.c (build_indirect_ref): Include type in error message. 77 (build_binary_op): Pass types to binary_op_error. 78 * c-common.c (binary_op_error): Take two type arguments, print out 79 types with error. 80 * c-common.h (binary_op_error): Update prototype. 81 822007-05-27 Eric Christopher <echristo@apple.com> (r125116) 83 84 * config/rs6000/rs6000.c (rs6000_emit_prologue): Update 85 sp_offset depending on stack size. Save r12 depending 86 on registers we're saving later. 87 (rs6000_emit_epilogue): Update sp_offset depending only 88 on stack size. 89 902007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037) 91 92 * postreload-gcse.c (reg_changed_after_insn_p): New function. 93 (oprs_unchanged_p): Use it to check all registers in a REG. 94 (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE. 95 (reg_set_between_after_reload_p): Delete. 96 (reg_used_between_after_reload_p): Likewise. 97 (reg_set_or_used_since_bb_start): Likewise. 98 (eliminate_partially_redundant_load): Use reg_changed_after_insn_p 99 and reg_used_between_p instead of reg_set_or_used_since_bb_start. 100 Use reg_set_between_p instead of reg_set_between_after_reload_p. 101 * rtlanal.c (reg_set_p): Check whether REG overlaps 102 regs_invalidated_by_call, rather than just checking the 103 membership of REGNO (REG). 104 1052007-05-18 Geoffrey Keating <geoffk@apple.com> (r124839) 106 107 * dwarf2out.c (print_die): Use '%ld' not '%lu' to print a 'long'. 108 (output_die): Use 'unsigned long' with %x. 109 * sched-vis.c (print_value): Use 'unsigned HOST_WIDE_INT' and 110 HOST_WIDE_INT_PRINT_HEX to print HOST_WIDE_INT. 111 * tree-dump.c (dump_pointer): Use 'unsigned long' for %lx. 112 1132007-05-16 Eric Christopher <echristo@apple.com> (r124763) 114 115 * config/rs6000/rs6000.c (rs6000_emit_prologue): Move altivec register 116 saving after stack push. Set sp_offset whenever we push. 117 (rs6000_emit_epilogue): Move altivec register restore before stack push. 118 1192007-05-03 Ian Lance Taylor <iant@google.com> (r124381) 120 121 * config/rs6000/rs6000.c (rs6000_override_options): Don't set 122 MASK_PPC_GFXOPT for 8540 or 8548. 123 1242007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 125 126 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 127 'AMD Family 10 core'. 128 1292007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 130 131 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 132 and athlon64-sse3 as improved versions of k8, opteron and athlon64 133 with SSE3 instruction set support. 134 * doc/invoke.texi: Likewise. 135 1362007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 137 138 * config/i386/i386.c (override_options): Tuning 32-byte loop 139 alignment for amdfam10 architecture. Increasing the max loop 140 alignment to 24 bytes. 141 1422007-04-16 Lawrence Crowl <crowl@google.com> (r123909) 143 144 * doc/invoke.texi (Debugging Options): Add documentation for the 145 -femit-struct-debug options -femit-struct-debug-baseonly, 146 -femit-struct-debug-reduced, and 147 -femit-struct-debug-detailed[=...]. 148 149 * c-opts.c (c_common_handle_option): Add 150 OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced, 151 and OPT_femit_struct_debug_detailed_. 152 * c.opt: Add specifications for 153 -femit-struct-debug-baseonly, -femit-struct-debug-reduced, 154 and -femit-struct-debug-detailed[=...]. 155 * opts.c (set_struct_debug_option): Parse the 156 -femit-struct-debug-... options. 157 * opts.c (matches_main_base, main_input_basename, 158 main_input_baselength, base_of_path, matches_main_base): Add 159 variables and functions to compare header base name to compilation 160 unit base name. 161 * opts.c (should_emit_struct_debug): Add to determine to emit a 162 structure based on the option. 163 (dump_struct_debug) Also disabled function to debug this 164 function. 165 * opts.c (handle_options): Save the base name of the 166 compilation unit. 167 168 * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define. 169 (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add. 170 This hook indicates if a type is generic. Set it by default 171 to "never generic". 172 * langhooks.h (struct lang_hooks_for_types): Add a new hook 173 to determine if a struct type is generic or not. 174 * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook. 175 * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook. 176 * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook 177 with live C++ hook. 178 179 * flags.h (enum debug_info_usage): Add an enumeration to describe 180 a program's use of a structure type. 181 * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter 182 to indicate the program's usage of the type. Filter structs based 183 on the -femit-struct-debug-... specification. 184 (gen_type_die): Split into two routines, gen_type_die and 185 gen_type_die_with_usage. gen_type_die is now a wrapper 186 that assumes direct usage. 187 (gen_type_die_with_usage): Replace calls to gen_type_die 188 with gen_type_die_with_usage adding the program usage of 189 the referenced type. 190 (dwarf2out_imported_module_or_decl): Suppress struct debug 191 information using should_emit_struct_debug when appropriate. 192 1932007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 194 195 PR tree-optimization/24689 196 PR tree-optimization/31307 197 * fold-const.c (operand_equal_p): Compare INTEGER_CST array 198 indices by value. 199 * gimplify.c (canonicalize_addr_expr): To be consistent with 200 gimplify_compound_lval only set operands two and three of 201 ARRAY_REFs if they are not gimple_min_invariant. This makes 202 it never at this place. 203 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 204 2052007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 206 207 * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 208 2092007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 210 211 * config.gcc: Accept barcelona as a variant of amdfam10. 212 * config/i386/i386.c (override_options): Likewise. 213 * doc/invoke.texi: Likewise. 214 2152007-03-12 Seongbae Park <seongbae.park@gmail.com> (r122851) 216 217 * c-decl.c (warn_variable_length_array): New function. 218 Refactored from grokdeclarator to handle warn_vla 219 and handle unnamed array case. 220 (grokdeclarator): Refactored VLA warning case. 221 * c.opt (Wvla): New flag. 222 2232007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 224 225 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 226 the *_DIV_EXPR codes correctly with overflow infinities. 227 2282007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 229 230 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 231 (bit_SSE4a): New. 232 2332007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 234 235 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 236 conditional to __SSE2__. 237 (Entries below should have been added to first ChangeLog 238 entry for amdfam10 dated 2007-02-05) 239 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 240 defined. 241 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 242 defined. 243 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 244 defined. 245 2462007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 247 248 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 249 2502007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 251 252 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 253 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 254 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 255 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 256 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 257 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 258 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 259 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 260 2612007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 262 263 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 264 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 265 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 266 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 267 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 268 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 269 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 270 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 271 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 272 umuldi3_highpart_rex64, umulsi3_highpart_insn, 273 umulsi3_highpart_zext, smuldi3_highpart_rex64, 274 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 275 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 276 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 277 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 278 sqrtextenddfxf2_i387): Added amdfam10_decode. 279 280 * config/i386/athlon.md (athlon_idirect_amdfam10, 281 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 282 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 283 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 284 athlon_ivector_store_amdfam10): New define_insn_reservation. 285 (athlon_idirect_loadmov, athlon_idirect_movstore): Added 286 amdfam10. 287 2882007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 289 290 * config/i386/athlon.md (athlon_call_amdfam10, 291 athlon_pop_amdfam10, athlon_lea_amdfam10): New 292 define_insn_reservation. 293 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 294 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 295 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 296 2972007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 298 299 * config/i386/athlon.md (athlon_sseld_amdfam10, 300 athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 301 athlon_mmxssest_short_amdfam10): New define_insn_reservation. 302 3032007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 304 305 * config/i386/athlon.md (athlon_sseins_amdfam10): New 306 define_insn_reservation. 307 * config/i386/i386.md (sseins): Added sseins to define_attr type 308 and define_attr unit. 309 * config/i386/sse.md: Set type attribute to sseins for insertq 310 and insertqi. 311 3122007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 313 314 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 315 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 316 ssecomi_load_amdfam10, ssecomi_amdfam10, 317 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 318 define_insn_reservation. 319 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 320 3212007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 322 323 * config/i386/athlon.md (cvtss2sd_load_amdfam10, 324 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 325 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 326 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 327 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 328 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 329 define_insn_reservation. 330 331 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 332 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 333 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 334 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 335 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 336 3372007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 338 339 * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 340 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 341 athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 342 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 343 athlon_ssemul_load_k8): Added amdfam10. 344 3452007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 346 347 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 348 (x86_sse_unaligned_move_optimal): New variable. 349 350 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 351 m_AMDFAM10. 352 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 353 for unaligned vector SSE double/single precision loads for AMDFAM10. 354 3552007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 356 357 * config/i386/i386.h (TARGET_AMDFAM10): New macro. 358 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 359 Define TARGET_CPU_DEFAULT_amdfam10. 360 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 361 (processor_type): Add PROCESSOR_AMDFAM10. 362 363 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 364 processor_type in config/i386/i386.h. 365 Enable imul peepholes for TARGET_AMDFAM10. 366 367 * config.gcc: Add support for --with-cpu option for amdfam10. 368 369 * config/i386/i386.c (amdfam10_cost): New variable. 370 (m_AMDFAM10): New macro. 371 (m_ATHLON_K8_AMDFAM10): New macro. 372 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 373 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 374 x86_promote_QImode, x86_integer_DFmode_moves, 375 x86_partial_reg_dependency, x86_memory_mismatch_stall, 376 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 377 x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 378 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 379 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 380 Enable/disable for amdfam10. 381 (override_options): Add amdfam10_cost to processor_target_table. 382 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 383 processor_alias_table. 384 (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 385 (ix86_adjust_cost): Add code for amdfam10. 386 3872007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 388 389 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 390 instruction set feature flag. Add new (-mpopcnt) flag for popcnt 391 instruction. Add new SSE4A (-msse4a) instruction set feature flag. 392 * config/i386/i386.h: Add builtin definition for SSE4A. 393 * config/i386/i386.md: Add support for ABM instructions 394 (popcnt and lzcnt). 395 * config/i386/sse.md: Add support for SSE4A instructions 396 (movntss, movntsd, extrq, insertq). 397 * config/i386/i386.c: Add support for ABM and SSE4A builtins. 398 Add -march=amdfam10 flag. 399 * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 400 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 401 and amdfam10. 402 * doc/extend.texi: Add documentation for SSE4A builtins. 403 4042007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 405 406 * config/i386/i386.h (x86_cmpxchg16b): Remove const. 407 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 408 * config/i386/i386.c (x86_cmpxchg16b): Remove const. 409 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 410 for CPUs that have PTA_CX16 set. 411 4122007-01-18 Josh Conner <jconner@apple.com> (r120902) 413 414 PR target/30485 415 * config/rs6000/rs6000.c (rs6000_emit_vector_compare): Add 416 support for UNLE, UNLT, UNGE, and UNGT. 417 4182007-01-17 Eric Christopher <echristo@apple.com> (r120846) 419 420 * config.gcc: Support core2 processor. 421 4222007-01-11 Joseph Myers <joseph@codesourcery.com> (r120688) 423 424 * c-common.c (vector_types_convertible_p): Treat opaque types as 425 always convertible if they have the same size, but not otherwise. 426 4272007-01-11 Joseph Myers <joseph@codesourcery.com> (r120688) 428 429 * c-common.c (vector_types_convertible_p): Treat opaque types as 430 always convertible if they have the same size, but not otherwise. 431 4322007-01-08 Geoffrey Keating <geoffk@apple.com> (r120611) 433 434 * target.h (struct gcc_target): New field library_rtti_comdat. 435 * target-def.h (TARGET_CXX_LIBRARY_RTTI_COMDAT): New. 436 (TARGET_CXX): Add TARGET_CXX_LIBRARY_RTTI_COMDAT. 437 * doc/tm.texi (C++ ABI): Document TARGET_CXX_LIBRARY_RTTI_COMDAT. 438 * config/darwin.h (TARGET_CXX_LIBRARY_RTTI_COMDAT): Define. 439 4402007-01-08 Mark Shinwell <shinwell@codesourcery.com> (r120572) 441 442 * c.opt: Add -flax-vector-conversions. 443 * c-typeck.c (convert_for_assignment): Pass flag to 444 vector_types_convertible_p to allow emission of note. 445 (digest_init): Likewise. 446 * c-opts.c: Handle -flax-vector-conversions. 447 * c-common.c (flag_lax_vector_conversions): New. 448 (vector_types_convertible_p): Unless -flax-vector conversions 449 has been passed, disallow conversions between vectors with 450 differing numbers of subparts and/or element types. If such 451 a conversion is disallowed, possibly emit a note on the first 452 occasion only to inform the user of -flax-vector-conversions. 453 The new last argument specifies this. 454 * c-common.h (flag_lax_vector_conversions): New. 455 (vector_types_convertible_p): Add extra argument. 456 * config/i386/i386.c (ix86_init_mmx_sse_builtins): Use 457 char_type_node for V*QI type vectors. 458 * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): 459 Update to satisfy new typechecking rules. 460 * config/rs6000/altivec.h (vec_cmple): Use vec_cmpge, for both 461 C and C++ variants. 462 * doc/invoke.texi (C Dialect Options): Document 463 -flax-vector-conversions. 464 4652007-01-05 Manuel Lopez-Ibanez <manu@gcc.gnu.org> (r120505) 466 467 PR c/19978 468 * tree.h (TREE_OVERFLOW_P): New. 469 * c-typeck.c (parser_build_unary_op): Warn only if result 470 overflowed and operands did not. 471 (parser_build_binary_op): Likewise. 472 (convert_for_assignment): Remove redundant overflow_warning. 473 * c-common.c (overflow_warning): Don't check or set TREE_OVERFLOW. 474 4752006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 476 477 PR c++/19564 478 PR c++/19756 479 * c-typeck.c (parser_build_binary_op): Move parentheses warnings 480 to warn_about_parentheses in c-common.c. 481 * c-common.c (warn_about_parentheses): New function. 482 * c-common.h (warn_about_parentheses): Declare. 483 * doc/invoke.texi (Warning Options): Update -Wparentheses 484 description. 485 4862006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 487 488 PR target/30040 489 * config/i386/driver-i386.c (bit_SSSE3): New. 490 4912006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 492 493 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 494 and m_GENERIC64. 495 4962006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 497 498 * doc/invoke.texi (core2): Add item. 499 500 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 501 macros. 502 (TARGET_CPU_CPP_BUILTINS): Add code for core2. 503 (TARGET_CPU_DEFAULT_generic): Change value. 504 (TARGET_CPU_DEFAULT_NAMES): Add core2. 505 (processor_type): Add new constant PROCESSOR_CORE2. 506 507 * config/i386/i386.md (cpu): Add core2. 508 509 * config/i386/i386.c (core2_cost): New initialized variable. 510 (m_CORE2): New macro. 511 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 512 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 513 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 514 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 515 x86_partial_reg_dependency, x86_memory_mismatch_stall, 516 x86_accumulate_outgoing_args, x86_prologue_using_move, 517 x86_epilogue_using_move, x86_arch_always_fancy_math_387, 518 x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 519 x86_use_incdec, x86_four_jump_limit, x86_schedule, 520 x86_pad_returns): Add m_CORE2. 521 (override_options): Add entries for Core2. 522 (ix86_issue_rate): Add case for Core2. 523 5242006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356) 525 526 * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on 527 inline static functions in c99 mode. 528 529 PR 16622 530 * doc/extend.texi (Inline): Update. 531 * c-tree.h (struct language_function): Remove field 'extern_inline'. 532 * c-decl.c (current_extern_inline): Delete. 533 (pop_scope): Adjust test for an undefined nested function. 534 Add warning about undeclared inline function. 535 (diagnose_mismatched_decls): Update comments. Disallow overriding 536 of inline functions in a translation unit in C99. Allow inline 537 declarations in C99 at any time. 538 (merge_decls): Boolize variables. Handle C99 'extern inline' 539 semantics. 540 (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle 541 C99 inline semantics. 542 (start_function): Don't clear current_extern_inline. Don't set 543 DECL_EXTERNAL. 544 (c_push_function_context): Don't push current_extern_inline. 545 (c_pop_function_context): Don't restore current_extern_inline. 546 547 PR 11377 548 * c-typeck.c (build_external_ref): Warn about static variables 549 used in extern inline functions. 550 * c-decl.c (start_decl): Warn about static variables declared 551 in extern inline functions. 552 5532006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 554 555 * config/i386/i386.h (TARGET_GEODE): 556 (TARGET_CPU_CPP_BUILTINS): Add code for geode. 557 (TARGET_CPU_DEFAULT_geode): New macro. 558 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 559 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 560 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 561 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 562 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 563 the macro values. 564 (TARGET_CPU_DEFAULT_NAMES): Add geode. 565 (processor_type): Add PROCESSOR_GEODE. 566 567 * config/i386/i386.md: Include geode.md. 568 (cpu): Add geode. 569 570 * config/i386/i386.c (geode_cost): New initialized global 571 variable. 572 (m_GEODE, m_K6_GEODE): New macros. 573 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 574 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 575 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 576 x86_schedule): Use m_K6_GEODE instead of m_K6. 577 (x86_movx, x86_cmove): Set up m_GEODE. 578 (x86_integer_DFmode_moves): Clear m_GEODE. 579 (processor_target_table): Add entry for geode. 580 (processor_alias_table): Ditto. 581 582 * config/i386/geode.md: New file. 583 584 * doc/invoke.texi: Add entry about geode processor. 585 5862006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 587 588 PR middle-end/28796 589 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 590 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 591 for deciding optimizations in consistency with fold-const.c 592 (fold_builtin_unordered_cmp): Likewise. 593 5942006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 595 596 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 597 (x86_64-*-*): Likewise. 598 599 * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 600 (override_options): Check SSSE3. 601 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 602 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 603 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 604 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 605 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 606 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 607 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 608 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 609 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 610 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 611 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 612 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 613 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 614 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 615 IX86_BUILTIN_PABSD128. 616 (bdesc_2arg): Add SSSE3. 617 (bdesc_1arg): Likewise. 618 (ix86_init_mmx_sse_builtins): Support SSSE3. 619 (ix86_expand_builtin): Likewise. 620 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 621 622 * config/i386/i386.md (UNSPEC_PSHUFB): New. 623 (UNSPEC_PSIGN): Likewise. 624 (UNSPEC_PALIGNR): Likewise. 625 Include mmx.md before sse.md. 626 627 * config/i386/i386.opt: Add -mssse3. 628 629 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 630 (ssse3_phaddwv4hi3): Likewise. 631 (ssse3_phadddv4si3): Likewise. 632 (ssse3_phadddv2si3): Likewise. 633 (ssse3_phaddswv8hi3): Likewise. 634 (ssse3_phaddswv4hi3): Likewise. 635 (ssse3_phsubwv8hi3): Likewise. 636 (ssse3_phsubwv4hi3): Likewise. 637 (ssse3_phsubdv4si3): Likewise. 638 (ssse3_phsubdv2si3): Likewise. 639 (ssse3_phsubswv8hi3): Likewise. 640 (ssse3_phsubswv4hi3): Likewise. 641 (ssse3_pmaddubswv8hi3): Likewise. 642 (ssse3_pmaddubswv4hi3): Likewise. 643 (ssse3_pmulhrswv8hi3): Likewise. 644 (ssse3_pmulhrswv4hi3): Likewise. 645 (ssse3_pshufbv16qi3): Likewise. 646 (ssse3_pshufbv8qi3): Likewise. 647 (ssse3_psign<mode>3): Likewise. 648 (ssse3_psign<mode>3): Likewise. 649 (ssse3_palignrti): Likewise. 650 (ssse3_palignrdi): Likewise. 651 (abs<mode>2): Likewise. 652 (abs<mode>2): Likewise. 653 654 * config/i386/tmmintrin.h: New file. 655 656 * doc/extend.texi: Document SSSE3 built-in functions. 657 658 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 659 6602006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 661 662 * config/i386/tmmintrin.h: Remove the duplicated content. 663 6642006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 665 666 PR tree-optimization/3511 667 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 668 got new invariant arguments during PHI translation. 669 6702006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 671 672 * builtins.c (fold_builtin_classify): Fix typo. 673 674