ChangeLog.gcc43 revision 259707
1259269Spfg2007-08-08 Andrew Haley <aph@redhat.com> (r128087) 2255252Spfg 3259269Spfg * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New. 4259269Spfg * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New. 5259269Spfg * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New. 6259269Spfg 7259705Spfg2007-07-12 Geoffrey Keating <geoffk@apple.com> (r126588) 8259705Spfg 9259705Spfg * builtins.c (get_pointer_alignment): Honor DECL_ALIGN on a 10259705Spfg FUNCTION_DECL. 11259705Spfg * tree.c (build_decl_stat): Move code from here... 12259705Spfg (make_node_stat): ... to here. Don't uselessly clear DECL_USER_ALIGN. 13259705Spfg (expr_align): Honor DECL_ALIGN on a FUNCTION_DECL. Add comment 14259705Spfg about using DECL_ALIGN of LABEL_DECL and CONST_DECL. 15259705Spfg * tree.h (DECL_USER_ALIGN): Fix misplaced comment. 16259705Spfg * varasm.c (assemble_start_function): Use DECL_ALIGN instead of 17259705Spfg FUNCTION_BOUNDARY. 18259705Spfg 19259705Spfg2007-07-09 Geoffrey Keating <geoffk@apple.com> (r126529) 20259705Spfg 21259705Spfg PR 32617 22259705Spfg * c-common.c (c_alignof_expr): Look at DECL_ALIGN of 23259705Spfg FUNCTION_DECLs. 24259705Spfg (handle_aligned_attribute): Allow use on FUNCTION_DECLs. 25259705Spfg * varasm.c (assemble_start_function): Honor DECL_ALIGN 26259705Spfg for FUNCTION_DECLs. Don't use align_functions_log if 27259705Spfg DECL_USER_ALIGN. 28259705Spfg * print-tree.c (print_node): Print DECL_ALIGN and DECL_USER_ALIGN 29259705Spfg even for FUNCTION_DECLs. 30259705Spfg * c-decl.c (merge_decls): Propagate DECL_ALIGN even for 31259705Spfg FUNCTION_DECLs. 32259705Spfg * tree.h (DECL_ALIGN): Update for new location of 'align'. 33259705Spfg (DECL_FUNCTION_CODE): Update for new location and name of 34259705Spfg 'function_code'. 35259705Spfg (DECL_OFFSET_ALIGN): Update for new location of 'off_align'. 36259705Spfg (struct tree_decl_common): Move 'align' and 'off_align' out 37259705Spfg of union, ensure they're still on a 32-bit boundary. Remove 38259705Spfg other fields in union 'u1'. 39259705Spfg (struct tree_function_decl): Add field 'function_code' replacing 40259705Spfg 'u1.f' in tree_decl_common. 41259705Spfg * tree.c (build_decl_stat): Set initial value of DECL_ALIGN. 42259705Spfg * doc/extend.texi (Function Attributes): Add 'aligned' attribute. 43259705Spfg (Variable Attributes): Cross-reference 'aligned' attribute 44259705Spfg to Function Attributes. 45259705Spfg * flags.h (force_align_functions_log): Delete. 46259705Spfg * toplev.c (force_align_functions_log): Delete. 47259705Spfg 48259269Spfg2007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346) 49259269Spfg 50255252Spfg PR preprocessor/23479 51255252Spfg * doc/extend.texi: Document the 0b-prefixed binary integer 52255252Spfg constant extension. 53255252Spfg 54259707Spfg2007-05-27 Eric Christopher <echristo@apple.com> (r125116) 55259707Spfg 56259707Spfg * config/rs6000/rs6000.c (rs6000_emit_prologue): Update 57259707Spfg sp_offset depending on stack size. Save r12 depending 58259707Spfg on registers we're saving later. 59259707Spfg (rs6000_emit_epilogue): Update sp_offset depending only 60259707Spfg on stack size. 61259707Spfg 62259269Spfg2007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037) 63259269Spfg 64259269Spfg * postreload-gcse.c (reg_changed_after_insn_p): New function. 65259269Spfg (oprs_unchanged_p): Use it to check all registers in a REG. 66259269Spfg (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE. 67259269Spfg (reg_set_between_after_reload_p): Delete. 68259269Spfg (reg_used_between_after_reload_p): Likewise. 69259269Spfg (reg_set_or_used_since_bb_start): Likewise. 70259269Spfg (eliminate_partially_redundant_load): Use reg_changed_after_insn_p 71259269Spfg and reg_used_between_p instead of reg_set_or_used_since_bb_start. 72259269Spfg Use reg_set_between_p instead of reg_set_between_after_reload_p. 73259269Spfg * rtlanal.c (reg_set_p): Check whether REG overlaps 74259269Spfg regs_invalidated_by_call, rather than just checking the 75259269Spfg membership of REGNO (REG). 76259269Spfg 77259707Spfg2007-05-16 Eric Christopher <echristo@apple.com> (r124763) 78259707Spfg 79259707Spfg * config/rs6000/rs6000.c (rs6000_emit_prologue): Move altivec register 80259707Spfg saving after stack push. Set sp_offset whenever we push. 81259707Spfg (rs6000_emit_epilogue): Move altivec register restore before stack push. 82259707Spfg 83259269Spfg2007-05-03 Ian Lance Taylor <iant@google.com> (r124381) 84259269Spfg 85259269Spfg * config/rs6000/rs6000.c (rs6000_override_options): Don't set 86259269Spfg MASK_PPC_GFXOPT for 8540 or 8548. 87259269Spfg 88252080Spfg2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 89252080Spfg 90252080Spfg * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 91252080Spfg 'AMD Family 10 core'. 92252080Spfg 93221282Smm2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 94221282Smm 95221282Smm * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 96221282Smm and athlon64-sse3 as improved versions of k8, opteron and athlon64 97221282Smm with SSE3 instruction set support. 98221282Smm * doc/invoke.texi: Likewise. 99221282Smm 100252080Spfg2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 101252080Spfg 102252080Spfg * config/i386/i386.c (override_options): Tuning 32-byte loop 103252080Spfg alignment for amdfam10 architecture. Increasing the max loop 104252080Spfg alignment to 24 bytes. 105252080Spfg 106259705Spfg2007-04-16 Lawrence Crowl <crowl@google.com> (r123909) 107259269Spfg 108259269Spfg * doc/invoke.texi (Debugging Options): Add documentation for the 109259269Spfg -femit-struct-debug options -femit-struct-debug-baseonly, 110259269Spfg -femit-struct-debug-reduced, and 111259269Spfg -femit-struct-debug-detailed[=...]. 112259269Spfg 113259269Spfg * c-opts.c (c_common_handle_option): Add 114259269Spfg OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced, 115259269Spfg and OPT_femit_struct_debug_detailed_. 116259269Spfg * c.opt: Add specifications for 117259269Spfg -femit-struct-debug-baseonly, -femit-struct-debug-reduced, 118259269Spfg and -femit-struct-debug-detailed[=...]. 119259269Spfg * opts.c (set_struct_debug_option): Parse the 120259269Spfg -femit-struct-debug-... options. 121259269Spfg * opts.c (matches_main_base, main_input_basename, 122259269Spfg main_input_baselength, base_of_path, matches_main_base): Add 123259269Spfg variables and functions to compare header base name to compilation 124259269Spfg unit base name. 125259269Spfg * opts.c (should_emit_struct_debug): Add to determine to emit a 126259269Spfg structure based on the option. 127259269Spfg (dump_struct_debug) Also disabled function to debug this 128259269Spfg function. 129259269Spfg * opts.c (handle_options): Save the base name of the 130259269Spfg compilation unit. 131259269Spfg 132259269Spfg * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define. 133259269Spfg (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add. 134259269Spfg This hook indicates if a type is generic. Set it by default 135259269Spfg to "never generic". 136259269Spfg * langhooks.h (struct lang_hooks_for_types): Add a new hook 137259269Spfg to determine if a struct type is generic or not. 138259269Spfg * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook. 139259269Spfg * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook. 140259269Spfg * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook 141259269Spfg with live C++ hook. 142259269Spfg 143259269Spfg * flags.h (enum debug_info_usage): Add an enumeration to describe 144259269Spfg a program's use of a structure type. 145259269Spfg * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter 146259269Spfg to indicate the program's usage of the type. Filter structs based 147259269Spfg on the -femit-struct-debug-... specification. 148259269Spfg (gen_type_die): Split into two routines, gen_type_die and 149259269Spfg gen_type_die_with_usage. gen_type_die is now a wrapper 150259269Spfg that assumes direct usage. 151259269Spfg (gen_type_die_with_usage): Replace calls to gen_type_die 152259269Spfg with gen_type_die_with_usage adding the program usage of 153259269Spfg the referenced type. 154259269Spfg (dwarf2out_imported_module_or_decl): Suppress struct debug 155259269Spfg information using should_emit_struct_debug when appropriate. 156259269Spfg 157237678Spfg2007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 158237678Spfg 159237678Spfg PR tree-optimization/24689 160237678Spfg PR tree-optimization/31307 161237678Spfg * fold-const.c (operand_equal_p): Compare INTEGER_CST array 162237678Spfg indices by value. 163237678Spfg * gimplify.c (canonicalize_addr_expr): To be consistent with 164237678Spfg gimplify_compound_lval only set operands two and three of 165237678Spfg ARRAY_REFs if they are not gimple_min_invariant. This makes 166237678Spfg it never at this place. 167237678Spfg * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 168237678Spfg 169221282Smm2007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 170221282Smm 171221282Smm * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 172221282Smm 173252080Spfg2007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 174252080Spfg 175252080Spfg * config.gcc: Accept barcelona as a variant of amdfam10. 176252080Spfg * config/i386/i386.c (override_options): Likewise. 177252080Spfg * doc/invoke.texi: Likewise. 178252080Spfg 179259705Spfg2007-03-12 Seongbae Park <seongbae.park@gmail.com> (r122851) 180259269Spfg 181259269Spfg * c-decl.c (warn_variable_length_array): New function. 182259269Spfg Refactored from grokdeclarator to handle warn_vla 183259269Spfg and handle unnamed array case. 184259269Spfg (grokdeclarator): Refactored VLA warning case. 185259269Spfg * c.opt (Wvla): New flag. 186259269Spfg 187259269Spfg2007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 188259269Spfg 189259269Spfg * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 190259269Spfg the *_DIV_EXPR codes correctly with overflow infinities. 191259269Spfg 192252080Spfg2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 193252080Spfg 194252080Spfg * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 195252080Spfg (bit_SSE4a): New. 196252080Spfg 197221282Smm2007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 198221282Smm 199221282Smm * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 200221282Smm conditional to __SSE2__. 201221282Smm (Entries below should have been added to first ChangeLog 202221282Smm entry for amdfam10 dated 2007-02-05) 203221282Smm * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 204221282Smm defined. 205221282Smm * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 206221282Smm defined. 207221282Smm * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 208221282Smm defined. 209221282Smm 210221282Smm2007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 211221282Smm 212221282Smm * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 213221282Smm 214252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 215252080Spfg 216252080Spfg * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 217252080Spfg athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 218252080Spfg athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 219252080Spfg athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 220252080Spfg athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 221252080Spfg athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 222252080Spfg athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 223252080Spfg athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 224252080Spfg 225252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 226252080Spfg 227252080Spfg * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 228252080Spfg cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 229252080Spfg swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 230252080Spfg fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 231252080Spfg x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 232252080Spfg floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 233252080Spfg floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 234252080Spfg mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 235252080Spfg umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 236252080Spfg umuldi3_highpart_rex64, umulsi3_highpart_insn, 237252080Spfg umulsi3_highpart_zext, smuldi3_highpart_rex64, 238252080Spfg smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 239252080Spfg x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 240252080Spfg sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 241252080Spfg sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 242252080Spfg sqrtextenddfxf2_i387): Added amdfam10_decode. 243252080Spfg 244252080Spfg * config/i386/athlon.md (athlon_idirect_amdfam10, 245252080Spfg athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 246252080Spfg athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 247252080Spfg athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 248252080Spfg athlon_ivector_store_amdfam10): New define_insn_reservation. 249252080Spfg (athlon_idirect_loadmov, athlon_idirect_movstore): Added 250252080Spfg amdfam10. 251252080Spfg 252252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 253252080Spfg 254252080Spfg * config/i386/athlon.md (athlon_call_amdfam10, 255252080Spfg athlon_pop_amdfam10, athlon_lea_amdfam10): New 256252080Spfg define_insn_reservation. 257252080Spfg (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 258252080Spfg athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 259252080Spfg athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 260252080Spfg 261252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 262252080Spfg 263252080Spfg * config/i386/athlon.md (athlon_sseld_amdfam10, 264252080Spfg athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 265252080Spfg athlon_mmxssest_short_amdfam10): New define_insn_reservation. 266252080Spfg 267252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 268252080Spfg 269252080Spfg * config/i386/athlon.md (athlon_sseins_amdfam10): New 270252080Spfg define_insn_reservation. 271252080Spfg * config/i386/i386.md (sseins): Added sseins to define_attr type 272252080Spfg and define_attr unit. 273252080Spfg * config/i386/sse.md: Set type attribute to sseins for insertq 274252080Spfg and insertqi. 275252080Spfg 276252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 277252080Spfg 278252080Spfg * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 279252080Spfg ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 280252080Spfg ssecomi_load_amdfam10, ssecomi_amdfam10, 281252080Spfg sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 282252080Spfg define_insn_reservation. 283252080Spfg (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 284252080Spfg 285252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 286252080Spfg 287252080Spfg * config/i386/athlon.md (cvtss2sd_load_amdfam10, 288252080Spfg cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 289252080Spfg cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 290252080Spfg cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 291252080Spfg cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 292252080Spfg cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 293252080Spfg define_insn_reservation. 294252080Spfg 295252080Spfg * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 296252080Spfg cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 297252080Spfg cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 298252080Spfg cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 299252080Spfg cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 300252080Spfg 301252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 302252080Spfg 303252080Spfg * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 304252080Spfg athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 305252080Spfg athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 306252080Spfg (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 307252080Spfg athlon_ssemul_load_k8): Added amdfam10. 308252080Spfg 309252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 310252080Spfg 311252080Spfg * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 312252080Spfg (x86_sse_unaligned_move_optimal): New variable. 313252080Spfg 314252080Spfg * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 315252080Spfg m_AMDFAM10. 316252080Spfg (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 317252080Spfg for unaligned vector SSE double/single precision loads for AMDFAM10. 318252080Spfg 319252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 320252080Spfg 321252080Spfg * config/i386/i386.h (TARGET_AMDFAM10): New macro. 322252080Spfg (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 323252080Spfg Define TARGET_CPU_DEFAULT_amdfam10. 324252080Spfg (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 325252080Spfg (processor_type): Add PROCESSOR_AMDFAM10. 326252080Spfg 327252080Spfg * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 328252080Spfg processor_type in config/i386/i386.h. 329252080Spfg Enable imul peepholes for TARGET_AMDFAM10. 330252080Spfg 331252080Spfg * config.gcc: Add support for --with-cpu option for amdfam10. 332252080Spfg 333252080Spfg * config/i386/i386.c (amdfam10_cost): New variable. 334252080Spfg (m_AMDFAM10): New macro. 335252080Spfg (m_ATHLON_K8_AMDFAM10): New macro. 336252080Spfg (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 337252080Spfg x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 338252080Spfg x86_promote_QImode, x86_integer_DFmode_moves, 339252080Spfg x86_partial_reg_dependency, x86_memory_mismatch_stall, 340252080Spfg x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 341252080Spfg x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 342252080Spfg x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 343252080Spfg x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 344252080Spfg Enable/disable for amdfam10. 345252080Spfg (override_options): Add amdfam10_cost to processor_target_table. 346252080Spfg Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 347252080Spfg processor_alias_table. 348252080Spfg (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 349252080Spfg (ix86_adjust_cost): Add code for amdfam10. 350252080Spfg 351252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 352252080Spfg 353252080Spfg * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 354252080Spfg instruction set feature flag. Add new (-mpopcnt) flag for popcnt 355252080Spfg instruction. Add new SSE4A (-msse4a) instruction set feature flag. 356252080Spfg * config/i386/i386.h: Add builtin definition for SSE4A. 357252080Spfg * config/i386/i386.md: Add support for ABM instructions 358252080Spfg (popcnt and lzcnt). 359252080Spfg * config/i386/sse.md: Add support for SSE4A instructions 360252080Spfg (movntss, movntsd, extrq, insertq). 361252080Spfg * config/i386/i386.c: Add support for ABM and SSE4A builtins. 362252080Spfg Add -march=amdfam10 flag. 363252080Spfg * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 364252080Spfg * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 365252080Spfg and amdfam10. 366252080Spfg * doc/extend.texi: Add documentation for SSE4A builtins. 367252080Spfg 368252080Spfg2007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 369252080Spfg 370252080Spfg * config/i386/i386.h (x86_cmpxchg16b): Remove const. 371252080Spfg (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 372252080Spfg * config/i386/i386.c (x86_cmpxchg16b): Remove const. 373252080Spfg (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 374252080Spfg for CPUs that have PTA_CX16 set. 375252080Spfg 376221282Smm2007-01-17 Eric Christopher <echristo@apple.com> (r120846) 377221282Smm 378221282Smm * config.gcc: Support core2 processor. 379221282Smm 380259705Spfg2007-01-05 Manuel Lopez-Ibanez <manu@gcc.gnu.org> (r120505) 381259585Spfg 382259585Spfg PR c/19978 383259585Spfg * tree.h (TREE_OVERFLOW_P): New. 384259585Spfg * c-typeck.c (parser_build_unary_op): Warn only if result 385259585Spfg overflowed and operands did not. 386259585Spfg (parser_build_binary_op): Likewise. 387259585Spfg (convert_for_assignment): Remove redundant overflow_warning. 388259585Spfg * c-common.c (overflow_warning): Don't check or set TREE_OVERFLOW. 389259585Spfg 390259269Spfg2006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 391259269Spfg 392259269Spfg PR c++/19564 393259269Spfg PR c++/19756 394259269Spfg * c-typeck.c (parser_build_binary_op): Move parentheses warnings 395259269Spfg to warn_about_parentheses in c-common.c. 396259269Spfg * c-common.c (warn_about_parentheses): New function. 397259269Spfg * c-common.h (warn_about_parentheses): Declare. 398259269Spfg * doc/invoke.texi (Warning Options): Update -Wparentheses 399259269Spfg description. 400259269Spfg 401221282Smm2006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 402221282Smm 403221282Smm PR target/30040 404221282Smm * config/i386/driver-i386.c (bit_SSSE3): New. 405221282Smm 406252080Spfg2006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 407252080Spfg 408252080Spfg * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 409252080Spfg and m_GENERIC64. 410252080Spfg 411221282Smm2006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 412221282Smm 413221282Smm * doc/invoke.texi (core2): Add item. 414221282Smm 415221282Smm * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 416221282Smm macros. 417221282Smm (TARGET_CPU_CPP_BUILTINS): Add code for core2. 418221282Smm (TARGET_CPU_DEFAULT_generic): Change value. 419221282Smm (TARGET_CPU_DEFAULT_NAMES): Add core2. 420221282Smm (processor_type): Add new constant PROCESSOR_CORE2. 421221282Smm 422221282Smm * config/i386/i386.md (cpu): Add core2. 423221282Smm 424221282Smm * config/i386/i386.c (core2_cost): New initialized variable. 425221282Smm (m_CORE2): New macro. 426221282Smm (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 427221282Smm x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 428221282Smm x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 429221282Smm x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 430221282Smm x86_partial_reg_dependency, x86_memory_mismatch_stall, 431221282Smm x86_accumulate_outgoing_args, x86_prologue_using_move, 432221282Smm x86_epilogue_using_move, x86_arch_always_fancy_math_387, 433221282Smm x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 434221282Smm x86_use_incdec, x86_four_jump_limit, x86_schedule, 435221282Smm x86_pad_returns): Add m_CORE2. 436221282Smm (override_options): Add entries for Core2. 437221282Smm (ix86_issue_rate): Add case for Core2. 438221282Smm 439259269Spfg2006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356) 440259269Spfg 441259269Spfg * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on 442259269Spfg inline static functions in c99 mode. 443259269Spfg 444259269Spfg PR 16622 445259269Spfg * doc/extend.texi (Inline): Update. 446259269Spfg * c-tree.h (struct language_function): Remove field 'extern_inline'. 447259269Spfg * c-decl.c (current_extern_inline): Delete. 448259269Spfg (pop_scope): Adjust test for an undefined nested function. 449259269Spfg Add warning about undeclared inline function. 450259269Spfg (diagnose_mismatched_decls): Update comments. Disallow overriding 451259269Spfg of inline functions in a translation unit in C99. Allow inline 452259269Spfg declarations in C99 at any time. 453259269Spfg (merge_decls): Boolize variables. Handle C99 'extern inline' 454259269Spfg semantics. 455259269Spfg (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle 456259269Spfg C99 inline semantics. 457259269Spfg (start_function): Don't clear current_extern_inline. Don't set 458259269Spfg DECL_EXTERNAL. 459259269Spfg (c_push_function_context): Don't push current_extern_inline. 460259269Spfg (c_pop_function_context): Don't restore current_extern_inline. 461259269Spfg 462259269Spfg PR 11377 463259269Spfg * c-typeck.c (build_external_ref): Warn about static variables 464259269Spfg used in extern inline functions. 465259269Spfg * c-decl.c (start_decl): Warn about static variables declared 466259269Spfg in extern inline functions. 467259269Spfg 468221282Smm2006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 469221282Smm 470221282Smm * config/i386/i386.h (TARGET_GEODE): 471221282Smm (TARGET_CPU_CPP_BUILTINS): Add code for geode. 472221282Smm (TARGET_CPU_DEFAULT_geode): New macro. 473221282Smm (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 474221282Smm TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 475221282Smm TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 476221282Smm TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 477221282Smm TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 478221282Smm the macro values. 479221282Smm (TARGET_CPU_DEFAULT_NAMES): Add geode. 480221282Smm (processor_type): Add PROCESSOR_GEODE. 481221282Smm 482221282Smm * config/i386/i386.md: Include geode.md. 483221282Smm (cpu): Add geode. 484221282Smm 485221282Smm * config/i386/i386.c (geode_cost): New initialized global 486221282Smm variable. 487221282Smm (m_GEODE, m_K6_GEODE): New macros. 488221282Smm (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 489221282Smm x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 490221282Smm x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 491221282Smm x86_schedule): Use m_K6_GEODE instead of m_K6. 492221282Smm (x86_movx, x86_cmove): Set up m_GEODE. 493221282Smm (x86_integer_DFmode_moves): Clear m_GEODE. 494221282Smm (processor_target_table): Add entry for geode. 495221282Smm (processor_alias_table): Ditto. 496221282Smm 497221282Smm * config/i386/geode.md: New file. 498221282Smm 499221282Smm * doc/invoke.texi: Add entry about geode processor. 500221282Smm 501237678Spfg2006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 502229554Spfg 503229554Spfg PR middle-end/28796 504229554Spfg * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 505229554Spfg and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 506229554Spfg for deciding optimizations in consistency with fold-const.c 507229554Spfg (fold_builtin_unordered_cmp): Likewise. 508229554Spfg 509221282Smm2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 510221282Smm 511221282Smm * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 512221282Smm (x86_64-*-*): Likewise. 513221282Smm 514221282Smm * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 515221282Smm (override_options): Check SSSE3. 516221282Smm (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 517221282Smm IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 518221282Smm IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 519221282Smm IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 520221282Smm IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 521221282Smm IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 522221282Smm IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 523221282Smm IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 524221282Smm IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 525221282Smm IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 526221282Smm IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 527221282Smm IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 528221282Smm IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 529221282Smm IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 530221282Smm IX86_BUILTIN_PABSD128. 531221282Smm (bdesc_2arg): Add SSSE3. 532221282Smm (bdesc_1arg): Likewise. 533221282Smm (ix86_init_mmx_sse_builtins): Support SSSE3. 534221282Smm (ix86_expand_builtin): Likewise. 535221282Smm * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 536221282Smm 537221282Smm * config/i386/i386.md (UNSPEC_PSHUFB): New. 538221282Smm (UNSPEC_PSIGN): Likewise. 539221282Smm (UNSPEC_PALIGNR): Likewise. 540221282Smm Include mmx.md before sse.md. 541221282Smm 542221282Smm * config/i386/i386.opt: Add -mssse3. 543221282Smm 544221282Smm * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 545221282Smm (ssse3_phaddwv4hi3): Likewise. 546221282Smm (ssse3_phadddv4si3): Likewise. 547221282Smm (ssse3_phadddv2si3): Likewise. 548221282Smm (ssse3_phaddswv8hi3): Likewise. 549221282Smm (ssse3_phaddswv4hi3): Likewise. 550221282Smm (ssse3_phsubwv8hi3): Likewise. 551221282Smm (ssse3_phsubwv4hi3): Likewise. 552221282Smm (ssse3_phsubdv4si3): Likewise. 553221282Smm (ssse3_phsubdv2si3): Likewise. 554221282Smm (ssse3_phsubswv8hi3): Likewise. 555221282Smm (ssse3_phsubswv4hi3): Likewise. 556221282Smm (ssse3_pmaddubswv8hi3): Likewise. 557221282Smm (ssse3_pmaddubswv4hi3): Likewise. 558221282Smm (ssse3_pmulhrswv8hi3): Likewise. 559221282Smm (ssse3_pmulhrswv4hi3): Likewise. 560221282Smm (ssse3_pshufbv16qi3): Likewise. 561221282Smm (ssse3_pshufbv8qi3): Likewise. 562221282Smm (ssse3_psign<mode>3): Likewise. 563221282Smm (ssse3_psign<mode>3): Likewise. 564221282Smm (ssse3_palignrti): Likewise. 565221282Smm (ssse3_palignrdi): Likewise. 566221282Smm (abs<mode>2): Likewise. 567221282Smm (abs<mode>2): Likewise. 568221282Smm 569221282Smm * config/i386/tmmintrin.h: New file. 570221282Smm 571221282Smm * doc/extend.texi: Document SSSE3 built-in functions. 572221282Smm 573221282Smm * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 574234023Spfg 575252080Spfg2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 576250676Spfg 577250676Spfg * config/i386/tmmintrin.h: Remove the duplicated content. 578250676Spfg 579237678Spfg2006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 580234023Spfg 581237678Spfg PR tree-optimization/3511 582237678Spfg * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 583237678Spfg got new invariant arguments during PHI translation. 584237678Spfg 585237678Spfg2006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 586237678Spfg 587234023Spfg * builtins.c (fold_builtin_classify): Fix typo. 588234023Spfg 589