ChangeLog.gcc43 revision 259705
12007-08-08 Andrew Haley <aph@redhat.com> (r128087) 2 3 * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New. 4 * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New. 5 * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New. 6 72007-07-12 Geoffrey Keating <geoffk@apple.com> (r126588) 8 9 * builtins.c (get_pointer_alignment): Honor DECL_ALIGN on a 10 FUNCTION_DECL. 11 * tree.c (build_decl_stat): Move code from here... 12 (make_node_stat): ... to here. Don't uselessly clear DECL_USER_ALIGN. 13 (expr_align): Honor DECL_ALIGN on a FUNCTION_DECL. Add comment 14 about using DECL_ALIGN of LABEL_DECL and CONST_DECL. 15 * tree.h (DECL_USER_ALIGN): Fix misplaced comment. 16 * varasm.c (assemble_start_function): Use DECL_ALIGN instead of 17 FUNCTION_BOUNDARY. 18 192007-07-09 Geoffrey Keating <geoffk@apple.com> (r126529) 20 21 PR 32617 22 * c-common.c (c_alignof_expr): Look at DECL_ALIGN of 23 FUNCTION_DECLs. 24 (handle_aligned_attribute): Allow use on FUNCTION_DECLs. 25 * varasm.c (assemble_start_function): Honor DECL_ALIGN 26 for FUNCTION_DECLs. Don't use align_functions_log if 27 DECL_USER_ALIGN. 28 * print-tree.c (print_node): Print DECL_ALIGN and DECL_USER_ALIGN 29 even for FUNCTION_DECLs. 30 * c-decl.c (merge_decls): Propagate DECL_ALIGN even for 31 FUNCTION_DECLs. 32 * tree.h (DECL_ALIGN): Update for new location of 'align'. 33 (DECL_FUNCTION_CODE): Update for new location and name of 34 'function_code'. 35 (DECL_OFFSET_ALIGN): Update for new location of 'off_align'. 36 (struct tree_decl_common): Move 'align' and 'off_align' out 37 of union, ensure they're still on a 32-bit boundary. Remove 38 other fields in union 'u1'. 39 (struct tree_function_decl): Add field 'function_code' replacing 40 'u1.f' in tree_decl_common. 41 * tree.c (build_decl_stat): Set initial value of DECL_ALIGN. 42 * doc/extend.texi (Function Attributes): Add 'aligned' attribute. 43 (Variable Attributes): Cross-reference 'aligned' attribute 44 to Function Attributes. 45 * flags.h (force_align_functions_log): Delete. 46 * toplev.c (force_align_functions_log): Delete. 47 482007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346) 49 50 PR preprocessor/23479 51 * doc/extend.texi: Document the 0b-prefixed binary integer 52 constant extension. 53 542007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037) 55 56 * postreload-gcse.c (reg_changed_after_insn_p): New function. 57 (oprs_unchanged_p): Use it to check all registers in a REG. 58 (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE. 59 (reg_set_between_after_reload_p): Delete. 60 (reg_used_between_after_reload_p): Likewise. 61 (reg_set_or_used_since_bb_start): Likewise. 62 (eliminate_partially_redundant_load): Use reg_changed_after_insn_p 63 and reg_used_between_p instead of reg_set_or_used_since_bb_start. 64 Use reg_set_between_p instead of reg_set_between_after_reload_p. 65 * rtlanal.c (reg_set_p): Check whether REG overlaps 66 regs_invalidated_by_call, rather than just checking the 67 membership of REGNO (REG). 68 692007-05-03 Ian Lance Taylor <iant@google.com> (r124381) 70 71 * config/rs6000/rs6000.c (rs6000_override_options): Don't set 72 MASK_PPC_GFXOPT for 8540 or 8548. 73 742007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 75 76 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 77 'AMD Family 10 core'. 78 792007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 80 81 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 82 and athlon64-sse3 as improved versions of k8, opteron and athlon64 83 with SSE3 instruction set support. 84 * doc/invoke.texi: Likewise. 85 862007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 87 88 * config/i386/i386.c (override_options): Tuning 32-byte loop 89 alignment for amdfam10 architecture. Increasing the max loop 90 alignment to 24 bytes. 91 922007-04-16 Lawrence Crowl <crowl@google.com> (r123909) 93 94 * doc/invoke.texi (Debugging Options): Add documentation for the 95 -femit-struct-debug options -femit-struct-debug-baseonly, 96 -femit-struct-debug-reduced, and 97 -femit-struct-debug-detailed[=...]. 98 99 * c-opts.c (c_common_handle_option): Add 100 OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced, 101 and OPT_femit_struct_debug_detailed_. 102 * c.opt: Add specifications for 103 -femit-struct-debug-baseonly, -femit-struct-debug-reduced, 104 and -femit-struct-debug-detailed[=...]. 105 * opts.c (set_struct_debug_option): Parse the 106 -femit-struct-debug-... options. 107 * opts.c (matches_main_base, main_input_basename, 108 main_input_baselength, base_of_path, matches_main_base): Add 109 variables and functions to compare header base name to compilation 110 unit base name. 111 * opts.c (should_emit_struct_debug): Add to determine to emit a 112 structure based on the option. 113 (dump_struct_debug) Also disabled function to debug this 114 function. 115 * opts.c (handle_options): Save the base name of the 116 compilation unit. 117 118 * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define. 119 (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add. 120 This hook indicates if a type is generic. Set it by default 121 to "never generic". 122 * langhooks.h (struct lang_hooks_for_types): Add a new hook 123 to determine if a struct type is generic or not. 124 * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook. 125 * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook. 126 * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook 127 with live C++ hook. 128 129 * flags.h (enum debug_info_usage): Add an enumeration to describe 130 a program's use of a structure type. 131 * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter 132 to indicate the program's usage of the type. Filter structs based 133 on the -femit-struct-debug-... specification. 134 (gen_type_die): Split into two routines, gen_type_die and 135 gen_type_die_with_usage. gen_type_die is now a wrapper 136 that assumes direct usage. 137 (gen_type_die_with_usage): Replace calls to gen_type_die 138 with gen_type_die_with_usage adding the program usage of 139 the referenced type. 140 (dwarf2out_imported_module_or_decl): Suppress struct debug 141 information using should_emit_struct_debug when appropriate. 142 1432007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 144 145 PR tree-optimization/24689 146 PR tree-optimization/31307 147 * fold-const.c (operand_equal_p): Compare INTEGER_CST array 148 indices by value. 149 * gimplify.c (canonicalize_addr_expr): To be consistent with 150 gimplify_compound_lval only set operands two and three of 151 ARRAY_REFs if they are not gimple_min_invariant. This makes 152 it never at this place. 153 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 154 1552007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 156 157 * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 158 1592007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 160 161 * config.gcc: Accept barcelona as a variant of amdfam10. 162 * config/i386/i386.c (override_options): Likewise. 163 * doc/invoke.texi: Likewise. 164 1652007-03-12 Seongbae Park <seongbae.park@gmail.com> (r122851) 166 167 * c-decl.c (warn_variable_length_array): New function. 168 Refactored from grokdeclarator to handle warn_vla 169 and handle unnamed array case. 170 (grokdeclarator): Refactored VLA warning case. 171 * c.opt (Wvla): New flag. 172 1732007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 174 175 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 176 the *_DIV_EXPR codes correctly with overflow infinities. 177 1782007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 179 180 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 181 (bit_SSE4a): New. 182 1832007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 184 185 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 186 conditional to __SSE2__. 187 (Entries below should have been added to first ChangeLog 188 entry for amdfam10 dated 2007-02-05) 189 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 190 defined. 191 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 192 defined. 193 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 194 defined. 195 1962007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 197 198 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 199 2002007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 201 202 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 203 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 204 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 205 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 206 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 207 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 208 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 209 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 210 2112007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 212 213 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 214 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 215 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 216 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 217 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 218 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 219 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 220 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 221 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 222 umuldi3_highpart_rex64, umulsi3_highpart_insn, 223 umulsi3_highpart_zext, smuldi3_highpart_rex64, 224 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 225 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 226 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 227 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 228 sqrtextenddfxf2_i387): Added amdfam10_decode. 229 230 * config/i386/athlon.md (athlon_idirect_amdfam10, 231 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 232 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 233 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 234 athlon_ivector_store_amdfam10): New define_insn_reservation. 235 (athlon_idirect_loadmov, athlon_idirect_movstore): Added 236 amdfam10. 237 2382007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 239 240 * config/i386/athlon.md (athlon_call_amdfam10, 241 athlon_pop_amdfam10, athlon_lea_amdfam10): New 242 define_insn_reservation. 243 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 244 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 245 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 246 2472007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 248 249 * config/i386/athlon.md (athlon_sseld_amdfam10, 250 athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 251 athlon_mmxssest_short_amdfam10): New define_insn_reservation. 252 2532007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 254 255 * config/i386/athlon.md (athlon_sseins_amdfam10): New 256 define_insn_reservation. 257 * config/i386/i386.md (sseins): Added sseins to define_attr type 258 and define_attr unit. 259 * config/i386/sse.md: Set type attribute to sseins for insertq 260 and insertqi. 261 2622007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 263 264 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 265 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 266 ssecomi_load_amdfam10, ssecomi_amdfam10, 267 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 268 define_insn_reservation. 269 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 270 2712007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 272 273 * config/i386/athlon.md (cvtss2sd_load_amdfam10, 274 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 275 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 276 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 277 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 278 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 279 define_insn_reservation. 280 281 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 282 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 283 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 284 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 285 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 286 2872007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 288 289 * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 290 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 291 athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 292 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 293 athlon_ssemul_load_k8): Added amdfam10. 294 2952007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 296 297 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 298 (x86_sse_unaligned_move_optimal): New variable. 299 300 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 301 m_AMDFAM10. 302 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 303 for unaligned vector SSE double/single precision loads for AMDFAM10. 304 3052007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 306 307 * config/i386/i386.h (TARGET_AMDFAM10): New macro. 308 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 309 Define TARGET_CPU_DEFAULT_amdfam10. 310 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 311 (processor_type): Add PROCESSOR_AMDFAM10. 312 313 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 314 processor_type in config/i386/i386.h. 315 Enable imul peepholes for TARGET_AMDFAM10. 316 317 * config.gcc: Add support for --with-cpu option for amdfam10. 318 319 * config/i386/i386.c (amdfam10_cost): New variable. 320 (m_AMDFAM10): New macro. 321 (m_ATHLON_K8_AMDFAM10): New macro. 322 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 323 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 324 x86_promote_QImode, x86_integer_DFmode_moves, 325 x86_partial_reg_dependency, x86_memory_mismatch_stall, 326 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 327 x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 328 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 329 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 330 Enable/disable for amdfam10. 331 (override_options): Add amdfam10_cost to processor_target_table. 332 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 333 processor_alias_table. 334 (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 335 (ix86_adjust_cost): Add code for amdfam10. 336 3372007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 338 339 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 340 instruction set feature flag. Add new (-mpopcnt) flag for popcnt 341 instruction. Add new SSE4A (-msse4a) instruction set feature flag. 342 * config/i386/i386.h: Add builtin definition for SSE4A. 343 * config/i386/i386.md: Add support for ABM instructions 344 (popcnt and lzcnt). 345 * config/i386/sse.md: Add support for SSE4A instructions 346 (movntss, movntsd, extrq, insertq). 347 * config/i386/i386.c: Add support for ABM and SSE4A builtins. 348 Add -march=amdfam10 flag. 349 * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 350 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 351 and amdfam10. 352 * doc/extend.texi: Add documentation for SSE4A builtins. 353 3542007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 355 356 * config/i386/i386.h (x86_cmpxchg16b): Remove const. 357 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 358 * config/i386/i386.c (x86_cmpxchg16b): Remove const. 359 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 360 for CPUs that have PTA_CX16 set. 361 3622007-01-17 Eric Christopher <echristo@apple.com> (r120846) 363 364 * config.gcc: Support core2 processor. 365 3662007-01-05 Manuel Lopez-Ibanez <manu@gcc.gnu.org> (r120505) 367 368 PR c/19978 369 * tree.h (TREE_OVERFLOW_P): New. 370 * c-typeck.c (parser_build_unary_op): Warn only if result 371 overflowed and operands did not. 372 (parser_build_binary_op): Likewise. 373 (convert_for_assignment): Remove redundant overflow_warning. 374 * c-common.c (overflow_warning): Don't check or set TREE_OVERFLOW. 375 3762006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 377 378 PR c++/19564 379 PR c++/19756 380 * c-typeck.c (parser_build_binary_op): Move parentheses warnings 381 to warn_about_parentheses in c-common.c. 382 * c-common.c (warn_about_parentheses): New function. 383 * c-common.h (warn_about_parentheses): Declare. 384 * doc/invoke.texi (Warning Options): Update -Wparentheses 385 description. 386 3872006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 388 389 PR target/30040 390 * config/i386/driver-i386.c (bit_SSSE3): New. 391 3922006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 393 394 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 395 and m_GENERIC64. 396 3972006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 398 399 * doc/invoke.texi (core2): Add item. 400 401 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 402 macros. 403 (TARGET_CPU_CPP_BUILTINS): Add code for core2. 404 (TARGET_CPU_DEFAULT_generic): Change value. 405 (TARGET_CPU_DEFAULT_NAMES): Add core2. 406 (processor_type): Add new constant PROCESSOR_CORE2. 407 408 * config/i386/i386.md (cpu): Add core2. 409 410 * config/i386/i386.c (core2_cost): New initialized variable. 411 (m_CORE2): New macro. 412 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 413 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 414 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 415 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 416 x86_partial_reg_dependency, x86_memory_mismatch_stall, 417 x86_accumulate_outgoing_args, x86_prologue_using_move, 418 x86_epilogue_using_move, x86_arch_always_fancy_math_387, 419 x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 420 x86_use_incdec, x86_four_jump_limit, x86_schedule, 421 x86_pad_returns): Add m_CORE2. 422 (override_options): Add entries for Core2. 423 (ix86_issue_rate): Add case for Core2. 424 4252006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356) 426 427 * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on 428 inline static functions in c99 mode. 429 430 PR 16622 431 * doc/extend.texi (Inline): Update. 432 * c-tree.h (struct language_function): Remove field 'extern_inline'. 433 * c-decl.c (current_extern_inline): Delete. 434 (pop_scope): Adjust test for an undefined nested function. 435 Add warning about undeclared inline function. 436 (diagnose_mismatched_decls): Update comments. Disallow overriding 437 of inline functions in a translation unit in C99. Allow inline 438 declarations in C99 at any time. 439 (merge_decls): Boolize variables. Handle C99 'extern inline' 440 semantics. 441 (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle 442 C99 inline semantics. 443 (start_function): Don't clear current_extern_inline. Don't set 444 DECL_EXTERNAL. 445 (c_push_function_context): Don't push current_extern_inline. 446 (c_pop_function_context): Don't restore current_extern_inline. 447 448 PR 11377 449 * c-typeck.c (build_external_ref): Warn about static variables 450 used in extern inline functions. 451 * c-decl.c (start_decl): Warn about static variables declared 452 in extern inline functions. 453 4542006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 455 456 * config/i386/i386.h (TARGET_GEODE): 457 (TARGET_CPU_CPP_BUILTINS): Add code for geode. 458 (TARGET_CPU_DEFAULT_geode): New macro. 459 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 460 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 461 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 462 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 463 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 464 the macro values. 465 (TARGET_CPU_DEFAULT_NAMES): Add geode. 466 (processor_type): Add PROCESSOR_GEODE. 467 468 * config/i386/i386.md: Include geode.md. 469 (cpu): Add geode. 470 471 * config/i386/i386.c (geode_cost): New initialized global 472 variable. 473 (m_GEODE, m_K6_GEODE): New macros. 474 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 475 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 476 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 477 x86_schedule): Use m_K6_GEODE instead of m_K6. 478 (x86_movx, x86_cmove): Set up m_GEODE. 479 (x86_integer_DFmode_moves): Clear m_GEODE. 480 (processor_target_table): Add entry for geode. 481 (processor_alias_table): Ditto. 482 483 * config/i386/geode.md: New file. 484 485 * doc/invoke.texi: Add entry about geode processor. 486 4872006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 488 489 PR middle-end/28796 490 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 491 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 492 for deciding optimizations in consistency with fold-const.c 493 (fold_builtin_unordered_cmp): Likewise. 494 4952006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 496 497 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 498 (x86_64-*-*): Likewise. 499 500 * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 501 (override_options): Check SSSE3. 502 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 503 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 504 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 505 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 506 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 507 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 508 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 509 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 510 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 511 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 512 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 513 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 514 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 515 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 516 IX86_BUILTIN_PABSD128. 517 (bdesc_2arg): Add SSSE3. 518 (bdesc_1arg): Likewise. 519 (ix86_init_mmx_sse_builtins): Support SSSE3. 520 (ix86_expand_builtin): Likewise. 521 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 522 523 * config/i386/i386.md (UNSPEC_PSHUFB): New. 524 (UNSPEC_PSIGN): Likewise. 525 (UNSPEC_PALIGNR): Likewise. 526 Include mmx.md before sse.md. 527 528 * config/i386/i386.opt: Add -mssse3. 529 530 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 531 (ssse3_phaddwv4hi3): Likewise. 532 (ssse3_phadddv4si3): Likewise. 533 (ssse3_phadddv2si3): Likewise. 534 (ssse3_phaddswv8hi3): Likewise. 535 (ssse3_phaddswv4hi3): Likewise. 536 (ssse3_phsubwv8hi3): Likewise. 537 (ssse3_phsubwv4hi3): Likewise. 538 (ssse3_phsubdv4si3): Likewise. 539 (ssse3_phsubdv2si3): Likewise. 540 (ssse3_phsubswv8hi3): Likewise. 541 (ssse3_phsubswv4hi3): Likewise. 542 (ssse3_pmaddubswv8hi3): Likewise. 543 (ssse3_pmaddubswv4hi3): Likewise. 544 (ssse3_pmulhrswv8hi3): Likewise. 545 (ssse3_pmulhrswv4hi3): Likewise. 546 (ssse3_pshufbv16qi3): Likewise. 547 (ssse3_pshufbv8qi3): Likewise. 548 (ssse3_psign<mode>3): Likewise. 549 (ssse3_psign<mode>3): Likewise. 550 (ssse3_palignrti): Likewise. 551 (ssse3_palignrdi): Likewise. 552 (abs<mode>2): Likewise. 553 (abs<mode>2): Likewise. 554 555 * config/i386/tmmintrin.h: New file. 556 557 * doc/extend.texi: Document SSSE3 built-in functions. 558 559 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 560 5612006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 562 563 * config/i386/tmmintrin.h: Remove the duplicated content. 564 5652006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 566 567 PR tree-optimization/3511 568 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 569 got new invariant arguments during PHI translation. 570 5712006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 572 573 * builtins.c (fold_builtin_classify): Fix typo. 574 575