ChangeLog.gcc43 revision 255252
1255252Spfg2007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r23479) 2255252Spfg 3255252Spfg PR preprocessor/23479 4255252Spfg * doc/extend.texi: Document the 0b-prefixed binary integer 5255252Spfg constant extension. 6255252Spfg 7252080Spfg2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 8252080Spfg 9252080Spfg * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 10252080Spfg 'AMD Family 10 core'. 11252080Spfg 12221282Smm2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 13221282Smm 14221282Smm * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 15221282Smm and athlon64-sse3 as improved versions of k8, opteron and athlon64 16221282Smm with SSE3 instruction set support. 17221282Smm * doc/invoke.texi: Likewise. 18221282Smm 19252080Spfg2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 20252080Spfg 21252080Spfg * config/i386/i386.c (override_options): Tuning 32-byte loop 22252080Spfg alignment for amdfam10 architecture. Increasing the max loop 23252080Spfg alignment to 24 bytes. 24252080Spfg 25237678Spfg2007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 26237678Spfg 27237678Spfg PR tree-optimization/24689 28237678Spfg PR tree-optimization/31307 29237678Spfg * fold-const.c (operand_equal_p): Compare INTEGER_CST array 30237678Spfg indices by value. 31237678Spfg * gimplify.c (canonicalize_addr_expr): To be consistent with 32237678Spfg gimplify_compound_lval only set operands two and three of 33237678Spfg ARRAY_REFs if they are not gimple_min_invariant. This makes 34237678Spfg it never at this place. 35237678Spfg * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 36237678Spfg 37221282Smm2007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 38221282Smm 39221282Smm * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 40221282Smm 41252080Spfg2007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 42252080Spfg 43252080Spfg * config.gcc: Accept barcelona as a variant of amdfam10. 44252080Spfg * config/i386/i386.c (override_options): Likewise. 45252080Spfg * doc/invoke.texi: Likewise. 46252080Spfg 47252080Spfg2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 48252080Spfg 49252080Spfg * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 50252080Spfg (bit_SSE4a): New. 51252080Spfg 52221282Smm2007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 53221282Smm 54221282Smm * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 55221282Smm conditional to __SSE2__. 56221282Smm (Entries below should have been added to first ChangeLog 57221282Smm entry for amdfam10 dated 2007-02-05) 58221282Smm * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 59221282Smm defined. 60221282Smm * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 61221282Smm defined. 62221282Smm * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 63221282Smm defined. 64221282Smm 65221282Smm2007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 66221282Smm 67221282Smm * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 68221282Smm 69252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 70252080Spfg 71252080Spfg * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 72252080Spfg athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 73252080Spfg athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 74252080Spfg athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 75252080Spfg athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 76252080Spfg athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 77252080Spfg athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 78252080Spfg athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 79252080Spfg 80252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 81252080Spfg 82252080Spfg * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 83252080Spfg cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 84252080Spfg swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 85252080Spfg fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 86252080Spfg x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 87252080Spfg floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 88252080Spfg floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 89252080Spfg mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 90252080Spfg umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 91252080Spfg umuldi3_highpart_rex64, umulsi3_highpart_insn, 92252080Spfg umulsi3_highpart_zext, smuldi3_highpart_rex64, 93252080Spfg smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 94252080Spfg x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 95252080Spfg sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 96252080Spfg sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 97252080Spfg sqrtextenddfxf2_i387): Added amdfam10_decode. 98252080Spfg 99252080Spfg * config/i386/athlon.md (athlon_idirect_amdfam10, 100252080Spfg athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 101252080Spfg athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 102252080Spfg athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 103252080Spfg athlon_ivector_store_amdfam10): New define_insn_reservation. 104252080Spfg (athlon_idirect_loadmov, athlon_idirect_movstore): Added 105252080Spfg amdfam10. 106252080Spfg 107252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 108252080Spfg 109252080Spfg * config/i386/athlon.md (athlon_call_amdfam10, 110252080Spfg athlon_pop_amdfam10, athlon_lea_amdfam10): New 111252080Spfg define_insn_reservation. 112252080Spfg (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 113252080Spfg athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 114252080Spfg athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 115252080Spfg 116252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 117252080Spfg 118252080Spfg * config/i386/athlon.md (athlon_sseld_amdfam10, 119252080Spfg athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 120252080Spfg athlon_mmxssest_short_amdfam10): New define_insn_reservation. 121252080Spfg 122252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 123252080Spfg 124252080Spfg * config/i386/athlon.md (athlon_sseins_amdfam10): New 125252080Spfg define_insn_reservation. 126252080Spfg * config/i386/i386.md (sseins): Added sseins to define_attr type 127252080Spfg and define_attr unit. 128252080Spfg * config/i386/sse.md: Set type attribute to sseins for insertq 129252080Spfg and insertqi. 130252080Spfg 131252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 132252080Spfg 133252080Spfg * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 134252080Spfg ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 135252080Spfg ssecomi_load_amdfam10, ssecomi_amdfam10, 136252080Spfg sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 137252080Spfg define_insn_reservation. 138252080Spfg (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 139252080Spfg 140252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 141252080Spfg 142252080Spfg * config/i386/athlon.md (cvtss2sd_load_amdfam10, 143252080Spfg cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 144252080Spfg cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 145252080Spfg cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 146252080Spfg cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 147252080Spfg cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 148252080Spfg define_insn_reservation. 149252080Spfg 150252080Spfg * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 151252080Spfg cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 152252080Spfg cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 153252080Spfg cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 154252080Spfg cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 155252080Spfg 156252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 157252080Spfg 158252080Spfg * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 159252080Spfg athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 160252080Spfg athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 161252080Spfg (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 162252080Spfg athlon_ssemul_load_k8): Added amdfam10. 163252080Spfg 164252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 165252080Spfg 166252080Spfg * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 167252080Spfg (x86_sse_unaligned_move_optimal): New variable. 168252080Spfg 169252080Spfg * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 170252080Spfg m_AMDFAM10. 171252080Spfg (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 172252080Spfg for unaligned vector SSE double/single precision loads for AMDFAM10. 173252080Spfg 174252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 175252080Spfg 176252080Spfg * config/i386/i386.h (TARGET_AMDFAM10): New macro. 177252080Spfg (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 178252080Spfg Define TARGET_CPU_DEFAULT_amdfam10. 179252080Spfg (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 180252080Spfg (processor_type): Add PROCESSOR_AMDFAM10. 181252080Spfg 182252080Spfg * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 183252080Spfg processor_type in config/i386/i386.h. 184252080Spfg Enable imul peepholes for TARGET_AMDFAM10. 185252080Spfg 186252080Spfg * config.gcc: Add support for --with-cpu option for amdfam10. 187252080Spfg 188252080Spfg * config/i386/i386.c (amdfam10_cost): New variable. 189252080Spfg (m_AMDFAM10): New macro. 190252080Spfg (m_ATHLON_K8_AMDFAM10): New macro. 191252080Spfg (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 192252080Spfg x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 193252080Spfg x86_promote_QImode, x86_integer_DFmode_moves, 194252080Spfg x86_partial_reg_dependency, x86_memory_mismatch_stall, 195252080Spfg x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 196252080Spfg x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 197252080Spfg x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 198252080Spfg x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 199252080Spfg Enable/disable for amdfam10. 200252080Spfg (override_options): Add amdfam10_cost to processor_target_table. 201252080Spfg Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 202252080Spfg processor_alias_table. 203252080Spfg (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 204252080Spfg (ix86_adjust_cost): Add code for amdfam10. 205252080Spfg 206252080Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 207252080Spfg 208252080Spfg * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 209252080Spfg instruction set feature flag. Add new (-mpopcnt) flag for popcnt 210252080Spfg instruction. Add new SSE4A (-msse4a) instruction set feature flag. 211252080Spfg * config/i386/i386.h: Add builtin definition for SSE4A. 212252080Spfg * config/i386/i386.md: Add support for ABM instructions 213252080Spfg (popcnt and lzcnt). 214252080Spfg * config/i386/sse.md: Add support for SSE4A instructions 215252080Spfg (movntss, movntsd, extrq, insertq). 216252080Spfg * config/i386/i386.c: Add support for ABM and SSE4A builtins. 217252080Spfg Add -march=amdfam10 flag. 218252080Spfg * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 219252080Spfg * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 220252080Spfg and amdfam10. 221252080Spfg * doc/extend.texi: Add documentation for SSE4A builtins. 222252080Spfg 223252080Spfg2007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 224252080Spfg 225252080Spfg * config/i386/i386.h (x86_cmpxchg16b): Remove const. 226252080Spfg (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 227252080Spfg * config/i386/i386.c (x86_cmpxchg16b): Remove const. 228252080Spfg (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 229252080Spfg for CPUs that have PTA_CX16 set. 230252080Spfg 231221282Smm2007-01-17 Eric Christopher <echristo@apple.com> (r120846) 232221282Smm 233221282Smm * config.gcc: Support core2 processor. 234221282Smm 235221282Smm2006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 236221282Smm 237221282Smm PR target/30040 238221282Smm * config/i386/driver-i386.c (bit_SSSE3): New. 239221282Smm 240252080Spfg2006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 241252080Spfg 242252080Spfg * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 243252080Spfg and m_GENERIC64. 244252080Spfg 245221282Smm2006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 246221282Smm 247221282Smm * doc/invoke.texi (core2): Add item. 248221282Smm 249221282Smm * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 250221282Smm macros. 251221282Smm (TARGET_CPU_CPP_BUILTINS): Add code for core2. 252221282Smm (TARGET_CPU_DEFAULT_generic): Change value. 253221282Smm (TARGET_CPU_DEFAULT_NAMES): Add core2. 254221282Smm (processor_type): Add new constant PROCESSOR_CORE2. 255221282Smm 256221282Smm * config/i386/i386.md (cpu): Add core2. 257221282Smm 258221282Smm * config/i386/i386.c (core2_cost): New initialized variable. 259221282Smm (m_CORE2): New macro. 260221282Smm (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 261221282Smm x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 262221282Smm x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 263221282Smm x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 264221282Smm x86_partial_reg_dependency, x86_memory_mismatch_stall, 265221282Smm x86_accumulate_outgoing_args, x86_prologue_using_move, 266221282Smm x86_epilogue_using_move, x86_arch_always_fancy_math_387, 267221282Smm x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 268221282Smm x86_use_incdec, x86_four_jump_limit, x86_schedule, 269221282Smm x86_pad_returns): Add m_CORE2. 270221282Smm (override_options): Add entries for Core2. 271221282Smm (ix86_issue_rate): Add case for Core2. 272221282Smm 273221282Smm2006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 274221282Smm 275221282Smm * config/i386/i386.h (TARGET_GEODE): 276221282Smm (TARGET_CPU_CPP_BUILTINS): Add code for geode. 277221282Smm (TARGET_CPU_DEFAULT_geode): New macro. 278221282Smm (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 279221282Smm TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 280221282Smm TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 281221282Smm TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 282221282Smm TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 283221282Smm the macro values. 284221282Smm (TARGET_CPU_DEFAULT_NAMES): Add geode. 285221282Smm (processor_type): Add PROCESSOR_GEODE. 286221282Smm 287221282Smm * config/i386/i386.md: Include geode.md. 288221282Smm (cpu): Add geode. 289221282Smm 290221282Smm * config/i386/i386.c (geode_cost): New initialized global 291221282Smm variable. 292221282Smm (m_GEODE, m_K6_GEODE): New macros. 293221282Smm (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 294221282Smm x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 295221282Smm x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 296221282Smm x86_schedule): Use m_K6_GEODE instead of m_K6. 297221282Smm (x86_movx, x86_cmove): Set up m_GEODE. 298221282Smm (x86_integer_DFmode_moves): Clear m_GEODE. 299221282Smm (processor_target_table): Add entry for geode. 300221282Smm (processor_alias_table): Ditto. 301221282Smm 302221282Smm * config/i386/geode.md: New file. 303221282Smm 304221282Smm * doc/invoke.texi: Add entry about geode processor. 305221282Smm 306237678Spfg2006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 307229554Spfg 308229554Spfg PR middle-end/28796 309229554Spfg * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 310229554Spfg and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 311229554Spfg for deciding optimizations in consistency with fold-const.c 312229554Spfg (fold_builtin_unordered_cmp): Likewise. 313229554Spfg 314221282Smm2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 315221282Smm 316221282Smm * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 317221282Smm (x86_64-*-*): Likewise. 318221282Smm 319221282Smm * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 320221282Smm (override_options): Check SSSE3. 321221282Smm (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 322221282Smm IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 323221282Smm IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 324221282Smm IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 325221282Smm IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 326221282Smm IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 327221282Smm IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 328221282Smm IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 329221282Smm IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 330221282Smm IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 331221282Smm IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 332221282Smm IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 333221282Smm IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 334221282Smm IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 335221282Smm IX86_BUILTIN_PABSD128. 336221282Smm (bdesc_2arg): Add SSSE3. 337221282Smm (bdesc_1arg): Likewise. 338221282Smm (ix86_init_mmx_sse_builtins): Support SSSE3. 339221282Smm (ix86_expand_builtin): Likewise. 340221282Smm * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 341221282Smm 342221282Smm * config/i386/i386.md (UNSPEC_PSHUFB): New. 343221282Smm (UNSPEC_PSIGN): Likewise. 344221282Smm (UNSPEC_PALIGNR): Likewise. 345221282Smm Include mmx.md before sse.md. 346221282Smm 347221282Smm * config/i386/i386.opt: Add -mssse3. 348221282Smm 349221282Smm * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 350221282Smm (ssse3_phaddwv4hi3): Likewise. 351221282Smm (ssse3_phadddv4si3): Likewise. 352221282Smm (ssse3_phadddv2si3): Likewise. 353221282Smm (ssse3_phaddswv8hi3): Likewise. 354221282Smm (ssse3_phaddswv4hi3): Likewise. 355221282Smm (ssse3_phsubwv8hi3): Likewise. 356221282Smm (ssse3_phsubwv4hi3): Likewise. 357221282Smm (ssse3_phsubdv4si3): Likewise. 358221282Smm (ssse3_phsubdv2si3): Likewise. 359221282Smm (ssse3_phsubswv8hi3): Likewise. 360221282Smm (ssse3_phsubswv4hi3): Likewise. 361221282Smm (ssse3_pmaddubswv8hi3): Likewise. 362221282Smm (ssse3_pmaddubswv4hi3): Likewise. 363221282Smm (ssse3_pmulhrswv8hi3): Likewise. 364221282Smm (ssse3_pmulhrswv4hi3): Likewise. 365221282Smm (ssse3_pshufbv16qi3): Likewise. 366221282Smm (ssse3_pshufbv8qi3): Likewise. 367221282Smm (ssse3_psign<mode>3): Likewise. 368221282Smm (ssse3_psign<mode>3): Likewise. 369221282Smm (ssse3_palignrti): Likewise. 370221282Smm (ssse3_palignrdi): Likewise. 371221282Smm (abs<mode>2): Likewise. 372221282Smm (abs<mode>2): Likewise. 373221282Smm 374221282Smm * config/i386/tmmintrin.h: New file. 375221282Smm 376221282Smm * doc/extend.texi: Document SSSE3 built-in functions. 377221282Smm 378221282Smm * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 379234023Spfg 380252080Spfg2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 381250676Spfg 382250676Spfg * config/i386/tmmintrin.h: Remove the duplicated content. 383250676Spfg 384237678Spfg2006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 385234023Spfg 386237678Spfg PR tree-optimization/3511 387237678Spfg * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 388237678Spfg got new invariant arguments during PHI translation. 389237678Spfg 390237678Spfg2006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 391237678Spfg 392234023Spfg * builtins.c (fold_builtin_classify): Fix typo. 393234023Spfg 394