ChangeLog.gcc43 revision 250676 
12007-05-01  Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
2 
3	* config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 
4	and athlon64-sse3 as improved versions of k8, opteron and athlon64 
5	with SSE3 instruction set support.
6	* doc/invoke.texi: Likewise.
7
82007-04-12  Richard Guenther  <rguenther@suse.de> (r123736)
9
10	PR tree-optimization/24689
11	PR tree-optimization/31307
12	* fold-const.c (operand_equal_p): Compare INTEGER_CST array
13	indices by value.
14	* gimplify.c (canonicalize_addr_expr): To be consistent with
15	gimplify_compound_lval only set operands two and three of
16	ARRAY_REFs if they are not gimple_min_invariant.  This makes
17	it never at this place.
18	* tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
19
202007-04-07  H.J. Lu  <hongjiu.lu@intel.com> (r123639)
21
22	* config/i386/i386.c (ix86_handle_option): Handle SSSE3.
23
242007-02-08  Harsha Jagasia  <harsha.jagasia@amd.com> (r121726)
25
26	* config/i386/xmmintrin.h: Make inclusion of emmintrin.h
27	conditional to __SSE2__.
28	(Entries below should have been added to first ChangeLog
29	entry for amdfam10 dated 2007-02-05)
30	* config/i386/emmintrin.h: Generate #error if __SSE2__ is not
31	defined.
32	* config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
33	defined.
34	* config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
35	defined.
36
372007-02-07  Jakub Jelinek  <jakub@redhat.com> (r121687)
38
39	* config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
40
412007-01-17  Eric Christopher  <echristo@apple.com> (r120846)
42
43	* config.gcc: Support core2 processor.
44
452006-12-02  H.J. Lu  <hongjiu.lu@intel.com> (r119454 - partial)
46
47	PR target/30040
48	* config/i386/driver-i386.c (bit_SSSE3): New.
49
502006-11-18  Vladimir Makarov  <vmakarov@redhat.com> (r118973)
51
52	* doc/invoke.texi (core2): Add item.
53
54	* config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
55	macros.
56	(TARGET_CPU_CPP_BUILTINS): Add code for core2.
57	(TARGET_CPU_DEFAULT_generic): Change value.
58	(TARGET_CPU_DEFAULT_NAMES): Add core2.
59	(processor_type): Add new constant PROCESSOR_CORE2.
60
61	* config/i386/i386.md (cpu): Add core2.
62
63	* config/i386/i386.c (core2_cost): New initialized variable.
64	(m_CORE2): New macro.
65	(x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
66	x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
67	x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
68	x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
69	x86_partial_reg_dependency, x86_memory_mismatch_stall,
70	x86_accumulate_outgoing_args, x86_prologue_using_move,
71	x86_epilogue_using_move, x86_arch_always_fancy_math_387,
72	x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
73	x86_use_incdec, x86_four_jump_limit, x86_schedule,
74	x86_pad_returns): Add m_CORE2.
75	(override_options): Add entries for Core2.
76	(ix86_issue_rate): Add case for Core2.
77	
782006-10-27  Vladimir Makarov  <vmakarov@redhat.com> (r118090)
79
80	* config/i386/i386.h (TARGET_GEODE):
81	(TARGET_CPU_CPP_BUILTINS): Add code for geode.
82	(TARGET_CPU_DEFAULT_geode): New macro.
83	(TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2,
84	TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon,
85	TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8,
86	TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott,
87	TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase
88	the macro values.
89	(TARGET_CPU_DEFAULT_NAMES): Add geode.
90	(processor_type): Add PROCESSOR_GEODE.
91
92	* config/i386/i386.md: Include geode.md.
93	(cpu): Add geode.
94
95	* config/i386/i386.c (geode_cost): New initialized global
96	variable.
97	(m_GEODE, m_K6_GEODE): New macros.
98	(x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf,
99	x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4,
100	x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants,
101	x86_schedule): Use m_K6_GEODE instead of m_K6.
102	(x86_movx, x86_cmove): Set up m_GEODE.
103	(x86_integer_DFmode_moves): Clear m_GEODE.
104	(processor_target_table): Add entry for geode.
105	(processor_alias_table): Ditto.
106
107	* config/i386/geode.md: New file.
108
109	* doc/invoke.texi: Add entry about geode processor.
110    
1112006-10-24  Richard Guenther  <rguenther@suse.de> (r118001)
112
113	PR middle-end/28796
114	* builtins.c (fold_builtin_classify): Use HONOR_INFINITIES
115	and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS
116	for deciding optimizations in consistency with fold-const.c
117	(fold_builtin_unordered_cmp): Likewise.
118
1192006-10-22  H.J. Lu  <hongjiu.lu@intel.com> (r117958)
120
121	* config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
122	(x86_64-*-*): Likewise.
123
124	* config/i386/i386.c (pta_flags): Add PTA_SSSE3.
125	(override_options): Check SSSE3.
126	(ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
127	IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
128	IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
129	IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
130	IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
131	IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
132	IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
133	IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
134	IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
135	IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
136	IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
137	IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
138	IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
139	IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
140	IX86_BUILTIN_PABSD128.
141	(bdesc_2arg): Add SSSE3.
142	(bdesc_1arg): Likewise.
143	(ix86_init_mmx_sse_builtins): Support SSSE3.
144	(ix86_expand_builtin): Likewise.
145	* config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
146
147	* config/i386/i386.md (UNSPEC_PSHUFB): New.
148	(UNSPEC_PSIGN): Likewise.
149	(UNSPEC_PALIGNR): Likewise.
150	Include mmx.md before sse.md.
151
152	* config/i386/i386.opt: Add -mssse3.
153
154	* config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
155	(ssse3_phaddwv4hi3): Likewise.
156	(ssse3_phadddv4si3): Likewise.
157	(ssse3_phadddv2si3): Likewise.
158	(ssse3_phaddswv8hi3): Likewise.
159	(ssse3_phaddswv4hi3): Likewise.
160	(ssse3_phsubwv8hi3): Likewise.
161	(ssse3_phsubwv4hi3): Likewise.
162	(ssse3_phsubdv4si3): Likewise.
163	(ssse3_phsubdv2si3): Likewise.
164	(ssse3_phsubswv8hi3): Likewise.
165	(ssse3_phsubswv4hi3): Likewise.
166	(ssse3_pmaddubswv8hi3): Likewise.
167	(ssse3_pmaddubswv4hi3): Likewise.
168	(ssse3_pmulhrswv8hi3): Likewise.
169	(ssse3_pmulhrswv4hi3): Likewise.
170	(ssse3_pshufbv16qi3): Likewise.
171	(ssse3_pshufbv8qi3): Likewise.
172	(ssse3_psign<mode>3): Likewise.
173	(ssse3_psign<mode>3): Likewise.
174	(ssse3_palignrti): Likewise.
175	(ssse3_palignrdi): Likewise.
176	(abs<mode>2): Likewise.
177	(abs<mode>2): Likewise.
178
179	* config/i386/tmmintrin.h: New file.
180
181	* doc/extend.texi: Document SSSE3 built-in functions.
182
183	* doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
184
1852006-10-22  H.J. Lu  <hongjiu.lu@intel.com>
186  	 
187	* config/i386/tmmintrin.h: Remove the duplicated content.
188
1892006-10-21  Richard Guenther  <rguenther@suse.de> (r117932)
190
191	PR tree-optimization/3511
192	* tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
193	got new invariant arguments during PHI translation.
194
1952006-10-21  Richard Guenther  <rguenther@suse.de> (r117929)
196
197	* builtins.c (fold_builtin_classify): Fix typo.
198
199