arm-dis.c revision 218822
160484Sobrien/* Instruction printing code for the ARM 2218822Sdim Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 3218822Sdim 2007, Free Software Foundation, Inc. 460484Sobrien Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 560484Sobrien Modification by James G. Smith (jsmith@cygnus.co.uk) 660484Sobrien 7130561Sobrien This file is part of libopcodes. 860484Sobrien 9130561Sobrien This program is free software; you can redistribute it and/or modify it under 10130561Sobrien the terms of the GNU General Public License as published by the Free 11130561Sobrien Software Foundation; either version 2 of the License, or (at your option) 12130561Sobrien any later version. 1360484Sobrien 14130561Sobrien This program is distributed in the hope that it will be useful, but WITHOUT 15130561Sobrien ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16130561Sobrien FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17130561Sobrien more details. 1860484Sobrien 19130561Sobrien You should have received a copy of the GNU General Public License 20130561Sobrien along with this program; if not, write to the Free Software 21218822Sdim Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 2260484Sobrien 2360484Sobrien#include "sysdep.h" 24218822Sdim 2560484Sobrien#include "dis-asm.h" 26218822Sdim#include "opcode/arm.h" 2760484Sobrien#include "opintl.h" 28130561Sobrien#include "safe-ctype.h" 29218822Sdim#include "floatformat.h" 3060484Sobrien 31104834Sobrien/* FIXME: This shouldn't be done here. */ 32218822Sdim#include "coff/internal.h" 33218822Sdim#include "libcoff.h" 3460484Sobrien#include "elf-bfd.h" 3560484Sobrien#include "elf/internal.h" 3660484Sobrien#include "elf/arm.h" 3760484Sobrien 38218822Sdim/* FIXME: Belongs in global header. */ 3960484Sobrien#ifndef strneq 4060484Sobrien#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 4160484Sobrien#endif 4260484Sobrien 4360484Sobrien#ifndef NUM_ELEM 4460484Sobrien#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) 4560484Sobrien#endif 4660484Sobrien 47218822Sdimstruct opcode32 48218822Sdim{ 49218822Sdim unsigned long arch; /* Architecture defining this insn. */ 50218822Sdim unsigned long value, mask; /* Recognise insn if (op&mask)==value. */ 51218822Sdim const char *assembler; /* How to disassemble this insn. */ 52218822Sdim}; 53218822Sdim 54218822Sdimstruct opcode16 55218822Sdim{ 56218822Sdim unsigned long arch; /* Architecture defining this insn. */ 57218822Sdim unsigned short value, mask; /* Recognise insn if (op&mask)==value. */ 58218822Sdim const char *assembler; /* How to disassemble this insn. */ 59218822Sdim}; 60218822Sdim 61218822Sdim/* print_insn_coprocessor recognizes the following format control codes: 62218822Sdim 63218822Sdim %% % 64218822Sdim 65218822Sdim %c print condition code (always bits 28-31 in ARM mode) 66218822Sdim %q print shifter argument 67218822Sdim %u print condition code (unconditional in ARM mode) 68218822Sdim %A print address for ldc/stc/ldf/stf instruction 69218822Sdim %B print vstm/vldm register list 70218822Sdim %C print vstr/vldr address operand 71218822Sdim %I print cirrus signed shift immediate: bits 0..3|4..6 72218822Sdim %F print the COUNT field of a LFM/SFM instruction. 73218822Sdim %P print floating point precision in arithmetic insn 74218822Sdim %Q print floating point precision in ldf/stf insn 75218822Sdim %R print floating point rounding mode 76218822Sdim 77218822Sdim %<bitfield>r print as an ARM register 78218822Sdim %<bitfield>d print the bitfield in decimal 79218822Sdim %<bitfield>k print immediate for VFPv3 conversion instruction 80218822Sdim %<bitfield>x print the bitfield in hex 81218822Sdim %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 82218822Sdim %<bitfield>f print a floating point constant if >7 else a 83218822Sdim floating point register 84218822Sdim %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 85218822Sdim %<bitfield>g print as an iWMMXt 64-bit register 86218822Sdim %<bitfield>G print as an iWMMXt general purpose or control register 87218822Sdim %<bitfield>D print as a NEON D register 88218822Sdim %<bitfield>Q print as a NEON Q register 89218822Sdim 90218822Sdim %y<code> print a single precision VFP reg. 91218822Sdim Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 92218822Sdim %z<code> print a double precision VFP reg 93218822Sdim Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 94218822Sdim 95218822Sdim %<bitfield>'c print specified char iff bitfield is all ones 96218822Sdim %<bitfield>`c print specified char iff bitfield is all zeroes 97218822Sdim %<bitfield>?ab... select from array of values in big endian order 98218822Sdim 99218822Sdim %L print as an iWMMXt N/M width field. 100218822Sdim %Z print the Immediate of a WSHUFH instruction. 101218822Sdim %l like 'A' except use byte offsets for 'B' & 'H' 102218822Sdim versions. 103218822Sdim %i print 5-bit immediate in bits 8,3..0 104218822Sdim (print "32" when 0) 105218822Sdim %r print register offset address for wldt/wstr instruction 106218822Sdim*/ 107218822Sdim 108218822Sdim/* Common coprocessor opcodes shared between Arm and Thumb-2. */ 109218822Sdim 110218822Sdimstatic const struct opcode32 coprocessor_opcodes[] = 111218822Sdim{ 112218822Sdim /* XScale instructions. */ 113218822Sdim {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, 114218822Sdim {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, 115218822Sdim {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 116218822Sdim {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 117218822Sdim {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 118218822Sdim 119218822Sdim /* Intel Wireless MMX technology instructions. */ 120218822Sdim#define FIRST_IWMMXT_INSN 0x0e130130 121218822Sdim#define IWMMXT_INSN_COUNT 73 122218822Sdim {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 123218822Sdim {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 124218822Sdim {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 125218822Sdim {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 126218822Sdim {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 127218822Sdim {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 128218822Sdim {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 129218822Sdim {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 130218822Sdim {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 131218822Sdim {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 132218822Sdim {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 133218822Sdim {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 134218822Sdim {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 135218822Sdim {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 136218822Sdim {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 137218822Sdim {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 138218822Sdim {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 139218822Sdim {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 140218822Sdim {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 141218822Sdim {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 142218822Sdim {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 143218822Sdim {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 144218822Sdim {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 145218822Sdim {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 146218822Sdim {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 147218822Sdim {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 148218822Sdim {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 149218822Sdim {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 150218822Sdim {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 151218822Sdim {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 152218822Sdim {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 153218822Sdim {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 154218822Sdim {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 155218822Sdim {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 156218822Sdim {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 157218822Sdim {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 158218822Sdim {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 159218822Sdim {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 160218822Sdim {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 161218822Sdim {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 162218822Sdim {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 163218822Sdim {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 164218822Sdim {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 165218822Sdim {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 166218822Sdim {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 167218822Sdim {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 168218822Sdim {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 169218822Sdim {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 170218822Sdim {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 171218822Sdim {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 172218822Sdim {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 173218822Sdim {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 174218822Sdim {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 175218822Sdim {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 176218822Sdim {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 177218822Sdim {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 178218822Sdim {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 179218822Sdim {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 180218822Sdim {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 181218822Sdim {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 182218822Sdim {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 183218822Sdim {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 184218822Sdim {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 185218822Sdim {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 186218822Sdim {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 187218822Sdim {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 188218822Sdim {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 189218822Sdim {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 190218822Sdim {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 191218822Sdim {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 192218822Sdim {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 193218822Sdim {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 194218822Sdim {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 195218822Sdim {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 196218822Sdim {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 197218822Sdim 198218822Sdim /* Floating point coprocessor (FPA) instructions */ 199218822Sdim {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 200218822Sdim {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 201218822Sdim {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 202218822Sdim {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 203218822Sdim {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 204218822Sdim {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 205218822Sdim {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 206218822Sdim {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 207218822Sdim {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 208218822Sdim {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 209218822Sdim {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 210218822Sdim {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 211218822Sdim {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 212218822Sdim {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 213218822Sdim {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 214218822Sdim {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 215218822Sdim {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 216218822Sdim {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 217218822Sdim {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 218218822Sdim {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 219218822Sdim {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 220218822Sdim {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 221218822Sdim {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 222218822Sdim {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 223218822Sdim {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 224218822Sdim {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 225218822Sdim {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 226218822Sdim {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 227218822Sdim {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 228218822Sdim {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 229218822Sdim {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 230218822Sdim {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 231218822Sdim {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 232218822Sdim {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 233218822Sdim {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 234218822Sdim {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 235218822Sdim {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 236218822Sdim {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 237218822Sdim {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 238218822Sdim {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 239218822Sdim {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 240218822Sdim {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 241218822Sdim {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 242218822Sdim 243218822Sdim /* Register load/store */ 244218822Sdim {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"}, 245218822Sdim {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"}, 246218822Sdim {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 247218822Sdim {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 248218822Sdim {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"}, 249218822Sdim {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"}, 250218822Sdim 251218822Sdim /* Data transfer between ARM and NEON registers */ 252218822Sdim {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 253218822Sdim {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 254218822Sdim {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 255218822Sdim {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 256218822Sdim {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 257218822Sdim {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 258218822Sdim {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 259218822Sdim {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 260218822Sdim {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 261218822Sdim {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 262218822Sdim {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 263218822Sdim {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 264218822Sdim {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 265218822Sdim {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 266218822Sdim 267218822Sdim /* Floating point coprocessor (VFP) instructions */ 268218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"}, 269218822Sdim {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, 270218822Sdim {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, 271218822Sdim {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"}, 272218822Sdim {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"}, 273218822Sdim {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, 274218822Sdim {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, 275218822Sdim {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, 276218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, 277218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, 278218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"}, 279218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"}, 280218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, 281218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, 282218822Sdim {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, 283218822Sdim {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"}, 284218822Sdim {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"}, 285218822Sdim {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"}, 286218822Sdim {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"}, 287218822Sdim {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"}, 288218822Sdim {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"}, 289218822Sdim {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"}, 290218822Sdim {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"}, 291218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"}, 292218822Sdim {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"}, 293218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"}, 294218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"}, 295218822Sdim {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"}, 296218822Sdim {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"}, 297218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"}, 298218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"}, 299218822Sdim {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"}, 300218822Sdim {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"}, 301218822Sdim {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"}, 302218822Sdim {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"}, 303218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"}, 304218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"}, 305218822Sdim {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"}, 306218822Sdim {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"}, 307218822Sdim {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"}, 308218822Sdim {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"}, 309218822Sdim {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"}, 310218822Sdim {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"}, 311218822Sdim {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"}, 312218822Sdim {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"}, 313218822Sdim {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"}, 314218822Sdim {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"}, 315218822Sdim {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"}, 316218822Sdim {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"}, 317218822Sdim {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"}, 318218822Sdim {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"}, 319218822Sdim {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"}, 320218822Sdim {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"}, 321218822Sdim {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"}, 322218822Sdim {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"}, 323218822Sdim {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"}, 324218822Sdim {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"}, 325218822Sdim {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"}, 326218822Sdim {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"}, 327218822Sdim {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"}, 328218822Sdim {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"}, 329218822Sdim {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"}, 330218822Sdim {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"}, 331218822Sdim {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"}, 332218822Sdim {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"}, 333218822Sdim {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"}, 334218822Sdim {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"}, 335218822Sdim {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"}, 336218822Sdim {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"}, 337218822Sdim {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"}, 338218822Sdim {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"}, 339218822Sdim {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"}, 340218822Sdim {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"}, 341218822Sdim {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"}, 342218822Sdim {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"}, 343218822Sdim {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"}, 344218822Sdim {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"}, 345218822Sdim {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"}, 346218822Sdim {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"}, 347218822Sdim {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"}, 348218822Sdim {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"}, 349218822Sdim {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"}, 350218822Sdim {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"}, 351218822Sdim 352218822Sdim /* Cirrus coprocessor instructions. */ 353218822Sdim {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 354218822Sdim {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 355218822Sdim {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 356218822Sdim {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 357218822Sdim {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 358218822Sdim {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 359218822Sdim {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 360218822Sdim {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 361218822Sdim {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 362218822Sdim {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 363218822Sdim {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 364218822Sdim {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 365218822Sdim {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 366218822Sdim {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 367218822Sdim {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 368218822Sdim {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 369218822Sdim {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 370218822Sdim {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 371218822Sdim {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 372218822Sdim {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 373218822Sdim {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 374218822Sdim {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 375218822Sdim {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 376218822Sdim {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 377218822Sdim {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 378218822Sdim {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 379218822Sdim {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 380218822Sdim {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 381218822Sdim {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 382218822Sdim {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 383218822Sdim {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 384218822Sdim {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 385218822Sdim {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 386218822Sdim {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 387218822Sdim {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 388218822Sdim {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 389218822Sdim {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 390218822Sdim {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 391218822Sdim {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 392218822Sdim {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 393218822Sdim {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 394218822Sdim {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 395218822Sdim {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 396218822Sdim {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 397218822Sdim {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 398218822Sdim {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 399218822Sdim {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 400218822Sdim {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 401218822Sdim {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 402218822Sdim {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 403218822Sdim {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 404218822Sdim {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 405218822Sdim {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 406218822Sdim {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 407218822Sdim {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 408218822Sdim {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 409218822Sdim {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 410218822Sdim {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 411218822Sdim {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 412218822Sdim {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 413218822Sdim {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 414218822Sdim {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 415218822Sdim {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 416218822Sdim {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 417218822Sdim {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 418218822Sdim {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 419218822Sdim {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 420218822Sdim {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 421218822Sdim {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 422218822Sdim {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 423218822Sdim {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 424218822Sdim {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 425218822Sdim {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 426218822Sdim {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 427218822Sdim {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 428218822Sdim {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 429218822Sdim {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 430218822Sdim {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 431218822Sdim {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 432218822Sdim {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 433218822Sdim {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 434218822Sdim {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 435218822Sdim {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 436218822Sdim {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 437218822Sdim 438218822Sdim /* Generic coprocessor instructions */ 439218822Sdim {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 440218822Sdim {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 441218822Sdim {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 442218822Sdim {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 443218822Sdim {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 444218822Sdim {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 445218822Sdim {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 446218822Sdim 447218822Sdim /* V6 coprocessor instructions */ 448218822Sdim {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 449218822Sdim {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 450218822Sdim 451218822Sdim /* V5 coprocessor instructions */ 452218822Sdim {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 453218822Sdim {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 454218822Sdim {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 455218822Sdim {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 456218822Sdim {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 457218822Sdim 458218822Sdim {0, 0, 0, 0} 459218822Sdim}; 460218822Sdim 461218822Sdim/* Neon opcode table: This does not encode the top byte -- that is 462218822Sdim checked by the print_insn_neon routine, as it depends on whether we are 463218822Sdim doing thumb32 or arm32 disassembly. */ 464218822Sdim 465218822Sdim/* print_insn_neon recognizes the following format control codes: 466218822Sdim 467218822Sdim %% % 468218822Sdim 469218822Sdim %c print condition code 470218822Sdim %A print v{st,ld}[1234] operands 471218822Sdim %B print v{st,ld}[1234] any one operands 472218822Sdim %C print v{st,ld}[1234] single->all operands 473218822Sdim %D print scalar 474218822Sdim %E print vmov, vmvn, vorr, vbic encoded constant 475218822Sdim %F print vtbl,vtbx register list 476218822Sdim 477218822Sdim %<bitfield>r print as an ARM register 478218822Sdim %<bitfield>d print the bitfield in decimal 479218822Sdim %<bitfield>e print the 2^N - bitfield in decimal 480218822Sdim %<bitfield>D print as a NEON D register 481218822Sdim %<bitfield>Q print as a NEON Q register 482218822Sdim %<bitfield>R print as a NEON D or Q register 483218822Sdim %<bitfield>Sn print byte scaled width limited by n 484218822Sdim %<bitfield>Tn print short scaled width limited by n 485218822Sdim %<bitfield>Un print long scaled width limited by n 486218822Sdim 487218822Sdim %<bitfield>'c print specified char iff bitfield is all ones 488218822Sdim %<bitfield>`c print specified char iff bitfield is all zeroes 489218822Sdim %<bitfield>?ab... select from array of values in big endian order */ 490218822Sdim 491218822Sdimstatic const struct opcode32 neon_opcodes[] = 492218822Sdim{ 493218822Sdim /* Extract */ 494218822Sdim {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 495218822Sdim {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 496218822Sdim 497218822Sdim /* Move data element to all lanes */ 498218822Sdim {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 499218822Sdim {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 500218822Sdim {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 501218822Sdim 502218822Sdim /* Table lookup */ 503218822Sdim {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 504218822Sdim {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 505218822Sdim 506218822Sdim /* Two registers, miscellaneous */ 507218822Sdim {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 508218822Sdim {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 509218822Sdim {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 510218822Sdim {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 511218822Sdim {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 512218822Sdim {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 513218822Sdim {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 514218822Sdim {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 515218822Sdim {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 516218822Sdim {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 517218822Sdim {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 518218822Sdim {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 519218822Sdim {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 520218822Sdim {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 521218822Sdim {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 522218822Sdim {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 523218822Sdim {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 524218822Sdim {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 525218822Sdim {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 526218822Sdim {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 527218822Sdim {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 528218822Sdim {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 529218822Sdim {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 530218822Sdim {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 531218822Sdim {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 532218822Sdim {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 533218822Sdim {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 534218822Sdim {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 535218822Sdim {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 536218822Sdim {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 537218822Sdim {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 538218822Sdim {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 539218822Sdim {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 540218822Sdim 541218822Sdim /* Three registers of the same length */ 542218822Sdim {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 543218822Sdim {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 544218822Sdim {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 545218822Sdim {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 546218822Sdim {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 547218822Sdim {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 548218822Sdim {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 549218822Sdim {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 550218822Sdim {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 551218822Sdim {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 552218822Sdim {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 553218822Sdim {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 554218822Sdim {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 555218822Sdim {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 556218822Sdim {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 557218822Sdim {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 558218822Sdim {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 559218822Sdim {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 560218822Sdim {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 561218822Sdim {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 562218822Sdim {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 563218822Sdim {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 564218822Sdim {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 565218822Sdim {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 566218822Sdim {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 567218822Sdim {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 568218822Sdim {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 569218822Sdim {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 570218822Sdim {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 571218822Sdim {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 572218822Sdim {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 573218822Sdim {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 574218822Sdim {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 575218822Sdim {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 576218822Sdim {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 577218822Sdim {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 578218822Sdim {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 579218822Sdim {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 580218822Sdim {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 581218822Sdim {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 582218822Sdim {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 583218822Sdim {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 584218822Sdim {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 585218822Sdim {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 586218822Sdim {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 587218822Sdim {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 588218822Sdim {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 589218822Sdim {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 590218822Sdim {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 591218822Sdim {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 592218822Sdim {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 593218822Sdim {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 594218822Sdim {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 595218822Sdim 596218822Sdim /* One register and an immediate value */ 597218822Sdim {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 598218822Sdim {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 599218822Sdim {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 600218822Sdim {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 601218822Sdim {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 602218822Sdim {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 603218822Sdim {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 604218822Sdim {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 605218822Sdim {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 606218822Sdim {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 607218822Sdim {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 608218822Sdim {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 609218822Sdim {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 610218822Sdim 611218822Sdim /* Two registers and a shift amount */ 612218822Sdim {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 613218822Sdim {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 614218822Sdim {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 615218822Sdim {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 616218822Sdim {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 617218822Sdim {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 618218822Sdim {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, 619218822Sdim {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 620218822Sdim {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 621218822Sdim {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 622218822Sdim {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 623218822Sdim {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 624218822Sdim {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 625218822Sdim {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 626218822Sdim {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 627218822Sdim {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 628218822Sdim {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 629218822Sdim {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, 630218822Sdim {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 631218822Sdim {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 632218822Sdim {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 633218822Sdim {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 634218822Sdim {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 635218822Sdim {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 636218822Sdim {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 637218822Sdim {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 638218822Sdim {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 639218822Sdim {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 640218822Sdim {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 641218822Sdim {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, 642218822Sdim {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 643218822Sdim {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 644218822Sdim {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 645218822Sdim {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 646218822Sdim {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 647218822Sdim {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 648218822Sdim {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 649218822Sdim {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 650218822Sdim {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 651218822Sdim {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 652218822Sdim {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 653218822Sdim {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 654218822Sdim {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 655218822Sdim {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 656218822Sdim {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 657218822Sdim {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 658218822Sdim {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 659218822Sdim {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 660218822Sdim {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 661218822Sdim {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 662218822Sdim {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 663218822Sdim {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 664218822Sdim {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 665218822Sdim {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 666218822Sdim {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 667218822Sdim {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 668218822Sdim {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 669218822Sdim {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 670218822Sdim 671218822Sdim /* Three registers of different lengths */ 672218822Sdim {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 673218822Sdim {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 674218822Sdim {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 675218822Sdim {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 676218822Sdim {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 677218822Sdim {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 678218822Sdim {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 679218822Sdim {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 680218822Sdim {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 681218822Sdim {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 682218822Sdim {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 683218822Sdim {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 684218822Sdim {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 685218822Sdim {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 686218822Sdim {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 687218822Sdim {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 688218822Sdim {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 689218822Sdim 690218822Sdim /* Two registers and a scalar */ 691218822Sdim {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 692218822Sdim {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 693218822Sdim {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 694218822Sdim {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 695218822Sdim {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 696218822Sdim {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 697218822Sdim {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 698218822Sdim {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 699218822Sdim {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 700218822Sdim {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 701218822Sdim {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 702218822Sdim {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 703218822Sdim {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 704218822Sdim {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 705218822Sdim {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 706218822Sdim {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 707218822Sdim {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 708218822Sdim {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 709218822Sdim {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 710218822Sdim {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 711218822Sdim {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 712218822Sdim {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 713218822Sdim 714218822Sdim /* Element and structure load/store */ 715218822Sdim {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 716218822Sdim {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 717218822Sdim {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 718218822Sdim {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 719218822Sdim {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 720218822Sdim {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 721218822Sdim {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 722218822Sdim {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 723218822Sdim {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 724218822Sdim {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 725218822Sdim {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 726218822Sdim {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 727218822Sdim {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 728218822Sdim {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 729218822Sdim {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 730218822Sdim {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 731218822Sdim {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 732218822Sdim {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 733218822Sdim {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 734218822Sdim 735218822Sdim {0,0 ,0, 0} 736218822Sdim}; 737218822Sdim 738218822Sdim/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 739218822Sdim ordered: they must be searched linearly from the top to obtain a correct 740218822Sdim match. */ 741218822Sdim 742218822Sdim/* print_insn_arm recognizes the following format control codes: 743218822Sdim 744218822Sdim %% % 745218822Sdim 746218822Sdim %a print address for ldr/str instruction 747218822Sdim %s print address for ldr/str halfword/signextend instruction 748218822Sdim %b print branch destination 749218822Sdim %c print condition code (always bits 28-31) 750218822Sdim %m print register mask for ldm/stm instruction 751218822Sdim %o print operand2 (immediate or register + shift) 752218822Sdim %p print 'p' iff bits 12-15 are 15 753218822Sdim %t print 't' iff bit 21 set and bit 24 clear 754218822Sdim %B print arm BLX(1) destination 755218822Sdim %C print the PSR sub type. 756218822Sdim %U print barrier type. 757218822Sdim %P print address for pli instruction. 758218822Sdim 759218822Sdim %<bitfield>r print as an ARM register 760218822Sdim %<bitfield>d print the bitfield in decimal 761218822Sdim %<bitfield>W print the bitfield plus one in decimal 762218822Sdim %<bitfield>x print the bitfield in hex 763218822Sdim %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 764218822Sdim 765218822Sdim %<bitfield>'c print specified char iff bitfield is all ones 766218822Sdim %<bitfield>`c print specified char iff bitfield is all zeroes 767218822Sdim %<bitfield>?ab... select from array of values in big endian order 768218822Sdim 769218822Sdim %e print arm SMI operand (bits 0..7,8..19). 770218822Sdim %E print the LSB and WIDTH fields of a BFI or BFC instruction. 771218822Sdim %V print the 16-bit immediate field of a MOVT or MOVW instruction. */ 772218822Sdim 773218822Sdimstatic const struct opcode32 arm_opcodes[] = 774218822Sdim{ 775218822Sdim /* ARM instructions. */ 776218822Sdim {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, 777218822Sdim {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 778218822Sdim {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"}, 779218822Sdim {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 780218822Sdim {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"}, 781218822Sdim {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 782218822Sdim {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 783218822Sdim 784218822Sdim /* V7 instructions. */ 785218822Sdim {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, 786218822Sdim {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 787218822Sdim {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 788218822Sdim {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 789218822Sdim {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, 790218822Sdim 791218822Sdim /* ARM V6T2 instructions. */ 792218822Sdim {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, 793218822Sdim {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, 794218822Sdim {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 795218822Sdim {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"}, 796218822Sdim {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"}, 797218822Sdim {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, 798218822Sdim {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, 799218822Sdim {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, 800218822Sdim {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 801218822Sdim 802218822Sdim /* ARM V6Z instructions. */ 803218822Sdim {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 804218822Sdim 805218822Sdim /* ARM V6K instructions. */ 806218822Sdim {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, 807218822Sdim {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"}, 808218822Sdim {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"}, 809218822Sdim {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"}, 810218822Sdim {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"}, 811218822Sdim {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"}, 812218822Sdim {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"}, 813218822Sdim 814218822Sdim /* ARM V6K NOP hints. */ 815218822Sdim {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, 816218822Sdim {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, 817218822Sdim {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, 818218822Sdim {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, 819218822Sdim {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 820218822Sdim 821218822Sdim /* ARM V6 instructions. */ 822218822Sdim {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 823218822Sdim {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 824218822Sdim {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 825218822Sdim {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 826218822Sdim {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 827218822Sdim {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, 828218822Sdim {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"}, 829218822Sdim {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"}, 830218822Sdim {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"}, 831218822Sdim {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, 832218822Sdim {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, 833218822Sdim {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, 834218822Sdim {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 835218822Sdim {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, 836218822Sdim {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, 837218822Sdim {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 838218822Sdim {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, 839218822Sdim {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, 840218822Sdim {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, 841218822Sdim {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, 842218822Sdim {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, 843218822Sdim {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 844218822Sdim {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, 845218822Sdim {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, 846218822Sdim {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 847218822Sdim {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, 848218822Sdim {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, 849218822Sdim {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, 850218822Sdim {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, 851218822Sdim {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, 852218822Sdim {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 853218822Sdim {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, 854218822Sdim {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, 855218822Sdim {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 856218822Sdim {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, 857218822Sdim {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, 858218822Sdim {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 859218822Sdim {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, 860218822Sdim {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, 861218822Sdim {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 862218822Sdim {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, 863218822Sdim {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, 864218822Sdim {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 865218822Sdim {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, 866218822Sdim {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, 867218822Sdim {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, 868218822Sdim {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, 869218822Sdim {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, 870218822Sdim {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, 871218822Sdim {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, 872218822Sdim {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"}, 873218822Sdim {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"}, 874218822Sdim {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"}, 875218822Sdim {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"}, 876218822Sdim {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"}, 877218822Sdim {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"}, 878218822Sdim {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"}, 879218822Sdim {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"}, 880218822Sdim {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"}, 881218822Sdim {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"}, 882218822Sdim {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"}, 883218822Sdim {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"}, 884218822Sdim {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"}, 885218822Sdim {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"}, 886218822Sdim {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"}, 887218822Sdim {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"}, 888218822Sdim {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"}, 889218822Sdim {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"}, 890218822Sdim {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"}, 891218822Sdim {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"}, 892218822Sdim {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"}, 893218822Sdim {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"}, 894218822Sdim {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"}, 895218822Sdim {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"}, 896218822Sdim {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, 897218822Sdim {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 898218822Sdim {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 899218822Sdim {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 900218822Sdim {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, 901218822Sdim {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 902218822Sdim {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 903218822Sdim {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 904218822Sdim {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, 905218822Sdim {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 906218822Sdim {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 907218822Sdim {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 908218822Sdim {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, 909218822Sdim {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 910218822Sdim {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 911218822Sdim {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 912218822Sdim {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, 913218822Sdim {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 914218822Sdim {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 915218822Sdim {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 916218822Sdim {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, 917218822Sdim {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 918218822Sdim {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 919218822Sdim {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 920218822Sdim {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, 921218822Sdim {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 922218822Sdim {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, 923218822Sdim {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, 924218822Sdim {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 925218822Sdim {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 926218822Sdim {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 927218822Sdim {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 928218822Sdim {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, 929218822Sdim {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 930218822Sdim {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 931218822Sdim {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 932218822Sdim {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, 933218822Sdim {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"}, 934218822Sdim {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"}, 935218822Sdim {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 936218822Sdim {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, 937218822Sdim {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 938218822Sdim {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, 939218822Sdim {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 940218822Sdim {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, 941218822Sdim {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"}, 942218822Sdim {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"}, 943218822Sdim {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, 944218822Sdim 945218822Sdim /* V5J instruction. */ 946218822Sdim {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, 947218822Sdim 948218822Sdim /* V5 Instructions. */ 949218822Sdim {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 950218822Sdim {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, 951218822Sdim {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, 952218822Sdim {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, 953218822Sdim 954218822Sdim /* V5E "El Segundo" Instructions. */ 955218822Sdim {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 956218822Sdim {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 957218822Sdim {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, 958218822Sdim {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 959218822Sdim {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 960218822Sdim {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 961218822Sdim {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 962218822Sdim 963218822Sdim {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 964218822Sdim {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 965218822Sdim 966218822Sdim {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 967218822Sdim {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 968218822Sdim {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 969218822Sdim {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 970218822Sdim 971218822Sdim {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, 972218822Sdim {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, 973218822Sdim {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, 974218822Sdim {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, 975218822Sdim 976218822Sdim {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, 977218822Sdim {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, 978218822Sdim 979218822Sdim {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, 980218822Sdim {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, 981218822Sdim {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, 982218822Sdim {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, 983218822Sdim 984218822Sdim /* ARM Instructions. */ 985218822Sdim {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"}, 986218822Sdim {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"}, 987218822Sdim {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 988218822Sdim {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 989218822Sdim {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 990218822Sdim {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 991218822Sdim {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 992218822Sdim {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 993218822Sdim {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 994218822Sdim {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 995218822Sdim {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, 996218822Sdim {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, 997218822Sdim {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"}, 998218822Sdim {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"}, 999218822Sdim {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"}, 1000218822Sdim {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"}, 1001218822Sdim {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 1002218822Sdim {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 1003218822Sdim {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 1004218822Sdim {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"}, 1005218822Sdim {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"}, 1006218822Sdim {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"}, 1007218822Sdim {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 1008218822Sdim {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"}, 1009218822Sdim {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 1010218822Sdim {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"}, 1011218822Sdim {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 1012218822Sdim {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"}, 1013218822Sdim {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"}, 1014218822Sdim {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"}, 1015218822Sdim {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"}, 1016218822Sdim {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 1017218822Sdim {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"}, 1018218822Sdim {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, 1019218822Sdim {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"}, 1020218822Sdim {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, 1021218822Sdim {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 1022218822Sdim {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"}, 1023218822Sdim {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, 1024218822Sdim {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 1025218822Sdim {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 1026218822Sdim 1027218822Sdim /* The rest. */ 1028218822Sdim {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"}, 1029218822Sdim {0, 0x00000000, 0x00000000, 0} 1030218822Sdim}; 1031218822Sdim 1032218822Sdim/* print_insn_thumb16 recognizes the following format control codes: 1033218822Sdim 1034218822Sdim %S print Thumb register (bits 3..5 as high number if bit 6 set) 1035218822Sdim %D print Thumb register (bits 0..2 as high number if bit 7 set) 1036218822Sdim %<bitfield>I print bitfield as a signed decimal 1037218822Sdim (top bit of range being the sign bit) 1038218822Sdim %N print Thumb register mask (with LR) 1039218822Sdim %O print Thumb register mask (with PC) 1040218822Sdim %M print Thumb register mask 1041218822Sdim %b print CZB's 6-bit unsigned branch destination 1042218822Sdim %s print Thumb right-shift immediate (6..10; 0 == 32). 1043218822Sdim %c print the condition code 1044218822Sdim %C print the condition code, or "s" if not conditional 1045218822Sdim %x print warning if conditional an not at end of IT block" 1046218822Sdim %X print "\t; unpredictable <IT:code>" if conditional 1047218822Sdim %I print IT instruction suffix and operands 1048218822Sdim %<bitfield>r print bitfield as an ARM register 1049218822Sdim %<bitfield>d print bitfield as a decimal 1050218822Sdim %<bitfield>H print (bitfield * 2) as a decimal 1051218822Sdim %<bitfield>W print (bitfield * 4) as a decimal 1052218822Sdim %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 1053218822Sdim %<bitfield>B print Thumb branch destination (signed displacement) 1054218822Sdim %<bitfield>c print bitfield as a condition code 1055218822Sdim %<bitnum>'c print specified char iff bit is one 1056218822Sdim %<bitnum>?ab print a if bit is one else print b. */ 1057218822Sdim 1058218822Sdimstatic const struct opcode16 thumb_opcodes[] = 1059218822Sdim{ 1060218822Sdim /* Thumb instructions. */ 1061218822Sdim 1062218822Sdim /* ARM V6K no-argument instructions. */ 1063218822Sdim {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, 1064218822Sdim {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, 1065218822Sdim {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"}, 1066218822Sdim {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"}, 1067218822Sdim {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"}, 1068218822Sdim {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 1069218822Sdim 1070218822Sdim /* ARM V6T2 instructions. */ 1071218822Sdim {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 1072218822Sdim {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 1073218822Sdim {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"}, 1074218822Sdim 1075218822Sdim /* ARM V6. */ 1076218822Sdim {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 1077218822Sdim {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 1078218822Sdim {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 1079218822Sdim {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 1080218822Sdim {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 1081218822Sdim {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 1082218822Sdim {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"}, 1083218822Sdim {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 1084218822Sdim {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 1085218822Sdim {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 1086218822Sdim {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 1087218822Sdim 1088218822Sdim /* ARM V5 ISA extends Thumb. */ 1089218822Sdim {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 1090218822Sdim /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 1091218822Sdim {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 1092218822Sdim /* ARM V4T ISA (Thumb v1). */ 1093218822Sdim {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"}, 1094218822Sdim /* Format 4. */ 1095218822Sdim {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 1096218822Sdim {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 1097218822Sdim {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 1098218822Sdim {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 1099218822Sdim {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 1100218822Sdim {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 1101218822Sdim {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 1102218822Sdim {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 1103218822Sdim {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 1104218822Sdim {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 1105218822Sdim {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 1106218822Sdim {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 1107218822Sdim {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 1108218822Sdim {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 1109218822Sdim {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 1110218822Sdim {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 1111218822Sdim /* format 13 */ 1112218822Sdim {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 1113218822Sdim {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 1114218822Sdim /* format 5 */ 1115218822Sdim {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"}, 1116218822Sdim {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"}, 1117218822Sdim {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 1118218822Sdim {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"}, 1119218822Sdim /* format 14 */ 1120218822Sdim {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"}, 1121218822Sdim {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"}, 1122218822Sdim /* format 2 */ 1123218822Sdim {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 1124218822Sdim {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 1125218822Sdim {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 1126218822Sdim {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 1127218822Sdim /* format 8 */ 1128218822Sdim {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 1129218822Sdim {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 1130218822Sdim {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 1131218822Sdim /* format 7 */ 1132218822Sdim {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 1133218822Sdim {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 1134218822Sdim /* format 1 */ 1135218822Sdim {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 1136218822Sdim {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 1137218822Sdim {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 1138218822Sdim /* format 3 */ 1139218822Sdim {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 1140218822Sdim {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 1141218822Sdim {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 1142218822Sdim {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 1143218822Sdim /* format 6 */ 1144218822Sdim {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 1145218822Sdim /* format 9 */ 1146218822Sdim {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 1147218822Sdim {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 1148218822Sdim {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 1149218822Sdim {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 1150218822Sdim /* format 10 */ 1151218822Sdim {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 1152218822Sdim {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 1153218822Sdim /* format 11 */ 1154218822Sdim {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 1155218822Sdim {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 1156218822Sdim /* format 12 */ 1157218822Sdim {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"}, 1158218822Sdim {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 1159218822Sdim /* format 15 */ 1160218822Sdim {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 1161218822Sdim {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"}, 1162218822Sdim /* format 17 */ 1163218822Sdim {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 1164218822Sdim /* format 16 */ 1165218822Sdim {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"}, 1166218822Sdim {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 1167218822Sdim /* format 18 */ 1168218822Sdim {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 1169218822Sdim 1170218822Sdim /* The E800 .. FFFF range is unconditionally redirected to the 1171218822Sdim 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 1172218822Sdim are processed via that table. Thus, we can never encounter a 1173218822Sdim bare "second half of BL/BLX(1)" instruction here. */ 1174218822Sdim {ARM_EXT_V1, 0x0000, 0x0000, "undefined"}, 1175218822Sdim {0, 0, 0, 0} 1176218822Sdim}; 1177218822Sdim 1178218822Sdim/* Thumb32 opcodes use the same table structure as the ARM opcodes. 1179218822Sdim We adopt the convention that hw1 is the high 16 bits of .value and 1180218822Sdim .mask, hw2 the low 16 bits. 1181218822Sdim 1182218822Sdim print_insn_thumb32 recognizes the following format control codes: 1183218822Sdim 1184218822Sdim %% % 1185218822Sdim 1186218822Sdim %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 1187218822Sdim %M print a modified 12-bit immediate (same location) 1188218822Sdim %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 1189218822Sdim %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 1190218822Sdim %S print a possibly-shifted Rm 1191218822Sdim 1192218822Sdim %a print the address of a plain load/store 1193218822Sdim %w print the width and signedness of a core load/store 1194218822Sdim %m print register mask for ldm/stm 1195218822Sdim 1196218822Sdim %E print the lsb and width fields of a bfc/bfi instruction 1197218822Sdim %F print the lsb and width fields of a sbfx/ubfx instruction 1198218822Sdim %b print a conditional branch offset 1199218822Sdim %B print an unconditional branch offset 1200218822Sdim %s print the shift field of an SSAT instruction 1201218822Sdim %R print the rotation field of an SXT instruction 1202218822Sdim %U print barrier type. 1203218822Sdim %P print address for pli instruction. 1204218822Sdim %c print the condition code 1205218822Sdim %x print warning if conditional an not at end of IT block" 1206218822Sdim %X print "\t; unpredictable <IT:code>" if conditional 1207218822Sdim 1208218822Sdim %<bitfield>d print bitfield in decimal 1209218822Sdim %<bitfield>W print bitfield*4 in decimal 1210218822Sdim %<bitfield>r print bitfield as an ARM register 1211218822Sdim %<bitfield>c print bitfield as a condition code 1212218822Sdim 1213218822Sdim %<bitfield>'c print specified char iff bitfield is all ones 1214218822Sdim %<bitfield>`c print specified char iff bitfield is all zeroes 1215218822Sdim %<bitfield>?ab... select from array of values in big endian order 1216218822Sdim 1217218822Sdim With one exception at the bottom (done because BL and BLX(1) need 1218218822Sdim to come dead last), this table was machine-sorted first in 1219218822Sdim decreasing order of number of bits set in the mask, then in 1220218822Sdim increasing numeric order of mask, then in increasing numeric order 1221218822Sdim of opcode. This order is not the clearest for a human reader, but 1222218822Sdim is guaranteed never to catch a special-case bit pattern with a more 1223218822Sdim general mask, which is important, because this instruction encoding 1224218822Sdim makes heavy use of special-case bit patterns. */ 1225218822Sdimstatic const struct opcode32 thumb32_opcodes[] = 1226218822Sdim{ 1227218822Sdim /* V7 instructions. */ 1228218822Sdim {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, 1229218822Sdim {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 1230218822Sdim {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 1231218822Sdim {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 1232218822Sdim {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 1233218822Sdim {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 1234218822Sdim {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 1235218822Sdim 1236218822Sdim /* Instructions defined in the basic V6T2 set. */ 1237218822Sdim {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, 1238218822Sdim {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, 1239218822Sdim {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, 1240218822Sdim {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, 1241218822Sdim {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"}, 1242218822Sdim {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 1243218822Sdim 1244218822Sdim {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 1245218822Sdim {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 1246218822Sdim {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 1247218822Sdim {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 1248218822Sdim {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 1249218822Sdim {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 1250218822Sdim {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"}, 1251218822Sdim {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 1252218822Sdim {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 1253218822Sdim {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 1254218822Sdim {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 1255218822Sdim {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 1256218822Sdim {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 1257218822Sdim {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 1258218822Sdim {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 1259218822Sdim {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 1260218822Sdim {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 1261218822Sdim {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 1262218822Sdim {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 1263218822Sdim {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 1264218822Sdim {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 1265218822Sdim {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 1266218822Sdim {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 1267218822Sdim {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 1268218822Sdim {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 1269218822Sdim {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 1270218822Sdim {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 1271218822Sdim {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 1272218822Sdim {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 1273218822Sdim {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 1274218822Sdim {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 1275218822Sdim {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 1276218822Sdim {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 1277218822Sdim {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 1278218822Sdim {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 1279218822Sdim {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 1280218822Sdim {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 1281218822Sdim {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 1282218822Sdim {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 1283218822Sdim {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 1284218822Sdim {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 1285218822Sdim {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 1286218822Sdim {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 1287218822Sdim {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 1288218822Sdim {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 1289218822Sdim {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 1290218822Sdim {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1291218822Sdim {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1292218822Sdim {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1293218822Sdim {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1294218822Sdim {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1295218822Sdim {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1296218822Sdim {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 1297218822Sdim {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 1298218822Sdim {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 1299218822Sdim {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 1300218822Sdim {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 1301218822Sdim {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 1302218822Sdim {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 1303218822Sdim {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 1304218822Sdim {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 1305218822Sdim {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 1306218822Sdim {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 1307218822Sdim {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 1308218822Sdim {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 1309218822Sdim {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 1310218822Sdim {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1311218822Sdim {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1312218822Sdim {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1313218822Sdim {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1314218822Sdim {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1315218822Sdim {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1316218822Sdim {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 1317218822Sdim {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 1318218822Sdim {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1319218822Sdim {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1320218822Sdim {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1321218822Sdim {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1322218822Sdim {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 1323218822Sdim {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, 1324218822Sdim {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 1325218822Sdim {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 1326218822Sdim {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 1327218822Sdim {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 1328218822Sdim {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 1329218822Sdim {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 1330218822Sdim {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 1331218822Sdim {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 1332218822Sdim {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 1333218822Sdim {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 1334218822Sdim {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 1335218822Sdim {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 1336218822Sdim {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 1337218822Sdim {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 1338218822Sdim {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 1339218822Sdim {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 1340218822Sdim {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 1341218822Sdim {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 1342218822Sdim {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 1343218822Sdim {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 1344218822Sdim {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 1345218822Sdim {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 1346218822Sdim {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 1347218822Sdim {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 1348218822Sdim {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1349218822Sdim {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1350218822Sdim {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1351218822Sdim {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1352218822Sdim {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1353218822Sdim {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1354218822Sdim {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1355218822Sdim {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1356218822Sdim {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 1357218822Sdim {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 1358218822Sdim {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 1359218822Sdim {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 1360218822Sdim {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, 1361218822Sdim {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1362218822Sdim {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1363218822Sdim {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1364218822Sdim {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1365218822Sdim {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1366218822Sdim {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1367218822Sdim {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1368218822Sdim {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 1369218822Sdim {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 1370218822Sdim {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 1371218822Sdim {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 1372218822Sdim {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 1373218822Sdim {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1374218822Sdim {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1375218822Sdim {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 1376218822Sdim {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 1377218822Sdim {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, 1378218822Sdim {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 1379218822Sdim {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 1380218822Sdim {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 1381218822Sdim {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 1382218822Sdim {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 1383218822Sdim {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 1384218822Sdim {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 1385218822Sdim {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 1386218822Sdim {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 1387218822Sdim {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 1388218822Sdim {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 1389218822Sdim {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 1390218822Sdim {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 1391218822Sdim {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 1392218822Sdim {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 1393218822Sdim {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 1394218822Sdim {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 1395218822Sdim {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 1396218822Sdim {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 1397218822Sdim {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 1398218822Sdim {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 1399218822Sdim {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 1400218822Sdim {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 1401218822Sdim {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 1402218822Sdim {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 1403218822Sdim {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 1404218822Sdim {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 1405218822Sdim {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 1406218822Sdim {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 1407218822Sdim {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 1408218822Sdim {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 1409218822Sdim {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 1410218822Sdim {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, 1411218822Sdim {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, 1412218822Sdim {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, 1413218822Sdim {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, 1414218822Sdim {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 1415218822Sdim {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 1416218822Sdim 1417218822Sdim /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 1418218822Sdim {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 1419218822Sdim {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 1420218822Sdim {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 1421218822Sdim {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 1422218822Sdim 1423218822Sdim /* These have been 32-bit since the invention of Thumb. */ 1424218822Sdim {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"}, 1425218822Sdim {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 1426218822Sdim 1427218822Sdim /* Fallback. */ 1428218822Sdim {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"}, 1429218822Sdim {0, 0, 0, 0} 1430218822Sdim}; 1431218822Sdim 1432218822Sdimstatic const char *const arm_conditional[] = 143360484Sobrien{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 1434218822Sdim "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 143560484Sobrien 1436218822Sdimstatic const char *const arm_fp_const[] = 1437218822Sdim{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 1438218822Sdim 1439218822Sdimstatic const char *const arm_shift[] = 1440218822Sdim{"lsl", "lsr", "asr", "ror"}; 1441218822Sdim 144260484Sobrientypedef struct 144360484Sobrien{ 1444218822Sdim const char *name; 1445218822Sdim const char *description; 1446218822Sdim const char *reg_names[16]; 144760484Sobrien} 144860484Sobrienarm_regname; 144960484Sobrien 1450218822Sdimstatic const arm_regname regnames[] = 145160484Sobrien{ 145260484Sobrien { "raw" , "Select raw register names", 145360484Sobrien { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 145477298Sobrien { "gcc", "Select register names used by GCC", 145577298Sobrien { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 145660484Sobrien { "std", "Select register names used in ARM's ISA documentation", 145760484Sobrien { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 145860484Sobrien { "apcs", "Select register names used in the APCS", 145960484Sobrien { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 146060484Sobrien { "atpcs", "Select register names used in the ATPCS", 146160484Sobrien { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 146260484Sobrien { "special-atpcs", "Select special register names used in the ATPCS", 1463130561Sobrien { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 146460484Sobrien}; 146560484Sobrien 1466218822Sdimstatic const char *const iwmmxt_wwnames[] = 1467130561Sobrien{"b", "h", "w", "d"}; 1468130561Sobrien 1469218822Sdimstatic const char *const iwmmxt_wwssnames[] = 1470218822Sdim{"b", "bus", "bc", "bss", 1471218822Sdim "h", "hus", "hc", "hss", 1472218822Sdim "w", "wus", "wc", "wss", 1473218822Sdim "d", "dus", "dc", "dss" 1474130561Sobrien}; 1475130561Sobrien 1476218822Sdimstatic const char *const iwmmxt_regnames[] = 1477218822Sdim{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 1478218822Sdim "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 1479218822Sdim}; 1480218822Sdim 1481218822Sdimstatic const char *const iwmmxt_cregnames[] = 1482218822Sdim{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 1483218822Sdim "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 1484218822Sdim}; 1485218822Sdim 148677298Sobrien/* Default to GCC register name set. */ 148760484Sobrienstatic unsigned int regname_selected = 1; 148860484Sobrien 148960484Sobrien#define NUM_ARM_REGNAMES NUM_ELEM (regnames) 149060484Sobrien#define arm_regnames regnames[regname_selected].reg_names 149160484Sobrien 1492130561Sobrienstatic bfd_boolean force_thumb = FALSE; 149360484Sobrien 1494218822Sdim/* Current IT instruction state. This contains the same state as the IT 1495218822Sdim bits in the CPSR. */ 1496218822Sdimstatic unsigned int ifthen_state; 1497218822Sdim/* IT state for the next instruction. */ 1498218822Sdimstatic unsigned int ifthen_next_state; 1499218822Sdim/* The address of the insn for which the IT state is valid. */ 1500218822Sdimstatic bfd_vma ifthen_address; 1501218822Sdim#define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 150260484Sobrien 1503218822Sdim/* Cached mapping symbol state. */ 1504218822Sdimenum map_type { 1505218822Sdim MAP_ARM, 1506218822Sdim MAP_THUMB, 1507218822Sdim MAP_DATA 1508218822Sdim}; 1509130561Sobrien 1510218822Sdimenum map_type last_type; 1511218822Sdimint last_mapping_sym = -1; 1512218822Sdimbfd_vma last_mapping_addr = 0; 1513218822Sdim 151460484Sobrien 1515104834Sobrien/* Functions. */ 151660484Sobrienint 1517218822Sdimget_arm_regname_num_options (void) 151860484Sobrien{ 151960484Sobrien return NUM_ARM_REGNAMES; 152060484Sobrien} 152160484Sobrien 152260484Sobrienint 1523218822Sdimset_arm_regname_option (int option) 152460484Sobrien{ 152560484Sobrien int old = regname_selected; 152660484Sobrien regname_selected = option; 152760484Sobrien return old; 152860484Sobrien} 152960484Sobrien 153060484Sobrienint 1531218822Sdimget_arm_regnames (int option, const char **setname, const char **setdescription, 1532218822Sdim const char *const **register_names) 153360484Sobrien{ 153460484Sobrien *setname = regnames[option].name; 153560484Sobrien *setdescription = regnames[option].description; 153660484Sobrien *register_names = regnames[option].reg_names; 153760484Sobrien return 16; 153860484Sobrien} 153960484Sobrien 1540218822Sdim/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 1541218822Sdim Returns pointer to following character of the format string and 1542218822Sdim fills in *VALUEP and *WIDTHP with the extracted value and number of 1543218822Sdim bits extracted. WIDTHP can be NULL. */ 1544218822Sdim 1545218822Sdimstatic const char * 1546218822Sdimarm_decode_bitfield (const char *ptr, unsigned long insn, 1547218822Sdim unsigned long *valuep, int *widthp) 1548218822Sdim{ 1549218822Sdim unsigned long value = 0; 1550218822Sdim int width = 0; 1551218822Sdim 1552218822Sdim do 1553218822Sdim { 1554218822Sdim int start, end; 1555218822Sdim int bits; 1556218822Sdim 1557218822Sdim for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 1558218822Sdim start = start * 10 + *ptr - '0'; 1559218822Sdim if (*ptr == '-') 1560218822Sdim for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 1561218822Sdim end = end * 10 + *ptr - '0'; 1562218822Sdim else 1563218822Sdim end = start; 1564218822Sdim bits = end - start; 1565218822Sdim if (bits < 0) 1566218822Sdim abort (); 1567218822Sdim value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 1568218822Sdim width += bits + 1; 1569218822Sdim } 1570218822Sdim while (*ptr++ == ','); 1571218822Sdim *valuep = value; 1572218822Sdim if (widthp) 1573218822Sdim *widthp = width; 1574218822Sdim return ptr - 1; 1575218822Sdim} 1576218822Sdim 157760484Sobrienstatic void 1578218822Sdimarm_decode_shift (long given, fprintf_ftype func, void *stream, 1579218822Sdim int print_shift) 158060484Sobrien{ 158160484Sobrien func (stream, "%s", arm_regnames[given & 0xf]); 1582130561Sobrien 158360484Sobrien if ((given & 0xff0) != 0) 158460484Sobrien { 158560484Sobrien if ((given & 0x10) == 0) 158660484Sobrien { 158760484Sobrien int amount = (given & 0xf80) >> 7; 158860484Sobrien int shift = (given & 0x60) >> 5; 1589130561Sobrien 159060484Sobrien if (amount == 0) 159160484Sobrien { 159260484Sobrien if (shift == 3) 159360484Sobrien { 159460484Sobrien func (stream, ", rrx"); 159560484Sobrien return; 159660484Sobrien } 1597130561Sobrien 159860484Sobrien amount = 32; 159960484Sobrien } 1600130561Sobrien 1601218822Sdim if (print_shift) 1602218822Sdim func (stream, ", %s #%d", arm_shift[shift], amount); 1603218822Sdim else 1604218822Sdim func (stream, ", #%d", amount); 160560484Sobrien } 1606218822Sdim else if (print_shift) 160760484Sobrien func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 160860484Sobrien arm_regnames[(given & 0xf00) >> 8]); 1609218822Sdim else 1610218822Sdim func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 161160484Sobrien } 161260484Sobrien} 161360484Sobrien 1614218822Sdim/* Print one coprocessor instruction on INFO->STREAM. 1615218822Sdim Return TRUE if the instuction matched, FALSE if this is not a 1616218822Sdim recognised coprocessor instruction. */ 1617130561Sobrien 1618218822Sdimstatic bfd_boolean 1619218822Sdimprint_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, 1620218822Sdim bfd_boolean thumb) 162160484Sobrien{ 1622218822Sdim const struct opcode32 *insn; 1623130561Sobrien void *stream = info->stream; 1624218822Sdim fprintf_ftype func = info->fprintf_func; 1625218822Sdim unsigned long mask; 1626218822Sdim unsigned long value; 1627218822Sdim int cond; 162860484Sobrien 1629218822Sdim for (insn = coprocessor_opcodes; insn->assembler; insn++) 163060484Sobrien { 1631130561Sobrien if (insn->value == FIRST_IWMMXT_INSN 1632130561Sobrien && info->mach != bfd_mach_arm_XScale 1633218822Sdim && info->mach != bfd_mach_arm_iWMMXt 1634218822Sdim && info->mach != bfd_mach_arm_iWMMXt2) 1635130561Sobrien insn = insn + IWMMXT_INSN_COUNT; 1636130561Sobrien 1637218822Sdim mask = insn->mask; 1638218822Sdim value = insn->value; 1639218822Sdim if (thumb) 164060484Sobrien { 1641218822Sdim /* The high 4 bits are 0xe for Arm conditional instructions, and 1642218822Sdim 0xe for arm unconditional instructions. The rest of the 1643218822Sdim encoding is the same. */ 1644218822Sdim mask |= 0xf0000000; 1645218822Sdim value |= 0xe0000000; 1646218822Sdim if (ifthen_state) 1647218822Sdim cond = IFTHEN_COND; 1648218822Sdim else 1649218822Sdim cond = 16; 1650218822Sdim } 1651218822Sdim else 1652218822Sdim { 1653218822Sdim /* Only match unconditional instuctions against unconditional 1654218822Sdim patterns. */ 1655218822Sdim if ((given & 0xf0000000) == 0xf0000000) 1656218822Sdim { 1657218822Sdim mask |= 0xf0000000; 1658218822Sdim cond = 16; 1659218822Sdim } 1660218822Sdim else 1661218822Sdim { 1662218822Sdim cond = (given >> 28) & 0xf; 1663218822Sdim if (cond == 0xe) 1664218822Sdim cond = 16; 1665218822Sdim } 1666218822Sdim } 1667218822Sdim if ((given & mask) == value) 1668218822Sdim { 1669218822Sdim const char *c; 1670130561Sobrien 167160484Sobrien for (c = insn->assembler; *c; c++) 167260484Sobrien { 167360484Sobrien if (*c == '%') 167460484Sobrien { 167560484Sobrien switch (*++c) 167660484Sobrien { 167760484Sobrien case '%': 167860484Sobrien func (stream, "%%"); 167960484Sobrien break; 168060484Sobrien 1681218822Sdim case 'A': 1682218822Sdim func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 1683218822Sdim 1684218822Sdim if ((given & (1 << 24)) != 0) 168560484Sobrien { 1686218822Sdim int offset = given & 0xff; 1687130561Sobrien 1688218822Sdim if (offset) 1689218822Sdim func (stream, ", #%s%d]%s", 1690218822Sdim ((given & 0x00800000) == 0 ? "-" : ""), 1691218822Sdim offset * 4, 1692218822Sdim ((given & 0x00200000) != 0 ? "!" : "")); 1693218822Sdim else 1694218822Sdim func (stream, "]"); 1695218822Sdim } 1696218822Sdim else 1697218822Sdim { 1698218822Sdim int offset = given & 0xff; 1699130561Sobrien 1700218822Sdim func (stream, "]"); 1701218822Sdim 1702218822Sdim if (given & (1 << 21)) 170360484Sobrien { 1704218822Sdim if (offset) 1705218822Sdim func (stream, ", #%s%d", 1706218822Sdim ((given & 0x00800000) == 0 ? "-" : ""), 1707218822Sdim offset * 4); 1708218822Sdim } 1709218822Sdim else 1710218822Sdim func (stream, ", {%d}", offset); 1711218822Sdim } 1712218822Sdim break; 1713130561Sobrien 1714218822Sdim case 'B': 1715218822Sdim { 1716218822Sdim int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 1717218822Sdim int offset = (given >> 1) & 0x3f; 1718218822Sdim 1719218822Sdim if (offset == 1) 1720218822Sdim func (stream, "{d%d}", regno); 1721218822Sdim else if (regno + offset > 32) 1722218822Sdim func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 1723218822Sdim else 1724218822Sdim func (stream, "{d%d-d%d}", regno, regno + offset - 1); 1725218822Sdim } 1726218822Sdim break; 1727218822Sdim 1728218822Sdim case 'C': 1729218822Sdim { 1730218822Sdim int rn = (given >> 16) & 0xf; 1731218822Sdim int offset = (given & 0xff) * 4; 1732218822Sdim int add = (given >> 23) & 1; 1733218822Sdim 1734218822Sdim func (stream, "[%s", arm_regnames[rn]); 1735218822Sdim 1736218822Sdim if (offset) 1737218822Sdim { 1738218822Sdim if (!add) 1739218822Sdim offset = -offset; 1740218822Sdim func (stream, ", #%d", offset); 1741218822Sdim } 1742218822Sdim func (stream, "]"); 1743218822Sdim if (rn == 15) 1744218822Sdim { 1745218822Sdim func (stream, "\t; "); 1746218822Sdim /* FIXME: Unsure if info->bytes_per_chunk is the 1747218822Sdim right thing to use here. */ 1748218822Sdim info->print_address_func (offset + pc 1749218822Sdim + info->bytes_per_chunk * 2, info); 1750218822Sdim } 1751218822Sdim } 1752218822Sdim break; 175360484Sobrien 1754218822Sdim case 'c': 1755218822Sdim func (stream, "%s", arm_conditional[cond]); 1756218822Sdim break; 175760484Sobrien 1758218822Sdim case 'I': 1759218822Sdim /* Print a Cirrus/DSP shift immediate. */ 1760218822Sdim /* Immediates are 7bit signed ints with bits 0..3 in 1761218822Sdim bits 0..3 of opcode and bits 4..6 in bits 5..7 1762218822Sdim of opcode. */ 1763218822Sdim { 1764218822Sdim int imm; 176560484Sobrien 1766218822Sdim imm = (given & 0xf) | ((given & 0xe0) >> 1); 1767130561Sobrien 1768218822Sdim /* Is ``imm'' a negative number? */ 1769218822Sdim if (imm & 0x40) 1770218822Sdim imm |= (-1 << 7); 1771218822Sdim 1772218822Sdim func (stream, "%d", imm); 1773218822Sdim } 1774218822Sdim 1775218822Sdim break; 1776218822Sdim 1777218822Sdim case 'F': 1778218822Sdim switch (given & 0x00408000) 1779218822Sdim { 1780218822Sdim case 0: 1781218822Sdim func (stream, "4"); 1782218822Sdim break; 1783218822Sdim case 0x8000: 1784218822Sdim func (stream, "1"); 1785218822Sdim break; 1786218822Sdim case 0x00400000: 1787218822Sdim func (stream, "2"); 1788218822Sdim break; 1789218822Sdim default: 1790218822Sdim func (stream, "3"); 179160484Sobrien } 1792218822Sdim break; 1793218822Sdim 1794218822Sdim case 'P': 1795218822Sdim switch (given & 0x00080080) 179660484Sobrien { 1797218822Sdim case 0: 1798218822Sdim func (stream, "s"); 1799218822Sdim break; 1800218822Sdim case 0x80: 1801218822Sdim func (stream, "d"); 1802218822Sdim break; 1803218822Sdim case 0x00080000: 1804218822Sdim func (stream, "e"); 1805218822Sdim break; 1806218822Sdim default: 1807218822Sdim func (stream, _("<illegal precision>")); 1808218822Sdim break; 1809218822Sdim } 1810218822Sdim break; 1811218822Sdim case 'Q': 1812218822Sdim switch (given & 0x00408000) 1813218822Sdim { 1814218822Sdim case 0: 1815218822Sdim func (stream, "s"); 1816218822Sdim break; 1817218822Sdim case 0x8000: 1818218822Sdim func (stream, "d"); 1819218822Sdim break; 1820218822Sdim case 0x00400000: 1821218822Sdim func (stream, "e"); 1822218822Sdim break; 1823218822Sdim default: 1824218822Sdim func (stream, "p"); 1825218822Sdim break; 1826218822Sdim } 1827218822Sdim break; 1828218822Sdim case 'R': 1829218822Sdim switch (given & 0x60) 1830218822Sdim { 1831218822Sdim case 0: 1832218822Sdim break; 1833218822Sdim case 0x20: 1834218822Sdim func (stream, "p"); 1835218822Sdim break; 1836218822Sdim case 0x40: 1837218822Sdim func (stream, "m"); 1838218822Sdim break; 1839218822Sdim default: 1840218822Sdim func (stream, "z"); 1841218822Sdim break; 1842218822Sdim } 1843218822Sdim break; 1844218822Sdim 1845218822Sdim case '0': case '1': case '2': case '3': case '4': 1846218822Sdim case '5': case '6': case '7': case '8': case '9': 1847218822Sdim { 1848218822Sdim int width; 1849218822Sdim unsigned long value; 1850218822Sdim 1851218822Sdim c = arm_decode_bitfield (c, given, &value, &width); 1852218822Sdim 1853218822Sdim switch (*c) 1854218822Sdim { 1855218822Sdim case 'r': 1856218822Sdim func (stream, "%s", arm_regnames[value]); 1857218822Sdim break; 1858218822Sdim case 'D': 1859218822Sdim func (stream, "d%ld", value); 1860218822Sdim break; 1861218822Sdim case 'Q': 1862218822Sdim if (value & 1) 1863218822Sdim func (stream, "<illegal reg q%ld.5>", value >> 1); 1864218822Sdim else 1865218822Sdim func (stream, "q%ld", value >> 1); 1866218822Sdim break; 1867218822Sdim case 'd': 1868218822Sdim func (stream, "%ld", value); 1869218822Sdim break; 1870218822Sdim case 'k': 1871218822Sdim { 1872218822Sdim int from = (given & (1 << 7)) ? 32 : 16; 1873218822Sdim func (stream, "%ld", from - value); 1874218822Sdim } 1875218822Sdim break; 1876218822Sdim 1877218822Sdim case 'f': 1878218822Sdim if (value > 7) 1879218822Sdim func (stream, "#%s", arm_fp_const[value & 7]); 1880218822Sdim else 1881218822Sdim func (stream, "f%ld", value); 1882218822Sdim break; 1883218822Sdim 1884218822Sdim case 'w': 1885218822Sdim if (width == 2) 1886218822Sdim func (stream, "%s", iwmmxt_wwnames[value]); 1887218822Sdim else 1888218822Sdim func (stream, "%s", iwmmxt_wwssnames[value]); 1889218822Sdim break; 1890218822Sdim 1891218822Sdim case 'g': 1892218822Sdim func (stream, "%s", iwmmxt_regnames[value]); 1893218822Sdim break; 1894218822Sdim case 'G': 1895218822Sdim func (stream, "%s", iwmmxt_cregnames[value]); 1896218822Sdim break; 1897218822Sdim 1898218822Sdim case 'x': 1899218822Sdim func (stream, "0x%lx", value); 1900218822Sdim break; 1901218822Sdim 1902218822Sdim case '`': 1903218822Sdim c++; 1904218822Sdim if (value == 0) 1905218822Sdim func (stream, "%c", *c); 1906218822Sdim break; 1907218822Sdim case '\'': 1908218822Sdim c++; 1909218822Sdim if (value == ((1ul << width) - 1)) 1910218822Sdim func (stream, "%c", *c); 1911218822Sdim break; 1912218822Sdim case '?': 1913218822Sdim func (stream, "%c", c[(1 << width) - (int)value]); 1914218822Sdim c += 1 << width; 1915218822Sdim break; 1916218822Sdim default: 1917218822Sdim abort (); 1918218822Sdim } 1919218822Sdim break; 1920218822Sdim 1921218822Sdim case 'y': 1922218822Sdim case 'z': 1923218822Sdim { 1924218822Sdim int single = *c++ == 'y'; 1925218822Sdim int regno; 1926218822Sdim 1927218822Sdim switch (*c) 192860484Sobrien { 1929218822Sdim case '4': /* Sm pair */ 1930218822Sdim func (stream, "{"); 1931218822Sdim /* Fall through. */ 1932218822Sdim case '0': /* Sm, Dm */ 1933218822Sdim regno = given & 0x0000000f; 1934218822Sdim if (single) 193560484Sobrien { 1936218822Sdim regno <<= 1; 1937218822Sdim regno += (given >> 5) & 1; 193860484Sobrien } 1939218822Sdim else 1940218822Sdim regno += ((given >> 5) & 1) << 4; 1941218822Sdim break; 1942218822Sdim 1943218822Sdim case '1': /* Sd, Dd */ 1944218822Sdim regno = (given >> 12) & 0x0000000f; 1945218822Sdim if (single) 194660484Sobrien { 1947218822Sdim regno <<= 1; 1948218822Sdim regno += (given >> 22) & 1; 194960484Sobrien } 1950218822Sdim else 1951218822Sdim regno += ((given >> 22) & 1) << 4; 1952218822Sdim break; 195360484Sobrien 1954218822Sdim case '2': /* Sn, Dn */ 1955218822Sdim regno = (given >> 16) & 0x0000000f; 1956218822Sdim if (single) 1957218822Sdim { 1958218822Sdim regno <<= 1; 1959218822Sdim regno += (given >> 7) & 1; 1960218822Sdim } 1961218822Sdim else 1962218822Sdim regno += ((given >> 7) & 1) << 4; 1963218822Sdim break; 1964218822Sdim 1965218822Sdim case '3': /* List */ 1966218822Sdim func (stream, "{"); 1967218822Sdim regno = (given >> 12) & 0x0000000f; 1968218822Sdim if (single) 1969218822Sdim { 1970218822Sdim regno <<= 1; 1971218822Sdim regno += (given >> 22) & 1; 1972218822Sdim } 1973218822Sdim else 1974218822Sdim regno += ((given >> 22) & 1) << 4; 1975218822Sdim break; 1976218822Sdim 1977218822Sdim default: 1978218822Sdim abort (); 197960484Sobrien } 1980218822Sdim 1981218822Sdim func (stream, "%c%d", single ? 's' : 'd', regno); 1982218822Sdim 1983218822Sdim if (*c == '3') 198460484Sobrien { 1985218822Sdim int count = given & 0xff; 1986218822Sdim 1987218822Sdim if (single == 0) 1988218822Sdim count >>= 1; 1989218822Sdim 1990218822Sdim if (--count) 199160484Sobrien { 1992218822Sdim func (stream, "-%c%d", 1993218822Sdim single ? 's' : 'd', 1994218822Sdim regno + count); 199560484Sobrien } 1996218822Sdim 1997218822Sdim func (stream, "}"); 1998218822Sdim } 1999218822Sdim else if (*c == '4') 2000218822Sdim func (stream, ", %c%d}", single ? 's' : 'd', 2001218822Sdim regno + 1); 2002218822Sdim } 2003218822Sdim break; 2004218822Sdim 2005218822Sdim case 'L': 2006218822Sdim switch (given & 0x00400100) 2007218822Sdim { 2008218822Sdim case 0x00000000: func (stream, "b"); break; 2009218822Sdim case 0x00400000: func (stream, "h"); break; 2010218822Sdim case 0x00000100: func (stream, "w"); break; 2011218822Sdim case 0x00400100: func (stream, "d"); break; 2012218822Sdim default: 2013218822Sdim break; 2014218822Sdim } 2015218822Sdim break; 2016218822Sdim 2017218822Sdim case 'Z': 2018218822Sdim { 2019218822Sdim int value; 2020218822Sdim /* given (20, 23) | given (0, 3) */ 2021218822Sdim value = ((given >> 16) & 0xf0) | (given & 0xf); 2022218822Sdim func (stream, "%d", value); 2023218822Sdim } 2024218822Sdim break; 2025218822Sdim 2026218822Sdim case 'l': 2027218822Sdim /* This is like the 'A' operator, except that if 2028218822Sdim the width field "M" is zero, then the offset is 2029218822Sdim *not* multiplied by four. */ 2030218822Sdim { 2031218822Sdim int offset = given & 0xff; 2032218822Sdim int multiplier = (given & 0x00000100) ? 4 : 1; 2033218822Sdim 2034218822Sdim func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 2035218822Sdim 2036218822Sdim if (offset) 2037218822Sdim { 2038218822Sdim if ((given & 0x01000000) != 0) 2039218822Sdim func (stream, ", #%s%d]%s", 2040218822Sdim ((given & 0x00800000) == 0 ? "-" : ""), 2041218822Sdim offset * multiplier, 2042218822Sdim ((given & 0x00200000) != 0 ? "!" : "")); 204360484Sobrien else 2044218822Sdim func (stream, "], #%s%d", 2045218822Sdim ((given & 0x00800000) == 0 ? "-" : ""), 2046218822Sdim offset * multiplier); 204760484Sobrien } 2048218822Sdim else 2049218822Sdim func (stream, "]"); 205060484Sobrien } 2051218822Sdim break; 2052218822Sdim 2053218822Sdim case 'r': 2054218822Sdim { 2055218822Sdim int imm4 = (given >> 4) & 0xf; 2056218822Sdim int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1); 2057218822Sdim int ubit = (given >> 23) & 1; 2058218822Sdim const char *rm = arm_regnames [given & 0xf]; 2059218822Sdim const char *rn = arm_regnames [(given >> 16) & 0xf]; 2060218822Sdim 2061218822Sdim switch (puw_bits) 2062218822Sdim { 2063218822Sdim case 1: 2064218822Sdim /* fall through */ 2065218822Sdim case 3: 2066218822Sdim func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 2067218822Sdim if (imm4) 2068218822Sdim func (stream, ", lsl #%d", imm4); 2069218822Sdim break; 2070218822Sdim 2071218822Sdim case 4: 2072218822Sdim /* fall through */ 2073218822Sdim case 5: 2074218822Sdim /* fall through */ 2075218822Sdim case 6: 2076218822Sdim /* fall through */ 2077218822Sdim case 7: 2078218822Sdim func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 2079218822Sdim if (imm4 > 0) 2080218822Sdim func (stream, ", lsl #%d", imm4); 2081218822Sdim func (stream, "]"); 2082218822Sdim if (puw_bits == 5 || puw_bits == 7) 2083218822Sdim func (stream, "!"); 2084218822Sdim break; 2085218822Sdim 2086218822Sdim default: 2087218822Sdim func (stream, "INVALID"); 2088218822Sdim } 2089218822Sdim } 2090218822Sdim break; 2091218822Sdim 2092218822Sdim case 'i': 2093218822Sdim { 2094218822Sdim long imm5; 2095218822Sdim imm5 = ((given & 0x100) >> 4) | (given & 0xf); 2096218822Sdim func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 2097218822Sdim } 2098218822Sdim break; 2099218822Sdim 2100218822Sdim default: 2101218822Sdim abort (); 2102218822Sdim } 2103218822Sdim } 2104218822Sdim } 2105218822Sdim else 2106218822Sdim func (stream, "%c", *c); 2107218822Sdim } 2108218822Sdim return TRUE; 2109218822Sdim } 2110218822Sdim } 2111218822Sdim return FALSE; 2112218822Sdim} 2113218822Sdim 2114218822Sdimstatic void 2115218822Sdimprint_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 2116218822Sdim{ 2117218822Sdim void *stream = info->stream; 2118218822Sdim fprintf_ftype func = info->fprintf_func; 2119218822Sdim 2120218822Sdim if (((given & 0x000f0000) == 0x000f0000) 2121218822Sdim && ((given & 0x02000000) == 0)) 2122218822Sdim { 2123218822Sdim int offset = given & 0xfff; 2124218822Sdim 2125218822Sdim func (stream, "[pc"); 2126218822Sdim 2127218822Sdim if (given & 0x01000000) 2128218822Sdim { 2129218822Sdim if ((given & 0x00800000) == 0) 2130218822Sdim offset = - offset; 2131218822Sdim 2132218822Sdim /* Pre-indexed. */ 2133218822Sdim func (stream, ", #%d]", offset); 2134218822Sdim 2135218822Sdim offset += pc + 8; 2136218822Sdim 2137218822Sdim /* Cope with the possibility of write-back 2138218822Sdim being used. Probably a very dangerous thing 2139218822Sdim for the programmer to do, but who are we to 2140218822Sdim argue ? */ 2141218822Sdim if (given & 0x00200000) 2142218822Sdim func (stream, "!"); 2143218822Sdim } 2144218822Sdim else 2145218822Sdim { 2146218822Sdim /* Post indexed. */ 2147218822Sdim func (stream, "], #%d", offset); 2148218822Sdim 2149218822Sdim /* ie ignore the offset. */ 2150218822Sdim offset = pc + 8; 2151218822Sdim } 2152218822Sdim 2153218822Sdim func (stream, "\t; "); 2154218822Sdim info->print_address_func (offset, info); 2155218822Sdim } 2156218822Sdim else 2157218822Sdim { 2158218822Sdim func (stream, "[%s", 2159218822Sdim arm_regnames[(given >> 16) & 0xf]); 2160218822Sdim if ((given & 0x01000000) != 0) 2161218822Sdim { 2162218822Sdim if ((given & 0x02000000) == 0) 2163218822Sdim { 2164218822Sdim int offset = given & 0xfff; 2165218822Sdim if (offset) 2166218822Sdim func (stream, ", #%s%d", 2167218822Sdim (((given & 0x00800000) == 0) 2168218822Sdim ? "-" : ""), offset); 2169218822Sdim } 2170218822Sdim else 2171218822Sdim { 2172218822Sdim func (stream, ", %s", 2173218822Sdim (((given & 0x00800000) == 0) 2174218822Sdim ? "-" : "")); 2175218822Sdim arm_decode_shift (given, func, stream, 1); 2176218822Sdim } 2177218822Sdim 2178218822Sdim func (stream, "]%s", 2179218822Sdim ((given & 0x00200000) != 0) ? "!" : ""); 2180218822Sdim } 2181218822Sdim else 2182218822Sdim { 2183218822Sdim if ((given & 0x02000000) == 0) 2184218822Sdim { 2185218822Sdim int offset = given & 0xfff; 2186218822Sdim if (offset) 2187218822Sdim func (stream, "], #%s%d", 2188218822Sdim (((given & 0x00800000) == 0) 2189218822Sdim ? "-" : ""), offset); 2190218822Sdim else 2191218822Sdim func (stream, "]"); 2192218822Sdim } 2193218822Sdim else 2194218822Sdim { 2195218822Sdim func (stream, "], %s", 2196218822Sdim (((given & 0x00800000) == 0) 2197218822Sdim ? "-" : "")); 2198218822Sdim arm_decode_shift (given, func, stream, 1); 2199218822Sdim } 2200218822Sdim } 2201218822Sdim } 2202218822Sdim} 2203218822Sdim 2204218822Sdim/* Print one neon instruction on INFO->STREAM. 2205218822Sdim Return TRUE if the instuction matched, FALSE if this is not a 2206218822Sdim recognised neon instruction. */ 2207218822Sdim 2208218822Sdimstatic bfd_boolean 2209218822Sdimprint_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 2210218822Sdim{ 2211218822Sdim const struct opcode32 *insn; 2212218822Sdim void *stream = info->stream; 2213218822Sdim fprintf_ftype func = info->fprintf_func; 2214218822Sdim 2215218822Sdim if (thumb) 2216218822Sdim { 2217218822Sdim if ((given & 0xef000000) == 0xef000000) 2218218822Sdim { 2219218822Sdim /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 2220218822Sdim unsigned long bit28 = given & (1 << 28); 2221218822Sdim 2222218822Sdim given &= 0x00ffffff; 2223218822Sdim if (bit28) 2224218822Sdim given |= 0xf3000000; 2225218822Sdim else 2226218822Sdim given |= 0xf2000000; 2227218822Sdim } 2228218822Sdim else if ((given & 0xff000000) == 0xf9000000) 2229218822Sdim given ^= 0xf9000000 ^ 0xf4000000; 2230218822Sdim else 2231218822Sdim return FALSE; 2232218822Sdim } 2233218822Sdim 2234218822Sdim for (insn = neon_opcodes; insn->assembler; insn++) 2235218822Sdim { 2236218822Sdim if ((given & insn->mask) == insn->value) 2237218822Sdim { 2238218822Sdim const char *c; 2239218822Sdim 2240218822Sdim for (c = insn->assembler; *c; c++) 2241218822Sdim { 2242218822Sdim if (*c == '%') 2243218822Sdim { 2244218822Sdim switch (*++c) 2245218822Sdim { 2246218822Sdim case '%': 2247218822Sdim func (stream, "%%"); 224860484Sobrien break; 224960484Sobrien 2250218822Sdim case 'c': 2251218822Sdim if (thumb && ifthen_state) 2252218822Sdim func (stream, "%s", arm_conditional[IFTHEN_COND]); 2253218822Sdim break; 2254218822Sdim 2255218822Sdim case 'A': 2256218822Sdim { 2257218822Sdim static const unsigned char enc[16] = 2258218822Sdim { 2259218822Sdim 0x4, 0x14, /* st4 0,1 */ 2260218822Sdim 0x4, /* st1 2 */ 2261218822Sdim 0x4, /* st2 3 */ 2262218822Sdim 0x3, /* st3 4 */ 2263218822Sdim 0x13, /* st3 5 */ 2264218822Sdim 0x3, /* st1 6 */ 2265218822Sdim 0x1, /* st1 7 */ 2266218822Sdim 0x2, /* st2 8 */ 2267218822Sdim 0x12, /* st2 9 */ 2268218822Sdim 0x2, /* st1 10 */ 2269218822Sdim 0, 0, 0, 0, 0 2270218822Sdim }; 2271218822Sdim int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 2272218822Sdim int rn = ((given >> 16) & 0xf); 2273218822Sdim int rm = ((given >> 0) & 0xf); 2274218822Sdim int align = ((given >> 4) & 0x3); 2275218822Sdim int type = ((given >> 8) & 0xf); 2276218822Sdim int n = enc[type] & 0xf; 2277218822Sdim int stride = (enc[type] >> 4) + 1; 2278218822Sdim int ix; 2279218822Sdim 2280218822Sdim func (stream, "{"); 2281218822Sdim if (stride > 1) 2282218822Sdim for (ix = 0; ix != n; ix++) 2283218822Sdim func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 2284218822Sdim else if (n == 1) 2285218822Sdim func (stream, "d%d", rd); 2286218822Sdim else 2287218822Sdim func (stream, "d%d-d%d", rd, rd + n - 1); 2288218822Sdim func (stream, "}, [%s", arm_regnames[rn]); 2289218822Sdim if (align) 2290218822Sdim func (stream, ", :%d", 32 << align); 2291218822Sdim func (stream, "]"); 2292218822Sdim if (rm == 0xd) 2293218822Sdim func (stream, "!"); 2294218822Sdim else if (rm != 0xf) 2295218822Sdim func (stream, ", %s", arm_regnames[rm]); 2296218822Sdim } 2297218822Sdim break; 2298218822Sdim 2299218822Sdim case 'B': 2300218822Sdim { 2301218822Sdim int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 2302218822Sdim int rn = ((given >> 16) & 0xf); 2303218822Sdim int rm = ((given >> 0) & 0xf); 2304218822Sdim int idx_align = ((given >> 4) & 0xf); 2305218822Sdim int align = 0; 2306218822Sdim int size = ((given >> 10) & 0x3); 2307218822Sdim int idx = idx_align >> (size + 1); 2308218822Sdim int length = ((given >> 8) & 3) + 1; 2309218822Sdim int stride = 1; 2310218822Sdim int i; 2311218822Sdim 2312218822Sdim if (length > 1 && size > 0) 2313218822Sdim stride = (idx_align & (1 << size)) ? 2 : 1; 2314218822Sdim 2315218822Sdim switch (length) 2316218822Sdim { 2317218822Sdim case 1: 2318218822Sdim { 2319218822Sdim int amask = (1 << size) - 1; 2320218822Sdim if ((idx_align & (1 << size)) != 0) 2321218822Sdim return FALSE; 2322218822Sdim if (size > 0) 2323218822Sdim { 2324218822Sdim if ((idx_align & amask) == amask) 2325218822Sdim align = 8 << size; 2326218822Sdim else if ((idx_align & amask) != 0) 2327218822Sdim return FALSE; 2328218822Sdim } 2329218822Sdim } 2330218822Sdim break; 2331218822Sdim 2332218822Sdim case 2: 2333218822Sdim if (size == 2 && (idx_align & 2) != 0) 2334218822Sdim return FALSE; 2335218822Sdim align = (idx_align & 1) ? 16 << size : 0; 2336218822Sdim break; 2337218822Sdim 2338218822Sdim case 3: 2339218822Sdim if ((size == 2 && (idx_align & 3) != 0) 2340218822Sdim || (idx_align & 1) != 0) 2341218822Sdim return FALSE; 2342218822Sdim break; 2343218822Sdim 2344218822Sdim case 4: 2345218822Sdim if (size == 2) 2346218822Sdim { 2347218822Sdim if ((idx_align & 3) == 3) 2348218822Sdim return FALSE; 2349218822Sdim align = (idx_align & 3) * 64; 2350218822Sdim } 2351218822Sdim else 2352218822Sdim align = (idx_align & 1) ? 32 << size : 0; 2353218822Sdim break; 2354218822Sdim 2355218822Sdim default: 2356218822Sdim abort (); 2357218822Sdim } 2358218822Sdim 2359218822Sdim func (stream, "{"); 2360218822Sdim for (i = 0; i < length; i++) 2361218822Sdim func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 2362218822Sdim rd + i * stride, idx); 2363218822Sdim func (stream, "}, [%s", arm_regnames[rn]); 2364218822Sdim if (align) 2365218822Sdim func (stream, ", :%d", align); 2366218822Sdim func (stream, "]"); 2367218822Sdim if (rm == 0xd) 2368218822Sdim func (stream, "!"); 2369218822Sdim else if (rm != 0xf) 2370218822Sdim func (stream, ", %s", arm_regnames[rm]); 2371218822Sdim } 2372218822Sdim break; 2373218822Sdim 2374218822Sdim case 'C': 2375218822Sdim { 2376218822Sdim int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 2377218822Sdim int rn = ((given >> 16) & 0xf); 2378218822Sdim int rm = ((given >> 0) & 0xf); 2379218822Sdim int align = ((given >> 4) & 0x1); 2380218822Sdim int size = ((given >> 6) & 0x3); 2381218822Sdim int type = ((given >> 8) & 0x3); 2382218822Sdim int n = type + 1; 2383218822Sdim int stride = ((given >> 5) & 0x1); 2384218822Sdim int ix; 2385218822Sdim 2386218822Sdim if (stride && (n == 1)) 2387218822Sdim n++; 2388218822Sdim else 2389218822Sdim stride++; 2390218822Sdim 2391218822Sdim func (stream, "{"); 2392218822Sdim if (stride > 1) 2393218822Sdim for (ix = 0; ix != n; ix++) 2394218822Sdim func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 2395218822Sdim else if (n == 1) 2396218822Sdim func (stream, "d%d[]", rd); 2397218822Sdim else 2398218822Sdim func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 2399218822Sdim func (stream, "}, [%s", arm_regnames[rn]); 2400218822Sdim if (align) 2401218822Sdim { 2402218822Sdim int align = (8 * (type + 1)) << size; 2403218822Sdim if (type == 3) 2404218822Sdim align = (size > 1) ? align >> 1 : align; 2405218822Sdim if (type == 2 || (type == 0 && !size)) 2406218822Sdim func (stream, ", :<bad align %d>", align); 2407218822Sdim else 2408218822Sdim func (stream, ", :%d", align); 2409218822Sdim } 2410218822Sdim func (stream, "]"); 2411218822Sdim if (rm == 0xd) 2412218822Sdim func (stream, "!"); 2413218822Sdim else if (rm != 0xf) 2414218822Sdim func (stream, ", %s", arm_regnames[rm]); 2415218822Sdim } 2416218822Sdim break; 2417218822Sdim 2418218822Sdim case 'D': 2419218822Sdim { 2420218822Sdim int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 2421218822Sdim int size = (given >> 20) & 3; 2422218822Sdim int reg = raw_reg & ((4 << size) - 1); 2423218822Sdim int ix = raw_reg >> size >> 2; 2424218822Sdim 2425218822Sdim func (stream, "d%d[%d]", reg, ix); 2426218822Sdim } 2427218822Sdim break; 2428218822Sdim 2429218822Sdim case 'E': 2430218822Sdim /* Neon encoded constant for mov, mvn, vorr, vbic */ 2431218822Sdim { 2432218822Sdim int bits = 0; 2433218822Sdim int cmode = (given >> 8) & 0xf; 2434218822Sdim int op = (given >> 5) & 0x1; 2435218822Sdim unsigned long value = 0, hival = 0; 2436218822Sdim unsigned shift; 2437218822Sdim int size = 0; 2438218822Sdim int isfloat = 0; 2439218822Sdim 2440218822Sdim bits |= ((given >> 24) & 1) << 7; 2441218822Sdim bits |= ((given >> 16) & 7) << 4; 2442218822Sdim bits |= ((given >> 0) & 15) << 0; 2443218822Sdim 2444218822Sdim if (cmode < 8) 2445218822Sdim { 2446218822Sdim shift = (cmode >> 1) & 3; 2447218822Sdim value = (unsigned long)bits << (8 * shift); 2448218822Sdim size = 32; 2449218822Sdim } 2450218822Sdim else if (cmode < 12) 2451218822Sdim { 2452218822Sdim shift = (cmode >> 1) & 1; 2453218822Sdim value = (unsigned long)bits << (8 * shift); 2454218822Sdim size = 16; 2455218822Sdim } 2456218822Sdim else if (cmode < 14) 2457218822Sdim { 2458218822Sdim shift = (cmode & 1) + 1; 2459218822Sdim value = (unsigned long)bits << (8 * shift); 2460218822Sdim value |= (1ul << (8 * shift)) - 1; 2461218822Sdim size = 32; 2462218822Sdim } 2463218822Sdim else if (cmode == 14) 2464218822Sdim { 2465218822Sdim if (op) 2466218822Sdim { 2467218822Sdim /* bit replication into bytes */ 2468218822Sdim int ix; 2469218822Sdim unsigned long mask; 2470218822Sdim 2471218822Sdim value = 0; 2472218822Sdim hival = 0; 2473218822Sdim for (ix = 7; ix >= 0; ix--) 2474218822Sdim { 2475218822Sdim mask = ((bits >> ix) & 1) ? 0xff : 0; 2476218822Sdim if (ix <= 3) 2477218822Sdim value = (value << 8) | mask; 2478218822Sdim else 2479218822Sdim hival = (hival << 8) | mask; 2480218822Sdim } 2481218822Sdim size = 64; 2482218822Sdim } 2483218822Sdim else 2484218822Sdim { 2485218822Sdim /* byte replication */ 2486218822Sdim value = (unsigned long)bits; 2487218822Sdim size = 8; 2488218822Sdim } 2489218822Sdim } 2490218822Sdim else if (!op) 2491218822Sdim { 2492218822Sdim /* floating point encoding */ 2493218822Sdim int tmp; 2494218822Sdim 2495218822Sdim value = (unsigned long)(bits & 0x7f) << 19; 2496218822Sdim value |= (unsigned long)(bits & 0x80) << 24; 2497218822Sdim tmp = bits & 0x40 ? 0x3c : 0x40; 2498218822Sdim value |= (unsigned long)tmp << 24; 2499218822Sdim size = 32; 2500218822Sdim isfloat = 1; 2501218822Sdim } 2502218822Sdim else 2503218822Sdim { 2504218822Sdim func (stream, "<illegal constant %.8x:%x:%x>", 2505218822Sdim bits, cmode, op); 2506218822Sdim size = 32; 2507218822Sdim break; 2508218822Sdim } 2509218822Sdim switch (size) 2510218822Sdim { 2511218822Sdim case 8: 2512218822Sdim func (stream, "#%ld\t; 0x%.2lx", value, value); 2513218822Sdim break; 2514218822Sdim 2515218822Sdim case 16: 2516218822Sdim func (stream, "#%ld\t; 0x%.4lx", value, value); 2517218822Sdim break; 2518218822Sdim 2519218822Sdim case 32: 2520218822Sdim if (isfloat) 2521218822Sdim { 2522218822Sdim unsigned char valbytes[4]; 2523218822Sdim double fvalue; 2524218822Sdim 2525218822Sdim /* Do this a byte at a time so we don't have to 2526218822Sdim worry about the host's endianness. */ 2527218822Sdim valbytes[0] = value & 0xff; 2528218822Sdim valbytes[1] = (value >> 8) & 0xff; 2529218822Sdim valbytes[2] = (value >> 16) & 0xff; 2530218822Sdim valbytes[3] = (value >> 24) & 0xff; 2531218822Sdim 2532218822Sdim floatformat_to_double 2533218822Sdim (&floatformat_ieee_single_little, valbytes, 2534218822Sdim &fvalue); 2535218822Sdim 2536218822Sdim func (stream, "#%.7g\t; 0x%.8lx", fvalue, 2537218822Sdim value); 2538218822Sdim } 2539218822Sdim else 2540218822Sdim func (stream, "#%ld\t; 0x%.8lx", 2541218822Sdim (long) ((value & 0x80000000) 2542218822Sdim ? value | ~0xffffffffl : value), value); 2543218822Sdim break; 2544218822Sdim 2545218822Sdim case 64: 2546218822Sdim func (stream, "#0x%.8lx%.8lx", hival, value); 2547218822Sdim break; 2548218822Sdim 2549218822Sdim default: 2550218822Sdim abort (); 2551218822Sdim } 2552218822Sdim } 2553218822Sdim break; 2554218822Sdim 2555218822Sdim case 'F': 2556218822Sdim { 2557218822Sdim int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 2558218822Sdim int num = (given >> 8) & 0x3; 2559218822Sdim 2560218822Sdim if (!num) 2561218822Sdim func (stream, "{d%d}", regno); 2562218822Sdim else if (num + regno >= 32) 2563218822Sdim func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 2564218822Sdim else 2565218822Sdim func (stream, "{d%d-d%d}", regno, regno + num); 2566218822Sdim } 2567218822Sdim break; 2568218822Sdim 2569218822Sdim 2570218822Sdim case '0': case '1': case '2': case '3': case '4': 2571218822Sdim case '5': case '6': case '7': case '8': case '9': 2572218822Sdim { 2573218822Sdim int width; 2574218822Sdim unsigned long value; 2575218822Sdim 2576218822Sdim c = arm_decode_bitfield (c, given, &value, &width); 2577218822Sdim 2578218822Sdim switch (*c) 2579218822Sdim { 2580218822Sdim case 'r': 2581218822Sdim func (stream, "%s", arm_regnames[value]); 2582218822Sdim break; 2583218822Sdim case 'd': 2584218822Sdim func (stream, "%ld", value); 2585218822Sdim break; 2586218822Sdim case 'e': 2587218822Sdim func (stream, "%ld", (1ul << width) - value); 2588218822Sdim break; 2589218822Sdim 2590218822Sdim case 'S': 2591218822Sdim case 'T': 2592218822Sdim case 'U': 2593218822Sdim /* various width encodings */ 2594218822Sdim { 2595218822Sdim int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 2596218822Sdim int limit; 2597218822Sdim unsigned low, high; 2598218822Sdim 2599218822Sdim c++; 2600218822Sdim if (*c >= '0' && *c <= '9') 2601218822Sdim limit = *c - '0'; 2602218822Sdim else if (*c >= 'a' && *c <= 'f') 2603218822Sdim limit = *c - 'a' + 10; 2604218822Sdim else 2605218822Sdim abort (); 2606218822Sdim low = limit >> 2; 2607218822Sdim high = limit & 3; 2608218822Sdim 2609218822Sdim if (value < low || value > high) 2610218822Sdim func (stream, "<illegal width %d>", base << value); 2611218822Sdim else 2612218822Sdim func (stream, "%d", base << value); 2613218822Sdim } 2614218822Sdim break; 2615218822Sdim case 'R': 2616218822Sdim if (given & (1 << 6)) 2617218822Sdim goto Q; 2618218822Sdim /* FALLTHROUGH */ 2619218822Sdim case 'D': 2620218822Sdim func (stream, "d%ld", value); 2621218822Sdim break; 2622218822Sdim case 'Q': 2623218822Sdim Q: 2624218822Sdim if (value & 1) 2625218822Sdim func (stream, "<illegal reg q%ld.5>", value >> 1); 2626218822Sdim else 2627218822Sdim func (stream, "q%ld", value >> 1); 2628218822Sdim break; 2629218822Sdim 2630218822Sdim case '`': 2631218822Sdim c++; 2632218822Sdim if (value == 0) 2633218822Sdim func (stream, "%c", *c); 2634218822Sdim break; 2635218822Sdim case '\'': 2636218822Sdim c++; 2637218822Sdim if (value == ((1ul << width) - 1)) 2638218822Sdim func (stream, "%c", *c); 2639218822Sdim break; 2640218822Sdim case '?': 2641218822Sdim func (stream, "%c", c[(1 << width) - (int)value]); 2642218822Sdim c += 1 << width; 2643218822Sdim break; 2644218822Sdim default: 2645218822Sdim abort (); 2646218822Sdim } 2647218822Sdim break; 2648218822Sdim 2649218822Sdim default: 2650218822Sdim abort (); 2651218822Sdim } 2652218822Sdim } 2653218822Sdim } 2654218822Sdim else 2655218822Sdim func (stream, "%c", *c); 2656218822Sdim } 2657218822Sdim return TRUE; 2658218822Sdim } 2659218822Sdim } 2660218822Sdim return FALSE; 2661218822Sdim} 2662218822Sdim 2663218822Sdim/* Print one ARM instruction from PC on INFO->STREAM. */ 2664218822Sdim 2665218822Sdimstatic void 2666218822Sdimprint_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 2667218822Sdim{ 2668218822Sdim const struct opcode32 *insn; 2669218822Sdim void *stream = info->stream; 2670218822Sdim fprintf_ftype func = info->fprintf_func; 2671218822Sdim 2672218822Sdim if (print_insn_coprocessor (pc, info, given, FALSE)) 2673218822Sdim return; 2674218822Sdim 2675218822Sdim if (print_insn_neon (info, given, FALSE)) 2676218822Sdim return; 2677218822Sdim 2678218822Sdim for (insn = arm_opcodes; insn->assembler; insn++) 2679218822Sdim { 2680218822Sdim if (insn->value == FIRST_IWMMXT_INSN 2681218822Sdim && info->mach != bfd_mach_arm_XScale 2682218822Sdim && info->mach != bfd_mach_arm_iWMMXt) 2683218822Sdim insn = insn + IWMMXT_INSN_COUNT; 2684218822Sdim 2685218822Sdim if ((given & insn->mask) == insn->value 2686218822Sdim /* Special case: an instruction with all bits set in the condition field 2687218822Sdim (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 2688218822Sdim or by the catchall at the end of the table. */ 2689218822Sdim && ((given & 0xF0000000) != 0xF0000000 2690218822Sdim || (insn->mask & 0xF0000000) == 0xF0000000 2691218822Sdim || (insn->mask == 0 && insn->value == 0))) 2692218822Sdim { 2693218822Sdim const char *c; 2694218822Sdim 2695218822Sdim for (c = insn->assembler; *c; c++) 2696218822Sdim { 2697218822Sdim if (*c == '%') 2698218822Sdim { 2699218822Sdim switch (*++c) 2700218822Sdim { 2701218822Sdim case '%': 2702218822Sdim func (stream, "%%"); 2703218822Sdim break; 2704218822Sdim 2705218822Sdim case 'a': 2706218822Sdim print_arm_address (pc, info, given); 2707218822Sdim break; 2708218822Sdim 2709218822Sdim case 'P': 2710218822Sdim /* Set P address bit and use normal address 2711218822Sdim printing routine. */ 2712218822Sdim print_arm_address (pc, info, given | (1 << 24)); 2713218822Sdim break; 2714218822Sdim 271560484Sobrien case 's': 271660484Sobrien if ((given & 0x004f0000) == 0x004f0000) 271760484Sobrien { 271860484Sobrien /* PC relative with immediate offset. */ 271960484Sobrien int offset = ((given & 0xf00) >> 4) | (given & 0xf); 2720130561Sobrien 272160484Sobrien if ((given & 0x00800000) == 0) 272260484Sobrien offset = -offset; 2723130561Sobrien 272480016Sobrien func (stream, "[pc, #%d]\t; ", offset); 2725218822Sdim info->print_address_func (offset + pc + 8, info); 272660484Sobrien } 272760484Sobrien else 272860484Sobrien { 2729130561Sobrien func (stream, "[%s", 273060484Sobrien arm_regnames[(given >> 16) & 0xf]); 273160484Sobrien if ((given & 0x01000000) != 0) 273260484Sobrien { 273360484Sobrien /* Pre-indexed. */ 273460484Sobrien if ((given & 0x00400000) == 0x00400000) 273560484Sobrien { 273660484Sobrien /* Immediate. */ 273760484Sobrien int offset = ((given & 0xf00) >> 4) | (given & 0xf); 273860484Sobrien if (offset) 2739130561Sobrien func (stream, ", #%s%d", 274060484Sobrien (((given & 0x00800000) == 0) 274160484Sobrien ? "-" : ""), offset); 274260484Sobrien } 274360484Sobrien else 274460484Sobrien { 274560484Sobrien /* Register. */ 274660484Sobrien func (stream, ", %s%s", 274760484Sobrien (((given & 0x00800000) == 0) 274860484Sobrien ? "-" : ""), 274960484Sobrien arm_regnames[given & 0xf]); 275060484Sobrien } 275160484Sobrien 2752130561Sobrien func (stream, "]%s", 275360484Sobrien ((given & 0x00200000) != 0) ? "!" : ""); 275460484Sobrien } 275560484Sobrien else 275660484Sobrien { 275760484Sobrien /* Post-indexed. */ 275860484Sobrien if ((given & 0x00400000) == 0x00400000) 275960484Sobrien { 276060484Sobrien /* Immediate. */ 276160484Sobrien int offset = ((given & 0xf00) >> 4) | (given & 0xf); 276260484Sobrien if (offset) 2763130561Sobrien func (stream, "], #%s%d", 276460484Sobrien (((given & 0x00800000) == 0) 276560484Sobrien ? "-" : ""), offset); 2766130561Sobrien else 276760484Sobrien func (stream, "]"); 276860484Sobrien } 276960484Sobrien else 277060484Sobrien { 277160484Sobrien /* Register. */ 277260484Sobrien func (stream, "], %s%s", 277360484Sobrien (((given & 0x00800000) == 0) 277460484Sobrien ? "-" : ""), 277560484Sobrien arm_regnames[given & 0xf]); 277660484Sobrien } 277760484Sobrien } 277860484Sobrien } 277960484Sobrien break; 2780130561Sobrien 278160484Sobrien case 'b': 2782218822Sdim { 2783218822Sdim int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 2784218822Sdim info->print_address_func (disp*4 + pc + 8, info); 2785218822Sdim } 278660484Sobrien break; 278760484Sobrien 278860484Sobrien case 'c': 2789218822Sdim if (((given >> 28) & 0xf) != 0xe) 2790218822Sdim func (stream, "%s", 2791218822Sdim arm_conditional [(given >> 28) & 0xf]); 279260484Sobrien break; 279360484Sobrien 279460484Sobrien case 'm': 279560484Sobrien { 279660484Sobrien int started = 0; 279760484Sobrien int reg; 279860484Sobrien 279960484Sobrien func (stream, "{"); 280060484Sobrien for (reg = 0; reg < 16; reg++) 280160484Sobrien if ((given & (1 << reg)) != 0) 280260484Sobrien { 280360484Sobrien if (started) 280460484Sobrien func (stream, ", "); 280560484Sobrien started = 1; 280660484Sobrien func (stream, "%s", arm_regnames[reg]); 280760484Sobrien } 280860484Sobrien func (stream, "}"); 280960484Sobrien } 281060484Sobrien break; 281160484Sobrien 2812218822Sdim case 'q': 2813218822Sdim arm_decode_shift (given, func, stream, 0); 2814218822Sdim break; 2815218822Sdim 281660484Sobrien case 'o': 281760484Sobrien if ((given & 0x02000000) != 0) 281860484Sobrien { 281960484Sobrien int rotate = (given & 0xf00) >> 7; 282060484Sobrien int immed = (given & 0xff); 282160484Sobrien immed = (((immed << (32 - rotate)) 282260484Sobrien | (immed >> rotate)) & 0xffffffff); 282360484Sobrien func (stream, "#%d\t; 0x%x", immed, immed); 282460484Sobrien } 282560484Sobrien else 2826218822Sdim arm_decode_shift (given, func, stream, 1); 282760484Sobrien break; 282860484Sobrien 282960484Sobrien case 'p': 283060484Sobrien if ((given & 0x0000f000) == 0x0000f000) 283160484Sobrien func (stream, "p"); 283260484Sobrien break; 283360484Sobrien 283460484Sobrien case 't': 283560484Sobrien if ((given & 0x01200000) == 0x00200000) 283660484Sobrien func (stream, "t"); 283760484Sobrien break; 283860484Sobrien 283960484Sobrien case 'A': 284060484Sobrien func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 2841130561Sobrien 2842130561Sobrien if ((given & (1 << 24)) != 0) 284360484Sobrien { 284460484Sobrien int offset = given & 0xff; 2845130561Sobrien 284660484Sobrien if (offset) 2847130561Sobrien func (stream, ", #%s%d]%s", 284860484Sobrien ((given & 0x00800000) == 0 ? "-" : ""), 284960484Sobrien offset * 4, 285060484Sobrien ((given & 0x00200000) != 0 ? "!" : "")); 285160484Sobrien else 285260484Sobrien func (stream, "]"); 285360484Sobrien } 285460484Sobrien else 285560484Sobrien { 285660484Sobrien int offset = given & 0xff; 2857130561Sobrien 2858130561Sobrien func (stream, "]"); 2859130561Sobrien 2860130561Sobrien if (given & (1 << 21)) 2861130561Sobrien { 2862130561Sobrien if (offset) 2863130561Sobrien func (stream, ", #%s%d", 2864130561Sobrien ((given & 0x00800000) == 0 ? "-" : ""), 2865130561Sobrien offset * 4); 2866130561Sobrien } 286760484Sobrien else 2868130561Sobrien func (stream, ", {%d}", offset); 286960484Sobrien } 287060484Sobrien break; 287160484Sobrien 287277298Sobrien case 'B': 287377298Sobrien /* Print ARM V5 BLX(1) address: pc+25 bits. */ 287477298Sobrien { 287577298Sobrien bfd_vma address; 287677298Sobrien bfd_vma offset = 0; 2877130561Sobrien 287877298Sobrien if (given & 0x00800000) 287977298Sobrien /* Is signed, hi bits should be ones. */ 288077298Sobrien offset = (-1) ^ 0x00ffffff; 288177298Sobrien 288277298Sobrien /* Offset is (SignExtend(offset field)<<2). */ 288377298Sobrien offset += given & 0x00ffffff; 288477298Sobrien offset <<= 2; 288577298Sobrien address = offset + pc + 8; 2886130561Sobrien 288777298Sobrien if (given & 0x01000000) 288877298Sobrien /* H bit allows addressing to 2-byte boundaries. */ 288977298Sobrien address += 2; 289077298Sobrien 289177298Sobrien info->print_address_func (address, info); 289277298Sobrien } 289377298Sobrien break; 289477298Sobrien 289560484Sobrien case 'C': 289677298Sobrien func (stream, "_"); 289777298Sobrien if (given & 0x80000) 289877298Sobrien func (stream, "f"); 289977298Sobrien if (given & 0x40000) 290077298Sobrien func (stream, "s"); 290177298Sobrien if (given & 0x20000) 290277298Sobrien func (stream, "x"); 290377298Sobrien if (given & 0x10000) 290477298Sobrien func (stream, "c"); 290560484Sobrien break; 290660484Sobrien 2907218822Sdim case 'U': 2908218822Sdim switch (given & 0xf) 290960484Sobrien { 2910218822Sdim case 0xf: func(stream, "sy"); break; 2911218822Sdim case 0x7: func(stream, "un"); break; 2912218822Sdim case 0xe: func(stream, "st"); break; 2913218822Sdim case 0x6: func(stream, "unst"); break; 291460484Sobrien default: 2915218822Sdim func(stream, "#%d", (int)given & 0xf); 291660484Sobrien break; 291760484Sobrien } 291860484Sobrien break; 291960484Sobrien 2920130561Sobrien case '0': case '1': case '2': case '3': case '4': 292160484Sobrien case '5': case '6': case '7': case '8': case '9': 292260484Sobrien { 2923218822Sdim int width; 2924218822Sdim unsigned long value; 292560484Sobrien 2926218822Sdim c = arm_decode_bitfield (c, given, &value, &width); 2927218822Sdim 292860484Sobrien switch (*c) 292960484Sobrien { 2930218822Sdim case 'r': 2931218822Sdim func (stream, "%s", arm_regnames[value]); 2932218822Sdim break; 2933218822Sdim case 'd': 2934218822Sdim func (stream, "%ld", value); 2935218822Sdim break; 2936218822Sdim case 'b': 2937218822Sdim func (stream, "%ld", value * 8); 2938218822Sdim break; 2939218822Sdim case 'W': 2940218822Sdim func (stream, "%ld", value + 1); 2941218822Sdim break; 2942218822Sdim case 'x': 2943218822Sdim func (stream, "0x%08lx", value); 2944218822Sdim 2945218822Sdim /* Some SWI instructions have special 2946218822Sdim meanings. */ 2947218822Sdim if ((given & 0x0fffffff) == 0x0FF00000) 2948218822Sdim func (stream, "\t; IMB"); 2949218822Sdim else if ((given & 0x0fffffff) == 0x0FF00001) 2950218822Sdim func (stream, "\t; IMBRange"); 2951218822Sdim break; 2952218822Sdim case 'X': 2953218822Sdim func (stream, "%01lx", value & 0xf); 2954218822Sdim break; 2955218822Sdim case '`': 295660484Sobrien c++; 2957218822Sdim if (value == 0) 2958218822Sdim func (stream, "%c", *c); 2959218822Sdim break; 2960218822Sdim case '\'': 2961218822Sdim c++; 2962218822Sdim if (value == ((1ul << width) - 1)) 2963218822Sdim func (stream, "%c", *c); 2964218822Sdim break; 2965218822Sdim case '?': 2966218822Sdim func (stream, "%c", c[(1 << width) - (int)value]); 2967218822Sdim c += 1 << width; 2968218822Sdim break; 2969218822Sdim default: 2970218822Sdim abort (); 2971218822Sdim } 2972218822Sdim break; 2973130561Sobrien 2974218822Sdim case 'e': 2975218822Sdim { 2976218822Sdim int imm; 2977130561Sobrien 2978218822Sdim imm = (given & 0xf) | ((given & 0xfff00) >> 4); 2979218822Sdim func (stream, "%d", imm); 2980218822Sdim } 2981218822Sdim break; 2982130561Sobrien 2983218822Sdim case 'E': 2984218822Sdim /* LSB and WIDTH fields of BFI or BFC. The machine- 2985218822Sdim language instruction encodes LSB and MSB. */ 2986218822Sdim { 2987218822Sdim long msb = (given & 0x001f0000) >> 16; 2988218822Sdim long lsb = (given & 0x00000f80) >> 7; 2989130561Sobrien 2990218822Sdim long width = msb - lsb + 1; 2991218822Sdim if (width > 0) 2992218822Sdim func (stream, "#%lu, #%lu", lsb, width); 2993218822Sdim else 2994218822Sdim func (stream, "(invalid: %lu:%lu)", lsb, msb); 2995218822Sdim } 2996218822Sdim break; 2997130561Sobrien 2998218822Sdim case 'V': 2999218822Sdim /* 16-bit unsigned immediate from a MOVT or MOVW 3000218822Sdim instruction, encoded in bits 0:11 and 15:19. */ 3001218822Sdim { 3002218822Sdim long hi = (given & 0x000f0000) >> 4; 3003218822Sdim long lo = (given & 0x00000fff); 3004218822Sdim long imm16 = hi | lo; 3005218822Sdim func (stream, "#%lu\t; 0x%lx", imm16, imm16); 3006218822Sdim } 3007218822Sdim break; 3008130561Sobrien 3009218822Sdim default: 3010218822Sdim abort (); 3011218822Sdim } 3012218822Sdim } 3013218822Sdim } 3014218822Sdim else 3015218822Sdim func (stream, "%c", *c); 3016218822Sdim } 3017218822Sdim return; 3018218822Sdim } 3019218822Sdim } 3020218822Sdim abort (); 3021218822Sdim} 3022130561Sobrien 3023218822Sdim/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 3024130561Sobrien 3025218822Sdimstatic void 3026218822Sdimprint_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 3027218822Sdim{ 3028218822Sdim const struct opcode16 *insn; 3029218822Sdim void *stream = info->stream; 3030218822Sdim fprintf_ftype func = info->fprintf_func; 3031130561Sobrien 3032218822Sdim for (insn = thumb_opcodes; insn->assembler; insn++) 3033218822Sdim if ((given & insn->mask) == insn->value) 3034218822Sdim { 3035218822Sdim const char *c = insn->assembler; 3036218822Sdim for (; *c; c++) 3037218822Sdim { 3038218822Sdim int domaskpc = 0; 3039218822Sdim int domasklr = 0; 3040130561Sobrien 3041218822Sdim if (*c != '%') 3042218822Sdim { 3043218822Sdim func (stream, "%c", *c); 3044218822Sdim continue; 3045218822Sdim } 3046130561Sobrien 3047218822Sdim switch (*++c) 3048218822Sdim { 3049218822Sdim case '%': 3050218822Sdim func (stream, "%%"); 3051218822Sdim break; 3052130561Sobrien 3053218822Sdim case 'c': 3054218822Sdim if (ifthen_state) 3055218822Sdim func (stream, "%s", arm_conditional[IFTHEN_COND]); 3056218822Sdim break; 3057130561Sobrien 3058218822Sdim case 'C': 3059218822Sdim if (ifthen_state) 3060218822Sdim func (stream, "%s", arm_conditional[IFTHEN_COND]); 3061218822Sdim else 3062218822Sdim func (stream, "s"); 3063218822Sdim break; 3064130561Sobrien 3065218822Sdim case 'I': 3066218822Sdim { 3067218822Sdim unsigned int tmp; 3068130561Sobrien 3069218822Sdim ifthen_next_state = given & 0xff; 3070218822Sdim for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 3071218822Sdim func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 3072218822Sdim func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 3073218822Sdim } 3074218822Sdim break; 3075130561Sobrien 3076218822Sdim case 'x': 3077218822Sdim if (ifthen_next_state) 3078218822Sdim func (stream, "\t; unpredictable branch in IT block\n"); 3079218822Sdim break; 3080130561Sobrien 3081218822Sdim case 'X': 3082218822Sdim if (ifthen_state) 3083218822Sdim func (stream, "\t; unpredictable <IT:%s>", 3084218822Sdim arm_conditional[IFTHEN_COND]); 3085218822Sdim break; 3086130561Sobrien 3087218822Sdim case 'S': 3088218822Sdim { 3089218822Sdim long reg; 3090130561Sobrien 3091218822Sdim reg = (given >> 3) & 0x7; 3092218822Sdim if (given & (1 << 6)) 3093218822Sdim reg += 8; 3094130561Sobrien 3095218822Sdim func (stream, "%s", arm_regnames[reg]); 3096218822Sdim } 3097218822Sdim break; 3098130561Sobrien 3099218822Sdim case 'D': 3100218822Sdim { 3101218822Sdim long reg; 3102130561Sobrien 3103218822Sdim reg = given & 0x7; 3104218822Sdim if (given & (1 << 7)) 3105218822Sdim reg += 8; 3106130561Sobrien 3107218822Sdim func (stream, "%s", arm_regnames[reg]); 3108218822Sdim } 3109218822Sdim break; 311089857Sobrien 3111218822Sdim case 'N': 3112218822Sdim if (given & (1 << 8)) 3113218822Sdim domasklr = 1; 3114218822Sdim /* Fall through. */ 3115218822Sdim case 'O': 3116218822Sdim if (*c == 'O' && (given & (1 << 8))) 3117218822Sdim domaskpc = 1; 3118218822Sdim /* Fall through. */ 3119218822Sdim case 'M': 3120218822Sdim { 3121218822Sdim int started = 0; 3122218822Sdim int reg; 312389857Sobrien 3124218822Sdim func (stream, "{"); 312589857Sobrien 3126218822Sdim /* It would be nice if we could spot 3127218822Sdim ranges, and generate the rS-rE format: */ 3128218822Sdim for (reg = 0; (reg < 8); reg++) 3129218822Sdim if ((given & (1 << reg)) != 0) 3130218822Sdim { 3131218822Sdim if (started) 3132218822Sdim func (stream, ", "); 3133218822Sdim started = 1; 3134218822Sdim func (stream, "%s", arm_regnames[reg]); 3135218822Sdim } 313689857Sobrien 3137218822Sdim if (domasklr) 3138218822Sdim { 3139218822Sdim if (started) 3140218822Sdim func (stream, ", "); 3141218822Sdim started = 1; 3142218822Sdim func (stream, arm_regnames[14] /* "lr" */); 3143218822Sdim } 314489857Sobrien 3145218822Sdim if (domaskpc) 3146218822Sdim { 3147218822Sdim if (started) 3148218822Sdim func (stream, ", "); 3149218822Sdim func (stream, arm_regnames[15] /* "pc" */); 3150218822Sdim } 315189857Sobrien 3152218822Sdim func (stream, "}"); 3153218822Sdim } 3154218822Sdim break; 3155130561Sobrien 3156218822Sdim case 'b': 3157218822Sdim /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 3158218822Sdim { 3159218822Sdim bfd_vma address = (pc + 4 3160218822Sdim + ((given & 0x00f8) >> 2) 3161218822Sdim + ((given & 0x0200) >> 3)); 3162218822Sdim info->print_address_func (address, info); 3163218822Sdim } 3164218822Sdim break; 316589857Sobrien 3166218822Sdim case 's': 3167218822Sdim /* Right shift immediate -- bits 6..10; 1-31 print 3168218822Sdim as themselves, 0 prints as 32. */ 3169218822Sdim { 3170218822Sdim long imm = (given & 0x07c0) >> 6; 3171218822Sdim if (imm == 0) 3172218822Sdim imm = 32; 3173218822Sdim func (stream, "#%ld", imm); 3174218822Sdim } 3175218822Sdim break; 317689857Sobrien 3177218822Sdim case '0': case '1': case '2': case '3': case '4': 3178218822Sdim case '5': case '6': case '7': case '8': case '9': 3179218822Sdim { 3180218822Sdim int bitstart = *c++ - '0'; 3181218822Sdim int bitend = 0; 318289857Sobrien 3183218822Sdim while (*c >= '0' && *c <= '9') 3184218822Sdim bitstart = (bitstart * 10) + *c++ - '0'; 318589857Sobrien 3186218822Sdim switch (*c) 3187218822Sdim { 3188218822Sdim case '-': 3189218822Sdim { 3190218822Sdim long reg; 319189857Sobrien 3192218822Sdim c++; 3193218822Sdim while (*c >= '0' && *c <= '9') 3194218822Sdim bitend = (bitend * 10) + *c++ - '0'; 3195218822Sdim if (!bitend) 3196218822Sdim abort (); 3197218822Sdim reg = given >> bitstart; 3198218822Sdim reg &= (2 << (bitend - bitstart)) - 1; 3199218822Sdim switch (*c) 3200218822Sdim { 3201218822Sdim case 'r': 3202218822Sdim func (stream, "%s", arm_regnames[reg]); 3203218822Sdim break; 320489857Sobrien 3205218822Sdim case 'd': 3206218822Sdim func (stream, "%ld", reg); 3207218822Sdim break; 320889857Sobrien 3209218822Sdim case 'H': 3210218822Sdim func (stream, "%ld", reg << 1); 321160484Sobrien break; 3212218822Sdim 3213218822Sdim case 'W': 3214218822Sdim func (stream, "%ld", reg << 2); 321560484Sobrien break; 3216218822Sdim 3217218822Sdim case 'a': 3218218822Sdim /* PC-relative address -- the bottom two 3219218822Sdim bits of the address are dropped 3220218822Sdim before the calculation. */ 3221218822Sdim info->print_address_func 3222218822Sdim (((pc + 4) & ~3) + (reg << 2), info); 322360484Sobrien break; 322460484Sobrien 3225218822Sdim case 'x': 3226218822Sdim func (stream, "0x%04lx", reg); 3227130561Sobrien break; 3228130561Sobrien 3229218822Sdim case 'B': 3230218822Sdim reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 3231218822Sdim info->print_address_func (reg * 2 + pc + 4, info); 3232218822Sdim break; 3233130561Sobrien 3234218822Sdim case 'c': 3235218822Sdim func (stream, "%s", arm_conditional [reg]); 3236218822Sdim break; 3237130561Sobrien 3238218822Sdim default: 3239218822Sdim abort (); 3240218822Sdim } 3241218822Sdim } 3242218822Sdim break; 3243130561Sobrien 3244218822Sdim case '\'': 3245218822Sdim c++; 3246218822Sdim if ((given & (1 << bitstart)) != 0) 3247218822Sdim func (stream, "%c", *c); 3248218822Sdim break; 3249130561Sobrien 3250218822Sdim case '?': 3251218822Sdim ++c; 3252218822Sdim if ((given & (1 << bitstart)) != 0) 3253218822Sdim func (stream, "%c", *c++); 3254218822Sdim else 3255218822Sdim func (stream, "%c", *++c); 3256218822Sdim break; 3257218822Sdim 3258218822Sdim default: 3259218822Sdim abort (); 326060484Sobrien } 326160484Sobrien } 3262218822Sdim break; 3263218822Sdim 3264218822Sdim default: 3265218822Sdim abort (); 3266218822Sdim } 3267218822Sdim } 3268218822Sdim return; 3269218822Sdim } 3270218822Sdim 3271218822Sdim /* No match. */ 327260484Sobrien abort (); 327360484Sobrien} 327460484Sobrien 3275218822Sdim/* Return the name of an V7M special register. */ 3276218822Sdimstatic const char * 3277218822Sdimpsr_name (int regno) 3278218822Sdim{ 3279218822Sdim switch (regno) 3280218822Sdim { 3281218822Sdim case 0: return "APSR"; 3282218822Sdim case 1: return "IAPSR"; 3283218822Sdim case 2: return "EAPSR"; 3284218822Sdim case 3: return "PSR"; 3285218822Sdim case 5: return "IPSR"; 3286218822Sdim case 6: return "EPSR"; 3287218822Sdim case 7: return "IEPSR"; 3288218822Sdim case 8: return "MSP"; 3289218822Sdim case 9: return "PSP"; 3290218822Sdim case 16: return "PRIMASK"; 3291218822Sdim case 17: return "BASEPRI"; 3292218822Sdim case 18: return "BASEPRI_MASK"; 3293218822Sdim case 19: return "FAULTMASK"; 3294218822Sdim case 20: return "CONTROL"; 3295218822Sdim default: return "<unknown>"; 3296218822Sdim } 3297218822Sdim} 3298104834Sobrien 3299218822Sdim/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 3300218822Sdim 3301218822Sdimstatic void 3302218822Sdimprint_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 330360484Sobrien{ 3304218822Sdim const struct opcode32 *insn; 3305130561Sobrien void *stream = info->stream; 3306130561Sobrien fprintf_ftype func = info->fprintf_func; 330760484Sobrien 3308218822Sdim if (print_insn_coprocessor (pc, info, given, TRUE)) 3309218822Sdim return; 331060484Sobrien 3311218822Sdim if (print_insn_neon (info, given, TRUE)) 3312218822Sdim return; 3313130561Sobrien 3314218822Sdim for (insn = thumb32_opcodes; insn->assembler; insn++) 3315218822Sdim if ((given & insn->mask) == insn->value) 3316218822Sdim { 3317218822Sdim const char *c = insn->assembler; 3318218822Sdim for (; *c; c++) 3319218822Sdim { 3320218822Sdim if (*c != '%') 3321218822Sdim { 3322218822Sdim func (stream, "%c", *c); 3323218822Sdim continue; 3324218822Sdim } 332589857Sobrien 3326218822Sdim switch (*++c) 3327218822Sdim { 3328218822Sdim case '%': 3329218822Sdim func (stream, "%%"); 3330218822Sdim break; 3331104834Sobrien 3332218822Sdim case 'c': 3333218822Sdim if (ifthen_state) 3334218822Sdim func (stream, "%s", arm_conditional[IFTHEN_COND]); 3335218822Sdim break; 3336218822Sdim 3337218822Sdim case 'x': 3338218822Sdim if (ifthen_next_state) 3339218822Sdim func (stream, "\t; unpredictable branch in IT block\n"); 3340218822Sdim break; 3341218822Sdim 3342218822Sdim case 'X': 3343218822Sdim if (ifthen_state) 3344218822Sdim func (stream, "\t; unpredictable <IT:%s>", 3345218822Sdim arm_conditional[IFTHEN_COND]); 3346218822Sdim break; 3347218822Sdim 3348218822Sdim case 'I': 334989857Sobrien { 3350218822Sdim unsigned int imm12 = 0; 3351218822Sdim imm12 |= (given & 0x000000ffu); 3352218822Sdim imm12 |= (given & 0x00007000u) >> 4; 3353218822Sdim imm12 |= (given & 0x04000000u) >> 15; 3354218822Sdim func (stream, "#%u\t; 0x%x", imm12, imm12); 335589857Sobrien } 3356218822Sdim break; 335789857Sobrien 3358218822Sdim case 'M': 3359218822Sdim { 3360218822Sdim unsigned int bits = 0, imm, imm8, mod; 3361218822Sdim bits |= (given & 0x000000ffu); 3362218822Sdim bits |= (given & 0x00007000u) >> 4; 3363218822Sdim bits |= (given & 0x04000000u) >> 15; 3364218822Sdim imm8 = (bits & 0x0ff); 3365218822Sdim mod = (bits & 0xf00) >> 8; 3366218822Sdim switch (mod) 3367218822Sdim { 3368218822Sdim case 0: imm = imm8; break; 3369218822Sdim case 1: imm = ((imm8<<16) | imm8); break; 3370218822Sdim case 2: imm = ((imm8<<24) | (imm8 << 8)); break; 3371218822Sdim case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 3372218822Sdim default: 3373218822Sdim mod = (bits & 0xf80) >> 7; 3374218822Sdim imm8 = (bits & 0x07f) | 0x80; 3375218822Sdim imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 3376218822Sdim } 3377218822Sdim func (stream, "#%u\t; 0x%x", imm, imm); 3378218822Sdim } 3379218822Sdim break; 3380218822Sdim 3381218822Sdim case 'J': 3382218822Sdim { 3383218822Sdim unsigned int imm = 0; 3384218822Sdim imm |= (given & 0x000000ffu); 3385218822Sdim imm |= (given & 0x00007000u) >> 4; 3386218822Sdim imm |= (given & 0x04000000u) >> 15; 3387218822Sdim imm |= (given & 0x000f0000u) >> 4; 3388218822Sdim func (stream, "#%u\t; 0x%x", imm, imm); 3389218822Sdim } 3390218822Sdim break; 3391130561Sobrien 3392218822Sdim case 'K': 3393218822Sdim { 3394218822Sdim unsigned int imm = 0; 3395218822Sdim imm |= (given & 0x000f0000u) >> 16; 3396218822Sdim imm |= (given & 0x00000ff0u) >> 0; 3397218822Sdim imm |= (given & 0x0000000fu) << 12; 3398218822Sdim func (stream, "#%u\t; 0x%x", imm, imm); 3399218822Sdim } 3400218822Sdim break; 3401130561Sobrien 3402218822Sdim case 'S': 3403218822Sdim { 3404218822Sdim unsigned int reg = (given & 0x0000000fu); 3405218822Sdim unsigned int stp = (given & 0x00000030u) >> 4; 3406218822Sdim unsigned int imm = 0; 3407218822Sdim imm |= (given & 0x000000c0u) >> 6; 3408218822Sdim imm |= (given & 0x00007000u) >> 10; 3409130561Sobrien 3410218822Sdim func (stream, "%s", arm_regnames[reg]); 3411218822Sdim switch (stp) 3412218822Sdim { 3413218822Sdim case 0: 3414218822Sdim if (imm > 0) 3415218822Sdim func (stream, ", lsl #%u", imm); 3416218822Sdim break; 341760484Sobrien 3418218822Sdim case 1: 3419218822Sdim if (imm == 0) 3420218822Sdim imm = 32; 3421218822Sdim func (stream, ", lsr #%u", imm); 3422218822Sdim break; 3423130561Sobrien 3424218822Sdim case 2: 3425218822Sdim if (imm == 0) 3426218822Sdim imm = 32; 3427218822Sdim func (stream, ", asr #%u", imm); 3428218822Sdim break; 3429130561Sobrien 3430218822Sdim case 3: 3431218822Sdim if (imm == 0) 3432218822Sdim func (stream, ", rrx"); 3433218822Sdim else 3434218822Sdim func (stream, ", ror #%u", imm); 3435218822Sdim } 3436218822Sdim } 3437218822Sdim break; 343860484Sobrien 3439218822Sdim case 'a': 3440218822Sdim { 3441218822Sdim unsigned int Rn = (given & 0x000f0000) >> 16; 3442218822Sdim unsigned int U = (given & 0x00800000) >> 23; 3443218822Sdim unsigned int op = (given & 0x00000f00) >> 8; 3444218822Sdim unsigned int i12 = (given & 0x00000fff); 3445218822Sdim unsigned int i8 = (given & 0x000000ff); 3446218822Sdim bfd_boolean writeback = FALSE, postind = FALSE; 3447218822Sdim int offset = 0; 3448130561Sobrien 3449218822Sdim func (stream, "[%s", arm_regnames[Rn]); 3450218822Sdim if (U) /* 12-bit positive immediate offset */ 3451218822Sdim offset = i12; 3452218822Sdim else if (Rn == 15) /* 12-bit negative immediate offset */ 3453218822Sdim offset = -(int)i12; 3454218822Sdim else if (op == 0x0) /* shifted register offset */ 3455218822Sdim { 3456218822Sdim unsigned int Rm = (i8 & 0x0f); 3457218822Sdim unsigned int sh = (i8 & 0x30) >> 4; 3458218822Sdim func (stream, ", %s", arm_regnames[Rm]); 3459218822Sdim if (sh) 3460218822Sdim func (stream, ", lsl #%u", sh); 3461218822Sdim func (stream, "]"); 3462218822Sdim break; 3463218822Sdim } 3464218822Sdim else switch (op) 3465218822Sdim { 3466218822Sdim case 0xE: /* 8-bit positive immediate offset */ 3467218822Sdim offset = i8; 3468218822Sdim break; 3469130561Sobrien 3470218822Sdim case 0xC: /* 8-bit negative immediate offset */ 3471218822Sdim offset = -i8; 3472218822Sdim break; 347360484Sobrien 3474218822Sdim case 0xF: /* 8-bit + preindex with wb */ 3475218822Sdim offset = i8; 3476218822Sdim writeback = TRUE; 3477218822Sdim break; 347860484Sobrien 3479218822Sdim case 0xD: /* 8-bit - preindex with wb */ 3480218822Sdim offset = -i8; 3481218822Sdim writeback = TRUE; 3482218822Sdim break; 3483130561Sobrien 3484218822Sdim case 0xB: /* 8-bit + postindex */ 3485218822Sdim offset = i8; 3486218822Sdim postind = TRUE; 3487218822Sdim break; 3488130561Sobrien 3489218822Sdim case 0x9: /* 8-bit - postindex */ 3490218822Sdim offset = -i8; 3491218822Sdim postind = TRUE; 3492218822Sdim break; 349360484Sobrien 3494218822Sdim default: 3495218822Sdim func (stream, ", <undefined>]"); 3496218822Sdim goto skip; 3497218822Sdim } 349860484Sobrien 3499218822Sdim if (postind) 3500218822Sdim func (stream, "], #%d", offset); 3501218822Sdim else 3502218822Sdim { 3503218822Sdim if (offset) 3504218822Sdim func (stream, ", #%d", offset); 3505218822Sdim func (stream, writeback ? "]!" : "]"); 3506218822Sdim } 350760484Sobrien 3508218822Sdim if (Rn == 15) 3509218822Sdim { 3510218822Sdim func (stream, "\t; "); 3511218822Sdim info->print_address_func (((pc + 4) & ~3) + offset, info); 3512218822Sdim } 3513218822Sdim } 3514218822Sdim skip: 3515218822Sdim break; 351660484Sobrien 3517218822Sdim case 'A': 3518218822Sdim { 3519218822Sdim unsigned int P = (given & 0x01000000) >> 24; 3520218822Sdim unsigned int U = (given & 0x00800000) >> 23; 3521218822Sdim unsigned int W = (given & 0x00400000) >> 21; 3522218822Sdim unsigned int Rn = (given & 0x000f0000) >> 16; 3523218822Sdim unsigned int off = (given & 0x000000ff); 352460484Sobrien 3525218822Sdim func (stream, "[%s", arm_regnames[Rn]); 3526218822Sdim if (P) 3527218822Sdim { 3528218822Sdim if (off || !U) 3529218822Sdim func (stream, ", #%c%u", U ? '+' : '-', off * 4); 3530218822Sdim func (stream, "]"); 3531218822Sdim if (W) 3532218822Sdim func (stream, "!"); 3533218822Sdim } 3534218822Sdim else 3535218822Sdim { 3536218822Sdim func (stream, "], "); 3537218822Sdim if (W) 3538218822Sdim func (stream, "#%c%u", U ? '+' : '-', off * 4); 3539218822Sdim else 3540218822Sdim func (stream, "{%u}", off); 3541218822Sdim } 3542218822Sdim } 3543218822Sdim break; 3544130561Sobrien 3545218822Sdim case 'w': 3546218822Sdim { 3547218822Sdim unsigned int Sbit = (given & 0x01000000) >> 24; 3548218822Sdim unsigned int type = (given & 0x00600000) >> 21; 3549218822Sdim switch (type) 3550218822Sdim { 3551218822Sdim case 0: func (stream, Sbit ? "sb" : "b"); break; 3552218822Sdim case 1: func (stream, Sbit ? "sh" : "h"); break; 3553218822Sdim case 2: 3554218822Sdim if (Sbit) 3555218822Sdim func (stream, "??"); 3556218822Sdim break; 3557218822Sdim case 3: 3558218822Sdim func (stream, "??"); 3559218822Sdim break; 3560218822Sdim } 3561218822Sdim } 3562218822Sdim break; 356360484Sobrien 3564218822Sdim case 'm': 3565218822Sdim { 3566218822Sdim int started = 0; 3567218822Sdim int reg; 3568130561Sobrien 3569218822Sdim func (stream, "{"); 3570218822Sdim for (reg = 0; reg < 16; reg++) 3571218822Sdim if ((given & (1 << reg)) != 0) 3572218822Sdim { 3573218822Sdim if (started) 3574218822Sdim func (stream, ", "); 3575218822Sdim started = 1; 3576218822Sdim func (stream, "%s", arm_regnames[reg]); 3577218822Sdim } 3578218822Sdim func (stream, "}"); 3579218822Sdim } 3580218822Sdim break; 358160484Sobrien 3582218822Sdim case 'E': 3583218822Sdim { 3584218822Sdim unsigned int msb = (given & 0x0000001f); 3585218822Sdim unsigned int lsb = 0; 3586218822Sdim lsb |= (given & 0x000000c0u) >> 6; 3587218822Sdim lsb |= (given & 0x00007000u) >> 10; 3588218822Sdim func (stream, "#%u, #%u", lsb, msb - lsb + 1); 3589218822Sdim } 3590218822Sdim break; 359160484Sobrien 3592218822Sdim case 'F': 3593218822Sdim { 3594218822Sdim unsigned int width = (given & 0x0000001f) + 1; 3595218822Sdim unsigned int lsb = 0; 3596218822Sdim lsb |= (given & 0x000000c0u) >> 6; 3597218822Sdim lsb |= (given & 0x00007000u) >> 10; 3598218822Sdim func (stream, "#%u, #%u", lsb, width); 3599218822Sdim } 3600218822Sdim break; 360160484Sobrien 3602218822Sdim case 'b': 3603218822Sdim { 3604218822Sdim unsigned int S = (given & 0x04000000u) >> 26; 3605218822Sdim unsigned int J1 = (given & 0x00002000u) >> 13; 3606218822Sdim unsigned int J2 = (given & 0x00000800u) >> 11; 3607218822Sdim int offset = 0; 360860484Sobrien 3609218822Sdim offset |= !S << 20; 3610218822Sdim offset |= J2 << 19; 3611218822Sdim offset |= J1 << 18; 3612218822Sdim offset |= (given & 0x003f0000) >> 4; 3613218822Sdim offset |= (given & 0x000007ff) << 1; 3614218822Sdim offset -= (1 << 20); 361560484Sobrien 3616218822Sdim info->print_address_func (pc + 4 + offset, info); 3617218822Sdim } 3618218822Sdim break; 361960484Sobrien 3620218822Sdim case 'B': 3621218822Sdim { 3622218822Sdim unsigned int S = (given & 0x04000000u) >> 26; 3623218822Sdim unsigned int I1 = (given & 0x00002000u) >> 13; 3624218822Sdim unsigned int I2 = (given & 0x00000800u) >> 11; 3625218822Sdim int offset = 0; 362660484Sobrien 3627218822Sdim offset |= !S << 24; 3628218822Sdim offset |= !(I1 ^ S) << 23; 3629218822Sdim offset |= !(I2 ^ S) << 22; 3630218822Sdim offset |= (given & 0x03ff0000u) >> 4; 3631218822Sdim offset |= (given & 0x000007ffu) << 1; 3632218822Sdim offset -= (1 << 24); 3633218822Sdim offset += pc + 4; 363460484Sobrien 3635218822Sdim /* BLX target addresses are always word aligned. */ 3636218822Sdim if ((given & 0x00001000u) == 0) 3637218822Sdim offset &= ~2u; 363860484Sobrien 3639218822Sdim info->print_address_func (offset, info); 3640218822Sdim } 3641218822Sdim break; 364260484Sobrien 3643218822Sdim case 's': 3644218822Sdim { 3645218822Sdim unsigned int shift = 0; 3646218822Sdim shift |= (given & 0x000000c0u) >> 6; 3647218822Sdim shift |= (given & 0x00007000u) >> 10; 3648218822Sdim if (given & 0x00200000u) 3649218822Sdim func (stream, ", asr #%u", shift); 3650218822Sdim else if (shift) 3651218822Sdim func (stream, ", lsl #%u", shift); 3652218822Sdim /* else print nothing - lsl #0 */ 3653218822Sdim } 3654218822Sdim break; 365560484Sobrien 3656218822Sdim case 'R': 3657218822Sdim { 3658218822Sdim unsigned int rot = (given & 0x00000030) >> 4; 3659218822Sdim if (rot) 3660218822Sdim func (stream, ", ror #%u", rot * 8); 3661218822Sdim } 3662218822Sdim break; 366360484Sobrien 3664218822Sdim case 'U': 3665218822Sdim switch (given & 0xf) 3666218822Sdim { 3667218822Sdim case 0xf: func(stream, "sy"); break; 3668218822Sdim case 0x7: func(stream, "un"); break; 3669218822Sdim case 0xe: func(stream, "st"); break; 3670218822Sdim case 0x6: func(stream, "unst"); break; 3671218822Sdim default: 3672218822Sdim func(stream, "#%d", (int)given & 0xf); 3673218822Sdim break; 3674218822Sdim } 3675218822Sdim break; 367660484Sobrien 3677218822Sdim case 'C': 3678218822Sdim if ((given & 0xff) == 0) 3679218822Sdim { 3680218822Sdim func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 3681218822Sdim if (given & 0x800) 3682218822Sdim func (stream, "f"); 3683218822Sdim if (given & 0x400) 3684218822Sdim func (stream, "s"); 3685218822Sdim if (given & 0x200) 3686218822Sdim func (stream, "x"); 3687218822Sdim if (given & 0x100) 3688218822Sdim func (stream, "c"); 3689218822Sdim } 3690218822Sdim else 3691218822Sdim { 3692218822Sdim func (stream, psr_name (given & 0xff)); 3693218822Sdim } 3694218822Sdim break; 3695218822Sdim 3696218822Sdim case 'D': 3697218822Sdim if ((given & 0xff) == 0) 3698218822Sdim func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C'); 3699218822Sdim else 3700218822Sdim func (stream, psr_name (given & 0xff)); 3701218822Sdim break; 3702218822Sdim 3703218822Sdim case '0': case '1': case '2': case '3': case '4': 3704218822Sdim case '5': case '6': case '7': case '8': case '9': 3705218822Sdim { 3706218822Sdim int width; 3707218822Sdim unsigned long val; 3708218822Sdim 3709218822Sdim c = arm_decode_bitfield (c, given, &val, &width); 3710218822Sdim 3711218822Sdim switch (*c) 3712218822Sdim { 3713218822Sdim case 'd': func (stream, "%lu", val); break; 3714218822Sdim case 'W': func (stream, "%lu", val * 4); break; 3715218822Sdim case 'r': func (stream, "%s", arm_regnames[val]); break; 3716218822Sdim 3717218822Sdim case 'c': 3718218822Sdim func (stream, "%s", arm_conditional[val]); 3719218822Sdim break; 3720218822Sdim 3721218822Sdim case '\'': 3722218822Sdim c++; 3723218822Sdim if (val == ((1ul << width) - 1)) 3724218822Sdim func (stream, "%c", *c); 3725218822Sdim break; 3726218822Sdim 3727218822Sdim case '`': 3728218822Sdim c++; 3729218822Sdim if (val == 0) 3730218822Sdim func (stream, "%c", *c); 3731218822Sdim break; 3732218822Sdim 3733218822Sdim case '?': 3734218822Sdim func (stream, "%c", c[(1 << width) - (int)val]); 3735218822Sdim c += 1 << width; 3736218822Sdim break; 3737218822Sdim 3738218822Sdim default: 3739218822Sdim abort (); 3740218822Sdim } 3741218822Sdim } 3742218822Sdim break; 3743218822Sdim 3744218822Sdim default: 3745218822Sdim abort (); 3746218822Sdim } 3747218822Sdim } 3748218822Sdim return; 3749218822Sdim } 3750218822Sdim 375160484Sobrien /* No match. */ 375260484Sobrien abort (); 375360484Sobrien} 375460484Sobrien 3755218822Sdim/* Print data bytes on INFO->STREAM. */ 3756218822Sdim 3757218822Sdimstatic void 3758218822Sdimprint_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info, 3759218822Sdim long given) 3760218822Sdim{ 3761218822Sdim switch (info->bytes_per_chunk) 3762218822Sdim { 3763218822Sdim case 1: 3764218822Sdim info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 3765218822Sdim break; 3766218822Sdim case 2: 3767218822Sdim info->fprintf_func (info->stream, ".short\t0x%04lx", given); 3768218822Sdim break; 3769218822Sdim case 4: 3770218822Sdim info->fprintf_func (info->stream, ".word\t0x%08lx", given); 3771218822Sdim break; 3772218822Sdim default: 3773218822Sdim abort (); 3774218822Sdim } 3775218822Sdim} 3776218822Sdim 3777130561Sobrien/* Disallow mapping symbols ($a, $b, $d, $t etc) from 3778130561Sobrien being displayed in symbol relative addresses. */ 3779130561Sobrien 3780130561Sobrienbfd_boolean 3781130561Sobrienarm_symbol_is_valid (asymbol * sym, 3782130561Sobrien struct disassemble_info * info ATTRIBUTE_UNUSED) 3783130561Sobrien{ 3784130561Sobrien const char * name; 3785130561Sobrien 3786130561Sobrien if (sym == NULL) 3787130561Sobrien return FALSE; 3788130561Sobrien 3789130561Sobrien name = bfd_asymbol_name (sym); 3790130561Sobrien 3791130561Sobrien return (name && *name != '$'); 3792130561Sobrien} 3793130561Sobrien 379460484Sobrien/* Parse an individual disassembler option. */ 3795104834Sobrien 379660484Sobrienvoid 3797218822Sdimparse_arm_disassembler_option (char *option) 379860484Sobrien{ 379960484Sobrien if (option == NULL) 380060484Sobrien return; 3801130561Sobrien 3802218822Sdim if (CONST_STRNEQ (option, "reg-names-")) 380360484Sobrien { 380460484Sobrien int i; 3805130561Sobrien 380660484Sobrien option += 10; 380760484Sobrien 380860484Sobrien for (i = NUM_ARM_REGNAMES; i--;) 3809130561Sobrien if (strneq (option, regnames[i].name, strlen (regnames[i].name))) 381060484Sobrien { 381160484Sobrien regname_selected = i; 381260484Sobrien break; 381360484Sobrien } 3814130561Sobrien 381560484Sobrien if (i < 0) 3816130561Sobrien /* XXX - should break 'option' at following delimiter. */ 381760484Sobrien fprintf (stderr, _("Unrecognised register name set: %s\n"), option); 381860484Sobrien } 3819218822Sdim else if (CONST_STRNEQ (option, "force-thumb")) 382060484Sobrien force_thumb = 1; 3821218822Sdim else if (CONST_STRNEQ (option, "no-force-thumb")) 382260484Sobrien force_thumb = 0; 382360484Sobrien else 3824130561Sobrien /* XXX - should break 'option' at following delimiter. */ 382560484Sobrien fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); 3826130561Sobrien 382760484Sobrien return; 382860484Sobrien} 382960484Sobrien 3830130561Sobrien/* Parse the string of disassembler options, spliting it at whitespaces 3831130561Sobrien or commas. (Whitespace separators supported for backwards compatibility). */ 3832104834Sobrien 383360484Sobrienstatic void 3834218822Sdimparse_disassembler_options (char *options) 383560484Sobrien{ 383660484Sobrien if (options == NULL) 383760484Sobrien return; 383860484Sobrien 3839130561Sobrien while (*options) 384060484Sobrien { 3841130561Sobrien parse_arm_disassembler_option (options); 384260484Sobrien 3843130561Sobrien /* Skip forward to next seperator. */ 3844130561Sobrien while ((*options) && (! ISSPACE (*options)) && (*options != ',')) 3845130561Sobrien ++ options; 3846130561Sobrien /* Skip forward past seperators. */ 3847130561Sobrien while (ISSPACE (*options) || (*options == ',')) 3848130561Sobrien ++ options; 384960484Sobrien } 385060484Sobrien} 385160484Sobrien 3852218822Sdim/* Search back through the insn stream to determine if this instruction is 3853218822Sdim conditionally executed. */ 3854218822Sdimstatic void 3855218822Sdimfind_ifthen_state (bfd_vma pc, struct disassemble_info *info, 3856218822Sdim bfd_boolean little) 3857218822Sdim{ 3858218822Sdim unsigned char b[2]; 3859218822Sdim unsigned int insn; 3860218822Sdim int status; 3861218822Sdim /* COUNT is twice the number of instructions seen. It will be odd if we 3862218822Sdim just crossed an instruction boundary. */ 3863218822Sdim int count; 3864218822Sdim int it_count; 3865218822Sdim unsigned int seen_it; 3866218822Sdim bfd_vma addr; 3867218822Sdim 3868218822Sdim ifthen_address = pc; 3869218822Sdim ifthen_state = 0; 3870218822Sdim 3871218822Sdim addr = pc; 3872218822Sdim count = 1; 3873218822Sdim it_count = 0; 3874218822Sdim seen_it = 0; 3875218822Sdim /* Scan backwards looking for IT instructions, keeping track of where 3876218822Sdim instruction boundaries are. We don't know if something is actually an 3877218822Sdim IT instruction until we find a definite instruction boundary. */ 3878218822Sdim for (;;) 3879218822Sdim { 3880218822Sdim if (addr == 0 || info->symbol_at_address_func(addr, info)) 3881218822Sdim { 3882218822Sdim /* A symbol must be on an instruction boundary, and will not 3883218822Sdim be within an IT block. */ 3884218822Sdim if (seen_it && (count & 1)) 3885218822Sdim break; 3886218822Sdim 3887218822Sdim return; 3888218822Sdim } 3889218822Sdim addr -= 2; 3890218822Sdim status = info->read_memory_func (addr, (bfd_byte *)b, 2, info); 3891218822Sdim if (status) 3892218822Sdim return; 3893218822Sdim 3894218822Sdim if (little) 3895218822Sdim insn = (b[0]) | (b[1] << 8); 3896218822Sdim else 3897218822Sdim insn = (b[1]) | (b[0] << 8); 3898218822Sdim if (seen_it) 3899218822Sdim { 3900218822Sdim if ((insn & 0xf800) < 0xe800) 3901218822Sdim { 3902218822Sdim /* Addr + 2 is an instruction boundary. See if this matches 3903218822Sdim the expected boundary based on the position of the last 3904218822Sdim IT candidate. */ 3905218822Sdim if (count & 1) 3906218822Sdim break; 3907218822Sdim seen_it = 0; 3908218822Sdim } 3909218822Sdim } 3910218822Sdim if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 3911218822Sdim { 3912218822Sdim /* This could be an IT instruction. */ 3913218822Sdim seen_it = insn; 3914218822Sdim it_count = count >> 1; 3915218822Sdim } 3916218822Sdim if ((insn & 0xf800) >= 0xe800) 3917218822Sdim count++; 3918218822Sdim else 3919218822Sdim count = (count + 2) | 1; 3920218822Sdim /* IT blocks contain at most 4 instructions. */ 3921218822Sdim if (count >= 8 && !seen_it) 3922218822Sdim return; 3923218822Sdim } 3924218822Sdim /* We found an IT instruction. */ 3925218822Sdim ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 3926218822Sdim if ((ifthen_state & 0xf) == 0) 3927218822Sdim ifthen_state = 0; 3928218822Sdim} 3929218822Sdim 3930218822Sdim/* Try to infer the code type (Arm or Thumb) from a symbol. 3931218822Sdim Returns nonzero if *MAP_TYPE was set. */ 3932218822Sdim 3933218822Sdimstatic int 3934218822Sdimget_sym_code_type (struct disassemble_info *info, int n, 3935218822Sdim enum map_type *map_type) 3936218822Sdim{ 3937218822Sdim elf_symbol_type *es; 3938218822Sdim unsigned int type; 3939218822Sdim const char *name; 3940218822Sdim 3941218822Sdim es = *(elf_symbol_type **)(info->symtab + n); 3942218822Sdim type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 3943218822Sdim 3944218822Sdim /* If the symbol has function type then use that. */ 3945218822Sdim if (type == STT_FUNC || type == STT_ARM_TFUNC) 3946218822Sdim { 3947218822Sdim *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM; 3948218822Sdim return TRUE; 3949218822Sdim } 3950218822Sdim 3951218822Sdim /* Check for mapping symbols. */ 3952218822Sdim name = bfd_asymbol_name(info->symtab[n]); 3953218822Sdim if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 3954218822Sdim && (name[2] == 0 || name[2] == '.')) 3955218822Sdim { 3956218822Sdim *map_type = ((name[1] == 'a') ? MAP_ARM 3957218822Sdim : (name[1] == 't') ? MAP_THUMB 3958218822Sdim : MAP_DATA); 3959218822Sdim return TRUE; 3960218822Sdim } 3961218822Sdim 3962218822Sdim return FALSE; 3963218822Sdim} 3964218822Sdim 396560484Sobrien/* NOTE: There are no checks in these routines that 396660484Sobrien the relevant number of data bytes exist. */ 3967104834Sobrien 396860484Sobrienstatic int 3969218822Sdimprint_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 397060484Sobrien{ 3971218822Sdim unsigned char b[4]; 3972218822Sdim long given; 3973218822Sdim int status; 3974218822Sdim int is_thumb = FALSE; 3975218822Sdim int is_data = FALSE; 3976218822Sdim unsigned int size = 4; 3977218822Sdim void (*printer) (bfd_vma, struct disassemble_info *, long); 3978218822Sdim bfd_boolean found = FALSE; 397960484Sobrien 398060484Sobrien if (info->disassembler_options) 398160484Sobrien { 398260484Sobrien parse_disassembler_options (info->disassembler_options); 3983130561Sobrien 398460484Sobrien /* To avoid repeated parsing of these options, we remove them here. */ 398560484Sobrien info->disassembler_options = NULL; 398660484Sobrien } 3987130561Sobrien 3988218822Sdim /* First check the full symtab for a mapping symbol, even if there 3989218822Sdim are no usable non-mapping symbols for this address. */ 3990218822Sdim if (info->symtab != NULL 3991218822Sdim && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 3992218822Sdim { 3993218822Sdim bfd_vma addr; 3994218822Sdim int n; 3995218822Sdim int last_sym = -1; 3996218822Sdim enum map_type type = MAP_ARM; 3997130561Sobrien 3998218822Sdim if (pc <= last_mapping_addr) 3999218822Sdim last_mapping_sym = -1; 4000218822Sdim is_thumb = (last_type == MAP_THUMB); 4001218822Sdim found = FALSE; 4002218822Sdim /* Start scanning at the start of the function, or wherever 4003218822Sdim we finished last time. */ 4004218822Sdim n = info->symtab_pos + 1; 4005218822Sdim if (n < last_mapping_sym) 4006218822Sdim n = last_mapping_sym; 4007218822Sdim 4008218822Sdim /* Scan up to the location being disassembled. */ 4009218822Sdim for (; n < info->symtab_size; n++) 4010218822Sdim { 4011218822Sdim addr = bfd_asymbol_value (info->symtab[n]); 4012218822Sdim if (addr > pc) 4013218822Sdim break; 4014218822Sdim if ((info->section == NULL 4015218822Sdim || info->section == info->symtab[n]->section) 4016218822Sdim && get_sym_code_type (info, n, &type)) 4017218822Sdim { 4018218822Sdim last_sym = n; 4019218822Sdim found = TRUE; 4020218822Sdim } 4021218822Sdim } 4022218822Sdim 4023218822Sdim if (!found) 4024218822Sdim { 4025218822Sdim n = info->symtab_pos; 4026218822Sdim if (n < last_mapping_sym - 1) 4027218822Sdim n = last_mapping_sym - 1; 4028218822Sdim 4029218822Sdim /* No mapping symbol found at this address. Look backwards 4030218822Sdim for a preceeding one. */ 4031218822Sdim for (; n >= 0; n--) 4032218822Sdim { 4033218822Sdim if (get_sym_code_type (info, n, &type)) 4034218822Sdim { 4035218822Sdim last_sym = n; 4036218822Sdim found = TRUE; 4037218822Sdim break; 4038218822Sdim } 4039218822Sdim } 4040218822Sdim } 4041218822Sdim 4042218822Sdim last_mapping_sym = last_sym; 4043218822Sdim last_type = type; 4044218822Sdim is_thumb = (last_type == MAP_THUMB); 4045218822Sdim is_data = (last_type == MAP_DATA); 4046218822Sdim 4047218822Sdim /* Look a little bit ahead to see if we should print out 4048218822Sdim two or four bytes of data. If there's a symbol, 4049218822Sdim mapping or otherwise, after two bytes then don't 4050218822Sdim print more. */ 4051218822Sdim if (is_data) 4052218822Sdim { 4053218822Sdim size = 4 - (pc & 3); 4054218822Sdim for (n = last_sym + 1; n < info->symtab_size; n++) 4055218822Sdim { 4056218822Sdim addr = bfd_asymbol_value (info->symtab[n]); 4057218822Sdim if (addr > pc) 4058218822Sdim { 4059218822Sdim if (addr - pc < size) 4060218822Sdim size = addr - pc; 4061218822Sdim break; 4062218822Sdim } 4063218822Sdim } 4064218822Sdim /* If the next symbol is after three bytes, we need to 4065218822Sdim print only part of the data, so that we can use either 4066218822Sdim .byte or .short. */ 4067218822Sdim if (size == 3) 4068218822Sdim size = (pc & 1) ? 1 : 2; 4069218822Sdim } 4070218822Sdim } 4071218822Sdim 4072218822Sdim if (info->symbols != NULL) 407360484Sobrien { 407460484Sobrien if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 407560484Sobrien { 407660484Sobrien coff_symbol_type * cs; 4077130561Sobrien 407860484Sobrien cs = coffsymbol (*info->symbols); 407960484Sobrien is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 408060484Sobrien || cs->native->u.syment.n_sclass == C_THUMBSTAT 408160484Sobrien || cs->native->u.syment.n_sclass == C_THUMBLABEL 408260484Sobrien || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 408360484Sobrien || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 408460484Sobrien } 4085218822Sdim else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 4086218822Sdim && !found) 408760484Sobrien { 4088218822Sdim /* If no mapping symbol has been found then fall back to the type 4089218822Sdim of the function symbol. */ 409060484Sobrien elf_symbol_type * es; 409160484Sobrien unsigned int type; 4092130561Sobrien 409360484Sobrien es = *(elf_symbol_type **)(info->symbols); 409460484Sobrien type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 4095130561Sobrien 409660484Sobrien is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); 409760484Sobrien } 409860484Sobrien } 4099130561Sobrien 4100218822Sdim if (force_thumb) 4101218822Sdim is_thumb = TRUE; 410260484Sobrien 4103218822Sdim info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 4104218822Sdim info->bytes_per_line = 4; 4105218822Sdim 4106218822Sdim if (is_data) 410760484Sobrien { 4108218822Sdim int i; 4109130561Sobrien 4110218822Sdim /* size was already set above. */ 4111218822Sdim info->bytes_per_chunk = size; 4112218822Sdim printer = print_insn_data; 4113130561Sobrien 4114218822Sdim status = info->read_memory_func (pc, (bfd_byte *)b, size, info); 4115218822Sdim given = 0; 4116218822Sdim if (little) 4117218822Sdim for (i = size - 1; i >= 0; i--) 4118218822Sdim given = b[i] | (given << 8); 4119218822Sdim else 4120218822Sdim for (i = 0; i < (int) size; i++) 4121218822Sdim given = b[i] | (given << 8); 4122218822Sdim } 4123218822Sdim else if (!is_thumb) 4124218822Sdim { 4125218822Sdim /* In ARM mode endianness is a straightforward issue: the instruction 4126218822Sdim is four bytes long and is either ordered 0123 or 3210. */ 4127218822Sdim printer = print_insn_arm; 4128218822Sdim info->bytes_per_chunk = 4; 4129218822Sdim size = 4; 4130130561Sobrien 4131218822Sdim status = info->read_memory_func (pc, (bfd_byte *)b, 4, info); 4132218822Sdim if (little) 4133218822Sdim given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 4134218822Sdim else 4135218822Sdim given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); 413660484Sobrien } 413760484Sobrien else 413860484Sobrien { 4139218822Sdim /* In Thumb mode we have the additional wrinkle of two 4140218822Sdim instruction lengths. Fortunately, the bits that determine 4141218822Sdim the length of the current instruction are always to be found 4142218822Sdim in the first two bytes. */ 4143218822Sdim printer = print_insn_thumb16; 4144218822Sdim info->bytes_per_chunk = 2; 4145218822Sdim size = 2; 4146130561Sobrien 4147218822Sdim status = info->read_memory_func (pc, (bfd_byte *)b, 2, info); 4148218822Sdim if (little) 4149218822Sdim given = (b[0]) | (b[1] << 8); 4150218822Sdim else 4151218822Sdim given = (b[1]) | (b[0] << 8); 4152218822Sdim 4153218822Sdim if (!status) 415460484Sobrien { 4155218822Sdim /* These bit patterns signal a four-byte Thumb 4156218822Sdim instruction. */ 4157218822Sdim if ((given & 0xF800) == 0xF800 4158218822Sdim || (given & 0xF800) == 0xF000 4159218822Sdim || (given & 0xF800) == 0xE800) 416060484Sobrien { 4161218822Sdim status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info); 4162218822Sdim if (little) 4163218822Sdim given = (b[0]) | (b[1] << 8) | (given << 16); 4164218822Sdim else 4165218822Sdim given = (b[1]) | (b[0] << 8) | (given << 16); 4166130561Sobrien 4167218822Sdim printer = print_insn_thumb32; 4168218822Sdim size = 4; 4169218822Sdim } 4170218822Sdim } 4171130561Sobrien 4172218822Sdim if (ifthen_address != pc) 4173218822Sdim find_ifthen_state(pc, info, little); 4174218822Sdim 4175218822Sdim if (ifthen_state) 4176218822Sdim { 4177218822Sdim if ((ifthen_state & 0xf) == 0x8) 4178218822Sdim ifthen_next_state = 0; 417960484Sobrien else 4180218822Sdim ifthen_next_state = (ifthen_state & 0xe0) 4181218822Sdim | ((ifthen_state & 0xf) << 1); 418260484Sobrien } 418360484Sobrien } 4184130561Sobrien 4185218822Sdim if (status) 4186218822Sdim { 4187218822Sdim info->memory_error_func (status, pc, info); 4188218822Sdim return -1; 4189218822Sdim } 419077298Sobrien if (info->flags & INSN_HAS_RELOC) 419177298Sobrien /* If the instruction has a reloc associated with it, then 419277298Sobrien the offset field in the instruction will actually be the 419377298Sobrien addend for the reloc. (We are using REL type relocs). 419477298Sobrien In such cases, we can ignore the pc when computing 419577298Sobrien addresses, since the addend is not currently pc-relative. */ 419677298Sobrien pc = 0; 4197130561Sobrien 4198218822Sdim printer (pc, info, given); 4199218822Sdim 420060484Sobrien if (is_thumb) 4201218822Sdim { 4202218822Sdim ifthen_state = ifthen_next_state; 4203218822Sdim ifthen_address += size; 4204218822Sdim } 4205218822Sdim return size; 420660484Sobrien} 420760484Sobrien 420860484Sobrienint 4209218822Sdimprint_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 421060484Sobrien{ 4211130561Sobrien return print_insn (pc, info, FALSE); 421260484Sobrien} 421360484Sobrien 421460484Sobrienint 4215218822Sdimprint_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 421660484Sobrien{ 4217130561Sobrien return print_insn (pc, info, TRUE); 421860484Sobrien} 421960484Sobrien 422060484Sobrienvoid 4221218822Sdimprint_arm_disassembler_options (FILE *stream) 422260484Sobrien{ 422360484Sobrien int i; 422460484Sobrien 422560484Sobrien fprintf (stream, _("\n\ 422660484SobrienThe following ARM specific disassembler options are supported for use with\n\ 422760484Sobrienthe -M switch:\n")); 4228130561Sobrien 422960484Sobrien for (i = NUM_ARM_REGNAMES; i--;) 423060484Sobrien fprintf (stream, " reg-names-%s %*c%s\n", 423160484Sobrien regnames[i].name, 423289857Sobrien (int)(14 - strlen (regnames[i].name)), ' ', 423360484Sobrien regnames[i].description); 423460484Sobrien 423560484Sobrien fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); 423660484Sobrien fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); 423760484Sobrien} 4238