ppc.h revision 89857
1139749Simp/* ppc.h -- Header file for PowerPC opcode table 2127215Smarcel Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc. 3119815Smarcel Written by Ian Lance Taylor, Cygnus Support 4119815Smarcel 5119815SmarcelThis file is part of GDB, GAS, and the GNU binutils. 6119815Smarcel 7119815SmarcelGDB, GAS, and the GNU binutils are free software; you can redistribute 8119815Smarcelthem and/or modify them under the terms of the GNU General Public 9119815SmarcelLicense as published by the Free Software Foundation; either version 10119815Smarcel1, or (at your option) any later version. 11119815Smarcel 12119815SmarcelGDB, GAS, and the GNU binutils are distributed in the hope that they 13119815Smarcelwill be useful, but WITHOUT ANY WARRANTY; without even the implied 14119815Smarcelwarranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15119815Smarcelthe GNU General Public License for more details. 16119815Smarcel 17119815SmarcelYou should have received a copy of the GNU General Public License 18119815Smarcelalong with this file; see the file COPYING. If not, write to the Free 19119815SmarcelSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20119815Smarcel 21119815Smarcel#ifndef PPC_H 22119815Smarcel#define PPC_H 23119815Smarcel 24119815Smarcel/* The opcode table is an array of struct powerpc_opcode. */ 25119815Smarcel 26119815Smarcelstruct powerpc_opcode 27119815Smarcel{ 28119815Smarcel /* The opcode name. */ 29119815Smarcel const char *name; 30119815Smarcel 31119815Smarcel /* The opcode itself. Those bits which will be filled in with 32119815Smarcel operands are zeroes. */ 33119815Smarcel unsigned long opcode; 34119815Smarcel 35119815Smarcel /* The opcode mask. This is used by the disassembler. This is a 36119815Smarcel mask containing ones indicating those bits which must match the 37119815Smarcel opcode field, and zeroes indicating those bits which need not 38119815Smarcel match (and are presumably filled in by operands). */ 39119815Smarcel unsigned long mask; 40119815Smarcel 41119815Smarcel /* One bit flags for the opcode. These are used to indicate which 42127215Smarcel specific processors support the instructions. The defined values 43127215Smarcel are listed below. */ 44127215Smarcel unsigned long flags; 45119815Smarcel 46119815Smarcel /* An array of operand codes. Each code is an index into the 47138157Smarius operand table. They appear in the order which the operands must 48138157Smarius appear in assembly code, and are terminated by a zero. */ 49138157Smarius unsigned char operands[8]; 50138157Smarius}; 51138157Smarius 52138157Smarius/* The table itself is sorted by major opcode number, and is otherwise 53138157Smarius in the order in which the disassembler should consider 54138157Smarius instructions. */ 55119815Smarcelextern const struct powerpc_opcode powerpc_opcodes[]; 56119815Smarcelextern const int powerpc_num_opcodes; 57119815Smarcel 58119815Smarcel/* Values defined for the flags field of a struct powerpc_opcode. */ 59119815Smarcel 60119815Smarcel/* Opcode is defined for the PowerPC architecture. */ 61119815Smarcel#define PPC_OPCODE_PPC (01) 62119815Smarcel 63119815Smarcel/* Opcode is defined for the POWER (RS/6000) architecture. */ 64119815Smarcel#define PPC_OPCODE_POWER (02) 65119815Smarcel 66119815Smarcel/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 67119815Smarcel#define PPC_OPCODE_POWER2 (04) 68119815Smarcel 69120452Smarcel/* Opcode is only defined on 32 bit architectures. */ 70119815Smarcel#define PPC_OPCODE_32 (010) 71119815Smarcel 72119815Smarcel/* Opcode is only defined on 64 bit architectures. */ 73119866Smarcel#define PPC_OPCODE_64 (020) 74119866Smarcel 75119866Smarcel/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 76119866Smarcel is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 77119866Smarcel but it also supports many additional POWER instructions. */ 78119866Smarcel#define PPC_OPCODE_601 (040) 79127741Smarcel 80138157Smarius/* Opcode is supported in both the Power and PowerPC architectures 81149111Smarius (ie, compiler's -mcpu=common or assembler's -mcom). */ 82149111Smarius#define PPC_OPCODE_COMMON (0100) 83127741Smarcel 84127741Smarcel/* Opcode is supported for any Power or PowerPC platform (this is 85127741Smarcel for the assembler's -many option, and it eliminates duplicates). */ 86127825Smarcel#define PPC_OPCODE_ANY (0200) 87127825Smarcel 88127825Smarcel/* Opcode is supported as part of the 64-bit bridge. */ 89127825Smarcel#define PPC_OPCODE_64_BRIDGE (0400) 90127741Smarcel 91122466Sjake/* Opcode is supported by Altivec Vector Unit */ 92127741Smarcel#define PPC_OPCODE_ALTIVEC (01000) 93122466Sjake 94149111Smarius/* Opcode is supported by PowerPC 403 processor. */ 95149111Smarius#define PPC_OPCODE_403 (02000) 96149111Smarius 97122466Sjake/* Opcode is supported by PowerPC BookE processor. */ 98127741Smarcel#define PPC_OPCODE_BOOKE (04000) 99127741Smarcel 100149111Smarius/* Opcode is only supported by 64-bit PowerPC BookE processor. */ 101149111Smarius#define PPC_OPCODE_BOOKE64 (010000) 102127825Smarcel 103149111Smarius/* A macro to extract the major opcode from an instruction. */ 104149111Smarius#define PPC_OP(i) (((i) >> 26) & 0x3f) 105149111Smarius 106127825Smarcel/* The operands table is an array of struct powerpc_operand. */ 107127825Smarcel 108149111Smariusstruct powerpc_operand 109127825Smarcel{ 110149111Smarius /* The number of bits in the operand. */ 111127825Smarcel int bits; 112149111Smarius 113127825Smarcel /* How far the operand is left shifted in the instruction. */ 114149111Smarius int shift; 115127825Smarcel 116127825Smarcel /* Insertion function. This is used by the assembler. To insert an 117143468Smarius operand value into an instruction, check this field. 118149111Smarius 119149111Smarius If it is NULL, execute 120127741Smarcel i |= (op & ((1 << o->bits) - 1)) << o->shift; 121127741Smarcel (i is the instruction which we are filling in, o is a pointer to 122127741Smarcel this structure, and op is the opcode value; this assumes twos 123127741Smarcel complement arithmetic). 124127741Smarcel 125127741Smarcel If this field is not NULL, then simply call it with the 126127741Smarcel instruction and the operand value. It will return the new value 127127741Smarcel of the instruction. If the ERRMSG argument is not NULL, then if 128138157Smarius the operand value is illegal, *ERRMSG will be set to a warning 129138157Smarius string (the operand will be inserted in any case). If the 130127741Smarcel operand value is legal, *ERRMSG will be unchanged (most operands 131127741Smarcel can accept any value). */ 132127741Smarcel unsigned long (*insert) PARAMS ((unsigned long instruction, long op, 133127741Smarcel int dialect, 134127741Smarcel const char **errmsg)); 135149111Smarius 136127741Smarcel /* Extraction function. This is used by the disassembler. To 137149111Smarius extract this operand type from an instruction, check this field. 138127741Smarcel 139127741Smarcel If it is NULL, compute 140127741Smarcel op = ((i) >> o->shift) & ((1 << o->bits) - 1); 141127741Smarcel if ((o->flags & PPC_OPERAND_SIGNED) != 0 142127741Smarcel && (op & (1 << (o->bits - 1))) != 0) 143127741Smarcel op -= 1 << o->bits; 144127741Smarcel (i is the instruction, o is a pointer to this structure, and op 145127741Smarcel is the result; this assumes twos complement arithmetic). 146127741Smarcel 147127741Smarcel If this field is not NULL, then simply call it with the 148127741Smarcel instruction value. It will return the value of the operand. If 149127741Smarcel the INVALID argument is not NULL, *INVALID will be set to 150127741Smarcel non-zero if this operand type can not actually be extracted from 151138157Smarius this operand (i.e., the instruction does not match). If the 152146972Smarius operand is valid, *INVALID will not be changed. */ 153146972Smarius long (*extract) PARAMS ((unsigned long instruction, int dialect, 154146972Smarius int *invalid)); 155146972Smarius 156146972Smarius /* One bit syntax flags. */ 157138157Smarius unsigned long flags; 158127741Smarcel}; 159146972Smarius 160127741Smarcel/* Elements in the table are retrieved by indexing with values from 161149111Smarius the operands field of the powerpc_opcodes table. */ 162146972Smarius 163127741Smarcelextern const struct powerpc_operand powerpc_operands[]; 164146972Smarius 165146972Smarius/* Values defined for the flags field of a struct powerpc_operand. */ 166146972Smarius 167146972Smarius/* This operand takes signed values. */ 168146972Smarius#define PPC_OPERAND_SIGNED (01) 169146972Smarius 170146972Smarius/* This operand takes signed values, but also accepts a full positive 171146972Smarius range of values when running in 32 bit mode. That is, if bits is 172146972Smarius 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 173146972Smarius this flag is ignored. */ 174146972Smarius#define PPC_OPERAND_SIGNOPT (02) 175146972Smarius 176146972Smarius/* This operand does not actually exist in the assembler input. This 177146972Smarius is used to support extended mnemonics such as mr, for which two 178146972Smarius operands fields are identical. The assembler should call the 179122466Sjake insert function with any op value. The disassembler should call 180122466Sjake the extract function, ignore the return value, and check the value 181119866Smarcel placed in the valid argument. */ 182119815Smarcel#define PPC_OPERAND_FAKE (04) 183119815Smarcel 184149111Smarius/* The next operand should be wrapped in parentheses rather than 185127741Smarcel separated from this one by a comma. This is used for the load and 186119815Smarcel store instructions which want their operands to look like 187120452Smarcel reg,displacement(reg) 188119815Smarcel */ 189119815Smarcel#define PPC_OPERAND_PARENS (010) 190127741Smarcel 191127741Smarcel/* This operand may use the symbolic names for the CR fields, which 192127741Smarcel are 193127741Smarcel lt 0 gt 1 eq 2 so 3 un 3 194127741Smarcel cr0 0 cr1 1 cr2 2 cr3 3 195127741Smarcel cr4 4 cr5 5 cr6 6 cr7 7 196127741Smarcel These may be combined arithmetically, as in cr2*4+gt. These are 197149111Smarius only supported on the PowerPC, not the POWER. */ 198127741Smarcel#define PPC_OPERAND_CR (020) 199127741Smarcel 200146972Smarius/* This operand names a register. The disassembler uses this to print 201127741Smarcel register names with a leading 'r'. */ 202127741Smarcel#define PPC_OPERAND_GPR (040) 203127741Smarcel 204127741Smarcel/* This operand names a floating point register. The disassembler 205127741Smarcel prints these with a leading 'f'. */ 206127741Smarcel#define PPC_OPERAND_FPR (0100) 207127741Smarcel 208141753Smarius/* This operand is a relative branch displacement. The disassembler 209119815Smarcel prints these symbolically if possible. */ 210119815Smarcel#define PPC_OPERAND_RELATIVE (0200) 211119815Smarcel 212119815Smarcel/* This operand is an absolute branch address. The disassembler 213119815Smarcel prints these symbolically if possible. */ 214119815Smarcel#define PPC_OPERAND_ABSOLUTE (0400) 215120009Stmm 216120009Stmm/* This operand is optional, and is zero if omitted. This is used for 217119815Smarcel the optional BF and L fields in the comparison instructions. The 218119815Smarcel assembler must count the number of operands remaining on the line, 219148824Smarius and the number of operands remaining for the opcode, and decide 220119815Smarcel whether this operand is present or not. The disassembler should 221138157Smarius print this operand out only if it is not zero. */ 222138157Smarius#define PPC_OPERAND_OPTIONAL (01000) 223138157Smarius 224120452Smarcel/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 225119815Smarcel is omitted, then for the next operand use this operand value plus 226119815Smarcel 1, ignoring the next operand field for the opcode. This wretched 227138157Smarius hack is needed because the Power rotate instructions can take 228138157Smarius either 4 or 5 operands. The disassembler should print this operand 229138157Smarius out regardless of the PPC_OPERAND_OPTIONAL field. */ 230138157Smarius#define PPC_OPERAND_NEXT (02000) 231138157Smarius 232138157Smarius/* This operand should be regarded as a negative number for the 233138157Smarius purposes of overflow checking (i.e., the normal most negative 234138157Smarius number is disallowed and one more than the normal most positive 235138157Smarius number is allowed). This flag will only be set for a signed 236138157Smarius operand. */ 237138157Smarius#define PPC_OPERAND_NEGATIVE (04000) 238119815Smarcel 239120452Smarcel/* This operand names a vector unit register. The disassembler 240120009Stmm prints these with a leading 'v'. */ 241120452Smarcel#define PPC_OPERAND_VR (010000) 242119815Smarcel 243120452Smarcel/* This operand is for the DS field in a DS form instruction. */ 244120452Smarcel#define PPC_OPERAND_DS (020000) 245119815Smarcel 246119815Smarcel/* The POWER and PowerPC assemblers use a few macros. We keep them 247119815Smarcel with the operands table for simplicity. The macro table is an 248119815Smarcel array of struct powerpc_macro. */ 249119815Smarcel 250119815Smarcelstruct powerpc_macro 251119815Smarcel{ 252120545Sjake /* The macro name. */ 253120545Sjake const char *name; 254120545Sjake 255120545Sjake /* The number of operands the macro takes. */ 256119815Smarcel unsigned int operands; 257119815Smarcel 258119815Smarcel /* One bit flags for the opcode. These are used to indicate which 259119815Smarcel specific processors support the instructions. The values are the 260119815Smarcel same as those for the struct powerpc_opcode flags field. */ 261119815Smarcel unsigned long flags; 262119815Smarcel 263119815Smarcel /* A format string to turn the macro into a normal instruction. 264119815Smarcel Each %N in the string is replaced with operand number N (zero 265119815Smarcel based). */ 266119815Smarcel const char *format; 267119815Smarcel}; 268119815Smarcel 269119815Smarcelextern const struct powerpc_macro powerpc_macros[]; 270119815Smarcelextern const int powerpc_num_macros; 271119815Smarcel 272#endif /* PPC_H */ 273