ppc.h revision 60484
1/* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994, 1995 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5This file is part of GDB, GAS, and the GNU binutils. 6 7GDB, GAS, and the GNU binutils are free software; you can redistribute 8them and/or modify them under the terms of the GNU General Public 9License as published by the Free Software Foundation; either version 101, or (at your option) any later version. 11 12GDB, GAS, and the GNU binutils are distributed in the hope that they 13will be useful, but WITHOUT ANY WARRANTY; without even the implied 14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15the GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this file; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20 21#ifndef PPC_H 22#define PPC_H 23 24/* The opcode table is an array of struct powerpc_opcode. */ 25 26struct powerpc_opcode 27{ 28 /* The opcode name. */ 29 const char *name; 30 31 /* The opcode itself. Those bits which will be filled in with 32 operands are zeroes. */ 33 unsigned long opcode; 34 35 /* The opcode mask. This is used by the disassembler. This is a 36 mask containing ones indicating those bits which must match the 37 opcode field, and zeroes indicating those bits which need not 38 match (and are presumably filled in by operands). */ 39 unsigned long mask; 40 41 /* One bit flags for the opcode. These are used to indicate which 42 specific processors support the instructions. The defined values 43 are listed below. */ 44 unsigned long flags; 45 46 /* An array of operand codes. Each code is an index into the 47 operand table. They appear in the order which the operands must 48 appear in assembly code, and are terminated by a zero. */ 49 unsigned char operands[8]; 50}; 51 52/* The table itself is sorted by major opcode number, and is otherwise 53 in the order in which the disassembler should consider 54 instructions. */ 55extern const struct powerpc_opcode powerpc_opcodes[]; 56extern const int powerpc_num_opcodes; 57 58/* Values defined for the flags field of a struct powerpc_opcode. */ 59 60/* Opcode is defined for the PowerPC architecture. */ 61#define PPC_OPCODE_PPC (01) 62 63/* Opcode is defined for the POWER (RS/6000) architecture. */ 64#define PPC_OPCODE_POWER (02) 65 66/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 67#define PPC_OPCODE_POWER2 (04) 68 69/* Opcode is only defined on 32 bit architectures. */ 70#define PPC_OPCODE_32 (010) 71 72/* Opcode is only defined on 64 bit architectures. */ 73#define PPC_OPCODE_64 (020) 74 75/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 76 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 77 but it also supports many additional POWER instructions. */ 78#define PPC_OPCODE_601 (040) 79 80/* Opcode is supported in both the Power and PowerPC architectures 81 (ie, compiler's -mcpu=common or assembler's -mcom). */ 82#define PPC_OPCODE_COMMON (0100) 83 84/* Opcode is supported for any Power or PowerPC platform (this is 85 for the assembler's -many option, and it eliminates duplicates). */ 86#define PPC_OPCODE_ANY (0200) 87 88/* Opcode is supported as part of the 64-bit bridge. */ 89#define PPC_OPCODE_64_BRIDGE (0400) 90 91/* A macro to extract the major opcode from an instruction. */ 92#define PPC_OP(i) (((i) >> 26) & 0x3f) 93 94/* The operands table is an array of struct powerpc_operand. */ 95 96struct powerpc_operand 97{ 98 /* The number of bits in the operand. */ 99 int bits; 100 101 /* How far the operand is left shifted in the instruction. */ 102 int shift; 103 104 /* Insertion function. This is used by the assembler. To insert an 105 operand value into an instruction, check this field. 106 107 If it is NULL, execute 108 i |= (op & ((1 << o->bits) - 1)) << o->shift; 109 (i is the instruction which we are filling in, o is a pointer to 110 this structure, and op is the opcode value; this assumes twos 111 complement arithmetic). 112 113 If this field is not NULL, then simply call it with the 114 instruction and the operand value. It will return the new value 115 of the instruction. If the ERRMSG argument is not NULL, then if 116 the operand value is illegal, *ERRMSG will be set to a warning 117 string (the operand will be inserted in any case). If the 118 operand value is legal, *ERRMSG will be unchanged (most operands 119 can accept any value). */ 120 unsigned long (*insert) PARAMS ((unsigned long instruction, long op, 121 const char **errmsg)); 122 123 /* Extraction function. This is used by the disassembler. To 124 extract this operand type from an instruction, check this field. 125 126 If it is NULL, compute 127 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 128 if ((o->flags & PPC_OPERAND_SIGNED) != 0 129 && (op & (1 << (o->bits - 1))) != 0) 130 op -= 1 << o->bits; 131 (i is the instruction, o is a pointer to this structure, and op 132 is the result; this assumes twos complement arithmetic). 133 134 If this field is not NULL, then simply call it with the 135 instruction value. It will return the value of the operand. If 136 the INVALID argument is not NULL, *INVALID will be set to 137 non-zero if this operand type can not actually be extracted from 138 this operand (i.e., the instruction does not match). If the 139 operand is valid, *INVALID will not be changed. */ 140 long (*extract) PARAMS ((unsigned long instruction, int *invalid)); 141 142 /* One bit syntax flags. */ 143 unsigned long flags; 144}; 145 146/* Elements in the table are retrieved by indexing with values from 147 the operands field of the powerpc_opcodes table. */ 148 149extern const struct powerpc_operand powerpc_operands[]; 150 151/* Values defined for the flags field of a struct powerpc_operand. */ 152 153/* This operand takes signed values. */ 154#define PPC_OPERAND_SIGNED (01) 155 156/* This operand takes signed values, but also accepts a full positive 157 range of values when running in 32 bit mode. That is, if bits is 158 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 159 this flag is ignored. */ 160#define PPC_OPERAND_SIGNOPT (02) 161 162/* This operand does not actually exist in the assembler input. This 163 is used to support extended mnemonics such as mr, for which two 164 operands fields are identical. The assembler should call the 165 insert function with any op value. The disassembler should call 166 the extract function, ignore the return value, and check the value 167 placed in the valid argument. */ 168#define PPC_OPERAND_FAKE (04) 169 170/* The next operand should be wrapped in parentheses rather than 171 separated from this one by a comma. This is used for the load and 172 store instructions which want their operands to look like 173 reg,displacement(reg) 174 */ 175#define PPC_OPERAND_PARENS (010) 176 177/* This operand may use the symbolic names for the CR fields, which 178 are 179 lt 0 gt 1 eq 2 so 3 un 3 180 cr0 0 cr1 1 cr2 2 cr3 3 181 cr4 4 cr5 5 cr6 6 cr7 7 182 These may be combined arithmetically, as in cr2*4+gt. These are 183 only supported on the PowerPC, not the POWER. */ 184#define PPC_OPERAND_CR (020) 185 186/* This operand names a register. The disassembler uses this to print 187 register names with a leading 'r'. */ 188#define PPC_OPERAND_GPR (040) 189 190/* This operand names a floating point register. The disassembler 191 prints these with a leading 'f'. */ 192#define PPC_OPERAND_FPR (0100) 193 194/* This operand is a relative branch displacement. The disassembler 195 prints these symbolically if possible. */ 196#define PPC_OPERAND_RELATIVE (0200) 197 198/* This operand is an absolute branch address. The disassembler 199 prints these symbolically if possible. */ 200#define PPC_OPERAND_ABSOLUTE (0400) 201 202/* This operand is optional, and is zero if omitted. This is used for 203 the optional BF and L fields in the comparison instructions. The 204 assembler must count the number of operands remaining on the line, 205 and the number of operands remaining for the opcode, and decide 206 whether this operand is present or not. The disassembler should 207 print this operand out only if it is not zero. */ 208#define PPC_OPERAND_OPTIONAL (01000) 209 210/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 211 is omitted, then for the next operand use this operand value plus 212 1, ignoring the next operand field for the opcode. This wretched 213 hack is needed because the Power rotate instructions can take 214 either 4 or 5 operands. The disassembler should print this operand 215 out regardless of the PPC_OPERAND_OPTIONAL field. */ 216#define PPC_OPERAND_NEXT (02000) 217 218/* This operand should be regarded as a negative number for the 219 purposes of overflow checking (i.e., the normal most negative 220 number is disallowed and one more than the normal most positive 221 number is allowed). This flag will only be set for a signed 222 operand. */ 223#define PPC_OPERAND_NEGATIVE (04000) 224 225/* The POWER and PowerPC assemblers use a few macros. We keep them 226 with the operands table for simplicity. The macro table is an 227 array of struct powerpc_macro. */ 228 229struct powerpc_macro 230{ 231 /* The macro name. */ 232 const char *name; 233 234 /* The number of operands the macro takes. */ 235 unsigned int operands; 236 237 /* One bit flags for the opcode. These are used to indicate which 238 specific processors support the instructions. The values are the 239 same as those for the struct powerpc_opcode flags field. */ 240 unsigned long flags; 241 242 /* A format string to turn the macro into a normal instruction. 243 Each %N in the string is replaced with operand number N (zero 244 based). */ 245 const char *format; 246}; 247 248extern const struct powerpc_macro powerpc_macros[]; 249extern const int powerpc_num_macros; 250 251#endif /* PPC_H */ 252