1214571Sdim/* cr16.h -- Header file for CR16 opcode and register tables. 2214571Sdim Copyright 2007 Free Software Foundation, Inc. 3214571Sdim Contributed by M R Swami Reddy 4214571Sdim 5214571Sdim This file is part of GAS, GDB and the GNU binutils. 6214571Sdim 7214571Sdim GAS, GDB, and GNU binutils is free software; you can redistribute it 8214571Sdim and/or modify it under the terms of the GNU General Public License as 9214571Sdim published by the Free Software Foundation; either version 2, or (at your 10214571Sdim option) any later version. 11214571Sdim 12214571Sdim GAS, GDB, and GNU binutils are distributed in the hope that they will be 13214571Sdim useful, but WITHOUT ANY WARRANTY; without even the implied warranty of 14214571Sdim MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15214571Sdim GNU General Public License for more details. 16214571Sdim 17214571Sdim You should have received a copy of the GNU General Public License 18214571Sdim along with this program; if not, write to the Free Software Foundation, 19214571Sdim Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 20214571Sdim 21214571Sdim#ifndef _CR16_H_ 22214571Sdim#define _CR16_H_ 23214571Sdim 24214571Sdim/* CR16 core Registers : 25214571Sdim The enums are used as indices to CR16 registers table (cr16_regtab). 26214571Sdim Therefore, order MUST be preserved. */ 27214571Sdim 28214571Sdimtypedef enum 29214571Sdim { 30214571Sdim /* 16-bit general purpose registers. */ 31214571Sdim r0, r1, r2, r3, 32214571Sdim r4, r5, r6, r7, 33214571Sdim r8, r9, r10, r11, 34214571Sdim r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, 35214571Sdim 36214571Sdim /* 32-bit general purpose registers. */ 37214571Sdim r12 = 12, r13 = 13, r14 = 14, r15 = 15, 38214571Sdim era = 14, sp = 15, RA, 39214571Sdim 40214571Sdim /* Not a register. */ 41214571Sdim nullregister, 42214571Sdim MAX_REG 43214571Sdim } 44214571Sdimreg; 45214571Sdim 46214571Sdim/* CR16 processor registers and special registers : 47214571Sdim The enums are used as indices to CR16 processor registers table 48214571Sdim (cr16_pregtab). Therefore, order MUST be preserved. */ 49214571Sdim 50214571Sdimtypedef enum 51214571Sdim { 52214571Sdim /* processor registers. */ 53214571Sdim dbs = MAX_REG, 54214571Sdim dsr, dcrl, dcrh, 55214571Sdim car0l, car0h, car1l, car1h, 56214571Sdim cfg, psr, intbasel, intbaseh, 57214571Sdim ispl, isph, uspl, usph, 58214571Sdim dcr = dcrl, 59214571Sdim car0 = car0l, 60214571Sdim car1 = car1l, 61214571Sdim intbase = intbasel, 62214571Sdim isp = ispl, 63214571Sdim usp = uspl, 64214571Sdim /* Not a processor register. */ 65214571Sdim nullpregister = usph + 1, 66214571Sdim MAX_PREG 67214571Sdim } 68214571Sdimpreg; 69214571Sdim 70214571Sdim/* CR16 Register types. */ 71214571Sdim 72214571Sdimtypedef enum 73214571Sdim { 74214571Sdim CR16_R_REGTYPE, /* r<N> */ 75214571Sdim CR16_RP_REGTYPE, /* reg pair */ 76214571Sdim CR16_P_REGTYPE /* Processor register */ 77214571Sdim } 78214571Sdimreg_type; 79214571Sdim 80214571Sdim/* CR16 argument types : 81214571Sdim The argument types correspond to instructions operands 82214571Sdim 83214571Sdim Argument types : 84214571Sdim r - register 85214571Sdim rp - register pair 86214571Sdim c - constant 87214571Sdim i - immediate 88214571Sdim idxr - index with register 89214571Sdim idxrp - index with register pair 90214571Sdim rbase - register base 91214571Sdim rpbase - register pair base 92214571Sdim pr - processor register */ 93214571Sdim 94214571Sdimtypedef enum 95214571Sdim { 96214571Sdim arg_r, 97214571Sdim arg_c, 98214571Sdim arg_cr, 99214571Sdim arg_crp, 100214571Sdim arg_ic, 101214571Sdim arg_icr, 102214571Sdim arg_idxr, 103214571Sdim arg_idxrp, 104214571Sdim arg_rbase, 105214571Sdim arg_rpbase, 106214571Sdim arg_rp, 107214571Sdim arg_pr, 108214571Sdim arg_prp, 109214571Sdim arg_cc, 110214571Sdim arg_ra, 111214571Sdim /* Not an argument. */ 112214571Sdim nullargs 113214571Sdim } 114214571Sdimargtype; 115214571Sdim 116214571Sdim/* CR16 operand types:The operand types correspond to instructions operands.*/ 117214571Sdim 118214571Sdimtypedef enum 119214571Sdim { 120214571Sdim dummy, 121214571Sdim /* N-bit signed immediate. */ 122214571Sdim imm3, imm4, imm5, imm6, imm16, imm20, imm32, 123214571Sdim /* N-bit unsigned immediate. */ 124214571Sdim uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, 125214571Sdim /* N-bit signed displacement. */ 126214571Sdim disps5, disps17, disps25, 127214571Sdim /* N-bit unsigned displacement. */ 128214571Sdim dispe9, 129214571Sdim /* N-bit absolute address. */ 130214571Sdim abs20, abs24, 131214571Sdim /* Register relative. */ 132214571Sdim rra, rbase, rbase_disps20, rbase_dispe20, 133214571Sdim /* Register pair relative. */ 134214571Sdim rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, 135214571Sdim rpbase_disps20, rpbase_dispe20, 136214571Sdim /* Register index. */ 137214571Sdim rindex7_abs20, rindex8_abs20, 138214571Sdim /* Register pair index. */ 139214571Sdim rpindex_disps0, rpindex_disps14, rpindex_disps20, 140214571Sdim /* register. */ 141214571Sdim regr, 142214571Sdim /* register pair. */ 143214571Sdim regp, 144214571Sdim /* processor register. */ 145214571Sdim pregr, 146214571Sdim /* processor register 32 bit. */ 147214571Sdim pregrp, 148214571Sdim /* condition code - 4 bit. */ 149214571Sdim cc, 150214571Sdim /* Not an operand. */ 151214571Sdim nulloperand, 152214571Sdim /* Maximum supported operand. */ 153214571Sdim MAX_OPRD 154214571Sdim } 155214571Sdimoperand_type; 156214571Sdim 157214571Sdim/* CR16 instruction types. */ 158214571Sdim 159214571Sdim#define NO_TYPE_INS 0 160214571Sdim#define ARITH_INS 1 161214571Sdim#define LD_STOR_INS 2 162214571Sdim#define BRANCH_INS 3 163214571Sdim#define ARITH_BYTE_INS 4 164214571Sdim#define SHIFT_INS 5 165214571Sdim#define BRANCH_NEQ_INS 6 166214571Sdim#define LD_STOR_INS_INC 7 167214571Sdim#define STOR_IMM_INS 8 168214571Sdim#define CSTBIT_INS 9 169214571Sdim 170214571Sdim/* Maximum value supported for instruction types. */ 171214571Sdim#define CR16_INS_MAX (1 << 4) 172214571Sdim/* Mask to record an instruction type. */ 173214571Sdim#define CR16_INS_MASK (CR16_INS_MAX - 1) 174214571Sdim/* Return instruction type, given instruction's attributes. */ 175214571Sdim#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) 176214571Sdim 177214571Sdim/* Indicates whether this instruction has a register list as parameter. */ 178214571Sdim#define REG_LIST CR16_INS_MAX 179214571Sdim 180214571Sdim/* The operands in binary and assembly are placed in reverse order. 181214571Sdim load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ 182214571Sdim#define REVERSE_MATCH (1 << 5) 183214571Sdim 184214571Sdim/* Printing formats, where the instruction prefix isn't consecutive. */ 185214571Sdim#define FMT_1 (1 << 9) /* 0xF0F00000 */ 186214571Sdim#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ 187214571Sdim#define FMT_3 (1 << 11) /* 0xFFF00F00 */ 188214571Sdim#define FMT_4 (1 << 12) /* 0xFFF0F000 */ 189214571Sdim#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ 190214571Sdim#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) 191214571Sdim 192214571Sdim/* Indicates whether this instruction can be relaxed. */ 193214571Sdim#define RELAXABLE (1 << 14) 194214571Sdim 195214571Sdim/* Indicates that instruction uses user registers (and not 196214571Sdim general-purpose registers) as operands. */ 197214571Sdim#define USER_REG (1 << 15) 198214571Sdim 199214571Sdim 200214571Sdim/* Instruction shouldn't allow 'sp' usage. */ 201214571Sdim#define NO_SP (1 << 17) 202214571Sdim 203214571Sdim/* Instruction shouldn't allow to push a register which is used as a rptr. */ 204214571Sdim#define NO_RPTR (1 << 18) 205214571Sdim 206214571Sdim/* Maximum operands per instruction. */ 207214571Sdim#define MAX_OPERANDS 5 208214571Sdim/* Maximum register name length. */ 209214571Sdim#define MAX_REGNAME_LEN 10 210214571Sdim/* Maximum instruction length. */ 211214571Sdim#define MAX_INST_LEN 256 212214571Sdim 213214571Sdim 214214571Sdim/* Values defined for the flags field of a struct operand_entry. */ 215214571Sdim 216214571Sdim/* Operand must be an unsigned number. */ 217214571Sdim#define OP_UNSIGNED (1 << 0) 218214571Sdim/* Operand must be a signed number. */ 219214571Sdim#define OP_SIGNED (1 << 1) 220214571Sdim/* Operand must be a negative number. */ 221214571Sdim#define OP_NEG (1 << 2) 222214571Sdim/* A special load/stor 4-bit unsigned displacement operand. */ 223214571Sdim#define OP_DEC (1 << 3) 224214571Sdim/* Operand must be an even number. */ 225214571Sdim#define OP_EVEN (1 << 4) 226214571Sdim/* Operand is shifted right. */ 227214571Sdim#define OP_SHIFT (1 << 5) 228214571Sdim/* Operand is shifted right and decremented. */ 229214571Sdim#define OP_SHIFT_DEC (1 << 6) 230214571Sdim/* Operand has reserved escape sequences. */ 231214571Sdim#define OP_ESC (1 << 7) 232214571Sdim/* Operand must be a ABS20 number. */ 233214571Sdim#define OP_ABS20 (1 << 8) 234214571Sdim/* Operand must be a ABS24 number. */ 235214571Sdim#define OP_ABS24 (1 << 9) 236214571Sdim/* Operand has reserved escape sequences type 1. */ 237214571Sdim#define OP_ESC1 (1 << 10) 238214571Sdim 239214571Sdim/* Single operand description. */ 240214571Sdim 241214571Sdimtypedef struct 242214571Sdim { 243214571Sdim /* Operand type. */ 244214571Sdim operand_type op_type; 245214571Sdim /* Operand location within the opcode. */ 246214571Sdim unsigned int shift; 247214571Sdim } 248214571Sdimoperand_desc; 249214571Sdim 250214571Sdim/* Instruction data structure used in instruction table. */ 251214571Sdim 252214571Sdimtypedef struct 253214571Sdim { 254214571Sdim /* Name. */ 255214571Sdim const char *mnemonic; 256214571Sdim /* Size (in words). */ 257214571Sdim unsigned int size; 258214571Sdim /* Constant prefix (matched by the disassembler). */ 259214571Sdim unsigned long match; /* ie opcode */ 260214571Sdim /* Match size (in bits). */ 261214571Sdim /* MASK: if( (i & match_bits) == match ) then match */ 262214571Sdim int match_bits; 263214571Sdim /* Attributes. */ 264214571Sdim unsigned int flags; 265214571Sdim /* Operands (always last, so unreferenced operands are initialized). */ 266214571Sdim operand_desc operands[MAX_OPERANDS]; 267214571Sdim } 268214571Sdiminst; 269214571Sdim 270214571Sdim/* Data structure for a single instruction's arguments (Operands). */ 271214571Sdim 272214571Sdimtypedef struct 273214571Sdim { 274214571Sdim /* Register or base register. */ 275214571Sdim reg r; 276214571Sdim /* Register pair register. */ 277214571Sdim reg rp; 278214571Sdim /* Index register. */ 279214571Sdim reg i_r; 280214571Sdim /* Processor register. */ 281214571Sdim preg pr; 282214571Sdim /* Processor register. 32 bit */ 283214571Sdim preg prp; 284214571Sdim /* Constant/immediate/absolute value. */ 285214571Sdim long constant; 286214571Sdim /* CC code. */ 287214571Sdim unsigned int cc; 288214571Sdim /* Scaled index mode. */ 289214571Sdim unsigned int scale; 290214571Sdim /* Argument type. */ 291214571Sdim argtype type; 292214571Sdim /* Size of the argument (in bits) required to represent. */ 293214571Sdim int size; 294214571Sdim /* The type of the expression. */ 295214571Sdim unsigned char X_op; 296214571Sdim } 297214571Sdimargument; 298214571Sdim 299214571Sdim/* Internal structure to hold the various entities 300214571Sdim corresponding to the current assembling instruction. */ 301214571Sdim 302214571Sdimtypedef struct 303214571Sdim { 304214571Sdim /* Number of arguments. */ 305214571Sdim int nargs; 306214571Sdim /* The argument data structure for storing args (operands). */ 307214571Sdim argument arg[MAX_OPERANDS]; 308214571Sdim/* The following fields are required only by CR16-assembler. */ 309214571Sdim#ifdef TC_CR16 310214571Sdim /* Expression used for setting the fixups (if any). */ 311214571Sdim expressionS exp; 312214571Sdim bfd_reloc_code_real_type rtype; 313214571Sdim#endif /* TC_CR16 */ 314214571Sdim /* Instruction size (in bytes). */ 315214571Sdim int size; 316214571Sdim } 317214571Sdimins; 318214571Sdim 319214571Sdim/* Structure to hold information about predefined operands. */ 320214571Sdim 321214571Sdimtypedef struct 322214571Sdim { 323214571Sdim /* Size (in bits). */ 324214571Sdim unsigned int bit_size; 325214571Sdim /* Argument type. */ 326214571Sdim argtype arg_type; 327214571Sdim /* One bit syntax flags. */ 328214571Sdim int flags; 329214571Sdim } 330214571Sdimoperand_entry; 331214571Sdim 332214571Sdim/* Structure to hold trap handler information. */ 333214571Sdim 334214571Sdimtypedef struct 335214571Sdim { 336214571Sdim /* Trap name. */ 337214571Sdim char *name; 338214571Sdim /* Index in dispatch table. */ 339214571Sdim unsigned int entry; 340214571Sdim } 341214571Sdimtrap_entry; 342214571Sdim 343214571Sdim/* Structure to hold information about predefined registers. */ 344214571Sdim 345214571Sdimtypedef struct 346214571Sdim { 347214571Sdim /* Name (string representation). */ 348214571Sdim char *name; 349214571Sdim /* Value (enum representation). */ 350214571Sdim union 351214571Sdim { 352214571Sdim /* Register. */ 353214571Sdim reg reg_val; 354214571Sdim /* processor register. */ 355214571Sdim preg preg_val; 356214571Sdim } value; 357214571Sdim /* Register image. */ 358214571Sdim int image; 359214571Sdim /* Register type. */ 360214571Sdim reg_type type; 361214571Sdim } 362214571Sdimreg_entry; 363214571Sdim 364214571Sdim/* CR16 opcode table. */ 365214571Sdimextern const inst cr16_instruction[]; 366214571Sdimextern const unsigned int cr16_num_opcodes; 367214571Sdim#define NUMOPCODES cr16_num_opcodes 368214571Sdim 369214571Sdim/* CR16 operands table. */ 370214571Sdimextern const operand_entry cr16_optab[]; 371214571Sdim 372214571Sdim/* CR16 registers table. */ 373214571Sdimextern const reg_entry cr16_regtab[]; 374214571Sdimextern const unsigned int cr16_num_regs; 375214571Sdim#define NUMREGS cr16_num_regs 376214571Sdim 377214571Sdim/* CR16 register pair table. */ 378214571Sdimextern const reg_entry cr16_regptab[]; 379214571Sdimextern const unsigned int cr16_num_regps; 380214571Sdim#define NUMREGPS cr16_num_regps 381214571Sdim 382214571Sdim/* CR16 processor registers table. */ 383214571Sdimextern const reg_entry cr16_pregtab[]; 384214571Sdimextern const unsigned int cr16_num_pregs; 385214571Sdim#define NUMPREGS cr16_num_pregs 386214571Sdim 387214571Sdim/* CR16 processor registers - 32 bit table. */ 388214571Sdimextern const reg_entry cr16_pregptab[]; 389214571Sdimextern const unsigned int cr16_num_pregps; 390214571Sdim#define NUMPREGPS cr16_num_pregps 391214571Sdim 392214571Sdim/* CR16 trap/interrupt table. */ 393214571Sdimextern const trap_entry cr16_traps[]; 394214571Sdimextern const unsigned int cr16_num_traps; 395214571Sdim#define NUMTRAPS cr16_num_traps 396214571Sdim 397214571Sdim/* CR16 CC - codes bit table. */ 398214571Sdimextern const char * cr16_b_cond_tab[]; 399214571Sdimextern const unsigned int cr16_num_cc; 400214571Sdim#define NUMCC cr16_num_cc; 401214571Sdim 402214571Sdim 403214571Sdim/* Table of instructions with no operands. */ 404214571Sdimextern const char * cr16_no_op_insn[]; 405214571Sdim 406214571Sdim/* Current instruction we're assembling. */ 407214571Sdimextern const inst *instruction; 408214571Sdim 409214571Sdim/* A macro for representing the instruction "constant" opcode, that is, 410214571Sdim the FIXED part of the instruction. The "constant" opcode is represented 411214571Sdim as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) 412214571Sdim over that range. */ 413214571Sdim#define BIN(OPC,SHIFT) (OPC << SHIFT) 414214571Sdim 415214571Sdim/* Is the current instruction type is TYPE ? */ 416214571Sdim#define IS_INSN_TYPE(TYPE) \ 417214571Sdim (CR16_INS_TYPE (instruction->flags) == TYPE) 418214571Sdim 419214571Sdim/* Is the current instruction mnemonic is MNEMONIC ? */ 420214571Sdim#define IS_INSN_MNEMONIC(MNEMONIC) \ 421214571Sdim (strcmp (instruction->mnemonic, MNEMONIC) == 0) 422214571Sdim 423214571Sdim/* Does the current instruction has register list ? */ 424214571Sdim#define INST_HAS_REG_LIST \ 425214571Sdim (instruction->flags & REG_LIST) 426214571Sdim 427214571Sdim 428214571Sdim/* Utility macros for string comparison. */ 429214571Sdim#define streq(a, b) (strcmp (a, b) == 0) 430214571Sdim#define strneq(a, b, c) (strncmp (a, b, c) == 0) 431214571Sdim 432214571Sdim/* Long long type handling. */ 433214571Sdim/* Replace all appearances of 'long long int' with LONGLONG. */ 434214571Sdimtypedef long long int LONGLONG; 435214571Sdimtypedef unsigned long long ULONGLONG; 436214571Sdim 437214571Sdim#endif /* _CR16_H_ */ 438