tc-sparc.c revision 60484
1/* tc-sparc.c -- Assemble for the SPARC 2 Copyright (C) 1989, 90-96, 97, 98, 99, 2000 Free Software Foundation, Inc. 3 This file is part of GAS, the GNU Assembler. 4 5 GAS is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2, or (at your option) 8 any later version. 9 10 GAS is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public 16 License along with GAS; see the file COPYING. If not, write 17 to the Free Software Foundation, 59 Temple Place - Suite 330, 18 Boston, MA 02111-1307, USA. */ 19 20#include <stdio.h> 21#include <ctype.h> 22 23#include "as.h" 24#include "subsegs.h" 25 26#include "opcode/sparc.h" 27 28#ifdef OBJ_ELF 29#include "elf/sparc.h" 30#endif 31 32static struct sparc_arch *lookup_arch PARAMS ((char *)); 33static void init_default_arch PARAMS ((void)); 34static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); 35static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 36static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); 37static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 38static int sparc_ffs PARAMS ((unsigned int)); 39static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); 40static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); 41static void synthetize_setx PARAMS ((const struct sparc_opcode *)); 42static bfd_vma BSR PARAMS ((bfd_vma, int)); 43static int cmp_reg_entry PARAMS ((const PTR, const PTR)); 44static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); 45static int parse_const_expr_arg PARAMS ((char **, int *)); 46static int get_expression PARAMS ((char *str)); 47 48/* Default architecture. */ 49/* ??? The default value should be V8, but sparclite support was added 50 by making it the default. GCC now passes -Asparclite, so maybe sometime in 51 the future we can set this to V8. */ 52#ifndef DEFAULT_ARCH 53#define DEFAULT_ARCH "sparclite" 54#endif 55static char *default_arch = DEFAULT_ARCH; 56 57/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 58 have been set. */ 59static int default_init_p; 60 61/* Current architecture. We don't bump up unless necessary. */ 62static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 63 64/* The maximum architecture level we can bump up to. 65 In a 32 bit environment, don't allow bumping up to v9 by default. 66 The native assembler works this way. The user is required to pass 67 an explicit argument before we'll create v9 object files. However, if 68 we don't see any v9 insns, a v8plus object file is not created. */ 69static enum sparc_opcode_arch_val max_architecture; 70 71/* Either 32 or 64, selects file format. */ 72static int sparc_arch_size; 73/* Initial (default) value, recorded separately in case a user option 74 changes the value before md_show_usage is called. */ 75static int default_arch_size; 76 77#ifdef OBJ_ELF 78/* The currently selected v9 memory model. Currently only used for 79 ELF. */ 80static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 81#endif 82 83static int architecture_requested; 84static int warn_on_bump; 85 86/* If warn_on_bump and the needed architecture is higher than this 87 architecture, issue a warning. */ 88static enum sparc_opcode_arch_val warn_after_architecture; 89 90/* Non-zero if as should generate error if an undeclared g[23] register 91 has been used in -64. */ 92static int no_undeclared_regs; 93 94/* Non-zero if we are generating PIC code. */ 95int sparc_pic_code; 96 97/* Non-zero if we should give an error when misaligned data is seen. */ 98static int enforce_aligned_data; 99 100extern int target_big_endian; 101 102static int target_little_endian_data; 103 104/* Symbols for global registers on v9. */ 105static symbolS *globals[8]; 106 107/* V9 and 86x have big and little endian data, but instructions are always big 108 endian. The sparclet has bi-endian support but both data and insns have 109 the same endianness. Global `target_big_endian' is used for data. 110 The following macro is used for instructions. */ 111#ifndef INSN_BIG_ENDIAN 112#define INSN_BIG_ENDIAN (target_big_endian \ 113 || default_arch_type == sparc86x \ 114 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 115#endif 116 117/* handle of the OPCODE hash table */ 118static struct hash_control *op_hash; 119 120static int log2 PARAMS ((int)); 121static void s_data1 PARAMS ((void)); 122static void s_seg PARAMS ((int)); 123static void s_proc PARAMS ((int)); 124static void s_reserve PARAMS ((int)); 125static void s_common PARAMS ((int)); 126static void s_empty PARAMS ((int)); 127static void s_uacons PARAMS ((int)); 128static void s_ncons PARAMS ((int)); 129static void s_register PARAMS ((int)); 130 131const pseudo_typeS md_pseudo_table[] = 132{ 133 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */ 134 {"common", s_common, 0}, 135 {"empty", s_empty, 0}, 136 {"global", s_globl, 0}, 137 {"half", cons, 2}, 138 {"nword", s_ncons, 0}, 139 {"optim", s_ignore, 0}, 140 {"proc", s_proc, 0}, 141 {"reserve", s_reserve, 0}, 142 {"seg", s_seg, 0}, 143 {"skip", s_space, 0}, 144 {"word", cons, 4}, 145 {"xword", cons, 8}, 146 {"uahalf", s_uacons, 2}, 147 {"uaword", s_uacons, 4}, 148 {"uaxword", s_uacons, 8}, 149#ifdef OBJ_ELF 150 /* these are specific to sparc/svr4 */ 151 {"2byte", s_uacons, 2}, 152 {"4byte", s_uacons, 4}, 153 {"8byte", s_uacons, 8}, 154 {"register", s_register, 0}, 155#endif 156 {NULL, 0, 0}, 157}; 158 159const int md_reloc_size = 12; /* Size of relocation record */ 160 161/* This array holds the chars that always start a comment. If the 162 pre-processor is disabled, these aren't very useful */ 163const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */ 164 165/* This array holds the chars that only start a comment at the beginning of 166 a line. If the line seems to have the form '# 123 filename' 167 .line and .file directives will appear in the pre-processed output */ 168/* Note that input_file.c hand checks for '#' at the beginning of the 169 first line of the input file. This is because the compiler outputs 170 #NO_APP at the beginning of its output. */ 171/* Also note that comments started like this one will always 172 work if '/' isn't otherwise defined. */ 173const char line_comment_chars[] = "#"; 174 175const char line_separator_chars[] = ""; 176 177/* Chars that can be used to separate mant from exp in floating point nums */ 178const char EXP_CHARS[] = "eE"; 179 180/* Chars that mean this number is a floating point constant */ 181/* As in 0f12.456 */ 182/* or 0d1.2345e12 */ 183const char FLT_CHARS[] = "rRsSfFdDxXpP"; 184 185/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 186 changed in read.c. Ideally it shouldn't have to know about it at all, 187 but nothing is ideal around here. */ 188 189#define isoctal(c) ((unsigned)((c) - '0') < '8') 190 191struct sparc_it 192 { 193 char *error; 194 unsigned long opcode; 195 struct nlist *nlistp; 196 expressionS exp; 197 expressionS exp2; 198 int pcrel; 199 bfd_reloc_code_real_type reloc; 200 }; 201 202struct sparc_it the_insn, set_insn; 203 204static void output_insn 205 PARAMS ((const struct sparc_opcode *, struct sparc_it *)); 206 207/* Table of arguments to -A. 208 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 209 for this use. That table is for opcodes only. This table is for opcodes 210 and file formats. */ 211 212enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 213 v8plusa, v9, v9a, v9_64}; 214 215static struct sparc_arch { 216 char *name; 217 char *opcode_arch; 218 enum sparc_arch_types arch_type; 219 /* Default word size, as specified during configuration. 220 A value of zero means can't be used to specify default architecture. */ 221 int default_arch_size; 222 /* Allowable arg to -A? */ 223 int user_option_p; 224} sparc_arch_table[] = { 225 { "v6", "v6", v6, 0, 1 }, 226 { "v7", "v7", v7, 0, 1 }, 227 { "v8", "v8", v8, 32, 1 }, 228 { "sparclet", "sparclet", sparclet, 32, 1 }, 229 { "sparclite", "sparclite", sparclite, 32, 1 }, 230 { "sparc86x", "sparclite", sparc86x, 32, 1 }, 231 { "v8plus", "v9", v9, 0, 1 }, 232 { "v8plusa", "v9a", v9, 0, 1 }, 233 { "v9", "v9", v9, 0, 1 }, 234 { "v9a", "v9a", v9, 0, 1 }, 235 /* This exists to allow configure.in/Makefile.in to pass one 236 value to specify both the default machine and default word size. */ 237 { "v9-64", "v9", v9, 64, 0 }, 238 { NULL, NULL, v8, 0, 0 } 239}; 240 241/* Variant of default_arch */ 242static enum sparc_arch_types default_arch_type; 243 244static struct sparc_arch * 245lookup_arch (name) 246 char *name; 247{ 248 struct sparc_arch *sa; 249 250 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 251 if (strcmp (sa->name, name) == 0) 252 break; 253 if (sa->name == NULL) 254 return NULL; 255 return sa; 256} 257 258/* Initialize the default opcode arch and word size from the default 259 architecture name. */ 260 261static void 262init_default_arch () 263{ 264 struct sparc_arch *sa = lookup_arch (default_arch); 265 266 if (sa == NULL 267 || sa->default_arch_size == 0) 268 as_fatal (_("Invalid default architecture, broken assembler.")); 269 270 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 271 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 272 as_fatal (_("Bad opcode table, broken assembler.")); 273 default_arch_size = sparc_arch_size = sa->default_arch_size; 274 default_init_p = 1; 275 default_arch_type = sa->arch_type; 276} 277 278/* Called by TARGET_FORMAT. */ 279 280const char * 281sparc_target_format () 282{ 283 /* We don't get a chance to initialize anything before we're called, 284 so handle that now. */ 285 if (! default_init_p) 286 init_default_arch (); 287 288#ifdef OBJ_AOUT 289#ifdef TE_NetBSD 290 return "a.out-sparc-netbsd"; 291#else 292#ifdef TE_SPARCAOUT 293 if (target_big_endian) 294 return "a.out-sunos-big"; 295 else if (default_arch_type == sparc86x && target_little_endian_data) 296 return "a.out-sunos-big"; 297 else return "a.out-sparc-little"; 298#else 299 return "a.out-sunos-big"; 300#endif 301#endif 302#endif 303 304#ifdef OBJ_BOUT 305 return "b.out.big"; 306#endif 307 308#ifdef OBJ_COFF 309#ifdef TE_LYNX 310 return "coff-sparc-lynx"; 311#else 312 return "coff-sparc"; 313#endif 314#endif 315 316#ifdef OBJ_ELF 317 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; 318#endif 319 320 abort (); 321} 322 323/* 324 * md_parse_option 325 * Invocation line includes a switch not recognized by the base assembler. 326 * See if it's a processor-specific option. These are: 327 * 328 * -bump 329 * Warn on architecture bumps. See also -A. 330 * 331 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 332 * Standard 32 bit architectures. 333 * -Av8plus, -Av8plusa 334 * Sparc64 in a 32 bit world. 335 * -Av9, -Av9a 336 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 337 * This used to only mean 64 bits, but properly specifying it 338 * complicated gcc's ASM_SPECs, so now opcode selection is 339 * specified orthogonally to word size (except when specifying 340 * the default, but that is an internal implementation detail). 341 * -xarch=v8plus, -xarch=v8plusa 342 * Same as -Av8plus{,a}, for compatibility with Sun's assembler. 343 * 344 * Select the architecture and possibly the file format. 345 * Instructions or features not supported by the selected 346 * architecture cause fatal errors. 347 * 348 * The default is to start at v6, and bump the architecture up 349 * whenever an instruction is seen at a higher level. In 32 bit 350 * environments, v9 is not bumped up to, the user must pass 351 * -Av8plus{,a}. 352 * 353 * If -bump is specified, a warning is printing when bumping to 354 * higher levels. 355 * 356 * If an architecture is specified, all instructions must match 357 * that architecture. Any higher level instructions are flagged 358 * as errors. Note that in the 32 bit environment specifying 359 * -Av8plus does not automatically create a v8plus object file, a 360 * v9 insn must be seen. 361 * 362 * If both an architecture and -bump are specified, the 363 * architecture starts at the specified level, but bumps are 364 * warnings. Note that we can't set `current_architecture' to 365 * the requested level in this case: in the 32 bit environment, 366 * we still must avoid creating v8plus object files unless v9 367 * insns are seen. 368 * 369 * Note: 370 * Bumping between incompatible architectures is always an 371 * error. For example, from sparclite to v9. 372 */ 373 374#ifdef OBJ_ELF 375CONST char *md_shortopts = "A:K:VQ:sq"; 376#else 377#ifdef OBJ_AOUT 378CONST char *md_shortopts = "A:k"; 379#else 380CONST char *md_shortopts = "A:"; 381#endif 382#endif 383struct option md_longopts[] = { 384#define OPTION_BUMP (OPTION_MD_BASE) 385 {"bump", no_argument, NULL, OPTION_BUMP}, 386#define OPTION_SPARC (OPTION_MD_BASE + 1) 387 {"sparc", no_argument, NULL, OPTION_SPARC}, 388#define OPTION_XARCH (OPTION_MD_BASE + 2) 389 {"xarch", required_argument, NULL, OPTION_XARCH}, 390#ifdef OBJ_ELF 391#define OPTION_32 (OPTION_MD_BASE + 3) 392 {"32", no_argument, NULL, OPTION_32}, 393#define OPTION_64 (OPTION_MD_BASE + 4) 394 {"64", no_argument, NULL, OPTION_64}, 395#define OPTION_TSO (OPTION_MD_BASE + 5) 396 {"TSO", no_argument, NULL, OPTION_TSO}, 397#define OPTION_PSO (OPTION_MD_BASE + 6) 398 {"PSO", no_argument, NULL, OPTION_PSO}, 399#define OPTION_RMO (OPTION_MD_BASE + 7) 400 {"RMO", no_argument, NULL, OPTION_RMO}, 401#endif 402#ifdef SPARC_BIENDIAN 403#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 404 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 405#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 406 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 407#endif 408#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 409 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 410#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 411 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 412#ifdef OBJ_ELF 413#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 414 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 415#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 416 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 417#endif 418 {NULL, no_argument, NULL, 0} 419}; 420size_t md_longopts_size = sizeof(md_longopts); 421 422int 423md_parse_option (c, arg) 424 int c; 425 char *arg; 426{ 427 /* We don't get a chance to initialize anything before we're called, 428 so handle that now. */ 429 if (! default_init_p) 430 init_default_arch (); 431 432 switch (c) 433 { 434 case OPTION_BUMP: 435 warn_on_bump = 1; 436 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 437 break; 438 439 case OPTION_XARCH: 440 /* This is for compatibility with Sun's assembler. */ 441 if (strcmp (arg, "v8plus") != 0 442 && strcmp (arg, "v8plusa") != 0) 443 { 444 as_bad (_("invalid architecture -xarch=%s"), arg); 445 return 0; 446 } 447 448 /* fall through */ 449 450 case 'A': 451 { 452 struct sparc_arch *sa; 453 enum sparc_opcode_arch_val opcode_arch; 454 455 sa = lookup_arch (arg); 456 if (sa == NULL 457 || ! sa->user_option_p) 458 { 459 as_bad (_("invalid architecture -A%s"), arg); 460 return 0; 461 } 462 463 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 464 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 465 as_fatal (_("Bad opcode table, broken assembler.")); 466 467 max_architecture = opcode_arch; 468 architecture_requested = 1; 469 } 470 break; 471 472 case OPTION_SPARC: 473 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 474 break; 475 476 case OPTION_ENFORCE_ALIGNED_DATA: 477 enforce_aligned_data = 1; 478 break; 479 480#ifdef SPARC_BIENDIAN 481 case OPTION_LITTLE_ENDIAN: 482 target_big_endian = 0; 483 if (default_arch_type != sparclet) 484 as_fatal ("This target does not support -EL"); 485 break; 486 case OPTION_LITTLE_ENDIAN_DATA: 487 target_little_endian_data = 1; 488 target_big_endian = 0; 489 if (default_arch_type != sparc86x 490 && default_arch_type != v9) 491 as_fatal ("This target does not support --little-endian-data"); 492 break; 493 case OPTION_BIG_ENDIAN: 494 target_big_endian = 1; 495 break; 496#endif 497 498#ifdef OBJ_AOUT 499 case 'k': 500 sparc_pic_code = 1; 501 break; 502#endif 503 504#ifdef OBJ_ELF 505 case OPTION_32: 506 case OPTION_64: 507 { 508 const char **list, **l; 509 510 sparc_arch_size = c == OPTION_32 ? 32 : 64; 511 list = bfd_target_list (); 512 for (l = list; *l != NULL; l++) 513 { 514 if (sparc_arch_size == 32) 515 { 516 if (strcmp (*l, "elf32-sparc") == 0) 517 break; 518 } 519 else 520 { 521 if (strcmp (*l, "elf64-sparc") == 0) 522 break; 523 } 524 } 525 if (*l == NULL) 526 as_fatal (_("No compiled in support for %d bit object file format"), 527 sparc_arch_size); 528 free (list); 529 } 530 break; 531 532 case OPTION_TSO: 533 sparc_memory_model = MM_TSO; 534 break; 535 536 case OPTION_PSO: 537 sparc_memory_model = MM_PSO; 538 break; 539 540 case OPTION_RMO: 541 sparc_memory_model = MM_RMO; 542 break; 543 544 case 'V': 545 print_version_id (); 546 break; 547 548 case 'Q': 549 /* Qy - do emit .comment 550 Qn - do not emit .comment */ 551 break; 552 553 case 's': 554 /* use .stab instead of .stab.excl */ 555 break; 556 557 case 'q': 558 /* quick -- native assembler does fewer checks */ 559 break; 560 561 case 'K': 562 if (strcmp (arg, "PIC") != 0) 563 as_warn (_("Unrecognized option following -K")); 564 else 565 sparc_pic_code = 1; 566 break; 567 568 case OPTION_NO_UNDECLARED_REGS: 569 no_undeclared_regs = 1; 570 break; 571 572 case OPTION_UNDECLARED_REGS: 573 no_undeclared_regs = 0; 574 break; 575#endif 576 577 default: 578 return 0; 579 } 580 581 return 1; 582} 583 584void 585md_show_usage (stream) 586 FILE *stream; 587{ 588 const struct sparc_arch *arch; 589 590 /* We don't get a chance to initialize anything before we're called, 591 so handle that now. */ 592 if (! default_init_p) 593 init_default_arch (); 594 595 fprintf(stream, _("SPARC options:\n")); 596 for (arch = &sparc_arch_table[0]; arch->name; arch++) 597 { 598 if (arch != &sparc_arch_table[0]) 599 fprintf (stream, " | "); 600 if (arch->user_option_p) 601 fprintf (stream, "-A%s", arch->name); 602 } 603 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n")); 604 fprintf (stream, _("\ 605 specify variant of SPARC architecture\n\ 606-bump warn when assembler switches architectures\n\ 607-sparc ignored\n\ 608--enforce-aligned-data force .long, etc., to be aligned correctly\n")); 609#ifdef OBJ_AOUT 610 fprintf (stream, _("\ 611-k generate PIC\n")); 612#endif 613#ifdef OBJ_ELF 614 fprintf (stream, _("\ 615-32 create 32 bit object file\n\ 616-64 create 64 bit object file\n")); 617 fprintf (stream, _("\ 618 [default is %d]\n"), default_arch_size); 619 fprintf (stream, _("\ 620-TSO use Total Store Ordering\n\ 621-PSO use Partial Store Ordering\n\ 622-RMO use Relaxed Memory Ordering\n")); 623 fprintf (stream, _("\ 624 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 625 fprintf (stream, _("\ 626-KPIC generate PIC\n\ 627-V print assembler version number\n\ 628-undeclared-regs ignore application global register usage without\n\ 629 appropriate .register directive (default)\n\ 630-no-undeclared-regs force error on application global register usage\n\ 631 without appropriate .register directive\n\ 632-q ignored\n\ 633-Qy, -Qn ignored\n\ 634-s ignored\n")); 635#endif 636#ifdef SPARC_BIENDIAN 637 fprintf (stream, _("\ 638-EL generate code for a little endian machine\n\ 639-EB generate code for a big endian machine\n\ 640--little-endian-data generate code for a machine having big endian\n\ 641 instructions and little endian data.\n")); 642#endif 643} 644 645/* native operand size opcode translation */ 646struct 647 { 648 char *name; 649 char *name32; 650 char *name64; 651 } native_op_table[] = 652{ 653 {"ldn", "ld", "ldx"}, 654 {"ldna", "lda", "ldxa"}, 655 {"stn", "st", "stx"}, 656 {"stna", "sta", "stxa"}, 657 {"slln", "sll", "sllx"}, 658 {"srln", "srl", "srlx"}, 659 {"sran", "sra", "srax"}, 660 {"casn", "cas", "casx"}, 661 {"casna", "casa", "casxa"}, 662 {"clrn", "clr", "clrx"}, 663 {NULL, NULL, NULL}, 664}; 665 666/* sparc64 priviledged registers */ 667 668struct priv_reg_entry 669 { 670 char *name; 671 int regnum; 672 }; 673 674struct priv_reg_entry priv_reg_table[] = 675{ 676 {"tpc", 0}, 677 {"tnpc", 1}, 678 {"tstate", 2}, 679 {"tt", 3}, 680 {"tick", 4}, 681 {"tba", 5}, 682 {"pstate", 6}, 683 {"tl", 7}, 684 {"pil", 8}, 685 {"cwp", 9}, 686 {"cansave", 10}, 687 {"canrestore", 11}, 688 {"cleanwin", 12}, 689 {"otherwin", 13}, 690 {"wstate", 14}, 691 {"fq", 15}, 692 {"ver", 31}, 693 {"", -1}, /* end marker */ 694}; 695 696/* v9a specific asrs */ 697 698struct priv_reg_entry v9a_asr_table[] = 699{ 700 {"tick_cmpr", 23}, 701 {"softint", 22}, 702 {"set_softint", 20}, 703 {"pic", 17}, 704 {"pcr", 16}, 705 {"gsr", 19}, 706 {"dcr", 18}, 707 {"clear_softint", 21}, 708 {"", -1}, /* end marker */ 709}; 710 711static int 712cmp_reg_entry (parg, qarg) 713 const PTR parg; 714 const PTR qarg; 715{ 716 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 717 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 718 719 return strcmp (q->name, p->name); 720} 721 722/* This function is called once, at assembler startup time. It should 723 set up all the tables, etc. that the MD part of the assembler will need. */ 724 725void 726md_begin () 727{ 728 register const char *retval = NULL; 729 int lose = 0; 730 register unsigned int i = 0; 731 732 /* We don't get a chance to initialize anything before md_parse_option 733 is called, and it may not be called, so handle default initialization 734 now if not already done. */ 735 if (! default_init_p) 736 init_default_arch (); 737 738 op_hash = hash_new (); 739 740 while (i < (unsigned int) sparc_num_opcodes) 741 { 742 const char *name = sparc_opcodes[i].name; 743 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); 744 if (retval != NULL) 745 { 746 as_bad (_("Internal error: can't hash `%s': %s\n"), 747 sparc_opcodes[i].name, retval); 748 lose = 1; 749 } 750 do 751 { 752 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 753 { 754 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 755 sparc_opcodes[i].name, sparc_opcodes[i].args); 756 lose = 1; 757 } 758 ++i; 759 } 760 while (i < (unsigned int) sparc_num_opcodes 761 && !strcmp (sparc_opcodes[i].name, name)); 762 } 763 764 for (i = 0; native_op_table[i].name; i++) 765 { 766 const struct sparc_opcode *insn; 767 char *name = sparc_arch_size == 32 ? native_op_table[i].name32 : 768 native_op_table[i].name64; 769 insn = (struct sparc_opcode *)hash_find (op_hash, name); 770 if (insn == NULL) 771 { 772 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 773 name, native_op_table[i].name); 774 lose = 1; 775 } 776 else 777 { 778 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); 779 if (retval != NULL) 780 { 781 as_bad (_("Internal error: can't hash `%s': %s\n"), 782 sparc_opcodes[i].name, retval); 783 lose = 1; 784 } 785 } 786 } 787 788 if (lose) 789 as_fatal (_("Broken assembler. No assembly attempted.")); 790 791 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 792 sizeof (priv_reg_table[0]), cmp_reg_entry); 793 794 /* If -bump, record the architecture level at which we start issuing 795 warnings. The behaviour is different depending upon whether an 796 architecture was explicitly specified. If it wasn't, we issue warnings 797 for all upwards bumps. If it was, we don't start issuing warnings until 798 we need to bump beyond the requested architecture or when we bump between 799 conflicting architectures. */ 800 801 if (warn_on_bump 802 && architecture_requested) 803 { 804 /* `max_architecture' records the requested architecture. 805 Issue warnings if we go above it. */ 806 warn_after_architecture = max_architecture; 807 808 /* Find the highest architecture level that doesn't conflict with 809 the requested one. */ 810 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 811 max_architecture > warn_after_architecture; 812 --max_architecture) 813 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 814 warn_after_architecture)) 815 break; 816 } 817} 818 819/* Called after all assembly has been done. */ 820 821void 822sparc_md_end () 823{ 824 if (sparc_arch_size == 64) 825 { 826 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 827 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a); 828 else 829 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9); 830 } 831 else 832 { 833 if (current_architecture == SPARC_OPCODE_ARCH_V9) 834 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus); 835 else if (current_architecture == SPARC_OPCODE_ARCH_V9A) 836 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa); 837 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET) 838 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet); 839 else if (default_arch_type == sparc86x && target_little_endian_data) 840 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le); 841 else 842 { 843 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 844 be but for now it is (since that's the way it's always been 845 treated). */ 846 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc); 847 } 848 } 849} 850 851/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 852 853static INLINE int 854in_signed_range (val, max) 855 bfd_signed_vma val, max; 856{ 857 if (max <= 0) 858 abort (); 859 /* Sign-extend the value from the architecture word size, so that 860 0xffffffff is always considered -1 on sparc32. */ 861 if (sparc_arch_size == 32) 862 { 863 bfd_signed_vma sign = (bfd_signed_vma)1 << 31; 864 val = ((val & 0xffffffff) ^ sign) - sign; 865 } 866 if (val > max) 867 return 0; 868 if (val < ~max) 869 return 0; 870 return 1; 871} 872 873/* Return non-zero if VAL is in the range 0 to MAX. */ 874 875static INLINE int 876in_unsigned_range (val, max) 877 bfd_vma val, max; 878{ 879 if (val > max) 880 return 0; 881 return 1; 882} 883 884/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 885 (e.g. -15 to +31). */ 886 887static INLINE int 888in_bitfield_range (val, max) 889 bfd_signed_vma val, max; 890{ 891 if (max <= 0) 892 abort (); 893 if (val > max) 894 return 0; 895 if (val < ~(max >> 1)) 896 return 0; 897 return 1; 898} 899 900static int 901sparc_ffs (mask) 902 unsigned int mask; 903{ 904 int i; 905 906 if (mask == 0) 907 return -1; 908 909 for (i = 0; (mask & 1) == 0; ++i) 910 mask >>= 1; 911 return i; 912} 913 914/* Implement big shift right. */ 915static bfd_vma 916BSR (val, amount) 917 bfd_vma val; 918 int amount; 919{ 920 if (sizeof (bfd_vma) <= 4 && amount >= 32) 921 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 922 return val >> amount; 923} 924 925/* For communication between sparc_ip and get_expression. */ 926static char *expr_end; 927 928/* Values for `special_case'. 929 Instructions that require wierd handling because they're longer than 930 4 bytes. */ 931#define SPECIAL_CASE_NONE 0 932#define SPECIAL_CASE_SET 1 933#define SPECIAL_CASE_SETSW 2 934#define SPECIAL_CASE_SETX 3 935/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 936#define SPECIAL_CASE_FDIV 4 937 938/* Bit masks of various insns. */ 939#define NOP_INSN 0x01000000 940#define OR_INSN 0x80100000 941#define XOR_INSN 0x80180000 942#define FMOVS_INSN 0x81A00020 943#define SETHI_INSN 0x01000000 944#define SLLX_INSN 0x81281000 945#define SRA_INSN 0x81380000 946 947/* The last instruction to be assembled. */ 948static const struct sparc_opcode *last_insn; 949/* The assembled opcode of `last_insn'. */ 950static unsigned long last_opcode; 951 952/* Handle the set and setuw synthetic instructions. */ 953static void 954synthetize_setuw (insn) 955 const struct sparc_opcode *insn; 956{ 957 int need_hi22_p = 0; 958 int rd = (the_insn.opcode & RD (~0)) >> 25; 959 960 if (the_insn.exp.X_op == O_constant) 961 { 962 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 963 { 964 if (sizeof(offsetT) > 4 965 && (the_insn.exp.X_add_number < 0 966 || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) 967 as_warn (_("set: number not in 0..4294967295 range")); 968 } 969 else 970 { 971 if (sizeof(offsetT) > 4 972 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 973 || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) 974 as_warn (_("set: number not in -2147483648..4294967295 range")); 975 the_insn.exp.X_add_number = (int)the_insn.exp.X_add_number; 976 } 977 } 978 979 /* See if operand is absolute and small; skip sethi if so. */ 980 if (the_insn.exp.X_op != O_constant 981 || the_insn.exp.X_add_number >= (1 << 12) 982 || the_insn.exp.X_add_number < -(1 << 12)) 983 { 984 the_insn.opcode = (SETHI_INSN | RD (rd) 985 | ((the_insn.exp.X_add_number >> 10) 986 & (the_insn.exp.X_op == O_constant ? 0x3fffff : 0))); 987 the_insn.reloc = (the_insn.exp.X_op != O_constant 988 ? BFD_RELOC_HI22 989 : BFD_RELOC_NONE); 990 output_insn (insn, &the_insn); 991 need_hi22_p = 1; 992 } 993 994 /* See if operand has no low-order bits; skip OR if so. */ 995 if (the_insn.exp.X_op != O_constant 996 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 997 || ! need_hi22_p) 998 { 999 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1000 | RD (rd) | IMMED 1001 | (the_insn.exp.X_add_number 1002 & (the_insn.exp.X_op != O_constant ? 0 : 1003 need_hi22_p ? 0x3ff : 0x1fff))); 1004 the_insn.reloc = (the_insn.exp.X_op != O_constant 1005 ? BFD_RELOC_LO10 1006 : BFD_RELOC_NONE); 1007 output_insn (insn, &the_insn); 1008 } 1009} 1010 1011/* Handle the setsw synthetic instruction. */ 1012static void 1013synthetize_setsw (insn) 1014 const struct sparc_opcode *insn; 1015{ 1016 int low32, rd, opc; 1017 1018 rd = (the_insn.opcode & RD (~0)) >> 25; 1019 1020 if (the_insn.exp.X_op != O_constant) 1021 { 1022 synthetize_setuw (insn); 1023 1024 /* Need to sign extend it. */ 1025 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1026 the_insn.reloc = BFD_RELOC_NONE; 1027 output_insn (insn, &the_insn); 1028 return; 1029 } 1030 1031 if (sizeof(offsetT) > 4 1032 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 1033 || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) 1034 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1035 1036 low32 = the_insn.exp.X_add_number; 1037 1038 if (low32 >= 0) 1039 { 1040 synthetize_setuw (insn); 1041 return; 1042 } 1043 1044 opc = OR_INSN; 1045 1046 the_insn.reloc = BFD_RELOC_NONE; 1047 /* See if operand is absolute and small; skip sethi if so. */ 1048 if (low32 < -(1 << 12)) 1049 { 1050 the_insn.opcode = (SETHI_INSN | RD (rd) 1051 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1052 output_insn (insn, &the_insn); 1053 low32 = 0x1c00 | (low32 & 0x3ff); 1054 opc = RS1 (rd) | XOR_INSN; 1055 } 1056 1057 the_insn.opcode = (opc | RD (rd) | IMMED 1058 | (low32 & 0x1fff)); 1059 output_insn (insn, &the_insn); 1060} 1061 1062/* Handle the setsw synthetic instruction. */ 1063static void 1064synthetize_setx (insn) 1065 const struct sparc_opcode *insn; 1066{ 1067 int upper32, lower32; 1068 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1069 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1070 int upper_dstreg; 1071 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1072 int need_xor10_p = 0; 1073 1074#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000) 1075 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1076 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1077#undef SIGNEXT32 1078 1079 upper_dstreg = tmpreg; 1080 /* The tmp reg should not be the dst reg. */ 1081 if (tmpreg == dstreg) 1082 as_warn (_("setx: temporary register same as destination register")); 1083 1084 /* ??? Obviously there are other optimizations we can do 1085 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1086 doing some of these. Later. If you do change things, try to 1087 change all of this to be table driven as well. */ 1088 /* What to output depends on the number if it's constant. 1089 Compute that first, then output what we've decided upon. */ 1090 if (the_insn.exp.X_op != O_constant) 1091 { 1092 if (sparc_arch_size == 32) 1093 { 1094 /* When arch size is 32, we want setx to be equivalent 1095 to setuw for anything but constants. */ 1096 the_insn.exp.X_add_number &= 0xffffffff; 1097 synthetize_setuw (insn); 1098 return; 1099 } 1100 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1101 lower32 = 0; upper32 = 0; 1102 } 1103 else 1104 { 1105 /* Reset X_add_number, we've extracted it as upper32/lower32. 1106 Otherwise fixup_segment will complain about not being able to 1107 write an 8 byte number in a 4 byte field. */ 1108 the_insn.exp.X_add_number = 0; 1109 1110 /* Only need hh22 if `or' insn can't handle constant. */ 1111 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1112 need_hh22_p = 1; 1113 1114 /* Does bottom part (after sethi) have bits? */ 1115 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1116 /* No hh22, but does upper32 still have bits we can't set 1117 from lower32? */ 1118 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1119 need_hm10_p = 1; 1120 1121 /* If the lower half is all zero, we build the upper half directly 1122 into the dst reg. */ 1123 if (lower32 != 0 1124 /* Need lower half if number is zero or 0xffffffff00000000. */ 1125 || (! need_hh22_p && ! need_hm10_p)) 1126 { 1127 /* No need for sethi if `or' insn can handle constant. */ 1128 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1129 /* Note that we can't use a negative constant in the `or' 1130 insn unless the upper 32 bits are all ones. */ 1131 || (lower32 < 0 && upper32 != -1) 1132 || (lower32 >= 0 && upper32 == -1)) 1133 need_hi22_p = 1; 1134 1135 if (need_hi22_p && upper32 == -1) 1136 need_xor10_p = 1; 1137 1138 /* Does bottom part (after sethi) have bits? */ 1139 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1140 /* No sethi. */ 1141 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1142 /* Need `or' if we didn't set anything else. */ 1143 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1144 need_lo10_p = 1; 1145 } 1146 else 1147 /* Output directly to dst reg if lower 32 bits are all zero. */ 1148 upper_dstreg = dstreg; 1149 } 1150 1151 if (!upper_dstreg && dstreg) 1152 as_warn (_("setx: illegal temporary register g0")); 1153 1154 if (need_hh22_p) 1155 { 1156 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1157 | ((upper32 >> 10) & 0x3fffff)); 1158 the_insn.reloc = (the_insn.exp.X_op != O_constant 1159 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1160 output_insn (insn, &the_insn); 1161 } 1162 1163 if (need_hi22_p) 1164 { 1165 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1166 | (((need_xor10_p ? ~lower32 : lower32) 1167 >> 10) & 0x3fffff)); 1168 the_insn.reloc = (the_insn.exp.X_op != O_constant 1169 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1170 output_insn (insn, &the_insn); 1171 } 1172 1173 if (need_hm10_p) 1174 { 1175 the_insn.opcode = (OR_INSN 1176 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1177 | RD (upper_dstreg) 1178 | IMMED 1179 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1180 the_insn.reloc = (the_insn.exp.X_op != O_constant 1181 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1182 output_insn (insn, &the_insn); 1183 } 1184 1185 if (need_lo10_p) 1186 { 1187 /* FIXME: One nice optimization to do here is to OR the low part 1188 with the highpart if hi22 isn't needed and the low part is 1189 positive. */ 1190 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1191 | RD (dstreg) 1192 | IMMED 1193 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1194 the_insn.reloc = (the_insn.exp.X_op != O_constant 1195 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1196 output_insn (insn, &the_insn); 1197 } 1198 1199 /* If we needed to build the upper part, shift it into place. */ 1200 if (need_hh22_p || need_hm10_p) 1201 { 1202 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1203 | IMMED | 32); 1204 the_insn.reloc = BFD_RELOC_NONE; 1205 output_insn (insn, &the_insn); 1206 } 1207 1208 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1209 if (need_xor10_p) 1210 { 1211 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1212 | 0x1c00 | (lower32 & 0x3ff)); 1213 the_insn.reloc = BFD_RELOC_NONE; 1214 output_insn (insn, &the_insn); 1215 } 1216 1217 /* If we needed to build both upper and lower parts, OR them together. */ 1218 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1219 { 1220 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1221 | RD (dstreg)); 1222 the_insn.reloc = BFD_RELOC_NONE; 1223 output_insn (insn, &the_insn); 1224 } 1225} 1226 1227/* Main entry point to assemble one instruction. */ 1228 1229void 1230md_assemble (str) 1231 char *str; 1232{ 1233 const struct sparc_opcode *insn; 1234 int special_case; 1235 1236 know (str); 1237 special_case = sparc_ip (str, &insn); 1238 1239 /* We warn about attempts to put a floating point branch in a delay slot, 1240 unless the delay slot has been annulled. */ 1241 if (insn != NULL 1242 && last_insn != NULL 1243 && (insn->flags & F_FBR) != 0 1244 && (last_insn->flags & F_DELAYED) != 0 1245 /* ??? This test isn't completely accurate. We assume anything with 1246 F_{UNBR,CONDBR,FBR} set is annullable. */ 1247 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1248 || (last_opcode & ANNUL) == 0)) 1249 as_warn (_("FP branch in delay slot")); 1250 1251 /* SPARC before v9 requires a nop instruction between a floating 1252 point instruction and a floating point branch. We insert one 1253 automatically, with a warning. */ 1254 if (max_architecture < SPARC_OPCODE_ARCH_V9 1255 && insn != NULL 1256 && last_insn != NULL 1257 && (insn->flags & F_FBR) != 0 1258 && (last_insn->flags & F_FLOAT) != 0) 1259 { 1260 struct sparc_it nop_insn; 1261 1262 nop_insn.opcode = NOP_INSN; 1263 nop_insn.reloc = BFD_RELOC_NONE; 1264 output_insn (insn, &nop_insn); 1265 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1266 } 1267 1268 switch (special_case) 1269 { 1270 case SPECIAL_CASE_NONE: 1271 /* normal insn */ 1272 output_insn (insn, &the_insn); 1273 break; 1274 1275 case SPECIAL_CASE_SETSW: 1276 synthetize_setsw (insn); 1277 break; 1278 1279 case SPECIAL_CASE_SET: 1280 synthetize_setuw (insn); 1281 break; 1282 1283 case SPECIAL_CASE_SETX: 1284 synthetize_setx (insn); 1285 break; 1286 1287 case SPECIAL_CASE_FDIV: 1288 { 1289 int rd = (the_insn.opcode >> 25) & 0x1f; 1290 1291 output_insn (insn, &the_insn); 1292 1293 /* According to information leaked from Sun, the "fdiv" instructions 1294 on early SPARC machines would produce incorrect results sometimes. 1295 The workaround is to add an fmovs of the destination register to 1296 itself just after the instruction. This was true on machines 1297 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1298 assert (the_insn.reloc == BFD_RELOC_NONE); 1299 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1300 output_insn (insn, &the_insn); 1301 return; 1302 } 1303 1304 default: 1305 as_fatal (_("failed special case insn sanity check")); 1306 } 1307} 1308 1309/* Subroutine of md_assemble to do the actual parsing. */ 1310 1311static int 1312sparc_ip (str, pinsn) 1313 char *str; 1314 const struct sparc_opcode **pinsn; 1315{ 1316 char *error_message = ""; 1317 char *s; 1318 const char *args; 1319 char c; 1320 const struct sparc_opcode *insn; 1321 char *argsStart; 1322 unsigned long opcode; 1323 unsigned int mask = 0; 1324 int match = 0; 1325 int comma = 0; 1326 int v9_arg_p; 1327 int special_case = SPECIAL_CASE_NONE; 1328 1329 s = str; 1330 if (islower ((unsigned char) *s)) 1331 { 1332 do 1333 ++s; 1334 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s)); 1335 } 1336 1337 switch (*s) 1338 { 1339 case '\0': 1340 break; 1341 1342 case ',': 1343 comma = 1; 1344 1345 /*FALLTHROUGH */ 1346 1347 case ' ': 1348 *s++ = '\0'; 1349 break; 1350 1351 default: 1352 as_fatal (_("Unknown opcode: `%s'"), str); 1353 } 1354 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1355 *pinsn = insn; 1356 if (insn == NULL) 1357 { 1358 as_bad (_("Unknown opcode: `%s'"), str); 1359 return special_case; 1360 } 1361 if (comma) 1362 { 1363 *--s = ','; 1364 } 1365 1366 argsStart = s; 1367 for (;;) 1368 { 1369 opcode = insn->match; 1370 memset (&the_insn, '\0', sizeof (the_insn)); 1371 the_insn.reloc = BFD_RELOC_NONE; 1372 v9_arg_p = 0; 1373 1374 /* 1375 * Build the opcode, checking as we go to make 1376 * sure that the operands match 1377 */ 1378 for (args = insn->args;; ++args) 1379 { 1380 switch (*args) 1381 { 1382 case 'K': 1383 { 1384 int kmask = 0; 1385 1386 /* Parse a series of masks. */ 1387 if (*s == '#') 1388 { 1389 while (*s == '#') 1390 { 1391 int mask; 1392 1393 if (! parse_keyword_arg (sparc_encode_membar, &s, 1394 &mask)) 1395 { 1396 error_message = _(": invalid membar mask name"); 1397 goto error; 1398 } 1399 kmask |= mask; 1400 while (*s == ' ') { ++s; continue; } 1401 if (*s == '|' || *s == '+') 1402 ++s; 1403 while (*s == ' ') { ++s; continue; } 1404 } 1405 } 1406 else 1407 { 1408 if (! parse_const_expr_arg (&s, &kmask)) 1409 { 1410 error_message = _(": invalid membar mask expression"); 1411 goto error; 1412 } 1413 if (kmask < 0 || kmask > 127) 1414 { 1415 error_message = _(": invalid membar mask number"); 1416 goto error; 1417 } 1418 } 1419 1420 opcode |= MEMBAR (kmask); 1421 continue; 1422 } 1423 1424 case '*': 1425 { 1426 int fcn = 0; 1427 1428 /* Parse a prefetch function. */ 1429 if (*s == '#') 1430 { 1431 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1432 { 1433 error_message = _(": invalid prefetch function name"); 1434 goto error; 1435 } 1436 } 1437 else 1438 { 1439 if (! parse_const_expr_arg (&s, &fcn)) 1440 { 1441 error_message = _(": invalid prefetch function expression"); 1442 goto error; 1443 } 1444 if (fcn < 0 || fcn > 31) 1445 { 1446 error_message = _(": invalid prefetch function number"); 1447 goto error; 1448 } 1449 } 1450 opcode |= RD (fcn); 1451 continue; 1452 } 1453 1454 case '!': 1455 case '?': 1456 /* Parse a sparc64 privileged register. */ 1457 if (*s == '%') 1458 { 1459 struct priv_reg_entry *p = priv_reg_table; 1460 unsigned int len = 9999999; /* init to make gcc happy */ 1461 1462 s += 1; 1463 while (p->name[0] > s[0]) 1464 p++; 1465 while (p->name[0] == s[0]) 1466 { 1467 len = strlen (p->name); 1468 if (strncmp (p->name, s, len) == 0) 1469 break; 1470 p++; 1471 } 1472 if (p->name[0] != s[0]) 1473 { 1474 error_message = _(": unrecognizable privileged register"); 1475 goto error; 1476 } 1477 if (*args == '?') 1478 opcode |= (p->regnum << 14); 1479 else 1480 opcode |= (p->regnum << 25); 1481 s += len; 1482 continue; 1483 } 1484 else 1485 { 1486 error_message = _(": unrecognizable privileged register"); 1487 goto error; 1488 } 1489 1490 case '_': 1491 case '/': 1492 /* Parse a v9a ancillary state register. */ 1493 if (*s == '%') 1494 { 1495 struct priv_reg_entry *p = v9a_asr_table; 1496 unsigned int len = 9999999; /* init to make gcc happy */ 1497 1498 s += 1; 1499 while (p->name[0] > s[0]) 1500 p++; 1501 while (p->name[0] == s[0]) 1502 { 1503 len = strlen (p->name); 1504 if (strncmp (p->name, s, len) == 0) 1505 break; 1506 p++; 1507 } 1508 if (p->name[0] != s[0]) 1509 { 1510 error_message = _(": unrecognizable v9a ancillary state register"); 1511 goto error; 1512 } 1513 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1514 { 1515 error_message = _(": rd on write only ancillary state register"); 1516 goto error; 1517 } 1518 if (*args == '/') 1519 opcode |= (p->regnum << 14); 1520 else 1521 opcode |= (p->regnum << 25); 1522 s += len; 1523 continue; 1524 } 1525 else 1526 { 1527 error_message = _(": unrecognizable v9a ancillary state register"); 1528 goto error; 1529 } 1530 1531 case 'M': 1532 case 'm': 1533 if (strncmp (s, "%asr", 4) == 0) 1534 { 1535 s += 4; 1536 1537 if (isdigit ((unsigned char) *s)) 1538 { 1539 long num = 0; 1540 1541 while (isdigit ((unsigned char) *s)) 1542 { 1543 num = num * 10 + *s - '0'; 1544 ++s; 1545 } 1546 1547 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1548 { 1549 if (num < 16 || 31 < num) 1550 { 1551 error_message = _(": asr number must be between 16 and 31"); 1552 goto error; 1553 } 1554 } 1555 else 1556 { 1557 if (num < 0 || 31 < num) 1558 { 1559 error_message = _(": asr number must be between 0 and 31"); 1560 goto error; 1561 } 1562 } 1563 1564 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1565 continue; 1566 } 1567 else 1568 { 1569 error_message = _(": expecting %asrN"); 1570 goto error; 1571 } 1572 } /* if %asr */ 1573 break; 1574 1575 case 'I': 1576 the_insn.reloc = BFD_RELOC_SPARC_11; 1577 goto immediate; 1578 1579 case 'j': 1580 the_insn.reloc = BFD_RELOC_SPARC_10; 1581 goto immediate; 1582 1583 case 'X': 1584 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1585 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1586 the_insn.reloc = BFD_RELOC_SPARC_5; 1587 else 1588 the_insn.reloc = BFD_RELOC_SPARC13; 1589 /* These fields are unsigned, but for upward compatibility, 1590 allow negative values as well. */ 1591 goto immediate; 1592 1593 case 'Y': 1594 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1595 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1596 the_insn.reloc = BFD_RELOC_SPARC_6; 1597 else 1598 the_insn.reloc = BFD_RELOC_SPARC13; 1599 /* These fields are unsigned, but for upward compatibility, 1600 allow negative values as well. */ 1601 goto immediate; 1602 1603 case 'k': 1604 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1605 the_insn.pcrel = 1; 1606 goto immediate; 1607 1608 case 'G': 1609 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1610 the_insn.pcrel = 1; 1611 goto immediate; 1612 1613 case 'N': 1614 if (*s == 'p' && s[1] == 'n') 1615 { 1616 s += 2; 1617 continue; 1618 } 1619 break; 1620 1621 case 'T': 1622 if (*s == 'p' && s[1] == 't') 1623 { 1624 s += 2; 1625 continue; 1626 } 1627 break; 1628 1629 case 'z': 1630 if (*s == ' ') 1631 { 1632 ++s; 1633 } 1634 if (strncmp (s, "%icc", 4) == 0) 1635 { 1636 s += 4; 1637 continue; 1638 } 1639 break; 1640 1641 case 'Z': 1642 if (*s == ' ') 1643 { 1644 ++s; 1645 } 1646 if (strncmp (s, "%xcc", 4) == 0) 1647 { 1648 s += 4; 1649 continue; 1650 } 1651 break; 1652 1653 case '6': 1654 if (*s == ' ') 1655 { 1656 ++s; 1657 } 1658 if (strncmp (s, "%fcc0", 5) == 0) 1659 { 1660 s += 5; 1661 continue; 1662 } 1663 break; 1664 1665 case '7': 1666 if (*s == ' ') 1667 { 1668 ++s; 1669 } 1670 if (strncmp (s, "%fcc1", 5) == 0) 1671 { 1672 s += 5; 1673 continue; 1674 } 1675 break; 1676 1677 case '8': 1678 if (*s == ' ') 1679 { 1680 ++s; 1681 } 1682 if (strncmp (s, "%fcc2", 5) == 0) 1683 { 1684 s += 5; 1685 continue; 1686 } 1687 break; 1688 1689 case '9': 1690 if (*s == ' ') 1691 { 1692 ++s; 1693 } 1694 if (strncmp (s, "%fcc3", 5) == 0) 1695 { 1696 s += 5; 1697 continue; 1698 } 1699 break; 1700 1701 case 'P': 1702 if (strncmp (s, "%pc", 3) == 0) 1703 { 1704 s += 3; 1705 continue; 1706 } 1707 break; 1708 1709 case 'W': 1710 if (strncmp (s, "%tick", 5) == 0) 1711 { 1712 s += 5; 1713 continue; 1714 } 1715 break; 1716 1717 case '\0': /* end of args */ 1718 if (*s == '\0') 1719 { 1720 match = 1; 1721 } 1722 break; 1723 1724 case '+': 1725 if (*s == '+') 1726 { 1727 ++s; 1728 continue; 1729 } 1730 if (*s == '-') 1731 { 1732 continue; 1733 } 1734 break; 1735 1736 case '[': /* these must match exactly */ 1737 case ']': 1738 case ',': 1739 case ' ': 1740 if (*s++ == *args) 1741 continue; 1742 break; 1743 1744 case '#': /* must be at least one digit */ 1745 if (isdigit ((unsigned char) *s++)) 1746 { 1747 while (isdigit ((unsigned char) *s)) 1748 { 1749 ++s; 1750 } 1751 continue; 1752 } 1753 break; 1754 1755 case 'C': /* coprocessor state register */ 1756 if (strncmp (s, "%csr", 4) == 0) 1757 { 1758 s += 4; 1759 continue; 1760 } 1761 break; 1762 1763 case 'b': /* next operand is a coprocessor register */ 1764 case 'c': 1765 case 'D': 1766 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s)) 1767 { 1768 mask = *s++; 1769 if (isdigit ((unsigned char) *s)) 1770 { 1771 mask = 10 * (mask - '0') + (*s++ - '0'); 1772 if (mask >= 32) 1773 { 1774 break; 1775 } 1776 } 1777 else 1778 { 1779 mask -= '0'; 1780 } 1781 switch (*args) 1782 { 1783 1784 case 'b': 1785 opcode |= mask << 14; 1786 continue; 1787 1788 case 'c': 1789 opcode |= mask; 1790 continue; 1791 1792 case 'D': 1793 opcode |= mask << 25; 1794 continue; 1795 } 1796 } 1797 break; 1798 1799 case 'r': /* next operand must be a register */ 1800 case 'O': 1801 case '1': 1802 case '2': 1803 case 'd': 1804 if (*s++ == '%') 1805 { 1806 switch (c = *s++) 1807 { 1808 1809 case 'f': /* frame pointer */ 1810 if (*s++ == 'p') 1811 { 1812 mask = 0x1e; 1813 break; 1814 } 1815 goto error; 1816 1817 case 'g': /* global register */ 1818 c = *s++; 1819 if (isoctal (c)) 1820 { 1821 mask = c - '0'; 1822 break; 1823 } 1824 goto error; 1825 1826 case 'i': /* in register */ 1827 c = *s++; 1828 if (isoctal (c)) 1829 { 1830 mask = c - '0' + 24; 1831 break; 1832 } 1833 goto error; 1834 1835 case 'l': /* local register */ 1836 c = *s++; 1837 if (isoctal (c)) 1838 { 1839 mask = (c - '0' + 16); 1840 break; 1841 } 1842 goto error; 1843 1844 case 'o': /* out register */ 1845 c = *s++; 1846 if (isoctal (c)) 1847 { 1848 mask = (c - '0' + 8); 1849 break; 1850 } 1851 goto error; 1852 1853 case 's': /* stack pointer */ 1854 if (*s++ == 'p') 1855 { 1856 mask = 0xe; 1857 break; 1858 } 1859 goto error; 1860 1861 case 'r': /* any register */ 1862 if (!isdigit ((unsigned char) (c = *s++))) 1863 { 1864 goto error; 1865 } 1866 /* FALLTHROUGH */ 1867 case '0': 1868 case '1': 1869 case '2': 1870 case '3': 1871 case '4': 1872 case '5': 1873 case '6': 1874 case '7': 1875 case '8': 1876 case '9': 1877 if (isdigit ((unsigned char) *s)) 1878 { 1879 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 1880 { 1881 goto error; 1882 } 1883 } 1884 else 1885 { 1886 c -= '0'; 1887 } 1888 mask = c; 1889 break; 1890 1891 default: 1892 goto error; 1893 } 1894 1895 if ((mask & ~1) == 2 && sparc_arch_size == 64 1896 && no_undeclared_regs && ! globals [mask]) 1897 as_bad (_("detected global register use not covered by .register pseudo-op")); 1898 1899 /* Got the register, now figure out where 1900 it goes in the opcode. */ 1901 switch (*args) 1902 { 1903 case '1': 1904 opcode |= mask << 14; 1905 continue; 1906 1907 case '2': 1908 opcode |= mask; 1909 continue; 1910 1911 case 'd': 1912 opcode |= mask << 25; 1913 continue; 1914 1915 case 'r': 1916 opcode |= (mask << 25) | (mask << 14); 1917 continue; 1918 1919 case 'O': 1920 opcode |= (mask << 25) | (mask << 0); 1921 continue; 1922 } 1923 } 1924 break; 1925 1926 case 'e': /* next operand is a floating point register */ 1927 case 'v': 1928 case 'V': 1929 1930 case 'f': 1931 case 'B': 1932 case 'R': 1933 1934 case 'g': 1935 case 'H': 1936 case 'J': 1937 { 1938 char format; 1939 1940 if (*s++ == '%' 1941 && ((format = *s) == 'f') 1942 && isdigit ((unsigned char) *++s)) 1943 { 1944 for (mask = 0; isdigit ((unsigned char) *s); ++s) 1945 { 1946 mask = 10 * mask + (*s - '0'); 1947 } /* read the number */ 1948 1949 if ((*args == 'v' 1950 || *args == 'B' 1951 || *args == 'H') 1952 && (mask & 1)) 1953 { 1954 break; 1955 } /* register must be even numbered */ 1956 1957 if ((*args == 'V' 1958 || *args == 'R' 1959 || *args == 'J') 1960 && (mask & 3)) 1961 { 1962 break; 1963 } /* register must be multiple of 4 */ 1964 1965 if (mask >= 64) 1966 { 1967 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1968 error_message = _(": There are only 64 f registers; [0-63]"); 1969 else 1970 error_message = _(": There are only 32 f registers; [0-31]"); 1971 goto error; 1972 } /* on error */ 1973 else if (mask >= 32) 1974 { 1975 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1976 { 1977 v9_arg_p = 1; 1978 mask -= 31; /* wrap high bit */ 1979 } 1980 else 1981 { 1982 error_message = _(": There are only 32 f registers; [0-31]"); 1983 goto error; 1984 } 1985 } 1986 } 1987 else 1988 { 1989 break; 1990 } /* if not an 'f' register. */ 1991 1992 switch (*args) 1993 { 1994 case 'v': 1995 case 'V': 1996 case 'e': 1997 opcode |= RS1 (mask); 1998 continue; 1999 2000 2001 case 'f': 2002 case 'B': 2003 case 'R': 2004 opcode |= RS2 (mask); 2005 continue; 2006 2007 case 'g': 2008 case 'H': 2009 case 'J': 2010 opcode |= RD (mask); 2011 continue; 2012 } /* pack it in. */ 2013 2014 know (0); 2015 break; 2016 } /* float arg */ 2017 2018 case 'F': 2019 if (strncmp (s, "%fsr", 4) == 0) 2020 { 2021 s += 4; 2022 continue; 2023 } 2024 break; 2025 2026 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2027 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2028 goto immediate; 2029 2030 case 'l': /* 22 bit PC relative immediate */ 2031 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2032 the_insn.pcrel = 1; 2033 goto immediate; 2034 2035 case 'L': /* 30 bit immediate */ 2036 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2037 the_insn.pcrel = 1; 2038 goto immediate; 2039 2040 case 'h': 2041 case 'n': /* 22 bit immediate */ 2042 the_insn.reloc = BFD_RELOC_SPARC22; 2043 goto immediate; 2044 2045 case 'i': /* 13 bit immediate */ 2046 the_insn.reloc = BFD_RELOC_SPARC13; 2047 2048 /* fallthrough */ 2049 2050 immediate: 2051 if (*s == ' ') 2052 s++; 2053 2054 { 2055 char *s1; 2056 char *op_arg = NULL; 2057 expressionS op_exp; 2058 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2059 2060 /* Check for %hi, etc. */ 2061 if (*s == '%') 2062 { 2063 static const struct ops { 2064 /* The name as it appears in assembler. */ 2065 char *name; 2066 /* strlen (name), precomputed for speed */ 2067 int len; 2068 /* The reloc this pseudo-op translates to. */ 2069 int reloc; 2070 /* Non-zero if for v9 only. */ 2071 int v9_p; 2072 /* Non-zero if can be used in pc-relative contexts. */ 2073 int pcrel_p;/*FIXME:wip*/ 2074 } ops[] = { 2075 /* hix/lox must appear before hi/lo so %hix won't be 2076 mistaken for %hi. */ 2077 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2078 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2079 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2080 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2081 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2082 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2083 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2084 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2085 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2086 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2087 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2088 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2089 { NULL } 2090 }; 2091 const struct ops *o; 2092 2093 for (o = ops; o->name; o++) 2094 if (strncmp (s + 1, o->name, o->len) == 0) 2095 break; 2096 if (o->name == NULL) 2097 break; 2098 2099 if (s[o->len + 1] != '(') 2100 { 2101 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2102 return special_case; 2103 } 2104 2105 op_arg = o->name; 2106 the_insn.reloc = o->reloc; 2107 s += o->len + 2; 2108 v9_arg_p = o->v9_p; 2109 } 2110 2111 /* Note that if the get_expression() fails, we will still 2112 have created U entries in the symbol table for the 2113 'symbols' in the input string. Try not to create U 2114 symbols for registers, etc. */ 2115 2116 /* This stuff checks to see if the expression ends in 2117 +%reg. If it does, it removes the register from 2118 the expression, and re-sets 's' to point to the 2119 right place. */ 2120 2121 if (op_arg) 2122 { 2123 int npar = 0; 2124 2125 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2126 if (*s1 == '(') 2127 npar++; 2128 else if (*s1 == ')') 2129 { 2130 if (!npar) 2131 break; 2132 npar--; 2133 } 2134 2135 if (*s1 != ')') 2136 { 2137 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2138 return special_case; 2139 } 2140 2141 *s1 = '\0'; 2142 (void) get_expression (s); 2143 *s1 = ')'; 2144 s = s1 + 1; 2145 if (*s == ',' || *s == ']' || !*s) 2146 continue; 2147 if (*s != '+' && *s != '-') 2148 { 2149 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2150 return special_case; 2151 } 2152 *s1 = '0'; 2153 s = s1; 2154 op_exp = the_insn.exp; 2155 memset (&the_insn.exp, 0, sizeof(the_insn.exp)); 2156 } 2157 2158 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ; 2159 2160 if (s1 != s && isdigit ((unsigned char) s1[-1])) 2161 { 2162 if (s1[-2] == '%' && s1[-3] == '+') 2163 s1 -= 3; 2164 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2165 s1 -= 4; 2166 else 2167 s1 = NULL; 2168 if (s1) 2169 { 2170 *s1 = '\0'; 2171 if (op_arg && s1 == s + 1) 2172 the_insn.exp.X_op = O_absent; 2173 else 2174 (void) get_expression (s); 2175 *s1 = '+'; 2176 if (op_arg) 2177 *s = ')'; 2178 s = s1; 2179 } 2180 } 2181 else 2182 s1 = NULL; 2183 2184 if (!s1) 2185 { 2186 (void) get_expression (s); 2187 if (op_arg) 2188 *s = ')'; 2189 s = expr_end; 2190 } 2191 2192 if (op_arg) 2193 { 2194 the_insn.exp2 = the_insn.exp; 2195 the_insn.exp = op_exp; 2196 if (the_insn.exp2.X_op == O_absent) 2197 the_insn.exp2.X_op = O_illegal; 2198 else if (the_insn.exp.X_op == O_absent) 2199 { 2200 the_insn.exp = the_insn.exp2; 2201 the_insn.exp2.X_op = O_illegal; 2202 } 2203 else if (the_insn.exp.X_op == O_constant) 2204 { 2205 valueT val = the_insn.exp.X_add_number; 2206 switch (the_insn.reloc) 2207 { 2208 default: 2209 break; 2210 2211 case BFD_RELOC_SPARC_HH22: 2212 val = BSR (val, 32); 2213 /* intentional fallthrough */ 2214 2215 case BFD_RELOC_SPARC_LM22: 2216 case BFD_RELOC_HI22: 2217 val = (val >> 10) & 0x3fffff; 2218 break; 2219 2220 case BFD_RELOC_SPARC_HM10: 2221 val = BSR (val, 32); 2222 /* intentional fallthrough */ 2223 2224 case BFD_RELOC_LO10: 2225 val &= 0x3ff; 2226 break; 2227 2228 case BFD_RELOC_SPARC_H44: 2229 val >>= 22; 2230 val &= 0x3fffff; 2231 break; 2232 2233 case BFD_RELOC_SPARC_M44: 2234 val >>= 12; 2235 val &= 0x3ff; 2236 break; 2237 2238 case BFD_RELOC_SPARC_L44: 2239 val &= 0xfff; 2240 break; 2241 2242 case BFD_RELOC_SPARC_HIX22: 2243 val = ~ val; 2244 val = (val >> 10) & 0x3fffff; 2245 break; 2246 2247 case BFD_RELOC_SPARC_LOX10: 2248 val = (val & 0x3ff) | 0x1c00; 2249 break; 2250 } 2251 the_insn.exp = the_insn.exp2; 2252 the_insn.exp.X_add_number += val; 2253 the_insn.exp2.X_op = O_illegal; 2254 the_insn.reloc = old_reloc; 2255 } 2256 else if (the_insn.exp2.X_op != O_constant) 2257 { 2258 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2259 return special_case; 2260 } 2261 else 2262 { 2263 if (old_reloc != BFD_RELOC_SPARC13 2264 || the_insn.reloc != BFD_RELOC_LO10 2265 || sparc_arch_size != 64 2266 || sparc_pic_code) 2267 { 2268 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2269 return special_case; 2270 } 2271 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2272 } 2273 } 2274 } 2275 /* Check for constants that don't require emitting a reloc. */ 2276 if (the_insn.exp.X_op == O_constant 2277 && the_insn.exp.X_add_symbol == 0 2278 && the_insn.exp.X_op_symbol == 0) 2279 { 2280 /* For pc-relative call instructions, we reject 2281 constants to get better code. */ 2282 if (the_insn.pcrel 2283 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2284 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2285 { 2286 error_message = _(": PC-relative operand can't be a constant"); 2287 goto error; 2288 } 2289 2290 /* Constants that won't fit are checked in md_apply_fix3 2291 and bfd_install_relocation. 2292 ??? It would be preferable to install the constants 2293 into the insn here and save having to create a fixS 2294 for each one. There already exists code to handle 2295 all the various cases (e.g. in md_apply_fix3 and 2296 bfd_install_relocation) so duplicating all that code 2297 here isn't right. */ 2298 } 2299 2300 continue; 2301 2302 case 'a': 2303 if (*s++ == 'a') 2304 { 2305 opcode |= ANNUL; 2306 continue; 2307 } 2308 break; 2309 2310 case 'A': 2311 { 2312 int asi = 0; 2313 2314 /* Parse an asi. */ 2315 if (*s == '#') 2316 { 2317 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2318 { 2319 error_message = _(": invalid ASI name"); 2320 goto error; 2321 } 2322 } 2323 else 2324 { 2325 if (! parse_const_expr_arg (&s, &asi)) 2326 { 2327 error_message = _(": invalid ASI expression"); 2328 goto error; 2329 } 2330 if (asi < 0 || asi > 255) 2331 { 2332 error_message = _(": invalid ASI number"); 2333 goto error; 2334 } 2335 } 2336 opcode |= ASI (asi); 2337 continue; 2338 } /* alternate space */ 2339 2340 case 'p': 2341 if (strncmp (s, "%psr", 4) == 0) 2342 { 2343 s += 4; 2344 continue; 2345 } 2346 break; 2347 2348 case 'q': /* floating point queue */ 2349 if (strncmp (s, "%fq", 3) == 0) 2350 { 2351 s += 3; 2352 continue; 2353 } 2354 break; 2355 2356 case 'Q': /* coprocessor queue */ 2357 if (strncmp (s, "%cq", 3) == 0) 2358 { 2359 s += 3; 2360 continue; 2361 } 2362 break; 2363 2364 case 'S': 2365 if (strcmp (str, "set") == 0 2366 || strcmp (str, "setuw") == 0) 2367 { 2368 special_case = SPECIAL_CASE_SET; 2369 continue; 2370 } 2371 else if (strcmp (str, "setsw") == 0) 2372 { 2373 special_case = SPECIAL_CASE_SETSW; 2374 continue; 2375 } 2376 else if (strcmp (str, "setx") == 0) 2377 { 2378 special_case = SPECIAL_CASE_SETX; 2379 continue; 2380 } 2381 else if (strncmp (str, "fdiv", 4) == 0) 2382 { 2383 special_case = SPECIAL_CASE_FDIV; 2384 continue; 2385 } 2386 break; 2387 2388 case 'o': 2389 if (strncmp (s, "%asi", 4) != 0) 2390 break; 2391 s += 4; 2392 continue; 2393 2394 case 's': 2395 if (strncmp (s, "%fprs", 5) != 0) 2396 break; 2397 s += 5; 2398 continue; 2399 2400 case 'E': 2401 if (strncmp (s, "%ccr", 4) != 0) 2402 break; 2403 s += 4; 2404 continue; 2405 2406 case 't': 2407 if (strncmp (s, "%tbr", 4) != 0) 2408 break; 2409 s += 4; 2410 continue; 2411 2412 case 'w': 2413 if (strncmp (s, "%wim", 4) != 0) 2414 break; 2415 s += 4; 2416 continue; 2417 2418 case 'x': 2419 { 2420 char *push = input_line_pointer; 2421 expressionS e; 2422 2423 input_line_pointer = s; 2424 expression (&e); 2425 if (e.X_op == O_constant) 2426 { 2427 int n = e.X_add_number; 2428 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2429 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2430 else 2431 opcode |= e.X_add_number << 5; 2432 } 2433 else 2434 as_bad (_("non-immediate OPF operand, ignored")); 2435 s = input_line_pointer; 2436 input_line_pointer = push; 2437 continue; 2438 } 2439 2440 case 'y': 2441 if (strncmp (s, "%y", 2) != 0) 2442 break; 2443 s += 2; 2444 continue; 2445 2446 case 'u': 2447 case 'U': 2448 { 2449 /* Parse a sparclet cpreg. */ 2450 int cpreg; 2451 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2452 { 2453 error_message = _(": invalid cpreg name"); 2454 goto error; 2455 } 2456 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2457 continue; 2458 } 2459 2460 default: 2461 as_fatal (_("failed sanity check.")); 2462 } /* switch on arg code */ 2463 2464 /* Break out of for() loop. */ 2465 break; 2466 } /* for each arg that we expect */ 2467 2468 error: 2469 if (match == 0) 2470 { 2471 /* Args don't match. */ 2472 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2473 && (insn->name == insn[1].name 2474 || !strcmp (insn->name, insn[1].name))) 2475 { 2476 ++insn; 2477 s = argsStart; 2478 continue; 2479 } 2480 else 2481 { 2482 as_bad (_("Illegal operands%s"), error_message); 2483 return special_case; 2484 } 2485 } 2486 else 2487 { 2488 /* We have a match. Now see if the architecture is ok. */ 2489 int needed_arch_mask = insn->architecture; 2490 2491 if (v9_arg_p) 2492 { 2493 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9) 2494 | (1 << SPARC_OPCODE_ARCH_V9A)); 2495 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9); 2496 } 2497 2498 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture)) 2499 ; /* ok */ 2500 /* Can we bump up the architecture? */ 2501 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture)) 2502 { 2503 enum sparc_opcode_arch_val needed_architecture = 2504 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2505 & needed_arch_mask); 2506 2507 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2508 if (warn_on_bump 2509 && needed_architecture > warn_after_architecture) 2510 { 2511 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2512 sparc_opcode_archs[current_architecture].name, 2513 sparc_opcode_archs[needed_architecture].name, 2514 str); 2515 warn_after_architecture = needed_architecture; 2516 } 2517 current_architecture = needed_architecture; 2518 } 2519 /* Conflict. */ 2520 /* ??? This seems to be a bit fragile. What if the next entry in 2521 the opcode table is the one we want and it is supported? 2522 It is possible to arrange the table today so that this can't 2523 happen but what about tomorrow? */ 2524 else 2525 { 2526 int arch,printed_one_p = 0; 2527 char *p; 2528 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2529 2530 /* Create a list of the architectures that support the insn. */ 2531 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture); 2532 p = required_archs; 2533 arch = sparc_ffs (needed_arch_mask); 2534 while ((1 << arch) <= needed_arch_mask) 2535 { 2536 if ((1 << arch) & needed_arch_mask) 2537 { 2538 if (printed_one_p) 2539 *p++ = '|'; 2540 strcpy (p, sparc_opcode_archs[arch].name); 2541 p += strlen (p); 2542 printed_one_p = 1; 2543 } 2544 ++arch; 2545 } 2546 2547 as_bad (_("Architecture mismatch on \"%s\"."), str); 2548 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2549 required_archs, 2550 sparc_opcode_archs[max_architecture].name); 2551 return special_case; 2552 } 2553 } /* if no match */ 2554 2555 break; 2556 } /* forever looking for a match */ 2557 2558 the_insn.opcode = opcode; 2559 return special_case; 2560} 2561 2562/* Parse an argument that can be expressed as a keyword. 2563 (eg: #StoreStore or %ccfr). 2564 The result is a boolean indicating success. 2565 If successful, INPUT_POINTER is updated. */ 2566 2567static int 2568parse_keyword_arg (lookup_fn, input_pointerP, valueP) 2569 int (*lookup_fn) PARAMS ((const char *)); 2570 char **input_pointerP; 2571 int *valueP; 2572{ 2573 int value; 2574 char c, *p, *q; 2575 2576 p = *input_pointerP; 2577 for (q = p + (*p == '#' || *p == '%'); 2578 isalnum ((unsigned char) *q) || *q == '_'; 2579 ++q) 2580 continue; 2581 c = *q; 2582 *q = 0; 2583 value = (*lookup_fn) (p); 2584 *q = c; 2585 if (value == -1) 2586 return 0; 2587 *valueP = value; 2588 *input_pointerP = q; 2589 return 1; 2590} 2591 2592/* Parse an argument that is a constant expression. 2593 The result is a boolean indicating success. */ 2594 2595static int 2596parse_const_expr_arg (input_pointerP, valueP) 2597 char **input_pointerP; 2598 int *valueP; 2599{ 2600 char *save = input_line_pointer; 2601 expressionS exp; 2602 2603 input_line_pointer = *input_pointerP; 2604 /* The next expression may be something other than a constant 2605 (say if we're not processing the right variant of the insn). 2606 Don't call expression unless we're sure it will succeed as it will 2607 signal an error (which we want to defer until later). */ 2608 /* FIXME: It might be better to define md_operand and have it recognize 2609 things like %asi, etc. but continuing that route through to the end 2610 is a lot of work. */ 2611 if (*input_line_pointer == '%') 2612 { 2613 input_line_pointer = save; 2614 return 0; 2615 } 2616 expression (&exp); 2617 *input_pointerP = input_line_pointer; 2618 input_line_pointer = save; 2619 if (exp.X_op != O_constant) 2620 return 0; 2621 *valueP = exp.X_add_number; 2622 return 1; 2623} 2624 2625/* Subroutine of sparc_ip to parse an expression. */ 2626 2627static int 2628get_expression (str) 2629 char *str; 2630{ 2631 char *save_in; 2632 segT seg; 2633 2634 save_in = input_line_pointer; 2635 input_line_pointer = str; 2636 seg = expression (&the_insn.exp); 2637 if (seg != absolute_section 2638 && seg != text_section 2639 && seg != data_section 2640 && seg != bss_section 2641 && seg != undefined_section) 2642 { 2643 the_insn.error = _("bad segment"); 2644 expr_end = input_line_pointer; 2645 input_line_pointer = save_in; 2646 return 1; 2647 } 2648 expr_end = input_line_pointer; 2649 input_line_pointer = save_in; 2650 return 0; 2651} 2652 2653/* Subroutine of md_assemble to output one insn. */ 2654 2655static void 2656output_insn (insn, the_insn) 2657 const struct sparc_opcode *insn; 2658 struct sparc_it *the_insn; 2659{ 2660 char *toP = frag_more (4); 2661 2662 /* put out the opcode */ 2663 if (INSN_BIG_ENDIAN) 2664 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); 2665 else 2666 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); 2667 2668 /* put out the symbol-dependent stuff */ 2669 if (the_insn->reloc != BFD_RELOC_NONE) 2670 { 2671 fixS *fixP = fix_new_exp (frag_now, /* which frag */ 2672 (toP - frag_now->fr_literal), /* where */ 2673 4, /* size */ 2674 &the_insn->exp, 2675 the_insn->pcrel, 2676 the_insn->reloc); 2677 /* Turn off overflow checking in fixup_segment. We'll do our 2678 own overflow checking in md_apply_fix3. This is necessary because 2679 the insn size is 4 and fixup_segment will signal an overflow for 2680 large 8 byte quantities. */ 2681 fixP->fx_no_overflow = 1; 2682 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) 2683 fixP->tc_fix_data = the_insn->exp2.X_add_number; 2684 } 2685 2686 last_insn = insn; 2687 last_opcode = the_insn->opcode; 2688} 2689 2690/* 2691 This is identical to the md_atof in m68k.c. I think this is right, 2692 but I'm not sure. 2693 2694 Turn a string in input_line_pointer into a floating point constant of type 2695 type, and store the appropriate bytes in *litP. The number of LITTLENUMS 2696 emitted is stored in *sizeP . An error message is returned, or NULL on OK. 2697 */ 2698 2699/* Equal to MAX_PRECISION in atof-ieee.c */ 2700#define MAX_LITTLENUMS 6 2701 2702char * 2703md_atof (type, litP, sizeP) 2704 char type; 2705 char *litP; 2706 int *sizeP; 2707{ 2708 int i,prec; 2709 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2710 char *t; 2711 2712 switch (type) 2713 { 2714 case 'f': 2715 case 'F': 2716 case 's': 2717 case 'S': 2718 prec = 2; 2719 break; 2720 2721 case 'd': 2722 case 'D': 2723 case 'r': 2724 case 'R': 2725 prec = 4; 2726 break; 2727 2728 case 'x': 2729 case 'X': 2730 prec = 6; 2731 break; 2732 2733 case 'p': 2734 case 'P': 2735 prec = 6; 2736 break; 2737 2738 default: 2739 *sizeP = 0; 2740 return _("Bad call to MD_ATOF()"); 2741 } 2742 2743 t = atof_ieee (input_line_pointer, type, words); 2744 if (t) 2745 input_line_pointer = t; 2746 *sizeP = prec * sizeof (LITTLENUM_TYPE); 2747 2748 if (target_big_endian) 2749 { 2750 for (i = 0; i < prec; i++) 2751 { 2752 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); 2753 litP += sizeof (LITTLENUM_TYPE); 2754 } 2755 } 2756 else 2757 { 2758 for (i = prec - 1; i >= 0; i--) 2759 { 2760 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); 2761 litP += sizeof (LITTLENUM_TYPE); 2762 } 2763 } 2764 2765 return 0; 2766} 2767 2768/* Write a value out to the object file, using the appropriate 2769 endianness. */ 2770 2771void 2772md_number_to_chars (buf, val, n) 2773 char *buf; 2774 valueT val; 2775 int n; 2776{ 2777 if (target_big_endian) 2778 number_to_chars_bigendian (buf, val, n); 2779 else if (target_little_endian_data 2780 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 2781 /* Output debug words, which are not in allocated sections, as big endian */ 2782 number_to_chars_bigendian (buf, val, n); 2783 else if (target_little_endian_data || ! target_big_endian) 2784 number_to_chars_littleendian (buf, val, n); 2785} 2786 2787/* Apply a fixS to the frags, now that we know the value it ought to 2788 hold. */ 2789 2790int 2791md_apply_fix3 (fixP, value, segment) 2792 fixS *fixP; 2793 valueT *value; 2794 segT segment; 2795{ 2796 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2797 offsetT val; 2798 long insn; 2799 2800 val = *value; 2801 2802 assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 2803 2804 fixP->fx_addnumber = val; /* Remember value for emit_reloc */ 2805 2806#ifdef OBJ_ELF 2807 /* FIXME: SPARC ELF relocations don't use an addend in the data 2808 field itself. This whole approach should be somehow combined 2809 with the calls to bfd_install_relocation. Also, the value passed 2810 in by fixup_segment includes the value of a defined symbol. We 2811 don't want to include the value of an externally visible symbol. */ 2812 if (fixP->fx_addsy != NULL) 2813 { 2814 if (symbol_used_in_reloc_p (fixP->fx_addsy) 2815 && (S_IS_EXTERNAL (fixP->fx_addsy) 2816 || S_IS_WEAK (fixP->fx_addsy) 2817 || (sparc_pic_code && ! fixP->fx_pcrel) 2818 || (S_GET_SEGMENT (fixP->fx_addsy) != segment 2819 && ((bfd_get_section_flags (stdoutput, 2820 S_GET_SEGMENT (fixP->fx_addsy)) 2821 & SEC_LINK_ONCE) != 0 2822 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), 2823 ".gnu.linkonce", 2824 sizeof ".gnu.linkonce" - 1) == 0))) 2825 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section 2826 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section 2827 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy))) 2828 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy); 2829 return 1; 2830 } 2831#endif 2832 2833 /* This is a hack. There should be a better way to 2834 handle this. Probably in terms of howto fields, once 2835 we can look at these fixups in terms of howtos. */ 2836 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 2837 val += fixP->fx_where + fixP->fx_frag->fr_address; 2838 2839#ifdef OBJ_AOUT 2840 /* FIXME: More ridiculous gas reloc hacking. If we are going to 2841 generate a reloc, then we just want to let the reloc addend set 2842 the value. We do not want to also stuff the addend into the 2843 object file. Including the addend in the object file works when 2844 doing a static link, because the linker will ignore the object 2845 file contents. However, the dynamic linker does not ignore the 2846 object file contents. */ 2847 if (fixP->fx_addsy != NULL 2848 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 2849 val = 0; 2850 2851 /* When generating PIC code, we do not want an addend for a reloc 2852 against a local symbol. We adjust fx_addnumber to cancel out the 2853 value already included in val, and to also cancel out the 2854 adjustment which bfd_install_relocation will create. */ 2855 if (sparc_pic_code 2856 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 2857 && fixP->fx_addsy != NULL 2858 && ! S_IS_COMMON (fixP->fx_addsy) 2859 && symbol_section_p (fixP->fx_addsy)) 2860 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 2861 2862 /* When generating PIC code, we need to fiddle to get 2863 bfd_install_relocation to do the right thing for a PC relative 2864 reloc against a local symbol which we are going to keep. */ 2865 if (sparc_pic_code 2866 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 2867 && fixP->fx_addsy != NULL 2868 && (S_IS_EXTERNAL (fixP->fx_addsy) 2869 || S_IS_WEAK (fixP->fx_addsy)) 2870 && S_IS_DEFINED (fixP->fx_addsy) 2871 && ! S_IS_COMMON (fixP->fx_addsy)) 2872 { 2873 val = 0; 2874 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 2875 } 2876#endif 2877 2878 /* If this is a data relocation, just output VAL. */ 2879 2880 if (fixP->fx_r_type == BFD_RELOC_16) 2881 { 2882 md_number_to_chars (buf, val, 2); 2883 } 2884 else if (fixP->fx_r_type == BFD_RELOC_32 2885 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 2886 { 2887 md_number_to_chars (buf, val, 4); 2888 } 2889 else if (fixP->fx_r_type == BFD_RELOC_64) 2890 { 2891 md_number_to_chars (buf, val, 8); 2892 } 2893 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 2894 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 2895 { 2896 fixP->fx_done = 0; 2897 return 1; 2898 } 2899 else 2900 { 2901 /* It's a relocation against an instruction. */ 2902 2903 if (INSN_BIG_ENDIAN) 2904 insn = bfd_getb32 ((unsigned char *) buf); 2905 else 2906 insn = bfd_getl32 ((unsigned char *) buf); 2907 2908 switch (fixP->fx_r_type) 2909 { 2910 case BFD_RELOC_32_PCREL_S2: 2911 val = val >> 2; 2912 /* FIXME: This increment-by-one deserves a comment of why it's 2913 being done! */ 2914 if (! sparc_pic_code 2915 || fixP->fx_addsy == NULL 2916 || symbol_section_p (fixP->fx_addsy)) 2917 ++val; 2918 insn |= val & 0x3fffffff; 2919 break; 2920 2921 case BFD_RELOC_SPARC_11: 2922 if (! in_signed_range (val, 0x7ff)) 2923 as_bad_where (fixP->fx_file, fixP->fx_line, 2924 _("relocation overflow")); 2925 insn |= val & 0x7ff; 2926 break; 2927 2928 case BFD_RELOC_SPARC_10: 2929 if (! in_signed_range (val, 0x3ff)) 2930 as_bad_where (fixP->fx_file, fixP->fx_line, 2931 _("relocation overflow")); 2932 insn |= val & 0x3ff; 2933 break; 2934 2935 case BFD_RELOC_SPARC_7: 2936 if (! in_bitfield_range (val, 0x7f)) 2937 as_bad_where (fixP->fx_file, fixP->fx_line, 2938 _("relocation overflow")); 2939 insn |= val & 0x7f; 2940 break; 2941 2942 case BFD_RELOC_SPARC_6: 2943 if (! in_bitfield_range (val, 0x3f)) 2944 as_bad_where (fixP->fx_file, fixP->fx_line, 2945 _("relocation overflow")); 2946 insn |= val & 0x3f; 2947 break; 2948 2949 case BFD_RELOC_SPARC_5: 2950 if (! in_bitfield_range (val, 0x1f)) 2951 as_bad_where (fixP->fx_file, fixP->fx_line, 2952 _("relocation overflow")); 2953 insn |= val & 0x1f; 2954 break; 2955 2956 case BFD_RELOC_SPARC_WDISP16: 2957 /* FIXME: simplify */ 2958 if (((val > 0) && (val & ~0x3fffc)) 2959 || ((val < 0) && (~(val - 1) & ~0x3fffc))) 2960 as_bad_where (fixP->fx_file, fixP->fx_line, 2961 _("relocation overflow")); 2962 /* FIXME: The +1 deserves a comment. */ 2963 val = (val >> 2) + 1; 2964 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 2965 break; 2966 2967 case BFD_RELOC_SPARC_WDISP19: 2968 /* FIXME: simplify */ 2969 if (((val > 0) && (val & ~0x1ffffc)) 2970 || ((val < 0) && (~(val - 1) & ~0x1ffffc))) 2971 as_bad_where (fixP->fx_file, fixP->fx_line, 2972 _("relocation overflow")); 2973 /* FIXME: The +1 deserves a comment. */ 2974 val = (val >> 2) + 1; 2975 insn |= val & 0x7ffff; 2976 break; 2977 2978 case BFD_RELOC_SPARC_HH22: 2979 val = BSR (val, 32); 2980 /* intentional fallthrough */ 2981 2982 case BFD_RELOC_SPARC_LM22: 2983 case BFD_RELOC_HI22: 2984 if (!fixP->fx_addsy) 2985 { 2986 insn |= (val >> 10) & 0x3fffff; 2987 } 2988 else 2989 { 2990 /* FIXME: Need comment explaining why we do this. */ 2991 insn &= ~0xffff; 2992 } 2993 break; 2994 2995 case BFD_RELOC_SPARC22: 2996 if (val & ~0x003fffff) 2997 as_bad_where (fixP->fx_file, fixP->fx_line, 2998 _("relocation overflow")); 2999 insn |= (val & 0x3fffff); 3000 break; 3001 3002 case BFD_RELOC_SPARC_HM10: 3003 val = BSR (val, 32); 3004 /* intentional fallthrough */ 3005 3006 case BFD_RELOC_LO10: 3007 if (!fixP->fx_addsy) 3008 { 3009 insn |= val & 0x3ff; 3010 } 3011 else 3012 { 3013 /* FIXME: Need comment explaining why we do this. */ 3014 insn &= ~0xff; 3015 } 3016 break; 3017 3018 case BFD_RELOC_SPARC_OLO10: 3019 val &= 0x3ff; 3020 val += fixP->tc_fix_data; 3021 /* intentional fallthrough */ 3022 3023 case BFD_RELOC_SPARC13: 3024 if (! in_signed_range (val, 0x1fff)) 3025 as_bad_where (fixP->fx_file, fixP->fx_line, 3026 _("relocation overflow")); 3027 insn |= val & 0x1fff; 3028 break; 3029 3030 case BFD_RELOC_SPARC_WDISP22: 3031 val = (val >> 2) + 1; 3032 /* FALLTHROUGH */ 3033 case BFD_RELOC_SPARC_BASE22: 3034 insn |= val & 0x3fffff; 3035 break; 3036 3037 case BFD_RELOC_SPARC_H44: 3038 if (!fixP->fx_addsy) 3039 { 3040 bfd_vma tval = val; 3041 tval >>= 22; 3042 insn |= tval & 0x3fffff; 3043 } 3044 break; 3045 3046 case BFD_RELOC_SPARC_M44: 3047 if (!fixP->fx_addsy) 3048 insn |= (val >> 12) & 0x3ff; 3049 break; 3050 3051 case BFD_RELOC_SPARC_L44: 3052 if (!fixP->fx_addsy) 3053 insn |= val & 0xfff; 3054 break; 3055 3056 case BFD_RELOC_SPARC_HIX22: 3057 if (!fixP->fx_addsy) 3058 { 3059 val ^= ~ (offsetT) 0; 3060 insn |= (val >> 10) & 0x3fffff; 3061 } 3062 break; 3063 3064 case BFD_RELOC_SPARC_LOX10: 3065 if (!fixP->fx_addsy) 3066 insn |= 0x1c00 | (val & 0x3ff); 3067 break; 3068 3069 case BFD_RELOC_NONE: 3070 default: 3071 as_bad_where (fixP->fx_file, fixP->fx_line, 3072 _("bad or unhandled relocation type: 0x%02x"), 3073 fixP->fx_r_type); 3074 break; 3075 } 3076 3077 if (INSN_BIG_ENDIAN) 3078 bfd_putb32 (insn, (unsigned char *) buf); 3079 else 3080 bfd_putl32 (insn, (unsigned char *) buf); 3081 } 3082 3083 /* Are we finished with this relocation now? */ 3084 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3085 fixP->fx_done = 1; 3086 3087 return 1; 3088} 3089 3090/* Translate internal representation of relocation info to BFD target 3091 format. */ 3092arelent ** 3093tc_gen_reloc (section, fixp) 3094 asection *section; 3095 fixS *fixp; 3096{ 3097 static arelent *relocs[3]; 3098 arelent *reloc; 3099 bfd_reloc_code_real_type code; 3100 3101 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3102 relocs[1] = NULL; 3103 3104 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3105 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3106 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3107 3108 switch (fixp->fx_r_type) 3109 { 3110 case BFD_RELOC_16: 3111 case BFD_RELOC_32: 3112 case BFD_RELOC_HI22: 3113 case BFD_RELOC_LO10: 3114 case BFD_RELOC_32_PCREL_S2: 3115 case BFD_RELOC_SPARC13: 3116 case BFD_RELOC_SPARC22: 3117 case BFD_RELOC_SPARC_BASE13: 3118 case BFD_RELOC_SPARC_WDISP16: 3119 case BFD_RELOC_SPARC_WDISP19: 3120 case BFD_RELOC_SPARC_WDISP22: 3121 case BFD_RELOC_64: 3122 case BFD_RELOC_SPARC_5: 3123 case BFD_RELOC_SPARC_6: 3124 case BFD_RELOC_SPARC_7: 3125 case BFD_RELOC_SPARC_10: 3126 case BFD_RELOC_SPARC_11: 3127 case BFD_RELOC_SPARC_HH22: 3128 case BFD_RELOC_SPARC_HM10: 3129 case BFD_RELOC_SPARC_LM22: 3130 case BFD_RELOC_SPARC_PC_HH22: 3131 case BFD_RELOC_SPARC_PC_HM10: 3132 case BFD_RELOC_SPARC_PC_LM22: 3133 case BFD_RELOC_SPARC_H44: 3134 case BFD_RELOC_SPARC_M44: 3135 case BFD_RELOC_SPARC_L44: 3136 case BFD_RELOC_SPARC_HIX22: 3137 case BFD_RELOC_SPARC_LOX10: 3138 case BFD_RELOC_SPARC_REV32: 3139 case BFD_RELOC_SPARC_OLO10: 3140 case BFD_RELOC_VTABLE_ENTRY: 3141 case BFD_RELOC_VTABLE_INHERIT: 3142 code = fixp->fx_r_type; 3143 break; 3144 default: 3145 abort (); 3146 return NULL; 3147 } 3148 3149#if defined (OBJ_ELF) || defined (OBJ_AOUT) 3150 /* If we are generating PIC code, we need to generate a different 3151 set of relocs. */ 3152 3153#ifdef OBJ_ELF 3154#define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3155#else 3156#define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3157#endif 3158 3159 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3160 3161 if (sparc_pic_code) 3162 { 3163 switch (code) 3164 { 3165 case BFD_RELOC_32_PCREL_S2: 3166 if (! S_IS_DEFINED (fixp->fx_addsy) 3167 || S_IS_COMMON (fixp->fx_addsy) 3168 || S_IS_EXTERNAL (fixp->fx_addsy) 3169 || S_IS_WEAK (fixp->fx_addsy)) 3170 code = BFD_RELOC_SPARC_WPLT30; 3171 break; 3172 case BFD_RELOC_HI22: 3173 if (fixp->fx_addsy != NULL 3174 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3175 code = BFD_RELOC_SPARC_PC22; 3176 else 3177 code = BFD_RELOC_SPARC_GOT22; 3178 break; 3179 case BFD_RELOC_LO10: 3180 if (fixp->fx_addsy != NULL 3181 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3182 code = BFD_RELOC_SPARC_PC10; 3183 else 3184 code = BFD_RELOC_SPARC_GOT10; 3185 break; 3186 case BFD_RELOC_SPARC13: 3187 code = BFD_RELOC_SPARC_GOT13; 3188 break; 3189 default: 3190 break; 3191 } 3192 } 3193#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3194 3195 if (code == BFD_RELOC_SPARC_OLO10) 3196 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3197 else 3198 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3199 if (reloc->howto == 0) 3200 { 3201 as_bad_where (fixp->fx_file, fixp->fx_line, 3202 _("internal error: can't export reloc type %d (`%s')"), 3203 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3204 xfree (reloc); 3205 relocs[0] = NULL; 3206 return relocs; 3207 } 3208 3209 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3210#ifdef OBJ_AOUT 3211 3212 if (reloc->howto->pc_relative == 0 3213 || code == BFD_RELOC_SPARC_PC10 3214 || code == BFD_RELOC_SPARC_PC22) 3215 reloc->addend = fixp->fx_addnumber; 3216 else if (sparc_pic_code 3217 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3218 && fixp->fx_addsy != NULL 3219 && (S_IS_EXTERNAL (fixp->fx_addsy) 3220 || S_IS_WEAK (fixp->fx_addsy)) 3221 && S_IS_DEFINED (fixp->fx_addsy) 3222 && ! S_IS_COMMON (fixp->fx_addsy)) 3223 reloc->addend = fixp->fx_addnumber; 3224 else 3225 reloc->addend = fixp->fx_offset - reloc->address; 3226 3227#else /* elf or coff */ 3228 3229 if (reloc->howto->pc_relative == 0 3230 || code == BFD_RELOC_SPARC_PC10 3231 || code == BFD_RELOC_SPARC_PC22) 3232 reloc->addend = fixp->fx_addnumber; 3233 else if (symbol_section_p (fixp->fx_addsy)) 3234 reloc->addend = (section->vma 3235 + fixp->fx_addnumber 3236 + md_pcrel_from (fixp)); 3237 else 3238 reloc->addend = fixp->fx_offset; 3239#endif 3240 3241 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3242 on the same location. */ 3243 if (code == BFD_RELOC_SPARC_OLO10) 3244 { 3245 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3246 relocs[2] = NULL; 3247 3248 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3249 *reloc->sym_ptr_ptr = symbol_get_bfdsym (section_symbol (absolute_section)); 3250 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3251 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3252 reloc->addend = fixp->tc_fix_data; 3253 } 3254 3255 return relocs; 3256} 3257 3258/* We have no need to default values of symbols. */ 3259 3260/* ARGSUSED */ 3261symbolS * 3262md_undefined_symbol (name) 3263 char *name; 3264{ 3265 return 0; 3266} /* md_undefined_symbol() */ 3267 3268/* Round up a section size to the appropriate boundary. */ 3269valueT 3270md_section_align (segment, size) 3271 segT segment; 3272 valueT size; 3273{ 3274#ifndef OBJ_ELF 3275 /* This is not right for ELF; a.out wants it, and COFF will force 3276 the alignment anyways. */ 3277 valueT align = ((valueT) 1 3278 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3279 valueT newsize; 3280 /* turn alignment value into a mask */ 3281 align--; 3282 newsize = (size + align) & ~align; 3283 return newsize; 3284#else 3285 return size; 3286#endif 3287} 3288 3289/* Exactly what point is a PC-relative offset relative TO? 3290 On the sparc, they're relative to the address of the offset, plus 3291 its size. This gets us to the following instruction. 3292 (??? Is this right? FIXME-SOON) */ 3293long 3294md_pcrel_from (fixP) 3295 fixS *fixP; 3296{ 3297 long ret; 3298 3299 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3300 if (! sparc_pic_code 3301 || fixP->fx_addsy == NULL 3302 || symbol_section_p (fixP->fx_addsy)) 3303 ret += fixP->fx_size; 3304 return ret; 3305} 3306 3307/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3308 of two. */ 3309 3310static int 3311log2 (value) 3312 int value; 3313{ 3314 int shift; 3315 3316 if (value <= 0) 3317 return -1; 3318 3319 for (shift = 0; (value & 1) == 0; value >>= 1) 3320 ++shift; 3321 3322 return (value == 1) ? shift : -1; 3323} 3324 3325/* 3326 * sort of like s_lcomm 3327 */ 3328 3329#ifndef OBJ_ELF 3330static int max_alignment = 15; 3331#endif 3332 3333static void 3334s_reserve (ignore) 3335 int ignore; 3336{ 3337 char *name; 3338 char *p; 3339 char c; 3340 int align; 3341 int size; 3342 int temp; 3343 symbolS *symbolP; 3344 3345 name = input_line_pointer; 3346 c = get_symbol_end (); 3347 p = input_line_pointer; 3348 *p = c; 3349 SKIP_WHITESPACE (); 3350 3351 if (*input_line_pointer != ',') 3352 { 3353 as_bad (_("Expected comma after name")); 3354 ignore_rest_of_line (); 3355 return; 3356 } 3357 3358 ++input_line_pointer; 3359 3360 if ((size = get_absolute_expression ()) < 0) 3361 { 3362 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3363 ignore_rest_of_line (); 3364 return; 3365 } /* bad length */ 3366 3367 *p = 0; 3368 symbolP = symbol_find_or_make (name); 3369 *p = c; 3370 3371 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3372 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3373 { 3374 as_bad (_("bad .reserve segment -- expected BSS segment")); 3375 return; 3376 } 3377 3378 if (input_line_pointer[2] == '.') 3379 input_line_pointer += 7; 3380 else 3381 input_line_pointer += 6; 3382 SKIP_WHITESPACE (); 3383 3384 if (*input_line_pointer == ',') 3385 { 3386 ++input_line_pointer; 3387 3388 SKIP_WHITESPACE (); 3389 if (*input_line_pointer == '\n') 3390 { 3391 as_bad (_("missing alignment")); 3392 ignore_rest_of_line (); 3393 return; 3394 } 3395 3396 align = (int) get_absolute_expression (); 3397 3398#ifndef OBJ_ELF 3399 if (align > max_alignment) 3400 { 3401 align = max_alignment; 3402 as_warn (_("alignment too large; assuming %d"), align); 3403 } 3404#endif 3405 3406 if (align < 0) 3407 { 3408 as_bad (_("negative alignment")); 3409 ignore_rest_of_line (); 3410 return; 3411 } 3412 3413 if (align != 0) 3414 { 3415 temp = log2 (align); 3416 if (temp < 0) 3417 { 3418 as_bad (_("alignment not a power of 2")); 3419 ignore_rest_of_line (); 3420 return; 3421 } 3422 3423 align = temp; 3424 } 3425 3426 record_alignment (bss_section, align); 3427 } 3428 else 3429 align = 0; 3430 3431 if (!S_IS_DEFINED (symbolP) 3432#ifdef OBJ_AOUT 3433 && S_GET_OTHER (symbolP) == 0 3434 && S_GET_DESC (symbolP) == 0 3435#endif 3436 ) 3437 { 3438 if (! need_pass_2) 3439 { 3440 char *pfrag; 3441 segT current_seg = now_seg; 3442 subsegT current_subseg = now_subseg; 3443 3444 subseg_set (bss_section, 1); /* switch to bss */ 3445 3446 if (align) 3447 frag_align (align, 0, 0); /* do alignment */ 3448 3449 /* detach from old frag */ 3450 if (S_GET_SEGMENT(symbolP) == bss_section) 3451 symbol_get_frag (symbolP)->fr_symbol = NULL; 3452 3453 symbol_set_frag (symbolP, frag_now); 3454 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP, 3455 (offsetT) size, (char *)0); 3456 *pfrag = 0; 3457 3458 S_SET_SEGMENT (symbolP, bss_section); 3459 3460 subseg_set (current_seg, current_subseg); 3461 3462#ifdef OBJ_ELF 3463 S_SET_SIZE (symbolP, size); 3464#endif 3465 } 3466 } 3467 else 3468 { 3469 as_warn("Ignoring attempt to re-define symbol %s", 3470 S_GET_NAME (symbolP)); 3471 } /* if not redefining */ 3472 3473 demand_empty_rest_of_line (); 3474} 3475 3476static void 3477s_common (ignore) 3478 int ignore; 3479{ 3480 char *name; 3481 char c; 3482 char *p; 3483 int temp, size; 3484 symbolS *symbolP; 3485 3486 name = input_line_pointer; 3487 c = get_symbol_end (); 3488 /* just after name is now '\0' */ 3489 p = input_line_pointer; 3490 *p = c; 3491 SKIP_WHITESPACE (); 3492 if (*input_line_pointer != ',') 3493 { 3494 as_bad (_("Expected comma after symbol-name")); 3495 ignore_rest_of_line (); 3496 return; 3497 } 3498 input_line_pointer++; /* skip ',' */ 3499 if ((temp = get_absolute_expression ()) < 0) 3500 { 3501 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp); 3502 ignore_rest_of_line (); 3503 return; 3504 } 3505 size = temp; 3506 *p = 0; 3507 symbolP = symbol_find_or_make (name); 3508 *p = c; 3509 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 3510 { 3511 as_bad (_("Ignoring attempt to re-define symbol")); 3512 ignore_rest_of_line (); 3513 return; 3514 } 3515 if (S_GET_VALUE (symbolP) != 0) 3516 { 3517 if (S_GET_VALUE (symbolP) != (valueT) size) 3518 { 3519 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 3520 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 3521 } 3522 } 3523 else 3524 { 3525#ifndef OBJ_ELF 3526 S_SET_VALUE (symbolP, (valueT) size); 3527 S_SET_EXTERNAL (symbolP); 3528#endif 3529 } 3530 know (symbol_get_frag (symbolP) == &zero_address_frag); 3531 if (*input_line_pointer != ',') 3532 { 3533 as_bad (_("Expected comma after common length")); 3534 ignore_rest_of_line (); 3535 return; 3536 } 3537 input_line_pointer++; 3538 SKIP_WHITESPACE (); 3539 if (*input_line_pointer != '"') 3540 { 3541 temp = get_absolute_expression (); 3542 3543#ifndef OBJ_ELF 3544 if (temp > max_alignment) 3545 { 3546 temp = max_alignment; 3547 as_warn (_("alignment too large; assuming %d"), temp); 3548 } 3549#endif 3550 3551 if (temp < 0) 3552 { 3553 as_bad (_("negative alignment")); 3554 ignore_rest_of_line (); 3555 return; 3556 } 3557 3558#ifdef OBJ_ELF 3559 if (symbol_get_obj (symbolP)->local) 3560 { 3561 segT old_sec; 3562 int old_subsec; 3563 char *p; 3564 int align; 3565 3566 old_sec = now_seg; 3567 old_subsec = now_subseg; 3568 3569 if (temp == 0) 3570 align = 0; 3571 else 3572 align = log2 (temp); 3573 3574 if (align < 0) 3575 { 3576 as_bad (_("alignment not a power of 2")); 3577 ignore_rest_of_line (); 3578 return; 3579 } 3580 3581 record_alignment (bss_section, align); 3582 subseg_set (bss_section, 0); 3583 if (align) 3584 frag_align (align, 0, 0); 3585 if (S_GET_SEGMENT (symbolP) == bss_section) 3586 symbol_get_frag (symbolP)->fr_symbol = 0; 3587 symbol_set_frag (symbolP, frag_now); 3588 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3589 (offsetT) size, (char *) 0); 3590 *p = 0; 3591 S_SET_SEGMENT (symbolP, bss_section); 3592 S_CLEAR_EXTERNAL (symbolP); 3593 S_SET_SIZE (symbolP, size); 3594 subseg_set (old_sec, old_subsec); 3595 } 3596 else 3597#endif /* OBJ_ELF */ 3598 { 3599 allocate_common: 3600 S_SET_VALUE (symbolP, (valueT) size); 3601#ifdef OBJ_ELF 3602 S_SET_ALIGN (symbolP, temp); 3603 S_SET_SIZE (symbolP, size); 3604#endif 3605 S_SET_EXTERNAL (symbolP); 3606 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 3607 } 3608 } 3609 else 3610 { 3611 input_line_pointer++; 3612 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 3613 if (*input_line_pointer == '.') 3614 input_line_pointer++; 3615 /* @@ Some say data, some say bss. */ 3616 if (strncmp (input_line_pointer, "bss\"", 4) 3617 && strncmp (input_line_pointer, "data\"", 5)) 3618 { 3619 while (*--input_line_pointer != '"') 3620 ; 3621 input_line_pointer--; 3622 goto bad_common_segment; 3623 } 3624 while (*input_line_pointer++ != '"') 3625 ; 3626 goto allocate_common; 3627 } 3628 3629#ifdef BFD_ASSEMBLER 3630 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 3631#endif 3632 3633 demand_empty_rest_of_line (); 3634 return; 3635 3636 { 3637 bad_common_segment: 3638 p = input_line_pointer; 3639 while (*p && *p != '\n') 3640 p++; 3641 c = *p; 3642 *p = '\0'; 3643 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 3644 *p = c; 3645 input_line_pointer = p; 3646 ignore_rest_of_line (); 3647 return; 3648 } 3649} 3650 3651/* Handle the .empty pseudo-op. This supresses the warnings about 3652 invalid delay slot usage. */ 3653 3654static void 3655s_empty (ignore) 3656 int ignore; 3657{ 3658 /* The easy way to implement is to just forget about the last 3659 instruction. */ 3660 last_insn = NULL; 3661} 3662 3663static void 3664s_seg (ignore) 3665 int ignore; 3666{ 3667 3668 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 3669 { 3670 input_line_pointer += 6; 3671 s_text (0); 3672 return; 3673 } 3674 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 3675 { 3676 input_line_pointer += 6; 3677 s_data (0); 3678 return; 3679 } 3680 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 3681 { 3682 input_line_pointer += 7; 3683 s_data1 (); 3684 return; 3685 } 3686 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 3687 { 3688 input_line_pointer += 5; 3689 /* We only support 2 segments -- text and data -- for now, so 3690 things in the "bss segment" will have to go into data for now. 3691 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 3692 subseg_set (data_section, 255); /* FIXME-SOMEDAY */ 3693 return; 3694 } 3695 as_bad (_("Unknown segment type")); 3696 demand_empty_rest_of_line (); 3697} 3698 3699static void 3700s_data1 () 3701{ 3702 subseg_set (data_section, 1); 3703 demand_empty_rest_of_line (); 3704} 3705 3706static void 3707s_proc (ignore) 3708 int ignore; 3709{ 3710 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 3711 { 3712 ++input_line_pointer; 3713 } 3714 ++input_line_pointer; 3715} 3716 3717/* This static variable is set by s_uacons to tell sparc_cons_align 3718 that the expession does not need to be aligned. */ 3719 3720static int sparc_no_align_cons = 0; 3721 3722/* This handles the unaligned space allocation pseudo-ops, such as 3723 .uaword. .uaword is just like .word, but the value does not need 3724 to be aligned. */ 3725 3726static void 3727s_uacons (bytes) 3728 int bytes; 3729{ 3730 /* Tell sparc_cons_align not to align this value. */ 3731 sparc_no_align_cons = 1; 3732 cons (bytes); 3733} 3734 3735/* This handles the native word allocation pseudo-op .nword. 3736 For sparc_arch_size 32 it is equivalent to .word, for 3737 sparc_arch_size 64 it is equivalent to .xword. */ 3738 3739static void 3740s_ncons (bytes) 3741 int bytes; 3742{ 3743 cons (sparc_arch_size == 32 ? 4 : 8); 3744} 3745 3746#ifdef OBJ_ELF 3747/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 3748 global register. 3749 The syntax is: 3750 3751 .register %g[2367],{#scratch|symbolname|#ignore} 3752 */ 3753 3754static void 3755s_register (ignore) 3756 int ignore; 3757{ 3758 char c; 3759 int reg; 3760 int flags; 3761 const char *regname; 3762 3763 if (input_line_pointer[0] != '%' 3764 || input_line_pointer[1] != 'g' 3765 || ((input_line_pointer[2] & ~1) != '2' 3766 && (input_line_pointer[2] & ~1) != '6') 3767 || input_line_pointer[3] != ',') 3768 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 3769 reg = input_line_pointer[2] - '0'; 3770 input_line_pointer += 4; 3771 3772 if (*input_line_pointer == '#') 3773 { 3774 ++input_line_pointer; 3775 regname = input_line_pointer; 3776 c = get_symbol_end (); 3777 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 3778 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 3779 if (regname [0] == 'i') 3780 regname = NULL; 3781 else 3782 regname = ""; 3783 } 3784 else 3785 { 3786 regname = input_line_pointer; 3787 c = get_symbol_end (); 3788 } 3789 if (sparc_arch_size == 64) 3790 { 3791 if (globals [reg]) 3792 { 3793 if ((regname && globals [reg] != (symbolS *)1 3794 && strcmp (S_GET_NAME (globals [reg]), regname)) 3795 || ((regname != NULL) ^ (globals [reg] != (symbolS *)1))) 3796 as_bad (_("redefinition of global register")); 3797 } 3798 else 3799 { 3800 if (regname == NULL) 3801 globals [reg] = (symbolS *)1; 3802 else 3803 { 3804 if (*regname) 3805 { 3806 if (symbol_find (regname)) 3807 as_bad (_("Register symbol %s already defined."), 3808 regname); 3809 } 3810 globals [reg] = symbol_make (regname); 3811 flags = symbol_get_bfdsym (globals [reg])->flags; 3812 if (! *regname) 3813 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 3814 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 3815 flags |= BSF_GLOBAL; 3816 symbol_get_bfdsym (globals [reg])->flags = flags; 3817 S_SET_VALUE (globals [reg], (valueT)reg); 3818 S_SET_ALIGN (globals [reg], reg); 3819 S_SET_SIZE (globals [reg], 0); 3820 /* Although we actually want undefined_section here, 3821 we have to use absolute_section, because otherwise 3822 generic as code will make it a COM section. 3823 We fix this up in sparc_adjust_symtab. */ 3824 S_SET_SEGMENT (globals [reg], absolute_section); 3825 S_SET_OTHER (globals [reg], 0); 3826 elf_symbol (symbol_get_bfdsym (globals [reg])) 3827 ->internal_elf_sym.st_info = 3828 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 3829 elf_symbol (symbol_get_bfdsym (globals [reg])) 3830 ->internal_elf_sym.st_shndx = SHN_UNDEF; 3831 } 3832 } 3833 } 3834 3835 *input_line_pointer = c; 3836 3837 demand_empty_rest_of_line (); 3838} 3839 3840/* Adjust the symbol table. We set undefined sections for STT_REGISTER 3841 symbols which need it. */ 3842 3843void 3844sparc_adjust_symtab () 3845{ 3846 symbolS *sym; 3847 3848 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 3849 { 3850 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 3851 ->internal_elf_sym.st_info) != STT_REGISTER) 3852 continue; 3853 3854 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 3855 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 3856 continue; 3857 3858 S_SET_SEGMENT (sym, undefined_section); 3859 } 3860} 3861#endif 3862 3863/* If the --enforce-aligned-data option is used, we require .word, 3864 et. al., to be aligned correctly. We do it by setting up an 3865 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 3866 no unexpected alignment was introduced. 3867 3868 The SunOS and Solaris native assemblers enforce aligned data by 3869 default. We don't want to do that, because gcc can deliberately 3870 generate misaligned data if the packed attribute is used. Instead, 3871 we permit misaligned data by default, and permit the user to set an 3872 option to check for it. */ 3873 3874void 3875sparc_cons_align (nbytes) 3876 int nbytes; 3877{ 3878 int nalign; 3879 char *p; 3880 3881 /* Only do this if we are enforcing aligned data. */ 3882 if (! enforce_aligned_data) 3883 return; 3884 3885 if (sparc_no_align_cons) 3886 { 3887 /* This is an unaligned pseudo-op. */ 3888 sparc_no_align_cons = 0; 3889 return; 3890 } 3891 3892 nalign = log2 (nbytes); 3893 if (nalign == 0) 3894 return; 3895 3896 assert (nalign > 0); 3897 3898 if (now_seg == absolute_section) 3899 { 3900 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 3901 as_bad (_("misaligned data")); 3902 return; 3903 } 3904 3905 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0, 3906 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 3907 3908 record_alignment (now_seg, nalign); 3909} 3910 3911/* This is where we do the unexpected alignment check. 3912 This is called from HANDLE_ALIGN in tc-sparc.h. */ 3913 3914void 3915sparc_handle_align (fragp) 3916 fragS *fragp; 3917{ 3918 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype 3919 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0) 3920 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 3921 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024) 3922 { 3923 int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 3924 3925 if (count >= 4 3926 && !(count & 3) 3927 && count <= 1024 3928 && !((long)(fragp->fr_literal + fragp->fr_fix) & 3)) 3929 { 3930 unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix); 3931 int i; 3932 3933 for (i = 0; i < count; i += 4, p++) 3934 if (INSN_BIG_ENDIAN) 3935 number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */ 3936 else 3937 number_to_chars_littleendian ((char *)p, 0x10000000, 4); 3938 3939 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 3940 { 3941 char *waddr = &fragp->fr_literal[fragp->fr_fix]; 3942 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 3943 if (INSN_BIG_ENDIAN) 3944 number_to_chars_bigendian (waddr, wval, 4); 3945 else 3946 number_to_chars_littleendian (waddr, wval, 4); 3947 } 3948 fragp->fr_var = count; 3949 } 3950 } 3951} 3952 3953#ifdef OBJ_ELF 3954/* Some special processing for a Sparc ELF file. */ 3955 3956void 3957sparc_elf_final_processing () 3958{ 3959 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 3960 sort of BFD interface for this. */ 3961 if (sparc_arch_size == 64) 3962 { 3963 switch (sparc_memory_model) 3964 { 3965 case MM_RMO: 3966 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 3967 break; 3968 case MM_PSO: 3969 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 3970 break; 3971 default: 3972 break; 3973 } 3974 } 3975 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 3976 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 3977 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 3978 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 3979} 3980#endif 3981 3982/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 3983 reloc for a cons. We could use the definition there, except that 3984 we want to handle little endian relocs specially. */ 3985 3986void 3987cons_fix_new_sparc (frag, where, nbytes, exp) 3988 fragS *frag; 3989 int where; 3990 unsigned int nbytes; 3991 expressionS *exp; 3992{ 3993 bfd_reloc_code_real_type r; 3994 3995 r = (nbytes == 1 ? BFD_RELOC_8 : 3996 (nbytes == 2 ? BFD_RELOC_16 : 3997 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 3998 3999 if (target_little_endian_data && nbytes == 4 4000 && now_seg->flags & SEC_ALLOC) 4001 r = BFD_RELOC_SPARC_REV32; 4002 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4003} 4004 4005#ifdef OBJ_ELF 4006int 4007elf32_sparc_force_relocation (fixp) 4008 struct fix *fixp; 4009{ 4010 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4011 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4012 return 1; 4013 4014 return 0; 4015} 4016#endif 4017 4018