tc-sparc.c revision 225736
1/* tc-sparc.c -- Assemble for the SPARC 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 4 Free Software Foundation, Inc. 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public 18 License along with GAS; see the file COPYING. If not, write 19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22#include "as.h" 23#include "safe-ctype.h" 24#include "subsegs.h" 25 26#include "opcode/sparc.h" 27#include "dw2gencfi.h" 28 29#ifdef OBJ_ELF 30#include "elf/sparc.h" 31#include "dwarf2dbg.h" 32#endif 33 34/* Some ancient Sun C compilers would not take such hex constants as 35 unsigned, and would end up sign-extending them to form an offsetT, 36 so use these constants instead. */ 37#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 38#define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 39 40static struct sparc_arch *lookup_arch PARAMS ((char *)); 41static void init_default_arch PARAMS ((void)); 42static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); 43static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 44static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); 45static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 46static int sparc_ffs PARAMS ((unsigned int)); 47static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); 48static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); 49static void synthetize_setx PARAMS ((const struct sparc_opcode *)); 50static bfd_vma BSR PARAMS ((bfd_vma, int)); 51static int cmp_reg_entry PARAMS ((const PTR, const PTR)); 52static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); 53static int parse_const_expr_arg PARAMS ((char **, int *)); 54static int get_expression PARAMS ((char *str)); 55 56/* Default architecture. */ 57/* ??? The default value should be V8, but sparclite support was added 58 by making it the default. GCC now passes -Asparclite, so maybe sometime in 59 the future we can set this to V8. */ 60#ifndef DEFAULT_ARCH 61#define DEFAULT_ARCH "sparclite" 62#endif 63static char *default_arch = DEFAULT_ARCH; 64 65/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 66 have been set. */ 67static int default_init_p; 68 69/* Current architecture. We don't bump up unless necessary. */ 70static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 71 72/* The maximum architecture level we can bump up to. 73 In a 32 bit environment, don't allow bumping up to v9 by default. 74 The native assembler works this way. The user is required to pass 75 an explicit argument before we'll create v9 object files. However, if 76 we don't see any v9 insns, a v8plus object file is not created. */ 77static enum sparc_opcode_arch_val max_architecture; 78 79/* Either 32 or 64, selects file format. */ 80static int sparc_arch_size; 81/* Initial (default) value, recorded separately in case a user option 82 changes the value before md_show_usage is called. */ 83static int default_arch_size; 84 85#ifdef OBJ_ELF 86/* The currently selected v9 memory model. Currently only used for 87 ELF. */ 88static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 89#endif 90 91static int architecture_requested; 92static int warn_on_bump; 93 94/* If warn_on_bump and the needed architecture is higher than this 95 architecture, issue a warning. */ 96static enum sparc_opcode_arch_val warn_after_architecture; 97 98/* Non-zero if as should generate error if an undeclared g[23] register 99 has been used in -64. */ 100static int no_undeclared_regs; 101 102/* Non-zero if we should try to relax jumps and calls. */ 103static int sparc_relax; 104 105/* Non-zero if we are generating PIC code. */ 106int sparc_pic_code; 107 108/* Non-zero if we should give an error when misaligned data is seen. */ 109static int enforce_aligned_data; 110 111extern int target_big_endian; 112 113static int target_little_endian_data; 114 115/* Symbols for global registers on v9. */ 116static symbolS *globals[8]; 117 118/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 119int sparc_cie_data_alignment; 120 121/* V9 and 86x have big and little endian data, but instructions are always big 122 endian. The sparclet has bi-endian support but both data and insns have 123 the same endianness. Global `target_big_endian' is used for data. 124 The following macro is used for instructions. */ 125#ifndef INSN_BIG_ENDIAN 126#define INSN_BIG_ENDIAN (target_big_endian \ 127 || default_arch_type == sparc86x \ 128 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 129#endif 130 131/* Handle of the OPCODE hash table. */ 132static struct hash_control *op_hash; 133 134static int mylog2 PARAMS ((int)); 135static void s_data1 PARAMS ((void)); 136static void s_seg PARAMS ((int)); 137static void s_proc PARAMS ((int)); 138static void s_reserve PARAMS ((int)); 139static void s_common PARAMS ((int)); 140static void s_empty PARAMS ((int)); 141static void s_uacons PARAMS ((int)); 142static void s_ncons PARAMS ((int)); 143#ifdef OBJ_ELF 144static void s_register PARAMS ((int)); 145#endif 146 147const pseudo_typeS md_pseudo_table[] = 148{ 149 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 150 {"common", s_common, 0}, 151 {"empty", s_empty, 0}, 152 {"global", s_globl, 0}, 153 {"half", cons, 2}, 154 {"nword", s_ncons, 0}, 155 {"optim", s_ignore, 0}, 156 {"proc", s_proc, 0}, 157 {"reserve", s_reserve, 0}, 158 {"seg", s_seg, 0}, 159 {"skip", s_space, 0}, 160 {"word", cons, 4}, 161 {"xword", cons, 8}, 162 {"uahalf", s_uacons, 2}, 163 {"uaword", s_uacons, 4}, 164 {"uaxword", s_uacons, 8}, 165#ifdef OBJ_ELF 166 /* These are specific to sparc/svr4. */ 167 {"2byte", s_uacons, 2}, 168 {"4byte", s_uacons, 4}, 169 {"8byte", s_uacons, 8}, 170 {"register", s_register, 0}, 171#endif 172 {NULL, 0, 0}, 173}; 174 175/* This array holds the chars that always start a comment. If the 176 pre-processor is disabled, these aren't very useful. */ 177const char comment_chars[] = "!"; /* JF removed '|' from 178 comment_chars. */ 179 180/* This array holds the chars that only start a comment at the beginning of 181 a line. If the line seems to have the form '# 123 filename' 182 .line and .file directives will appear in the pre-processed output. */ 183/* Note that input_file.c hand checks for '#' at the beginning of the 184 first line of the input file. This is because the compiler outputs 185 #NO_APP at the beginning of its output. */ 186/* Also note that comments started like this one will always 187 work if '/' isn't otherwise defined. */ 188const char line_comment_chars[] = "#"; 189 190const char line_separator_chars[] = ";"; 191 192/* Chars that can be used to separate mant from exp in floating point 193 nums. */ 194const char EXP_CHARS[] = "eE"; 195 196/* Chars that mean this number is a floating point constant. 197 As in 0f12.456 198 or 0d1.2345e12 */ 199const char FLT_CHARS[] = "rRsSfFdDxXpP"; 200 201/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 202 changed in read.c. Ideally it shouldn't have to know about it at all, 203 but nothing is ideal around here. */ 204 205#define isoctal(c) ((unsigned) ((c) - '0') < 8) 206 207struct sparc_it 208 { 209 char *error; 210 unsigned long opcode; 211 struct nlist *nlistp; 212 expressionS exp; 213 expressionS exp2; 214 int pcrel; 215 bfd_reloc_code_real_type reloc; 216 }; 217 218struct sparc_it the_insn, set_insn; 219 220static void output_insn 221 PARAMS ((const struct sparc_opcode *, struct sparc_it *)); 222 223/* Table of arguments to -A. 224 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 225 for this use. That table is for opcodes only. This table is for opcodes 226 and file formats. */ 227 228enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 229 v8plusa, v9, v9a, v9b, v9_64}; 230 231static struct sparc_arch { 232 char *name; 233 char *opcode_arch; 234 enum sparc_arch_types arch_type; 235 /* Default word size, as specified during configuration. 236 A value of zero means can't be used to specify default architecture. */ 237 int default_arch_size; 238 /* Allowable arg to -A? */ 239 int user_option_p; 240} sparc_arch_table[] = { 241 { "v6", "v6", v6, 0, 1 }, 242 { "v7", "v7", v7, 0, 1 }, 243 { "v8", "v8", v8, 32, 1 }, 244 { "sparclet", "sparclet", sparclet, 32, 1 }, 245 { "sparclite", "sparclite", sparclite, 32, 1 }, 246 { "sparc86x", "sparclite", sparc86x, 32, 1 }, 247 { "v8plus", "v9", v9, 0, 1 }, 248 { "v8plusa", "v9a", v9, 0, 1 }, 249 { "v8plusb", "v9b", v9, 0, 1 }, 250 { "v9", "v9", v9, 0, 1 }, 251 { "v9a", "v9a", v9, 0, 1 }, 252 { "v9b", "v9b", v9, 0, 1 }, 253 /* This exists to allow configure.in/Makefile.in to pass one 254 value to specify both the default machine and default word size. */ 255 { "v9-64", "v9", v9, 64, 0 }, 256 { NULL, NULL, v8, 0, 0 } 257}; 258 259/* Variant of default_arch */ 260static enum sparc_arch_types default_arch_type; 261 262static struct sparc_arch * 263lookup_arch (name) 264 char *name; 265{ 266 struct sparc_arch *sa; 267 268 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 269 if (strcmp (sa->name, name) == 0) 270 break; 271 if (sa->name == NULL) 272 return NULL; 273 return sa; 274} 275 276/* Initialize the default opcode arch and word size from the default 277 architecture name. */ 278 279static void 280init_default_arch () 281{ 282 struct sparc_arch *sa = lookup_arch (default_arch); 283 284 if (sa == NULL 285 || sa->default_arch_size == 0) 286 as_fatal (_("Invalid default architecture, broken assembler.")); 287 288 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 289 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 290 as_fatal (_("Bad opcode table, broken assembler.")); 291 default_arch_size = sparc_arch_size = sa->default_arch_size; 292 default_init_p = 1; 293 default_arch_type = sa->arch_type; 294} 295 296/* Called by TARGET_FORMAT. */ 297 298const char * 299sparc_target_format () 300{ 301 /* We don't get a chance to initialize anything before we're called, 302 so handle that now. */ 303 if (! default_init_p) 304 init_default_arch (); 305 306#ifdef OBJ_AOUT 307#ifdef TE_NetBSD 308 return "a.out-sparc-netbsd"; 309#else 310#ifdef TE_SPARCAOUT 311 if (target_big_endian) 312 return "a.out-sunos-big"; 313 else if (default_arch_type == sparc86x && target_little_endian_data) 314 return "a.out-sunos-big"; 315 else 316 return "a.out-sparc-little"; 317#else 318 return "a.out-sunos-big"; 319#endif 320#endif 321#endif 322 323#ifdef OBJ_BOUT 324 return "b.out.big"; 325#endif 326 327#ifdef OBJ_COFF 328#ifdef TE_LYNX 329 return "coff-sparc-lynx"; 330#else 331 return "coff-sparc"; 332#endif 333#endif 334 335#ifdef TE_VXWORKS 336 return "elf32-sparc-vxworks"; 337#endif 338 339#ifdef OBJ_ELF 340 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; 341#endif 342 343 abort (); 344} 345 346/* md_parse_option 347 * Invocation line includes a switch not recognized by the base assembler. 348 * See if it's a processor-specific option. These are: 349 * 350 * -bump 351 * Warn on architecture bumps. See also -A. 352 * 353 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 354 * Standard 32 bit architectures. 355 * -Av9, -Av9a, -Av9b 356 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 357 * This used to only mean 64 bits, but properly specifying it 358 * complicated gcc's ASM_SPECs, so now opcode selection is 359 * specified orthogonally to word size (except when specifying 360 * the default, but that is an internal implementation detail). 361 * -Av8plus, -Av8plusa, -Av8plusb 362 * Same as -Av9{,a,b}. 363 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 364 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 365 * assembler. 366 * -xarch=v9, -xarch=v9a, -xarch=v9b 367 * Same as -Av9{,a,b} -64, for compatibility with Sun's 368 * assembler. 369 * 370 * Select the architecture and possibly the file format. 371 * Instructions or features not supported by the selected 372 * architecture cause fatal errors. 373 * 374 * The default is to start at v6, and bump the architecture up 375 * whenever an instruction is seen at a higher level. In 32 bit 376 * environments, v9 is not bumped up to, the user must pass 377 * -Av8plus{,a,b}. 378 * 379 * If -bump is specified, a warning is printing when bumping to 380 * higher levels. 381 * 382 * If an architecture is specified, all instructions must match 383 * that architecture. Any higher level instructions are flagged 384 * as errors. Note that in the 32 bit environment specifying 385 * -Av8plus does not automatically create a v8plus object file, a 386 * v9 insn must be seen. 387 * 388 * If both an architecture and -bump are specified, the 389 * architecture starts at the specified level, but bumps are 390 * warnings. Note that we can't set `current_architecture' to 391 * the requested level in this case: in the 32 bit environment, 392 * we still must avoid creating v8plus object files unless v9 393 * insns are seen. 394 * 395 * Note: 396 * Bumping between incompatible architectures is always an 397 * error. For example, from sparclite to v9. 398 */ 399 400#ifdef OBJ_ELF 401const char *md_shortopts = "A:K:VQ:sq"; 402#else 403#ifdef OBJ_AOUT 404const char *md_shortopts = "A:k"; 405#else 406const char *md_shortopts = "A:"; 407#endif 408#endif 409struct option md_longopts[] = { 410#define OPTION_BUMP (OPTION_MD_BASE) 411 {"bump", no_argument, NULL, OPTION_BUMP}, 412#define OPTION_SPARC (OPTION_MD_BASE + 1) 413 {"sparc", no_argument, NULL, OPTION_SPARC}, 414#define OPTION_XARCH (OPTION_MD_BASE + 2) 415 {"xarch", required_argument, NULL, OPTION_XARCH}, 416#ifdef OBJ_ELF 417#define OPTION_32 (OPTION_MD_BASE + 3) 418 {"32", no_argument, NULL, OPTION_32}, 419#define OPTION_64 (OPTION_MD_BASE + 4) 420 {"64", no_argument, NULL, OPTION_64}, 421#define OPTION_TSO (OPTION_MD_BASE + 5) 422 {"TSO", no_argument, NULL, OPTION_TSO}, 423#define OPTION_PSO (OPTION_MD_BASE + 6) 424 {"PSO", no_argument, NULL, OPTION_PSO}, 425#define OPTION_RMO (OPTION_MD_BASE + 7) 426 {"RMO", no_argument, NULL, OPTION_RMO}, 427#endif 428#ifdef SPARC_BIENDIAN 429#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 430 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 431#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 432 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 433#endif 434#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 435 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 436#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 437 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 438#ifdef OBJ_ELF 439#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 440 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 441#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 442 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 443#endif 444#define OPTION_RELAX (OPTION_MD_BASE + 14) 445 {"relax", no_argument, NULL, OPTION_RELAX}, 446#define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 447 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 448 {NULL, no_argument, NULL, 0} 449}; 450 451size_t md_longopts_size = sizeof (md_longopts); 452 453int 454md_parse_option (c, arg) 455 int c; 456 char *arg; 457{ 458 /* We don't get a chance to initialize anything before we're called, 459 so handle that now. */ 460 if (! default_init_p) 461 init_default_arch (); 462 463 switch (c) 464 { 465 case OPTION_BUMP: 466 warn_on_bump = 1; 467 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 468 break; 469 470 case OPTION_XARCH: 471#ifdef OBJ_ELF 472 if (strncmp (arg, "v9", 2) != 0) 473 md_parse_option (OPTION_32, NULL); 474 else 475 md_parse_option (OPTION_64, NULL); 476#endif 477 /* Fall through. */ 478 479 case 'A': 480 { 481 struct sparc_arch *sa; 482 enum sparc_opcode_arch_val opcode_arch; 483 484 sa = lookup_arch (arg); 485 if (sa == NULL 486 || ! sa->user_option_p) 487 { 488 if (c == OPTION_XARCH) 489 as_bad (_("invalid architecture -xarch=%s"), arg); 490 else 491 as_bad (_("invalid architecture -A%s"), arg); 492 return 0; 493 } 494 495 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 496 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 497 as_fatal (_("Bad opcode table, broken assembler.")); 498 499 max_architecture = opcode_arch; 500 architecture_requested = 1; 501 } 502 break; 503 504 case OPTION_SPARC: 505 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 506 break; 507 508 case OPTION_ENFORCE_ALIGNED_DATA: 509 enforce_aligned_data = 1; 510 break; 511 512#ifdef SPARC_BIENDIAN 513 case OPTION_LITTLE_ENDIAN: 514 target_big_endian = 0; 515 if (default_arch_type != sparclet) 516 as_fatal ("This target does not support -EL"); 517 break; 518 case OPTION_LITTLE_ENDIAN_DATA: 519 target_little_endian_data = 1; 520 target_big_endian = 0; 521 if (default_arch_type != sparc86x 522 && default_arch_type != v9) 523 as_fatal ("This target does not support --little-endian-data"); 524 break; 525 case OPTION_BIG_ENDIAN: 526 target_big_endian = 1; 527 break; 528#endif 529 530#ifdef OBJ_AOUT 531 case 'k': 532 sparc_pic_code = 1; 533 break; 534#endif 535 536#ifdef OBJ_ELF 537 case OPTION_32: 538 case OPTION_64: 539 { 540 const char **list, **l; 541 542 sparc_arch_size = c == OPTION_32 ? 32 : 64; 543 list = bfd_target_list (); 544 for (l = list; *l != NULL; l++) 545 { 546 if (sparc_arch_size == 32) 547 { 548 if (CONST_STRNEQ (*l, "elf32-sparc")) 549 break; 550 } 551 else 552 { 553 if (CONST_STRNEQ (*l, "elf64-sparc")) 554 break; 555 } 556 } 557 if (*l == NULL) 558 as_fatal (_("No compiled in support for %d bit object file format"), 559 sparc_arch_size); 560 free (list); 561 } 562 break; 563 564 case OPTION_TSO: 565 sparc_memory_model = MM_TSO; 566 break; 567 568 case OPTION_PSO: 569 sparc_memory_model = MM_PSO; 570 break; 571 572 case OPTION_RMO: 573 sparc_memory_model = MM_RMO; 574 break; 575 576 case 'V': 577 print_version_id (); 578 break; 579 580 case 'Q': 581 /* Qy - do emit .comment 582 Qn - do not emit .comment. */ 583 break; 584 585 case 's': 586 /* Use .stab instead of .stab.excl. */ 587 break; 588 589 case 'q': 590 /* quick -- Native assembler does fewer checks. */ 591 break; 592 593 case 'K': 594 if (strcmp (arg, "PIC") != 0) 595 as_warn (_("Unrecognized option following -K")); 596 else 597 sparc_pic_code = 1; 598 break; 599 600 case OPTION_NO_UNDECLARED_REGS: 601 no_undeclared_regs = 1; 602 break; 603 604 case OPTION_UNDECLARED_REGS: 605 no_undeclared_regs = 0; 606 break; 607#endif 608 609 case OPTION_RELAX: 610 sparc_relax = 1; 611 break; 612 613 case OPTION_NO_RELAX: 614 sparc_relax = 0; 615 break; 616 617 default: 618 return 0; 619 } 620 621 return 1; 622} 623 624void 625md_show_usage (stream) 626 FILE *stream; 627{ 628 const struct sparc_arch *arch; 629 int column; 630 631 /* We don't get a chance to initialize anything before we're called, 632 so handle that now. */ 633 if (! default_init_p) 634 init_default_arch (); 635 636 fprintf (stream, _("SPARC options:\n")); 637 column = 0; 638 for (arch = &sparc_arch_table[0]; arch->name; arch++) 639 { 640 if (!arch->user_option_p) 641 continue; 642 if (arch != &sparc_arch_table[0]) 643 fprintf (stream, " | "); 644 if (column + strlen (arch->name) > 70) 645 { 646 column = 0; 647 fputc ('\n', stream); 648 } 649 column += 5 + 2 + strlen (arch->name); 650 fprintf (stream, "-A%s", arch->name); 651 } 652 for (arch = &sparc_arch_table[0]; arch->name; arch++) 653 { 654 if (!arch->user_option_p) 655 continue; 656 fprintf (stream, " | "); 657 if (column + strlen (arch->name) > 65) 658 { 659 column = 0; 660 fputc ('\n', stream); 661 } 662 column += 5 + 7 + strlen (arch->name); 663 fprintf (stream, "-xarch=%s", arch->name); 664 } 665 fprintf (stream, _("\n\ 666 specify variant of SPARC architecture\n\ 667-bump warn when assembler switches architectures\n\ 668-sparc ignored\n\ 669--enforce-aligned-data force .long, etc., to be aligned correctly\n\ 670-relax relax jumps and branches (default)\n\ 671-no-relax avoid changing any jumps and branches\n")); 672#ifdef OBJ_AOUT 673 fprintf (stream, _("\ 674-k generate PIC\n")); 675#endif 676#ifdef OBJ_ELF 677 fprintf (stream, _("\ 678-32 create 32 bit object file\n\ 679-64 create 64 bit object file\n")); 680 fprintf (stream, _("\ 681 [default is %d]\n"), default_arch_size); 682 fprintf (stream, _("\ 683-TSO use Total Store Ordering\n\ 684-PSO use Partial Store Ordering\n\ 685-RMO use Relaxed Memory Ordering\n")); 686 fprintf (stream, _("\ 687 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 688 fprintf (stream, _("\ 689-KPIC generate PIC\n\ 690-V print assembler version number\n\ 691-undeclared-regs ignore application global register usage without\n\ 692 appropriate .register directive (default)\n\ 693-no-undeclared-regs force error on application global register usage\n\ 694 without appropriate .register directive\n\ 695-q ignored\n\ 696-Qy, -Qn ignored\n\ 697-s ignored\n")); 698#endif 699#ifdef SPARC_BIENDIAN 700 fprintf (stream, _("\ 701-EL generate code for a little endian machine\n\ 702-EB generate code for a big endian machine\n\ 703--little-endian-data generate code for a machine having big endian\n\ 704 instructions and little endian data.\n")); 705#endif 706} 707 708/* Native operand size opcode translation. */ 709struct 710 { 711 char *name; 712 char *name32; 713 char *name64; 714 } native_op_table[] = 715{ 716 {"ldn", "ld", "ldx"}, 717 {"ldna", "lda", "ldxa"}, 718 {"stn", "st", "stx"}, 719 {"stna", "sta", "stxa"}, 720 {"slln", "sll", "sllx"}, 721 {"srln", "srl", "srlx"}, 722 {"sran", "sra", "srax"}, 723 {"casn", "cas", "casx"}, 724 {"casna", "casa", "casxa"}, 725 {"clrn", "clr", "clrx"}, 726 {NULL, NULL, NULL}, 727}; 728 729/* sparc64 privileged and hyperprivileged registers. */ 730 731struct priv_reg_entry 732{ 733 char *name; 734 int regnum; 735}; 736 737struct priv_reg_entry priv_reg_table[] = 738{ 739 {"tpc", 0}, 740 {"tnpc", 1}, 741 {"tstate", 2}, 742 {"tt", 3}, 743 {"tick", 4}, 744 {"tba", 5}, 745 {"pstate", 6}, 746 {"tl", 7}, 747 {"pil", 8}, 748 {"cwp", 9}, 749 {"cansave", 10}, 750 {"canrestore", 11}, 751 {"cleanwin", 12}, 752 {"otherwin", 13}, 753 {"wstate", 14}, 754 {"fq", 15}, 755 {"gl", 16}, 756 {"ver", 31}, 757 {"", -1}, /* End marker. */ 758}; 759 760struct priv_reg_entry hpriv_reg_table[] = 761{ 762 {"hpstate", 0}, 763 {"htstate", 1}, 764 {"hintp", 3}, 765 {"htba", 5}, 766 {"hver", 6}, 767 {"hstick_cmpr", 31}, 768 {"", -1}, /* End marker. */ 769}; 770 771/* v9a specific asrs. */ 772 773struct priv_reg_entry v9a_asr_table[] = 774{ 775 {"tick_cmpr", 23}, 776 {"sys_tick_cmpr", 25}, 777 {"sys_tick", 24}, 778 {"softint", 22}, 779 {"set_softint", 20}, 780 {"pic", 17}, 781 {"pcr", 16}, 782 {"gsr", 19}, 783 {"dcr", 18}, 784 {"clear_softint", 21}, 785 {"", -1}, /* End marker. */ 786}; 787 788static int 789cmp_reg_entry (parg, qarg) 790 const PTR parg; 791 const PTR qarg; 792{ 793 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 794 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 795 796 return strcmp (q->name, p->name); 797} 798 799/* This function is called once, at assembler startup time. It should 800 set up all the tables, etc. that the MD part of the assembler will 801 need. */ 802 803void 804md_begin () 805{ 806 register const char *retval = NULL; 807 int lose = 0; 808 register unsigned int i = 0; 809 810 /* We don't get a chance to initialize anything before md_parse_option 811 is called, and it may not be called, so handle default initialization 812 now if not already done. */ 813 if (! default_init_p) 814 init_default_arch (); 815 816 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 817 op_hash = hash_new (); 818 819 while (i < (unsigned int) sparc_num_opcodes) 820 { 821 const char *name = sparc_opcodes[i].name; 822 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); 823 if (retval != NULL) 824 { 825 as_bad (_("Internal error: can't hash `%s': %s\n"), 826 sparc_opcodes[i].name, retval); 827 lose = 1; 828 } 829 do 830 { 831 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 832 { 833 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 834 sparc_opcodes[i].name, sparc_opcodes[i].args); 835 lose = 1; 836 } 837 ++i; 838 } 839 while (i < (unsigned int) sparc_num_opcodes 840 && !strcmp (sparc_opcodes[i].name, name)); 841 } 842 843 for (i = 0; native_op_table[i].name; i++) 844 { 845 const struct sparc_opcode *insn; 846 char *name = ((sparc_arch_size == 32) 847 ? native_op_table[i].name32 848 : native_op_table[i].name64); 849 insn = (struct sparc_opcode *) hash_find (op_hash, name); 850 if (insn == NULL) 851 { 852 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 853 name, native_op_table[i].name); 854 lose = 1; 855 } 856 else 857 { 858 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); 859 if (retval != NULL) 860 { 861 as_bad (_("Internal error: can't hash `%s': %s\n"), 862 sparc_opcodes[i].name, retval); 863 lose = 1; 864 } 865 } 866 } 867 868 if (lose) 869 as_fatal (_("Broken assembler. No assembly attempted.")); 870 871 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 872 sizeof (priv_reg_table[0]), cmp_reg_entry); 873 874 /* If -bump, record the architecture level at which we start issuing 875 warnings. The behaviour is different depending upon whether an 876 architecture was explicitly specified. If it wasn't, we issue warnings 877 for all upwards bumps. If it was, we don't start issuing warnings until 878 we need to bump beyond the requested architecture or when we bump between 879 conflicting architectures. */ 880 881 if (warn_on_bump 882 && architecture_requested) 883 { 884 /* `max_architecture' records the requested architecture. 885 Issue warnings if we go above it. */ 886 warn_after_architecture = max_architecture; 887 888 /* Find the highest architecture level that doesn't conflict with 889 the requested one. */ 890 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 891 max_architecture > warn_after_architecture; 892 --max_architecture) 893 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 894 warn_after_architecture)) 895 break; 896 } 897} 898 899/* Called after all assembly has been done. */ 900 901void 902sparc_md_end () 903{ 904 unsigned long mach = bfd_mach_sparc; 905 906 if (sparc_arch_size == 64) 907 switch (current_architecture) 908 { 909 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 910 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 911 default: mach = bfd_mach_sparc_v9; break; 912 } 913 else 914 switch (current_architecture) 915 { 916 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 917 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 918 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 919 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 920 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 921 be but for now it is (since that's the way it's always been 922 treated). */ 923 default: break; 924 } 925 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 926} 927 928/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 929 930static INLINE int 931in_signed_range (val, max) 932 bfd_signed_vma val, max; 933{ 934 if (max <= 0) 935 abort (); 936 /* Sign-extend the value from the architecture word size, so that 937 0xffffffff is always considered -1 on sparc32. */ 938 if (sparc_arch_size == 32) 939 { 940 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 941 val = ((val & U0xffffffff) ^ sign) - sign; 942 } 943 if (val > max) 944 return 0; 945 if (val < ~max) 946 return 0; 947 return 1; 948} 949 950/* Return non-zero if VAL is in the range 0 to MAX. */ 951 952static INLINE int 953in_unsigned_range (val, max) 954 bfd_vma val, max; 955{ 956 if (val > max) 957 return 0; 958 return 1; 959} 960 961/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 962 (e.g. -15 to +31). */ 963 964static INLINE int 965in_bitfield_range (val, max) 966 bfd_signed_vma val, max; 967{ 968 if (max <= 0) 969 abort (); 970 if (val > max) 971 return 0; 972 if (val < ~(max >> 1)) 973 return 0; 974 return 1; 975} 976 977static int 978sparc_ffs (mask) 979 unsigned int mask; 980{ 981 int i; 982 983 if (mask == 0) 984 return -1; 985 986 for (i = 0; (mask & 1) == 0; ++i) 987 mask >>= 1; 988 return i; 989} 990 991/* Implement big shift right. */ 992static bfd_vma 993BSR (val, amount) 994 bfd_vma val; 995 int amount; 996{ 997 if (sizeof (bfd_vma) <= 4 && amount >= 32) 998 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 999 return val >> amount; 1000} 1001 1002/* For communication between sparc_ip and get_expression. */ 1003static char *expr_end; 1004 1005/* Values for `special_case'. 1006 Instructions that require wierd handling because they're longer than 1007 4 bytes. */ 1008#define SPECIAL_CASE_NONE 0 1009#define SPECIAL_CASE_SET 1 1010#define SPECIAL_CASE_SETSW 2 1011#define SPECIAL_CASE_SETX 3 1012/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1013#define SPECIAL_CASE_FDIV 4 1014 1015/* Bit masks of various insns. */ 1016#define NOP_INSN 0x01000000 1017#define OR_INSN 0x80100000 1018#define XOR_INSN 0x80180000 1019#define FMOVS_INSN 0x81A00020 1020#define SETHI_INSN 0x01000000 1021#define SLLX_INSN 0x81281000 1022#define SRA_INSN 0x81380000 1023 1024/* The last instruction to be assembled. */ 1025static const struct sparc_opcode *last_insn; 1026/* The assembled opcode of `last_insn'. */ 1027static unsigned long last_opcode; 1028 1029/* Handle the set and setuw synthetic instructions. */ 1030 1031static void 1032synthetize_setuw (insn) 1033 const struct sparc_opcode *insn; 1034{ 1035 int need_hi22_p = 0; 1036 int rd = (the_insn.opcode & RD (~0)) >> 25; 1037 1038 if (the_insn.exp.X_op == O_constant) 1039 { 1040 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1041 { 1042 if (sizeof (offsetT) > 4 1043 && (the_insn.exp.X_add_number < 0 1044 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1045 as_warn (_("set: number not in 0..4294967295 range")); 1046 } 1047 else 1048 { 1049 if (sizeof (offsetT) > 4 1050 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1051 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1052 as_warn (_("set: number not in -2147483648..4294967295 range")); 1053 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1054 } 1055 } 1056 1057 /* See if operand is absolute and small; skip sethi if so. */ 1058 if (the_insn.exp.X_op != O_constant 1059 || the_insn.exp.X_add_number >= (1 << 12) 1060 || the_insn.exp.X_add_number < -(1 << 12)) 1061 { 1062 the_insn.opcode = (SETHI_INSN | RD (rd) 1063 | ((the_insn.exp.X_add_number >> 10) 1064 & (the_insn.exp.X_op == O_constant 1065 ? 0x3fffff : 0))); 1066 the_insn.reloc = (the_insn.exp.X_op != O_constant 1067 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1068 output_insn (insn, &the_insn); 1069 need_hi22_p = 1; 1070 } 1071 1072 /* See if operand has no low-order bits; skip OR if so. */ 1073 if (the_insn.exp.X_op != O_constant 1074 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1075 || ! need_hi22_p) 1076 { 1077 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1078 | RD (rd) | IMMED 1079 | (the_insn.exp.X_add_number 1080 & (the_insn.exp.X_op != O_constant 1081 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1082 the_insn.reloc = (the_insn.exp.X_op != O_constant 1083 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1084 output_insn (insn, &the_insn); 1085 } 1086} 1087 1088/* Handle the setsw synthetic instruction. */ 1089 1090static void 1091synthetize_setsw (insn) 1092 const struct sparc_opcode *insn; 1093{ 1094 int low32, rd, opc; 1095 1096 rd = (the_insn.opcode & RD (~0)) >> 25; 1097 1098 if (the_insn.exp.X_op != O_constant) 1099 { 1100 synthetize_setuw (insn); 1101 1102 /* Need to sign extend it. */ 1103 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1104 the_insn.reloc = BFD_RELOC_NONE; 1105 output_insn (insn, &the_insn); 1106 return; 1107 } 1108 1109 if (sizeof (offsetT) > 4 1110 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1111 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1112 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1113 1114 low32 = the_insn.exp.X_add_number; 1115 1116 if (low32 >= 0) 1117 { 1118 synthetize_setuw (insn); 1119 return; 1120 } 1121 1122 opc = OR_INSN; 1123 1124 the_insn.reloc = BFD_RELOC_NONE; 1125 /* See if operand is absolute and small; skip sethi if so. */ 1126 if (low32 < -(1 << 12)) 1127 { 1128 the_insn.opcode = (SETHI_INSN | RD (rd) 1129 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1130 output_insn (insn, &the_insn); 1131 low32 = 0x1c00 | (low32 & 0x3ff); 1132 opc = RS1 (rd) | XOR_INSN; 1133 } 1134 1135 the_insn.opcode = (opc | RD (rd) | IMMED 1136 | (low32 & 0x1fff)); 1137 output_insn (insn, &the_insn); 1138} 1139 1140/* Handle the setsw synthetic instruction. */ 1141 1142static void 1143synthetize_setx (insn) 1144 const struct sparc_opcode *insn; 1145{ 1146 int upper32, lower32; 1147 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1148 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1149 int upper_dstreg; 1150 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1151 int need_xor10_p = 0; 1152 1153#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1154 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1155 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1156#undef SIGNEXT32 1157 1158 upper_dstreg = tmpreg; 1159 /* The tmp reg should not be the dst reg. */ 1160 if (tmpreg == dstreg) 1161 as_warn (_("setx: temporary register same as destination register")); 1162 1163 /* ??? Obviously there are other optimizations we can do 1164 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1165 doing some of these. Later. If you do change things, try to 1166 change all of this to be table driven as well. */ 1167 /* What to output depends on the number if it's constant. 1168 Compute that first, then output what we've decided upon. */ 1169 if (the_insn.exp.X_op != O_constant) 1170 { 1171 if (sparc_arch_size == 32) 1172 { 1173 /* When arch size is 32, we want setx to be equivalent 1174 to setuw for anything but constants. */ 1175 the_insn.exp.X_add_number &= 0xffffffff; 1176 synthetize_setuw (insn); 1177 return; 1178 } 1179 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1180 lower32 = 0; 1181 upper32 = 0; 1182 } 1183 else 1184 { 1185 /* Reset X_add_number, we've extracted it as upper32/lower32. 1186 Otherwise fixup_segment will complain about not being able to 1187 write an 8 byte number in a 4 byte field. */ 1188 the_insn.exp.X_add_number = 0; 1189 1190 /* Only need hh22 if `or' insn can't handle constant. */ 1191 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1192 need_hh22_p = 1; 1193 1194 /* Does bottom part (after sethi) have bits? */ 1195 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1196 /* No hh22, but does upper32 still have bits we can't set 1197 from lower32? */ 1198 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1199 need_hm10_p = 1; 1200 1201 /* If the lower half is all zero, we build the upper half directly 1202 into the dst reg. */ 1203 if (lower32 != 0 1204 /* Need lower half if number is zero or 0xffffffff00000000. */ 1205 || (! need_hh22_p && ! need_hm10_p)) 1206 { 1207 /* No need for sethi if `or' insn can handle constant. */ 1208 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1209 /* Note that we can't use a negative constant in the `or' 1210 insn unless the upper 32 bits are all ones. */ 1211 || (lower32 < 0 && upper32 != -1) 1212 || (lower32 >= 0 && upper32 == -1)) 1213 need_hi22_p = 1; 1214 1215 if (need_hi22_p && upper32 == -1) 1216 need_xor10_p = 1; 1217 1218 /* Does bottom part (after sethi) have bits? */ 1219 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1220 /* No sethi. */ 1221 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1222 /* Need `or' if we didn't set anything else. */ 1223 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1224 need_lo10_p = 1; 1225 } 1226 else 1227 /* Output directly to dst reg if lower 32 bits are all zero. */ 1228 upper_dstreg = dstreg; 1229 } 1230 1231 if (!upper_dstreg && dstreg) 1232 as_warn (_("setx: illegal temporary register g0")); 1233 1234 if (need_hh22_p) 1235 { 1236 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1237 | ((upper32 >> 10) & 0x3fffff)); 1238 the_insn.reloc = (the_insn.exp.X_op != O_constant 1239 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1240 output_insn (insn, &the_insn); 1241 } 1242 1243 if (need_hi22_p) 1244 { 1245 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1246 | (((need_xor10_p ? ~lower32 : lower32) 1247 >> 10) & 0x3fffff)); 1248 the_insn.reloc = (the_insn.exp.X_op != O_constant 1249 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1250 output_insn (insn, &the_insn); 1251 } 1252 1253 if (need_hm10_p) 1254 { 1255 the_insn.opcode = (OR_INSN 1256 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1257 | RD (upper_dstreg) 1258 | IMMED 1259 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1260 the_insn.reloc = (the_insn.exp.X_op != O_constant 1261 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1262 output_insn (insn, &the_insn); 1263 } 1264 1265 if (need_lo10_p) 1266 { 1267 /* FIXME: One nice optimization to do here is to OR the low part 1268 with the highpart if hi22 isn't needed and the low part is 1269 positive. */ 1270 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1271 | RD (dstreg) 1272 | IMMED 1273 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1274 the_insn.reloc = (the_insn.exp.X_op != O_constant 1275 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1276 output_insn (insn, &the_insn); 1277 } 1278 1279 /* If we needed to build the upper part, shift it into place. */ 1280 if (need_hh22_p || need_hm10_p) 1281 { 1282 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1283 | IMMED | 32); 1284 the_insn.reloc = BFD_RELOC_NONE; 1285 output_insn (insn, &the_insn); 1286 } 1287 1288 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1289 if (need_xor10_p) 1290 { 1291 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1292 | 0x1c00 | (lower32 & 0x3ff)); 1293 the_insn.reloc = BFD_RELOC_NONE; 1294 output_insn (insn, &the_insn); 1295 } 1296 1297 /* If we needed to build both upper and lower parts, OR them together. */ 1298 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1299 { 1300 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1301 | RD (dstreg)); 1302 the_insn.reloc = BFD_RELOC_NONE; 1303 output_insn (insn, &the_insn); 1304 } 1305} 1306 1307/* Main entry point to assemble one instruction. */ 1308 1309void 1310md_assemble (str) 1311 char *str; 1312{ 1313 const struct sparc_opcode *insn; 1314 int special_case; 1315 1316 know (str); 1317 special_case = sparc_ip (str, &insn); 1318 if (insn == NULL) 1319 return; 1320 1321 /* We warn about attempts to put a floating point branch in a delay slot, 1322 unless the delay slot has been annulled. */ 1323 if (last_insn != NULL 1324 && (insn->flags & F_FBR) != 0 1325 && (last_insn->flags & F_DELAYED) != 0 1326 /* ??? This test isn't completely accurate. We assume anything with 1327 F_{UNBR,CONDBR,FBR} set is annullable. */ 1328 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1329 || (last_opcode & ANNUL) == 0)) 1330 as_warn (_("FP branch in delay slot")); 1331 1332 /* SPARC before v9 requires a nop instruction between a floating 1333 point instruction and a floating point branch. We insert one 1334 automatically, with a warning. */ 1335 if (max_architecture < SPARC_OPCODE_ARCH_V9 1336 && last_insn != NULL 1337 && (insn->flags & F_FBR) != 0 1338 && (last_insn->flags & F_FLOAT) != 0) 1339 { 1340 struct sparc_it nop_insn; 1341 1342 nop_insn.opcode = NOP_INSN; 1343 nop_insn.reloc = BFD_RELOC_NONE; 1344 output_insn (insn, &nop_insn); 1345 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1346 } 1347 1348 switch (special_case) 1349 { 1350 case SPECIAL_CASE_NONE: 1351 /* Normal insn. */ 1352 output_insn (insn, &the_insn); 1353 break; 1354 1355 case SPECIAL_CASE_SETSW: 1356 synthetize_setsw (insn); 1357 break; 1358 1359 case SPECIAL_CASE_SET: 1360 synthetize_setuw (insn); 1361 break; 1362 1363 case SPECIAL_CASE_SETX: 1364 synthetize_setx (insn); 1365 break; 1366 1367 case SPECIAL_CASE_FDIV: 1368 { 1369 int rd = (the_insn.opcode >> 25) & 0x1f; 1370 1371 output_insn (insn, &the_insn); 1372 1373 /* According to information leaked from Sun, the "fdiv" instructions 1374 on early SPARC machines would produce incorrect results sometimes. 1375 The workaround is to add an fmovs of the destination register to 1376 itself just after the instruction. This was true on machines 1377 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1378 assert (the_insn.reloc == BFD_RELOC_NONE); 1379 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1380 output_insn (insn, &the_insn); 1381 return; 1382 } 1383 1384 default: 1385 as_fatal (_("failed special case insn sanity check")); 1386 } 1387} 1388 1389/* Subroutine of md_assemble to do the actual parsing. */ 1390 1391static int 1392sparc_ip (str, pinsn) 1393 char *str; 1394 const struct sparc_opcode **pinsn; 1395{ 1396 char *error_message = ""; 1397 char *s; 1398 const char *args; 1399 char c; 1400 const struct sparc_opcode *insn; 1401 char *argsStart; 1402 unsigned long opcode; 1403 unsigned int mask = 0; 1404 int match = 0; 1405 int comma = 0; 1406 int v9_arg_p; 1407 int special_case = SPECIAL_CASE_NONE; 1408 1409 s = str; 1410 if (ISLOWER (*s)) 1411 { 1412 do 1413 ++s; 1414 while (ISLOWER (*s) || ISDIGIT (*s)); 1415 } 1416 1417 switch (*s) 1418 { 1419 case '\0': 1420 break; 1421 1422 case ',': 1423 comma = 1; 1424 /* Fall through. */ 1425 1426 case ' ': 1427 *s++ = '\0'; 1428 break; 1429 1430 default: 1431 as_bad (_("Unknown opcode: `%s'"), str); 1432 *pinsn = NULL; 1433 return special_case; 1434 } 1435 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1436 *pinsn = insn; 1437 if (insn == NULL) 1438 { 1439 as_bad (_("Unknown opcode: `%s'"), str); 1440 return special_case; 1441 } 1442 if (comma) 1443 { 1444 *--s = ','; 1445 } 1446 1447 argsStart = s; 1448 for (;;) 1449 { 1450 opcode = insn->match; 1451 memset (&the_insn, '\0', sizeof (the_insn)); 1452 the_insn.reloc = BFD_RELOC_NONE; 1453 v9_arg_p = 0; 1454 1455 /* Build the opcode, checking as we go to make sure that the 1456 operands match. */ 1457 for (args = insn->args;; ++args) 1458 { 1459 switch (*args) 1460 { 1461 case 'K': 1462 { 1463 int kmask = 0; 1464 1465 /* Parse a series of masks. */ 1466 if (*s == '#') 1467 { 1468 while (*s == '#') 1469 { 1470 int mask; 1471 1472 if (! parse_keyword_arg (sparc_encode_membar, &s, 1473 &mask)) 1474 { 1475 error_message = _(": invalid membar mask name"); 1476 goto error; 1477 } 1478 kmask |= mask; 1479 while (*s == ' ') 1480 ++s; 1481 if (*s == '|' || *s == '+') 1482 ++s; 1483 while (*s == ' ') 1484 ++s; 1485 } 1486 } 1487 else 1488 { 1489 if (! parse_const_expr_arg (&s, &kmask)) 1490 { 1491 error_message = _(": invalid membar mask expression"); 1492 goto error; 1493 } 1494 if (kmask < 0 || kmask > 127) 1495 { 1496 error_message = _(": invalid membar mask number"); 1497 goto error; 1498 } 1499 } 1500 1501 opcode |= MEMBAR (kmask); 1502 continue; 1503 } 1504 1505 case '3': 1506 { 1507 int smask = 0; 1508 1509 if (! parse_const_expr_arg (&s, &smask)) 1510 { 1511 error_message = _(": invalid siam mode expression"); 1512 goto error; 1513 } 1514 if (smask < 0 || smask > 7) 1515 { 1516 error_message = _(": invalid siam mode number"); 1517 goto error; 1518 } 1519 opcode |= smask; 1520 continue; 1521 } 1522 1523 case '*': 1524 { 1525 int fcn = 0; 1526 1527 /* Parse a prefetch function. */ 1528 if (*s == '#') 1529 { 1530 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1531 { 1532 error_message = _(": invalid prefetch function name"); 1533 goto error; 1534 } 1535 } 1536 else 1537 { 1538 if (! parse_const_expr_arg (&s, &fcn)) 1539 { 1540 error_message = _(": invalid prefetch function expression"); 1541 goto error; 1542 } 1543 if (fcn < 0 || fcn > 31) 1544 { 1545 error_message = _(": invalid prefetch function number"); 1546 goto error; 1547 } 1548 } 1549 opcode |= RD (fcn); 1550 continue; 1551 } 1552 1553 case '!': 1554 case '?': 1555 /* Parse a sparc64 privileged register. */ 1556 if (*s == '%') 1557 { 1558 struct priv_reg_entry *p = priv_reg_table; 1559 unsigned int len = 9999999; /* Init to make gcc happy. */ 1560 1561 s += 1; 1562 while (p->name[0] > s[0]) 1563 p++; 1564 while (p->name[0] == s[0]) 1565 { 1566 len = strlen (p->name); 1567 if (strncmp (p->name, s, len) == 0) 1568 break; 1569 p++; 1570 } 1571 if (p->name[0] != s[0]) 1572 { 1573 error_message = _(": unrecognizable privileged register"); 1574 goto error; 1575 } 1576 if (*args == '?') 1577 opcode |= (p->regnum << 14); 1578 else 1579 opcode |= (p->regnum << 25); 1580 s += len; 1581 continue; 1582 } 1583 else 1584 { 1585 error_message = _(": unrecognizable privileged register"); 1586 goto error; 1587 } 1588 1589 case '$': 1590 case '%': 1591 /* Parse a sparc64 hyperprivileged register. */ 1592 if (*s == '%') 1593 { 1594 struct priv_reg_entry *p = hpriv_reg_table; 1595 unsigned int len = 9999999; /* Init to make gcc happy. */ 1596 1597 s += 1; 1598 while (p->name[0] > s[0]) 1599 p++; 1600 while (p->name[0] == s[0]) 1601 { 1602 len = strlen (p->name); 1603 if (strncmp (p->name, s, len) == 0) 1604 break; 1605 p++; 1606 } 1607 if (p->name[0] != s[0]) 1608 { 1609 error_message = _(": unrecognizable hyperprivileged register"); 1610 goto error; 1611 } 1612 if (*args == '$') 1613 opcode |= (p->regnum << 14); 1614 else 1615 opcode |= (p->regnum << 25); 1616 s += len; 1617 continue; 1618 } 1619 else 1620 { 1621 error_message = _(": unrecognizable hyperprivileged register"); 1622 goto error; 1623 } 1624 1625 case '_': 1626 case '/': 1627 /* Parse a v9a/v9b ancillary state register. */ 1628 if (*s == '%') 1629 { 1630 struct priv_reg_entry *p = v9a_asr_table; 1631 unsigned int len = 9999999; /* Init to make gcc happy. */ 1632 1633 s += 1; 1634 while (p->name[0] > s[0]) 1635 p++; 1636 while (p->name[0] == s[0]) 1637 { 1638 len = strlen (p->name); 1639 if (strncmp (p->name, s, len) == 0) 1640 break; 1641 p++; 1642 } 1643 if (p->name[0] != s[0]) 1644 { 1645 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1646 goto error; 1647 } 1648 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1649 { 1650 error_message = _(": rd on write only ancillary state register"); 1651 goto error; 1652 } 1653 if (p->regnum >= 24 1654 && (insn->architecture 1655 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1656 { 1657 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1658 error_message = _(": unrecognizable v9a ancillary state register"); 1659 goto error; 1660 } 1661 if (*args == '/') 1662 opcode |= (p->regnum << 14); 1663 else 1664 opcode |= (p->regnum << 25); 1665 s += len; 1666 continue; 1667 } 1668 else 1669 { 1670 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1671 goto error; 1672 } 1673 1674 case 'M': 1675 case 'm': 1676 if (strncmp (s, "%asr", 4) == 0) 1677 { 1678 s += 4; 1679 1680 if (ISDIGIT (*s)) 1681 { 1682 long num = 0; 1683 1684 while (ISDIGIT (*s)) 1685 { 1686 num = num * 10 + *s - '0'; 1687 ++s; 1688 } 1689 1690 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1691 { 1692 if (num < 16 || 31 < num) 1693 { 1694 error_message = _(": asr number must be between 16 and 31"); 1695 goto error; 1696 } 1697 } 1698 else 1699 { 1700 if (num < 0 || 31 < num) 1701 { 1702 error_message = _(": asr number must be between 0 and 31"); 1703 goto error; 1704 } 1705 } 1706 1707 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1708 continue; 1709 } 1710 else 1711 { 1712 error_message = _(": expecting %asrN"); 1713 goto error; 1714 } 1715 } /* if %asr */ 1716 break; 1717 1718 case 'I': 1719 the_insn.reloc = BFD_RELOC_SPARC_11; 1720 goto immediate; 1721 1722 case 'j': 1723 the_insn.reloc = BFD_RELOC_SPARC_10; 1724 goto immediate; 1725 1726 case 'X': 1727 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1728 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1729 the_insn.reloc = BFD_RELOC_SPARC_5; 1730 else 1731 the_insn.reloc = BFD_RELOC_SPARC13; 1732 /* These fields are unsigned, but for upward compatibility, 1733 allow negative values as well. */ 1734 goto immediate; 1735 1736 case 'Y': 1737 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1738 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1739 the_insn.reloc = BFD_RELOC_SPARC_6; 1740 else 1741 the_insn.reloc = BFD_RELOC_SPARC13; 1742 /* These fields are unsigned, but for upward compatibility, 1743 allow negative values as well. */ 1744 goto immediate; 1745 1746 case 'k': 1747 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1748 the_insn.pcrel = 1; 1749 goto immediate; 1750 1751 case 'G': 1752 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1753 the_insn.pcrel = 1; 1754 goto immediate; 1755 1756 case 'N': 1757 if (*s == 'p' && s[1] == 'n') 1758 { 1759 s += 2; 1760 continue; 1761 } 1762 break; 1763 1764 case 'T': 1765 if (*s == 'p' && s[1] == 't') 1766 { 1767 s += 2; 1768 continue; 1769 } 1770 break; 1771 1772 case 'z': 1773 if (*s == ' ') 1774 { 1775 ++s; 1776 } 1777 if (strncmp (s, "%icc", 4) == 0) 1778 { 1779 s += 4; 1780 continue; 1781 } 1782 break; 1783 1784 case 'Z': 1785 if (*s == ' ') 1786 { 1787 ++s; 1788 } 1789 if (strncmp (s, "%xcc", 4) == 0) 1790 { 1791 s += 4; 1792 continue; 1793 } 1794 break; 1795 1796 case '6': 1797 if (*s == ' ') 1798 { 1799 ++s; 1800 } 1801 if (strncmp (s, "%fcc0", 5) == 0) 1802 { 1803 s += 5; 1804 continue; 1805 } 1806 break; 1807 1808 case '7': 1809 if (*s == ' ') 1810 { 1811 ++s; 1812 } 1813 if (strncmp (s, "%fcc1", 5) == 0) 1814 { 1815 s += 5; 1816 continue; 1817 } 1818 break; 1819 1820 case '8': 1821 if (*s == ' ') 1822 { 1823 ++s; 1824 } 1825 if (strncmp (s, "%fcc2", 5) == 0) 1826 { 1827 s += 5; 1828 continue; 1829 } 1830 break; 1831 1832 case '9': 1833 if (*s == ' ') 1834 { 1835 ++s; 1836 } 1837 if (strncmp (s, "%fcc3", 5) == 0) 1838 { 1839 s += 5; 1840 continue; 1841 } 1842 break; 1843 1844 case 'P': 1845 if (strncmp (s, "%pc", 3) == 0) 1846 { 1847 s += 3; 1848 continue; 1849 } 1850 break; 1851 1852 case 'W': 1853 if (strncmp (s, "%tick", 5) == 0) 1854 { 1855 s += 5; 1856 continue; 1857 } 1858 break; 1859 1860 case '\0': /* End of args. */ 1861 if (s[0] == ',' && s[1] == '%') 1862 { 1863 static const struct tls_ops 1864 { 1865 /* The name as it appears in assembler. */ 1866 char *name; 1867 /* strlen (name), precomputed for speed */ 1868 int len; 1869 /* The reloc this pseudo-op translates to. */ 1870 int reloc; 1871 /* 1 if call. */ 1872 int call; 1873 } 1874 tls_ops[] = 1875 { 1876 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, 1877 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, 1878 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, 1879 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, 1880 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, 1881 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, 1882 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, 1883 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, 1884 { NULL, 0, 0, 0 } 1885 }; 1886 const struct tls_ops *o; 1887 char *s1; 1888 int npar = 0; 1889 1890 for (o = tls_ops; o->name; o++) 1891 if (strncmp (s + 2, o->name, o->len) == 0) 1892 break; 1893 if (o->name == NULL) 1894 break; 1895 1896 if (s[o->len + 2] != '(') 1897 { 1898 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1899 return special_case; 1900 } 1901 1902 if (! o->call && the_insn.reloc != BFD_RELOC_NONE) 1903 { 1904 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 1905 o->name); 1906 return special_case; 1907 } 1908 1909 if (o->call 1910 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 1911 || the_insn.exp.X_add_number != 0 1912 || the_insn.exp.X_add_symbol 1913 != symbol_find_or_make ("__tls_get_addr"))) 1914 { 1915 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 1916 o->name); 1917 return special_case; 1918 } 1919 1920 the_insn.reloc = o->reloc; 1921 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 1922 s += o->len + 3; 1923 1924 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 1925 if (*s1 == '(') 1926 npar++; 1927 else if (*s1 == ')') 1928 { 1929 if (!npar) 1930 break; 1931 npar--; 1932 } 1933 1934 if (*s1 != ')') 1935 { 1936 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 1937 return special_case; 1938 } 1939 1940 *s1 = '\0'; 1941 (void) get_expression (s); 1942 *s1 = ')'; 1943 s = s1 + 1; 1944 } 1945 if (*s == '\0') 1946 match = 1; 1947 break; 1948 1949 case '+': 1950 if (*s == '+') 1951 { 1952 ++s; 1953 continue; 1954 } 1955 if (*s == '-') 1956 { 1957 continue; 1958 } 1959 break; 1960 1961 case '[': /* These must match exactly. */ 1962 case ']': 1963 case ',': 1964 case ' ': 1965 if (*s++ == *args) 1966 continue; 1967 break; 1968 1969 case '#': /* Must be at least one digit. */ 1970 if (ISDIGIT (*s++)) 1971 { 1972 while (ISDIGIT (*s)) 1973 { 1974 ++s; 1975 } 1976 continue; 1977 } 1978 break; 1979 1980 case 'C': /* Coprocessor state register. */ 1981 if (strncmp (s, "%csr", 4) == 0) 1982 { 1983 s += 4; 1984 continue; 1985 } 1986 break; 1987 1988 case 'b': /* Next operand is a coprocessor register. */ 1989 case 'c': 1990 case 'D': 1991 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 1992 { 1993 mask = *s++; 1994 if (ISDIGIT (*s)) 1995 { 1996 mask = 10 * (mask - '0') + (*s++ - '0'); 1997 if (mask >= 32) 1998 { 1999 break; 2000 } 2001 } 2002 else 2003 { 2004 mask -= '0'; 2005 } 2006 switch (*args) 2007 { 2008 2009 case 'b': 2010 opcode |= mask << 14; 2011 continue; 2012 2013 case 'c': 2014 opcode |= mask; 2015 continue; 2016 2017 case 'D': 2018 opcode |= mask << 25; 2019 continue; 2020 } 2021 } 2022 break; 2023 2024 case 'r': /* next operand must be a register */ 2025 case 'O': 2026 case '1': 2027 case '2': 2028 case 'd': 2029 if (*s++ == '%') 2030 { 2031 switch (c = *s++) 2032 { 2033 2034 case 'f': /* frame pointer */ 2035 if (*s++ == 'p') 2036 { 2037 mask = 0x1e; 2038 break; 2039 } 2040 goto error; 2041 2042 case 'g': /* global register */ 2043 c = *s++; 2044 if (isoctal (c)) 2045 { 2046 mask = c - '0'; 2047 break; 2048 } 2049 goto error; 2050 2051 case 'i': /* in register */ 2052 c = *s++; 2053 if (isoctal (c)) 2054 { 2055 mask = c - '0' + 24; 2056 break; 2057 } 2058 goto error; 2059 2060 case 'l': /* local register */ 2061 c = *s++; 2062 if (isoctal (c)) 2063 { 2064 mask = (c - '0' + 16); 2065 break; 2066 } 2067 goto error; 2068 2069 case 'o': /* out register */ 2070 c = *s++; 2071 if (isoctal (c)) 2072 { 2073 mask = (c - '0' + 8); 2074 break; 2075 } 2076 goto error; 2077 2078 case 's': /* stack pointer */ 2079 if (*s++ == 'p') 2080 { 2081 mask = 0xe; 2082 break; 2083 } 2084 goto error; 2085 2086 case 'r': /* any register */ 2087 if (!ISDIGIT ((c = *s++))) 2088 { 2089 goto error; 2090 } 2091 /* FALLTHROUGH */ 2092 case '0': 2093 case '1': 2094 case '2': 2095 case '3': 2096 case '4': 2097 case '5': 2098 case '6': 2099 case '7': 2100 case '8': 2101 case '9': 2102 if (ISDIGIT (*s)) 2103 { 2104 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2105 { 2106 goto error; 2107 } 2108 } 2109 else 2110 { 2111 c -= '0'; 2112 } 2113 mask = c; 2114 break; 2115 2116 default: 2117 goto error; 2118 } 2119 2120 if ((mask & ~1) == 2 && sparc_arch_size == 64 2121 && no_undeclared_regs && ! globals[mask]) 2122 as_bad (_("detected global register use not covered by .register pseudo-op")); 2123 2124 /* Got the register, now figure out where 2125 it goes in the opcode. */ 2126 switch (*args) 2127 { 2128 case '1': 2129 opcode |= mask << 14; 2130 continue; 2131 2132 case '2': 2133 opcode |= mask; 2134 continue; 2135 2136 case 'd': 2137 opcode |= mask << 25; 2138 continue; 2139 2140 case 'r': 2141 opcode |= (mask << 25) | (mask << 14); 2142 continue; 2143 2144 case 'O': 2145 opcode |= (mask << 25) | (mask << 0); 2146 continue; 2147 } 2148 } 2149 break; 2150 2151 case 'e': /* next operand is a floating point register */ 2152 case 'v': 2153 case 'V': 2154 2155 case 'f': 2156 case 'B': 2157 case 'R': 2158 2159 case 'g': 2160 case 'H': 2161 case 'J': 2162 { 2163 char format; 2164 2165 if (*s++ == '%' 2166 && ((format = *s) == 'f') 2167 && ISDIGIT (*++s)) 2168 { 2169 for (mask = 0; ISDIGIT (*s); ++s) 2170 { 2171 mask = 10 * mask + (*s - '0'); 2172 } /* read the number */ 2173 2174 if ((*args == 'v' 2175 || *args == 'B' 2176 || *args == 'H') 2177 && (mask & 1)) 2178 { 2179 break; 2180 } /* register must be even numbered */ 2181 2182 if ((*args == 'V' 2183 || *args == 'R' 2184 || *args == 'J') 2185 && (mask & 3)) 2186 { 2187 break; 2188 } /* register must be multiple of 4 */ 2189 2190 if (mask >= 64) 2191 { 2192 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2193 error_message = _(": There are only 64 f registers; [0-63]"); 2194 else 2195 error_message = _(": There are only 32 f registers; [0-31]"); 2196 goto error; 2197 } /* on error */ 2198 else if (mask >= 32) 2199 { 2200 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2201 { 2202 if (*args == 'e' || *args == 'f' || *args == 'g') 2203 { 2204 error_message 2205 = _(": There are only 32 single precision f registers; [0-31]"); 2206 goto error; 2207 } 2208 v9_arg_p = 1; 2209 mask -= 31; /* wrap high bit */ 2210 } 2211 else 2212 { 2213 error_message = _(": There are only 32 f registers; [0-31]"); 2214 goto error; 2215 } 2216 } 2217 } 2218 else 2219 { 2220 break; 2221 } /* if not an 'f' register. */ 2222 2223 switch (*args) 2224 { 2225 case 'v': 2226 case 'V': 2227 case 'e': 2228 opcode |= RS1 (mask); 2229 continue; 2230 2231 case 'f': 2232 case 'B': 2233 case 'R': 2234 opcode |= RS2 (mask); 2235 continue; 2236 2237 case 'g': 2238 case 'H': 2239 case 'J': 2240 opcode |= RD (mask); 2241 continue; 2242 } /* Pack it in. */ 2243 2244 know (0); 2245 break; 2246 } /* float arg */ 2247 2248 case 'F': 2249 if (strncmp (s, "%fsr", 4) == 0) 2250 { 2251 s += 4; 2252 continue; 2253 } 2254 break; 2255 2256 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2257 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2258 goto immediate; 2259 2260 case 'l': /* 22 bit PC relative immediate */ 2261 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2262 the_insn.pcrel = 1; 2263 goto immediate; 2264 2265 case 'L': /* 30 bit immediate */ 2266 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2267 the_insn.pcrel = 1; 2268 goto immediate; 2269 2270 case 'h': 2271 case 'n': /* 22 bit immediate */ 2272 the_insn.reloc = BFD_RELOC_SPARC22; 2273 goto immediate; 2274 2275 case 'i': /* 13 bit immediate */ 2276 the_insn.reloc = BFD_RELOC_SPARC13; 2277 2278 /* fallthrough */ 2279 2280 immediate: 2281 if (*s == ' ') 2282 s++; 2283 2284 { 2285 char *s1; 2286 char *op_arg = NULL; 2287 static expressionS op_exp; 2288 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2289 2290 /* Check for %hi, etc. */ 2291 if (*s == '%') 2292 { 2293 static const struct ops { 2294 /* The name as it appears in assembler. */ 2295 char *name; 2296 /* strlen (name), precomputed for speed */ 2297 int len; 2298 /* The reloc this pseudo-op translates to. */ 2299 int reloc; 2300 /* Non-zero if for v9 only. */ 2301 int v9_p; 2302 /* Non-zero if can be used in pc-relative contexts. */ 2303 int pcrel_p;/*FIXME:wip*/ 2304 } ops[] = { 2305 /* hix/lox must appear before hi/lo so %hix won't be 2306 mistaken for %hi. */ 2307 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2308 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2309 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2310 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2311 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2312 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2313 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2314 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2315 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2316 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2317 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2318 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2319 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, 2320 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, 2321 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, 2322 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, 2323 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, 2324 0 }, 2325 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, 2326 0 }, 2327 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, 2328 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, 2329 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, 2330 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, 2331 { NULL, 0, 0, 0, 0 } 2332 }; 2333 const struct ops *o; 2334 2335 for (o = ops; o->name; o++) 2336 if (strncmp (s + 1, o->name, o->len) == 0) 2337 break; 2338 if (o->name == NULL) 2339 break; 2340 2341 if (s[o->len + 1] != '(') 2342 { 2343 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2344 return special_case; 2345 } 2346 2347 op_arg = o->name; 2348 the_insn.reloc = o->reloc; 2349 s += o->len + 2; 2350 v9_arg_p = o->v9_p; 2351 } 2352 2353 /* Note that if the get_expression() fails, we will still 2354 have created U entries in the symbol table for the 2355 'symbols' in the input string. Try not to create U 2356 symbols for registers, etc. */ 2357 2358 /* This stuff checks to see if the expression ends in 2359 +%reg. If it does, it removes the register from 2360 the expression, and re-sets 's' to point to the 2361 right place. */ 2362 2363 if (op_arg) 2364 { 2365 int npar = 0; 2366 2367 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2368 if (*s1 == '(') 2369 npar++; 2370 else if (*s1 == ')') 2371 { 2372 if (!npar) 2373 break; 2374 npar--; 2375 } 2376 2377 if (*s1 != ')') 2378 { 2379 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2380 return special_case; 2381 } 2382 2383 *s1 = '\0'; 2384 (void) get_expression (s); 2385 *s1 = ')'; 2386 s = s1 + 1; 2387 if (*s == ',' || *s == ']' || !*s) 2388 continue; 2389 if (*s != '+' && *s != '-') 2390 { 2391 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2392 return special_case; 2393 } 2394 *s1 = '0'; 2395 s = s1; 2396 op_exp = the_insn.exp; 2397 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2398 } 2399 2400 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2401 ; 2402 2403 if (s1 != s && ISDIGIT (s1[-1])) 2404 { 2405 if (s1[-2] == '%' && s1[-3] == '+') 2406 s1 -= 3; 2407 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2408 s1 -= 4; 2409 else 2410 s1 = NULL; 2411 if (s1) 2412 { 2413 *s1 = '\0'; 2414 if (op_arg && s1 == s + 1) 2415 the_insn.exp.X_op = O_absent; 2416 else 2417 (void) get_expression (s); 2418 *s1 = '+'; 2419 if (op_arg) 2420 *s = ')'; 2421 s = s1; 2422 } 2423 } 2424 else 2425 s1 = NULL; 2426 2427 if (!s1) 2428 { 2429 (void) get_expression (s); 2430 if (op_arg) 2431 *s = ')'; 2432 s = expr_end; 2433 } 2434 2435 if (op_arg) 2436 { 2437 the_insn.exp2 = the_insn.exp; 2438 the_insn.exp = op_exp; 2439 if (the_insn.exp2.X_op == O_absent) 2440 the_insn.exp2.X_op = O_illegal; 2441 else if (the_insn.exp.X_op == O_absent) 2442 { 2443 the_insn.exp = the_insn.exp2; 2444 the_insn.exp2.X_op = O_illegal; 2445 } 2446 else if (the_insn.exp.X_op == O_constant) 2447 { 2448 valueT val = the_insn.exp.X_add_number; 2449 switch (the_insn.reloc) 2450 { 2451 default: 2452 break; 2453 2454 case BFD_RELOC_SPARC_HH22: 2455 val = BSR (val, 32); 2456 /* Fall through. */ 2457 2458 case BFD_RELOC_SPARC_LM22: 2459 case BFD_RELOC_HI22: 2460 val = (val >> 10) & 0x3fffff; 2461 break; 2462 2463 case BFD_RELOC_SPARC_HM10: 2464 val = BSR (val, 32); 2465 /* Fall through. */ 2466 2467 case BFD_RELOC_LO10: 2468 val &= 0x3ff; 2469 break; 2470 2471 case BFD_RELOC_SPARC_H44: 2472 val >>= 22; 2473 val &= 0x3fffff; 2474 break; 2475 2476 case BFD_RELOC_SPARC_M44: 2477 val >>= 12; 2478 val &= 0x3ff; 2479 break; 2480 2481 case BFD_RELOC_SPARC_L44: 2482 val &= 0xfff; 2483 break; 2484 2485 case BFD_RELOC_SPARC_HIX22: 2486 val = ~val; 2487 val = (val >> 10) & 0x3fffff; 2488 break; 2489 2490 case BFD_RELOC_SPARC_LOX10: 2491 val = (val & 0x3ff) | 0x1c00; 2492 break; 2493 } 2494 the_insn.exp = the_insn.exp2; 2495 the_insn.exp.X_add_number += val; 2496 the_insn.exp2.X_op = O_illegal; 2497 the_insn.reloc = old_reloc; 2498 } 2499 else if (the_insn.exp2.X_op != O_constant) 2500 { 2501 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2502 return special_case; 2503 } 2504 else 2505 { 2506 if (old_reloc != BFD_RELOC_SPARC13 2507 || the_insn.reloc != BFD_RELOC_LO10 2508 || sparc_arch_size != 64 2509 || sparc_pic_code) 2510 { 2511 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2512 return special_case; 2513 } 2514 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2515 } 2516 } 2517 } 2518 /* Check for constants that don't require emitting a reloc. */ 2519 if (the_insn.exp.X_op == O_constant 2520 && the_insn.exp.X_add_symbol == 0 2521 && the_insn.exp.X_op_symbol == 0) 2522 { 2523 /* For pc-relative call instructions, we reject 2524 constants to get better code. */ 2525 if (the_insn.pcrel 2526 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2527 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2528 { 2529 error_message = _(": PC-relative operand can't be a constant"); 2530 goto error; 2531 } 2532 2533 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2534 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2535 { 2536 error_message = _(": TLS operand can't be a constant"); 2537 goto error; 2538 } 2539 2540 /* Constants that won't fit are checked in md_apply_fix 2541 and bfd_install_relocation. 2542 ??? It would be preferable to install the constants 2543 into the insn here and save having to create a fixS 2544 for each one. There already exists code to handle 2545 all the various cases (e.g. in md_apply_fix and 2546 bfd_install_relocation) so duplicating all that code 2547 here isn't right. */ 2548 } 2549 2550 continue; 2551 2552 case 'a': 2553 if (*s++ == 'a') 2554 { 2555 opcode |= ANNUL; 2556 continue; 2557 } 2558 break; 2559 2560 case 'A': 2561 { 2562 int asi = 0; 2563 2564 /* Parse an asi. */ 2565 if (*s == '#') 2566 { 2567 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2568 { 2569 error_message = _(": invalid ASI name"); 2570 goto error; 2571 } 2572 } 2573 else 2574 { 2575 if (! parse_const_expr_arg (&s, &asi)) 2576 { 2577 error_message = _(": invalid ASI expression"); 2578 goto error; 2579 } 2580 if (asi < 0 || asi > 255) 2581 { 2582 error_message = _(": invalid ASI number"); 2583 goto error; 2584 } 2585 } 2586 opcode |= ASI (asi); 2587 continue; 2588 } /* Alternate space. */ 2589 2590 case 'p': 2591 if (strncmp (s, "%psr", 4) == 0) 2592 { 2593 s += 4; 2594 continue; 2595 } 2596 break; 2597 2598 case 'q': /* Floating point queue. */ 2599 if (strncmp (s, "%fq", 3) == 0) 2600 { 2601 s += 3; 2602 continue; 2603 } 2604 break; 2605 2606 case 'Q': /* Coprocessor queue. */ 2607 if (strncmp (s, "%cq", 3) == 0) 2608 { 2609 s += 3; 2610 continue; 2611 } 2612 break; 2613 2614 case 'S': 2615 if (strcmp (str, "set") == 0 2616 || strcmp (str, "setuw") == 0) 2617 { 2618 special_case = SPECIAL_CASE_SET; 2619 continue; 2620 } 2621 else if (strcmp (str, "setsw") == 0) 2622 { 2623 special_case = SPECIAL_CASE_SETSW; 2624 continue; 2625 } 2626 else if (strcmp (str, "setx") == 0) 2627 { 2628 special_case = SPECIAL_CASE_SETX; 2629 continue; 2630 } 2631 else if (strncmp (str, "fdiv", 4) == 0) 2632 { 2633 special_case = SPECIAL_CASE_FDIV; 2634 continue; 2635 } 2636 break; 2637 2638 case 'o': 2639 if (strncmp (s, "%asi", 4) != 0) 2640 break; 2641 s += 4; 2642 continue; 2643 2644 case 's': 2645 if (strncmp (s, "%fprs", 5) != 0) 2646 break; 2647 s += 5; 2648 continue; 2649 2650 case 'E': 2651 if (strncmp (s, "%ccr", 4) != 0) 2652 break; 2653 s += 4; 2654 continue; 2655 2656 case 't': 2657 if (strncmp (s, "%tbr", 4) != 0) 2658 break; 2659 s += 4; 2660 continue; 2661 2662 case 'w': 2663 if (strncmp (s, "%wim", 4) != 0) 2664 break; 2665 s += 4; 2666 continue; 2667 2668 case 'x': 2669 { 2670 char *push = input_line_pointer; 2671 expressionS e; 2672 2673 input_line_pointer = s; 2674 expression (&e); 2675 if (e.X_op == O_constant) 2676 { 2677 int n = e.X_add_number; 2678 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2679 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2680 else 2681 opcode |= e.X_add_number << 5; 2682 } 2683 else 2684 as_bad (_("non-immediate OPF operand, ignored")); 2685 s = input_line_pointer; 2686 input_line_pointer = push; 2687 continue; 2688 } 2689 2690 case 'y': 2691 if (strncmp (s, "%y", 2) != 0) 2692 break; 2693 s += 2; 2694 continue; 2695 2696 case 'u': 2697 case 'U': 2698 { 2699 /* Parse a sparclet cpreg. */ 2700 int cpreg; 2701 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2702 { 2703 error_message = _(": invalid cpreg name"); 2704 goto error; 2705 } 2706 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2707 continue; 2708 } 2709 2710 default: 2711 as_fatal (_("failed sanity check.")); 2712 } /* switch on arg code. */ 2713 2714 /* Break out of for() loop. */ 2715 break; 2716 } /* For each arg that we expect. */ 2717 2718 error: 2719 if (match == 0) 2720 { 2721 /* Args don't match. */ 2722 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2723 && (insn->name == insn[1].name 2724 || !strcmp (insn->name, insn[1].name))) 2725 { 2726 ++insn; 2727 s = argsStart; 2728 continue; 2729 } 2730 else 2731 { 2732 as_bad (_("Illegal operands%s"), error_message); 2733 return special_case; 2734 } 2735 } 2736 else 2737 { 2738 /* We have a match. Now see if the architecture is OK. */ 2739 int needed_arch_mask = insn->architecture; 2740 2741 if (v9_arg_p) 2742 { 2743 needed_arch_mask &= 2744 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 2745 if (! needed_arch_mask) 2746 needed_arch_mask = 2747 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 2748 } 2749 2750 if (needed_arch_mask 2751 & SPARC_OPCODE_SUPPORTED (current_architecture)) 2752 /* OK. */ 2753 ; 2754 /* Can we bump up the architecture? */ 2755 else if (needed_arch_mask 2756 & SPARC_OPCODE_SUPPORTED (max_architecture)) 2757 { 2758 enum sparc_opcode_arch_val needed_architecture = 2759 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2760 & needed_arch_mask); 2761 2762 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2763 if (warn_on_bump 2764 && needed_architecture > warn_after_architecture) 2765 { 2766 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2767 sparc_opcode_archs[current_architecture].name, 2768 sparc_opcode_archs[needed_architecture].name, 2769 str); 2770 warn_after_architecture = needed_architecture; 2771 } 2772 current_architecture = needed_architecture; 2773 } 2774 /* Conflict. */ 2775 /* ??? This seems to be a bit fragile. What if the next entry in 2776 the opcode table is the one we want and it is supported? 2777 It is possible to arrange the table today so that this can't 2778 happen but what about tomorrow? */ 2779 else 2780 { 2781 int arch, printed_one_p = 0; 2782 char *p; 2783 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2784 2785 /* Create a list of the architectures that support the insn. */ 2786 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 2787 p = required_archs; 2788 arch = sparc_ffs (needed_arch_mask); 2789 while ((1 << arch) <= needed_arch_mask) 2790 { 2791 if ((1 << arch) & needed_arch_mask) 2792 { 2793 if (printed_one_p) 2794 *p++ = '|'; 2795 strcpy (p, sparc_opcode_archs[arch].name); 2796 p += strlen (p); 2797 printed_one_p = 1; 2798 } 2799 ++arch; 2800 } 2801 2802 as_bad (_("Architecture mismatch on \"%s\"."), str); 2803 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2804 required_archs, 2805 sparc_opcode_archs[max_architecture].name); 2806 return special_case; 2807 } 2808 } /* If no match. */ 2809 2810 break; 2811 } /* Forever looking for a match. */ 2812 2813 the_insn.opcode = opcode; 2814 return special_case; 2815} 2816 2817/* Parse an argument that can be expressed as a keyword. 2818 (eg: #StoreStore or %ccfr). 2819 The result is a boolean indicating success. 2820 If successful, INPUT_POINTER is updated. */ 2821 2822static int 2823parse_keyword_arg (lookup_fn, input_pointerP, valueP) 2824 int (*lookup_fn) PARAMS ((const char *)); 2825 char **input_pointerP; 2826 int *valueP; 2827{ 2828 int value; 2829 char c, *p, *q; 2830 2831 p = *input_pointerP; 2832 for (q = p + (*p == '#' || *p == '%'); 2833 ISALNUM (*q) || *q == '_'; 2834 ++q) 2835 continue; 2836 c = *q; 2837 *q = 0; 2838 value = (*lookup_fn) (p); 2839 *q = c; 2840 if (value == -1) 2841 return 0; 2842 *valueP = value; 2843 *input_pointerP = q; 2844 return 1; 2845} 2846 2847/* Parse an argument that is a constant expression. 2848 The result is a boolean indicating success. */ 2849 2850static int 2851parse_const_expr_arg (input_pointerP, valueP) 2852 char **input_pointerP; 2853 int *valueP; 2854{ 2855 char *save = input_line_pointer; 2856 expressionS exp; 2857 2858 input_line_pointer = *input_pointerP; 2859 /* The next expression may be something other than a constant 2860 (say if we're not processing the right variant of the insn). 2861 Don't call expression unless we're sure it will succeed as it will 2862 signal an error (which we want to defer until later). */ 2863 /* FIXME: It might be better to define md_operand and have it recognize 2864 things like %asi, etc. but continuing that route through to the end 2865 is a lot of work. */ 2866 if (*input_line_pointer == '%') 2867 { 2868 input_line_pointer = save; 2869 return 0; 2870 } 2871 expression (&exp); 2872 *input_pointerP = input_line_pointer; 2873 input_line_pointer = save; 2874 if (exp.X_op != O_constant) 2875 return 0; 2876 *valueP = exp.X_add_number; 2877 return 1; 2878} 2879 2880/* Subroutine of sparc_ip to parse an expression. */ 2881 2882static int 2883get_expression (str) 2884 char *str; 2885{ 2886 char *save_in; 2887 segT seg; 2888 2889 save_in = input_line_pointer; 2890 input_line_pointer = str; 2891 seg = expression (&the_insn.exp); 2892 if (seg != absolute_section 2893 && seg != text_section 2894 && seg != data_section 2895 && seg != bss_section 2896 && seg != undefined_section) 2897 { 2898 the_insn.error = _("bad segment"); 2899 expr_end = input_line_pointer; 2900 input_line_pointer = save_in; 2901 return 1; 2902 } 2903 expr_end = input_line_pointer; 2904 input_line_pointer = save_in; 2905 return 0; 2906} 2907 2908/* Subroutine of md_assemble to output one insn. */ 2909 2910static void 2911output_insn (insn, the_insn) 2912 const struct sparc_opcode *insn; 2913 struct sparc_it *the_insn; 2914{ 2915 char *toP = frag_more (4); 2916 2917 /* Put out the opcode. */ 2918 if (INSN_BIG_ENDIAN) 2919 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); 2920 else 2921 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); 2922 2923 /* Put out the symbol-dependent stuff. */ 2924 if (the_insn->reloc != BFD_RELOC_NONE) 2925 { 2926 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 2927 (toP - frag_now->fr_literal), /* Where. */ 2928 4, /* Size. */ 2929 &the_insn->exp, 2930 the_insn->pcrel, 2931 the_insn->reloc); 2932 /* Turn off overflow checking in fixup_segment. We'll do our 2933 own overflow checking in md_apply_fix. This is necessary because 2934 the insn size is 4 and fixup_segment will signal an overflow for 2935 large 8 byte quantities. */ 2936 fixP->fx_no_overflow = 1; 2937 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) 2938 fixP->tc_fix_data = the_insn->exp2.X_add_number; 2939 } 2940 2941 last_insn = insn; 2942 last_opcode = the_insn->opcode; 2943 2944#ifdef OBJ_ELF 2945 dwarf2_emit_insn (4); 2946#endif 2947} 2948 2949/* This is identical to the md_atof in m68k.c. I think this is right, 2950 but I'm not sure. 2951 2952 Turn a string in input_line_pointer into a floating point constant 2953 of type TYPE, and store the appropriate bytes in *LITP. The number 2954 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2955 returned, or NULL on OK. */ 2956 2957/* Equal to MAX_PRECISION in atof-ieee.c. */ 2958#define MAX_LITTLENUMS 6 2959 2960char * 2961md_atof (type, litP, sizeP) 2962 char type; 2963 char *litP; 2964 int *sizeP; 2965{ 2966 int i, prec; 2967 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2968 char *t; 2969 2970 switch (type) 2971 { 2972 case 'f': 2973 case 'F': 2974 case 's': 2975 case 'S': 2976 prec = 2; 2977 break; 2978 2979 case 'd': 2980 case 'D': 2981 case 'r': 2982 case 'R': 2983 prec = 4; 2984 break; 2985 2986 case 'x': 2987 case 'X': 2988 prec = 6; 2989 break; 2990 2991 case 'p': 2992 case 'P': 2993 prec = 6; 2994 break; 2995 2996 default: 2997 *sizeP = 0; 2998 return _("Bad call to MD_ATOF()"); 2999 } 3000 3001 t = atof_ieee (input_line_pointer, type, words); 3002 if (t) 3003 input_line_pointer = t; 3004 *sizeP = prec * sizeof (LITTLENUM_TYPE); 3005 3006 if (target_big_endian) 3007 { 3008 for (i = 0; i < prec; i++) 3009 { 3010 md_number_to_chars (litP, (valueT) words[i], 3011 sizeof (LITTLENUM_TYPE)); 3012 litP += sizeof (LITTLENUM_TYPE); 3013 } 3014 } 3015 else 3016 { 3017 for (i = prec - 1; i >= 0; i--) 3018 { 3019 md_number_to_chars (litP, (valueT) words[i], 3020 sizeof (LITTLENUM_TYPE)); 3021 litP += sizeof (LITTLENUM_TYPE); 3022 } 3023 } 3024 3025 return 0; 3026} 3027 3028/* Write a value out to the object file, using the appropriate 3029 endianness. */ 3030 3031void 3032md_number_to_chars (buf, val, n) 3033 char *buf; 3034 valueT val; 3035 int n; 3036{ 3037 if (target_big_endian) 3038 number_to_chars_bigendian (buf, val, n); 3039 else if (target_little_endian_data 3040 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3041 /* Output debug words, which are not in allocated sections, as big 3042 endian. */ 3043 number_to_chars_bigendian (buf, val, n); 3044 else if (target_little_endian_data || ! target_big_endian) 3045 number_to_chars_littleendian (buf, val, n); 3046} 3047 3048/* Apply a fixS to the frags, now that we know the value it ought to 3049 hold. */ 3050 3051void 3052md_apply_fix (fixP, valP, segment) 3053 fixS *fixP; 3054 valueT *valP; 3055 segT segment ATTRIBUTE_UNUSED; 3056{ 3057 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3058 offsetT val = * (offsetT *) valP; 3059 long insn; 3060 3061 assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3062 3063 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3064 3065#ifdef OBJ_ELF 3066 /* SPARC ELF relocations don't use an addend in the data field. */ 3067 if (fixP->fx_addsy != NULL) 3068 { 3069 switch (fixP->fx_r_type) 3070 { 3071 case BFD_RELOC_SPARC_TLS_GD_HI22: 3072 case BFD_RELOC_SPARC_TLS_GD_LO10: 3073 case BFD_RELOC_SPARC_TLS_GD_ADD: 3074 case BFD_RELOC_SPARC_TLS_GD_CALL: 3075 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3076 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3077 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3078 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3079 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3080 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3081 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3082 case BFD_RELOC_SPARC_TLS_IE_HI22: 3083 case BFD_RELOC_SPARC_TLS_IE_LO10: 3084 case BFD_RELOC_SPARC_TLS_IE_LD: 3085 case BFD_RELOC_SPARC_TLS_IE_LDX: 3086 case BFD_RELOC_SPARC_TLS_IE_ADD: 3087 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3088 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3089 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3090 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3091 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3092 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3093 case BFD_RELOC_SPARC_TLS_TPOFF32: 3094 case BFD_RELOC_SPARC_TLS_TPOFF64: 3095 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3096 3097 default: 3098 break; 3099 } 3100 3101 return; 3102 } 3103#endif 3104 3105 /* This is a hack. There should be a better way to 3106 handle this. Probably in terms of howto fields, once 3107 we can look at these fixups in terms of howtos. */ 3108 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3109 val += fixP->fx_where + fixP->fx_frag->fr_address; 3110 3111#ifdef OBJ_AOUT 3112 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3113 generate a reloc, then we just want to let the reloc addend set 3114 the value. We do not want to also stuff the addend into the 3115 object file. Including the addend in the object file works when 3116 doing a static link, because the linker will ignore the object 3117 file contents. However, the dynamic linker does not ignore the 3118 object file contents. */ 3119 if (fixP->fx_addsy != NULL 3120 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3121 val = 0; 3122 3123 /* When generating PIC code, we do not want an addend for a reloc 3124 against a local symbol. We adjust fx_addnumber to cancel out the 3125 value already included in val, and to also cancel out the 3126 adjustment which bfd_install_relocation will create. */ 3127 if (sparc_pic_code 3128 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3129 && fixP->fx_addsy != NULL 3130 && ! S_IS_COMMON (fixP->fx_addsy) 3131 && symbol_section_p (fixP->fx_addsy)) 3132 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3133 3134 /* When generating PIC code, we need to fiddle to get 3135 bfd_install_relocation to do the right thing for a PC relative 3136 reloc against a local symbol which we are going to keep. */ 3137 if (sparc_pic_code 3138 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3139 && fixP->fx_addsy != NULL 3140 && (S_IS_EXTERNAL (fixP->fx_addsy) 3141 || S_IS_WEAK (fixP->fx_addsy)) 3142 && S_IS_DEFINED (fixP->fx_addsy) 3143 && ! S_IS_COMMON (fixP->fx_addsy)) 3144 { 3145 val = 0; 3146 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3147 } 3148#endif 3149 3150 /* If this is a data relocation, just output VAL. */ 3151 3152 if (fixP->fx_r_type == BFD_RELOC_16 3153 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3154 { 3155 md_number_to_chars (buf, val, 2); 3156 } 3157 else if (fixP->fx_r_type == BFD_RELOC_32 3158 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3159 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3160 { 3161 md_number_to_chars (buf, val, 4); 3162 } 3163 else if (fixP->fx_r_type == BFD_RELOC_64 3164 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3165 { 3166 md_number_to_chars (buf, val, 8); 3167 } 3168 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3169 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3170 { 3171 fixP->fx_done = 0; 3172 return; 3173 } 3174 else 3175 { 3176 /* It's a relocation against an instruction. */ 3177 3178 if (INSN_BIG_ENDIAN) 3179 insn = bfd_getb32 ((unsigned char *) buf); 3180 else 3181 insn = bfd_getl32 ((unsigned char *) buf); 3182 3183 switch (fixP->fx_r_type) 3184 { 3185 case BFD_RELOC_32_PCREL_S2: 3186 val = val >> 2; 3187 /* FIXME: This increment-by-one deserves a comment of why it's 3188 being done! */ 3189 if (! sparc_pic_code 3190 || fixP->fx_addsy == NULL 3191 || symbol_section_p (fixP->fx_addsy)) 3192 ++val; 3193 3194 insn |= val & 0x3fffffff; 3195 3196 /* See if we have a delay slot. */ 3197 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3198 { 3199#define G0 0 3200#define O7 15 3201#define XCC (2 << 20) 3202#define COND(x) (((x)&0xf)<<25) 3203#define CONDA COND(0x8) 3204#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3205#define INSN_BA (F2(0,2) | CONDA) 3206#define INSN_OR F3(2, 0x2, 0) 3207#define INSN_NOP F2(0,4) 3208 3209 long delay; 3210 3211 /* If the instruction is a call with either: 3212 restore 3213 arithmetic instruction with rd == %o7 3214 where rs1 != %o7 and rs2 if it is register != %o7 3215 then we can optimize if the call destination is near 3216 by changing the call into a branch always. */ 3217 if (INSN_BIG_ENDIAN) 3218 delay = bfd_getb32 ((unsigned char *) buf + 4); 3219 else 3220 delay = bfd_getl32 ((unsigned char *) buf + 4); 3221 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3222 break; 3223 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3224 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3225 || ((delay & RD (~0)) != RD (O7)))) 3226 break; 3227 if ((delay & RS1 (~0)) == RS1 (O7) 3228 || ((delay & F3I (~0)) == 0 3229 && (delay & RS2 (~0)) == RS2 (O7))) 3230 break; 3231 /* Ensure the branch will fit into simm22. */ 3232 if ((val & 0x3fe00000) 3233 && (val & 0x3fe00000) != 0x3fe00000) 3234 break; 3235 /* Check if the arch is v9 and branch will fit 3236 into simm19. */ 3237 if (((val & 0x3c0000) == 0 3238 || (val & 0x3c0000) == 0x3c0000) 3239 && (sparc_arch_size == 64 3240 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3241 /* ba,pt %xcc */ 3242 insn = INSN_BPA | (val & 0x7ffff); 3243 else 3244 /* ba */ 3245 insn = INSN_BA | (val & 0x3fffff); 3246 if (fixP->fx_where >= 4 3247 && ((delay & (0xffffffff ^ RS1 (~0))) 3248 == (INSN_OR | RD (O7) | RS2 (G0)))) 3249 { 3250 long setter; 3251 int reg; 3252 3253 if (INSN_BIG_ENDIAN) 3254 setter = bfd_getb32 ((unsigned char *) buf - 4); 3255 else 3256 setter = bfd_getl32 ((unsigned char *) buf - 4); 3257 if ((setter & (0xffffffff ^ RD (~0))) 3258 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3259 break; 3260 /* The sequence was 3261 or %o7, %g0, %rN 3262 call foo 3263 or %rN, %g0, %o7 3264 3265 If call foo was replaced with ba, replace 3266 or %rN, %g0, %o7 with nop. */ 3267 reg = (delay & RS1 (~0)) >> 14; 3268 if (reg != ((setter & RD (~0)) >> 25) 3269 || reg == G0 || reg == O7) 3270 break; 3271 3272 if (INSN_BIG_ENDIAN) 3273 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3274 else 3275 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3276 } 3277 } 3278 break; 3279 3280 case BFD_RELOC_SPARC_11: 3281 if (! in_signed_range (val, 0x7ff)) 3282 as_bad_where (fixP->fx_file, fixP->fx_line, 3283 _("relocation overflow")); 3284 insn |= val & 0x7ff; 3285 break; 3286 3287 case BFD_RELOC_SPARC_10: 3288 if (! in_signed_range (val, 0x3ff)) 3289 as_bad_where (fixP->fx_file, fixP->fx_line, 3290 _("relocation overflow")); 3291 insn |= val & 0x3ff; 3292 break; 3293 3294 case BFD_RELOC_SPARC_7: 3295 if (! in_bitfield_range (val, 0x7f)) 3296 as_bad_where (fixP->fx_file, fixP->fx_line, 3297 _("relocation overflow")); 3298 insn |= val & 0x7f; 3299 break; 3300 3301 case BFD_RELOC_SPARC_6: 3302 if (! in_bitfield_range (val, 0x3f)) 3303 as_bad_where (fixP->fx_file, fixP->fx_line, 3304 _("relocation overflow")); 3305 insn |= val & 0x3f; 3306 break; 3307 3308 case BFD_RELOC_SPARC_5: 3309 if (! in_bitfield_range (val, 0x1f)) 3310 as_bad_where (fixP->fx_file, fixP->fx_line, 3311 _("relocation overflow")); 3312 insn |= val & 0x1f; 3313 break; 3314 3315 case BFD_RELOC_SPARC_WDISP16: 3316 if ((val & 3) 3317 || val >= 0x1fffc 3318 || val <= -(offsetT) 0x20008) 3319 as_bad_where (fixP->fx_file, fixP->fx_line, 3320 _("relocation overflow")); 3321 /* FIXME: The +1 deserves a comment. */ 3322 val = (val >> 2) + 1; 3323 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3324 break; 3325 3326 case BFD_RELOC_SPARC_WDISP19: 3327 if ((val & 3) 3328 || val >= 0xffffc 3329 || val <= -(offsetT) 0x100008) 3330 as_bad_where (fixP->fx_file, fixP->fx_line, 3331 _("relocation overflow")); 3332 /* FIXME: The +1 deserves a comment. */ 3333 val = (val >> 2) + 1; 3334 insn |= val & 0x7ffff; 3335 break; 3336 3337 case BFD_RELOC_SPARC_HH22: 3338 val = BSR (val, 32); 3339 /* Fall through. */ 3340 3341 case BFD_RELOC_SPARC_LM22: 3342 case BFD_RELOC_HI22: 3343 if (!fixP->fx_addsy) 3344 insn |= (val >> 10) & 0x3fffff; 3345 else 3346 /* FIXME: Need comment explaining why we do this. */ 3347 insn &= ~0xffff; 3348 break; 3349 3350 case BFD_RELOC_SPARC22: 3351 if (val & ~0x003fffff) 3352 as_bad_where (fixP->fx_file, fixP->fx_line, 3353 _("relocation overflow")); 3354 insn |= (val & 0x3fffff); 3355 break; 3356 3357 case BFD_RELOC_SPARC_HM10: 3358 val = BSR (val, 32); 3359 /* Fall through. */ 3360 3361 case BFD_RELOC_LO10: 3362 if (!fixP->fx_addsy) 3363 insn |= val & 0x3ff; 3364 else 3365 /* FIXME: Need comment explaining why we do this. */ 3366 insn &= ~0xff; 3367 break; 3368 3369 case BFD_RELOC_SPARC_OLO10: 3370 val &= 0x3ff; 3371 val += fixP->tc_fix_data; 3372 /* Fall through. */ 3373 3374 case BFD_RELOC_SPARC13: 3375 if (! in_signed_range (val, 0x1fff)) 3376 as_bad_where (fixP->fx_file, fixP->fx_line, 3377 _("relocation overflow")); 3378 insn |= val & 0x1fff; 3379 break; 3380 3381 case BFD_RELOC_SPARC_WDISP22: 3382 val = (val >> 2) + 1; 3383 /* Fall through. */ 3384 case BFD_RELOC_SPARC_BASE22: 3385 insn |= val & 0x3fffff; 3386 break; 3387 3388 case BFD_RELOC_SPARC_H44: 3389 if (!fixP->fx_addsy) 3390 { 3391 bfd_vma tval = val; 3392 tval >>= 22; 3393 insn |= tval & 0x3fffff; 3394 } 3395 break; 3396 3397 case BFD_RELOC_SPARC_M44: 3398 if (!fixP->fx_addsy) 3399 insn |= (val >> 12) & 0x3ff; 3400 break; 3401 3402 case BFD_RELOC_SPARC_L44: 3403 if (!fixP->fx_addsy) 3404 insn |= val & 0xfff; 3405 break; 3406 3407 case BFD_RELOC_SPARC_HIX22: 3408 if (!fixP->fx_addsy) 3409 { 3410 val ^= ~(offsetT) 0; 3411 insn |= (val >> 10) & 0x3fffff; 3412 } 3413 break; 3414 3415 case BFD_RELOC_SPARC_LOX10: 3416 if (!fixP->fx_addsy) 3417 insn |= 0x1c00 | (val & 0x3ff); 3418 break; 3419 3420 case BFD_RELOC_NONE: 3421 default: 3422 as_bad_where (fixP->fx_file, fixP->fx_line, 3423 _("bad or unhandled relocation type: 0x%02x"), 3424 fixP->fx_r_type); 3425 break; 3426 } 3427 3428 if (INSN_BIG_ENDIAN) 3429 bfd_putb32 (insn, (unsigned char *) buf); 3430 else 3431 bfd_putl32 (insn, (unsigned char *) buf); 3432 } 3433 3434 /* Are we finished with this relocation now? */ 3435 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3436 fixP->fx_done = 1; 3437} 3438 3439/* Translate internal representation of relocation info to BFD target 3440 format. */ 3441 3442arelent ** 3443tc_gen_reloc (section, fixp) 3444 asection *section; 3445 fixS *fixp; 3446{ 3447 static arelent *relocs[3]; 3448 arelent *reloc; 3449 bfd_reloc_code_real_type code; 3450 3451 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3452 relocs[1] = NULL; 3453 3454 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3455 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3456 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3457 3458 switch (fixp->fx_r_type) 3459 { 3460 case BFD_RELOC_16: 3461 case BFD_RELOC_32: 3462 case BFD_RELOC_HI22: 3463 case BFD_RELOC_LO10: 3464 case BFD_RELOC_32_PCREL_S2: 3465 case BFD_RELOC_SPARC13: 3466 case BFD_RELOC_SPARC22: 3467 case BFD_RELOC_SPARC_BASE13: 3468 case BFD_RELOC_SPARC_WDISP16: 3469 case BFD_RELOC_SPARC_WDISP19: 3470 case BFD_RELOC_SPARC_WDISP22: 3471 case BFD_RELOC_64: 3472 case BFD_RELOC_SPARC_5: 3473 case BFD_RELOC_SPARC_6: 3474 case BFD_RELOC_SPARC_7: 3475 case BFD_RELOC_SPARC_10: 3476 case BFD_RELOC_SPARC_11: 3477 case BFD_RELOC_SPARC_HH22: 3478 case BFD_RELOC_SPARC_HM10: 3479 case BFD_RELOC_SPARC_LM22: 3480 case BFD_RELOC_SPARC_PC_HH22: 3481 case BFD_RELOC_SPARC_PC_HM10: 3482 case BFD_RELOC_SPARC_PC_LM22: 3483 case BFD_RELOC_SPARC_H44: 3484 case BFD_RELOC_SPARC_M44: 3485 case BFD_RELOC_SPARC_L44: 3486 case BFD_RELOC_SPARC_HIX22: 3487 case BFD_RELOC_SPARC_LOX10: 3488 case BFD_RELOC_SPARC_REV32: 3489 case BFD_RELOC_SPARC_OLO10: 3490 case BFD_RELOC_SPARC_UA16: 3491 case BFD_RELOC_SPARC_UA32: 3492 case BFD_RELOC_SPARC_UA64: 3493 case BFD_RELOC_8_PCREL: 3494 case BFD_RELOC_16_PCREL: 3495 case BFD_RELOC_32_PCREL: 3496 case BFD_RELOC_64_PCREL: 3497 case BFD_RELOC_SPARC_PLT32: 3498 case BFD_RELOC_SPARC_PLT64: 3499 case BFD_RELOC_VTABLE_ENTRY: 3500 case BFD_RELOC_VTABLE_INHERIT: 3501 case BFD_RELOC_SPARC_TLS_GD_HI22: 3502 case BFD_RELOC_SPARC_TLS_GD_LO10: 3503 case BFD_RELOC_SPARC_TLS_GD_ADD: 3504 case BFD_RELOC_SPARC_TLS_GD_CALL: 3505 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3506 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3507 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3508 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3509 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3510 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3511 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3512 case BFD_RELOC_SPARC_TLS_IE_HI22: 3513 case BFD_RELOC_SPARC_TLS_IE_LO10: 3514 case BFD_RELOC_SPARC_TLS_IE_LD: 3515 case BFD_RELOC_SPARC_TLS_IE_LDX: 3516 case BFD_RELOC_SPARC_TLS_IE_ADD: 3517 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3518 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3519 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3520 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3521 code = fixp->fx_r_type; 3522 break; 3523 default: 3524 abort (); 3525 return NULL; 3526 } 3527 3528#if defined (OBJ_ELF) || defined (OBJ_AOUT) 3529 /* If we are generating PIC code, we need to generate a different 3530 set of relocs. */ 3531 3532#ifdef OBJ_ELF 3533#define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3534#else 3535#define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3536#endif 3537#ifdef TE_VXWORKS 3538#define GOTT_BASE "__GOTT_BASE__" 3539#define GOTT_INDEX "__GOTT_INDEX__" 3540#endif 3541 3542 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3543 3544 if (sparc_pic_code) 3545 { 3546 switch (code) 3547 { 3548 case BFD_RELOC_32_PCREL_S2: 3549 if (generic_force_reloc (fixp)) 3550 code = BFD_RELOC_SPARC_WPLT30; 3551 break; 3552 case BFD_RELOC_HI22: 3553 code = BFD_RELOC_SPARC_GOT22; 3554 if (fixp->fx_addsy != NULL) 3555 { 3556 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3557 code = BFD_RELOC_SPARC_PC22; 3558#ifdef TE_VXWORKS 3559 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3560 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3561 code = BFD_RELOC_HI22; /* Unchanged. */ 3562#endif 3563 } 3564 break; 3565 case BFD_RELOC_LO10: 3566 code = BFD_RELOC_SPARC_GOT10; 3567 if (fixp->fx_addsy != NULL) 3568 { 3569 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3570 code = BFD_RELOC_SPARC_PC10; 3571#ifdef TE_VXWORKS 3572 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3573 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3574 code = BFD_RELOC_LO10; /* Unchanged. */ 3575#endif 3576 } 3577 break; 3578 case BFD_RELOC_SPARC13: 3579 code = BFD_RELOC_SPARC_GOT13; 3580 break; 3581 default: 3582 break; 3583 } 3584 } 3585#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3586 3587 /* Nothing is aligned in DWARF debugging sections. */ 3588 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) 3589 switch (code) 3590 { 3591 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; 3592 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; 3593 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; 3594 default: break; 3595 } 3596 3597 if (code == BFD_RELOC_SPARC_OLO10) 3598 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3599 else 3600 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3601 if (reloc->howto == 0) 3602 { 3603 as_bad_where (fixp->fx_file, fixp->fx_line, 3604 _("internal error: can't export reloc type %d (`%s')"), 3605 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3606 xfree (reloc); 3607 relocs[0] = NULL; 3608 return relocs; 3609 } 3610 3611 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3612#ifdef OBJ_AOUT 3613 3614 if (reloc->howto->pc_relative == 0 3615 || code == BFD_RELOC_SPARC_PC10 3616 || code == BFD_RELOC_SPARC_PC22) 3617 reloc->addend = fixp->fx_addnumber; 3618 else if (sparc_pic_code 3619 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3620 && fixp->fx_addsy != NULL 3621 && (S_IS_EXTERNAL (fixp->fx_addsy) 3622 || S_IS_WEAK (fixp->fx_addsy)) 3623 && S_IS_DEFINED (fixp->fx_addsy) 3624 && ! S_IS_COMMON (fixp->fx_addsy)) 3625 reloc->addend = fixp->fx_addnumber; 3626 else 3627 reloc->addend = fixp->fx_offset - reloc->address; 3628 3629#else /* elf or coff */ 3630 3631 if (code != BFD_RELOC_32_PCREL_S2 3632 && code != BFD_RELOC_SPARC_WDISP22 3633 && code != BFD_RELOC_SPARC_WDISP16 3634 && code != BFD_RELOC_SPARC_WDISP19 3635 && code != BFD_RELOC_SPARC_WPLT30 3636 && code != BFD_RELOC_SPARC_TLS_GD_CALL 3637 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 3638 reloc->addend = fixp->fx_addnumber; 3639 else if (symbol_section_p (fixp->fx_addsy)) 3640 reloc->addend = (section->vma 3641 + fixp->fx_addnumber 3642 + md_pcrel_from (fixp)); 3643 else 3644 reloc->addend = fixp->fx_offset; 3645#endif 3646 3647 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3648 on the same location. */ 3649 if (code == BFD_RELOC_SPARC_OLO10) 3650 { 3651 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3652 relocs[2] = NULL; 3653 3654 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3655 *reloc->sym_ptr_ptr 3656 = symbol_get_bfdsym (section_symbol (absolute_section)); 3657 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3658 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3659 reloc->addend = fixp->tc_fix_data; 3660 } 3661 3662 return relocs; 3663} 3664 3665/* We have no need to default values of symbols. */ 3666 3667symbolS * 3668md_undefined_symbol (name) 3669 char *name ATTRIBUTE_UNUSED; 3670{ 3671 return 0; 3672} 3673 3674/* Round up a section size to the appropriate boundary. */ 3675 3676valueT 3677md_section_align (segment, size) 3678 segT segment ATTRIBUTE_UNUSED; 3679 valueT size; 3680{ 3681#ifndef OBJ_ELF 3682 /* This is not right for ELF; a.out wants it, and COFF will force 3683 the alignment anyways. */ 3684 valueT align = ((valueT) 1 3685 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3686 valueT newsize; 3687 3688 /* Turn alignment value into a mask. */ 3689 align--; 3690 newsize = (size + align) & ~align; 3691 return newsize; 3692#else 3693 return size; 3694#endif 3695} 3696 3697/* Exactly what point is a PC-relative offset relative TO? 3698 On the sparc, they're relative to the address of the offset, plus 3699 its size. This gets us to the following instruction. 3700 (??? Is this right? FIXME-SOON) */ 3701long 3702md_pcrel_from (fixP) 3703 fixS *fixP; 3704{ 3705 long ret; 3706 3707 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3708 if (! sparc_pic_code 3709 || fixP->fx_addsy == NULL 3710 || symbol_section_p (fixP->fx_addsy)) 3711 ret += fixP->fx_size; 3712 return ret; 3713} 3714 3715/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3716 of two. */ 3717 3718static int 3719mylog2 (value) 3720 int value; 3721{ 3722 int shift; 3723 3724 if (value <= 0) 3725 return -1; 3726 3727 for (shift = 0; (value & 1) == 0; value >>= 1) 3728 ++shift; 3729 3730 return (value == 1) ? shift : -1; 3731} 3732 3733/* Sort of like s_lcomm. */ 3734 3735#ifndef OBJ_ELF 3736static int max_alignment = 15; 3737#endif 3738 3739static void 3740s_reserve (ignore) 3741 int ignore ATTRIBUTE_UNUSED; 3742{ 3743 char *name; 3744 char *p; 3745 char c; 3746 int align; 3747 int size; 3748 int temp; 3749 symbolS *symbolP; 3750 3751 name = input_line_pointer; 3752 c = get_symbol_end (); 3753 p = input_line_pointer; 3754 *p = c; 3755 SKIP_WHITESPACE (); 3756 3757 if (*input_line_pointer != ',') 3758 { 3759 as_bad (_("Expected comma after name")); 3760 ignore_rest_of_line (); 3761 return; 3762 } 3763 3764 ++input_line_pointer; 3765 3766 if ((size = get_absolute_expression ()) < 0) 3767 { 3768 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3769 ignore_rest_of_line (); 3770 return; 3771 } /* Bad length. */ 3772 3773 *p = 0; 3774 symbolP = symbol_find_or_make (name); 3775 *p = c; 3776 3777 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3778 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3779 { 3780 as_bad (_("bad .reserve segment -- expected BSS segment")); 3781 return; 3782 } 3783 3784 if (input_line_pointer[2] == '.') 3785 input_line_pointer += 7; 3786 else 3787 input_line_pointer += 6; 3788 SKIP_WHITESPACE (); 3789 3790 if (*input_line_pointer == ',') 3791 { 3792 ++input_line_pointer; 3793 3794 SKIP_WHITESPACE (); 3795 if (*input_line_pointer == '\n') 3796 { 3797 as_bad (_("missing alignment")); 3798 ignore_rest_of_line (); 3799 return; 3800 } 3801 3802 align = (int) get_absolute_expression (); 3803 3804#ifndef OBJ_ELF 3805 if (align > max_alignment) 3806 { 3807 align = max_alignment; 3808 as_warn (_("alignment too large; assuming %d"), align); 3809 } 3810#endif 3811 3812 if (align < 0) 3813 { 3814 as_bad (_("negative alignment")); 3815 ignore_rest_of_line (); 3816 return; 3817 } 3818 3819 if (align != 0) 3820 { 3821 temp = mylog2 (align); 3822 if (temp < 0) 3823 { 3824 as_bad (_("alignment not a power of 2")); 3825 ignore_rest_of_line (); 3826 return; 3827 } 3828 3829 align = temp; 3830 } 3831 3832 record_alignment (bss_section, align); 3833 } 3834 else 3835 align = 0; 3836 3837 if (!S_IS_DEFINED (symbolP) 3838#ifdef OBJ_AOUT 3839 && S_GET_OTHER (symbolP) == 0 3840 && S_GET_DESC (symbolP) == 0 3841#endif 3842 ) 3843 { 3844 if (! need_pass_2) 3845 { 3846 char *pfrag; 3847 segT current_seg = now_seg; 3848 subsegT current_subseg = now_subseg; 3849 3850 /* Switch to bss. */ 3851 subseg_set (bss_section, 1); 3852 3853 if (align) 3854 /* Do alignment. */ 3855 frag_align (align, 0, 0); 3856 3857 /* Detach from old frag. */ 3858 if (S_GET_SEGMENT (symbolP) == bss_section) 3859 symbol_get_frag (symbolP)->fr_symbol = NULL; 3860 3861 symbol_set_frag (symbolP, frag_now); 3862 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3863 (offsetT) size, (char *) 0); 3864 *pfrag = 0; 3865 3866 S_SET_SEGMENT (symbolP, bss_section); 3867 3868 subseg_set (current_seg, current_subseg); 3869 3870#ifdef OBJ_ELF 3871 S_SET_SIZE (symbolP, size); 3872#endif 3873 } 3874 } 3875 else 3876 { 3877 as_warn ("Ignoring attempt to re-define symbol %s", 3878 S_GET_NAME (symbolP)); 3879 } /* if not redefining. */ 3880 3881 demand_empty_rest_of_line (); 3882} 3883 3884static void 3885s_common (ignore) 3886 int ignore ATTRIBUTE_UNUSED; 3887{ 3888 char *name; 3889 char c; 3890 char *p; 3891 offsetT temp, size; 3892 symbolS *symbolP; 3893 3894 name = input_line_pointer; 3895 c = get_symbol_end (); 3896 /* Just after name is now '\0'. */ 3897 p = input_line_pointer; 3898 *p = c; 3899 SKIP_WHITESPACE (); 3900 if (*input_line_pointer != ',') 3901 { 3902 as_bad (_("Expected comma after symbol-name")); 3903 ignore_rest_of_line (); 3904 return; 3905 } 3906 3907 /* Skip ','. */ 3908 input_line_pointer++; 3909 3910 if ((temp = get_absolute_expression ()) < 0) 3911 { 3912 as_bad (_(".COMMon length (%lu) out of range ignored"), 3913 (unsigned long) temp); 3914 ignore_rest_of_line (); 3915 return; 3916 } 3917 size = temp; 3918 *p = 0; 3919 symbolP = symbol_find_or_make (name); 3920 *p = c; 3921 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 3922 { 3923 as_bad (_("Ignoring attempt to re-define symbol")); 3924 ignore_rest_of_line (); 3925 return; 3926 } 3927 if (S_GET_VALUE (symbolP) != 0) 3928 { 3929 if (S_GET_VALUE (symbolP) != (valueT) size) 3930 { 3931 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 3932 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 3933 } 3934 } 3935 else 3936 { 3937#ifndef OBJ_ELF 3938 S_SET_VALUE (symbolP, (valueT) size); 3939 S_SET_EXTERNAL (symbolP); 3940#endif 3941 } 3942 know (symbol_get_frag (symbolP) == &zero_address_frag); 3943 if (*input_line_pointer != ',') 3944 { 3945 as_bad (_("Expected comma after common length")); 3946 ignore_rest_of_line (); 3947 return; 3948 } 3949 input_line_pointer++; 3950 SKIP_WHITESPACE (); 3951 if (*input_line_pointer != '"') 3952 { 3953 temp = get_absolute_expression (); 3954 3955#ifndef OBJ_ELF 3956 if (temp > max_alignment) 3957 { 3958 temp = max_alignment; 3959 as_warn (_("alignment too large; assuming %ld"), (long) temp); 3960 } 3961#endif 3962 3963 if (temp < 0) 3964 { 3965 as_bad (_("negative alignment")); 3966 ignore_rest_of_line (); 3967 return; 3968 } 3969 3970#ifdef OBJ_ELF 3971 if (symbol_get_obj (symbolP)->local) 3972 { 3973 segT old_sec; 3974 int old_subsec; 3975 char *p; 3976 int align; 3977 3978 old_sec = now_seg; 3979 old_subsec = now_subseg; 3980 3981 if (temp == 0) 3982 align = 0; 3983 else 3984 align = mylog2 (temp); 3985 3986 if (align < 0) 3987 { 3988 as_bad (_("alignment not a power of 2")); 3989 ignore_rest_of_line (); 3990 return; 3991 } 3992 3993 record_alignment (bss_section, align); 3994 subseg_set (bss_section, 0); 3995 if (align) 3996 frag_align (align, 0, 0); 3997 if (S_GET_SEGMENT (symbolP) == bss_section) 3998 symbol_get_frag (symbolP)->fr_symbol = 0; 3999 symbol_set_frag (symbolP, frag_now); 4000 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4001 (offsetT) size, (char *) 0); 4002 *p = 0; 4003 S_SET_SEGMENT (symbolP, bss_section); 4004 S_CLEAR_EXTERNAL (symbolP); 4005 S_SET_SIZE (symbolP, size); 4006 subseg_set (old_sec, old_subsec); 4007 } 4008 else 4009#endif /* OBJ_ELF */ 4010 { 4011 allocate_common: 4012 S_SET_VALUE (symbolP, (valueT) size); 4013#ifdef OBJ_ELF 4014 S_SET_ALIGN (symbolP, temp); 4015 S_SET_SIZE (symbolP, size); 4016#endif 4017 S_SET_EXTERNAL (symbolP); 4018 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 4019 } 4020 } 4021 else 4022 { 4023 input_line_pointer++; 4024 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4025 if (*input_line_pointer == '.') 4026 input_line_pointer++; 4027 /* @@ Some say data, some say bss. */ 4028 if (strncmp (input_line_pointer, "bss\"", 4) 4029 && strncmp (input_line_pointer, "data\"", 5)) 4030 { 4031 while (*--input_line_pointer != '"') 4032 ; 4033 input_line_pointer--; 4034 goto bad_common_segment; 4035 } 4036 while (*input_line_pointer++ != '"') 4037 ; 4038 goto allocate_common; 4039 } 4040 4041 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4042 4043 demand_empty_rest_of_line (); 4044 return; 4045 4046 { 4047 bad_common_segment: 4048 p = input_line_pointer; 4049 while (*p && *p != '\n') 4050 p++; 4051 c = *p; 4052 *p = '\0'; 4053 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4054 *p = c; 4055 input_line_pointer = p; 4056 ignore_rest_of_line (); 4057 return; 4058 } 4059} 4060 4061/* Handle the .empty pseudo-op. This suppresses the warnings about 4062 invalid delay slot usage. */ 4063 4064static void 4065s_empty (ignore) 4066 int ignore ATTRIBUTE_UNUSED; 4067{ 4068 /* The easy way to implement is to just forget about the last 4069 instruction. */ 4070 last_insn = NULL; 4071} 4072 4073static void 4074s_seg (ignore) 4075 int ignore ATTRIBUTE_UNUSED; 4076{ 4077 4078 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4079 { 4080 input_line_pointer += 6; 4081 s_text (0); 4082 return; 4083 } 4084 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4085 { 4086 input_line_pointer += 6; 4087 s_data (0); 4088 return; 4089 } 4090 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4091 { 4092 input_line_pointer += 7; 4093 s_data1 (); 4094 return; 4095 } 4096 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4097 { 4098 input_line_pointer += 5; 4099 /* We only support 2 segments -- text and data -- for now, so 4100 things in the "bss segment" will have to go into data for now. 4101 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4102 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4103 return; 4104 } 4105 as_bad (_("Unknown segment type")); 4106 demand_empty_rest_of_line (); 4107} 4108 4109static void 4110s_data1 () 4111{ 4112 subseg_set (data_section, 1); 4113 demand_empty_rest_of_line (); 4114} 4115 4116static void 4117s_proc (ignore) 4118 int ignore ATTRIBUTE_UNUSED; 4119{ 4120 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4121 { 4122 ++input_line_pointer; 4123 } 4124 ++input_line_pointer; 4125} 4126 4127/* This static variable is set by s_uacons to tell sparc_cons_align 4128 that the expression does not need to be aligned. */ 4129 4130static int sparc_no_align_cons = 0; 4131 4132/* This static variable is set by sparc_cons to emit requested types 4133 of relocations in cons_fix_new_sparc. */ 4134 4135static const char *sparc_cons_special_reloc; 4136 4137/* This handles the unaligned space allocation pseudo-ops, such as 4138 .uaword. .uaword is just like .word, but the value does not need 4139 to be aligned. */ 4140 4141static void 4142s_uacons (bytes) 4143 int bytes; 4144{ 4145 /* Tell sparc_cons_align not to align this value. */ 4146 sparc_no_align_cons = 1; 4147 cons (bytes); 4148 sparc_no_align_cons = 0; 4149} 4150 4151/* This handles the native word allocation pseudo-op .nword. 4152 For sparc_arch_size 32 it is equivalent to .word, for 4153 sparc_arch_size 64 it is equivalent to .xword. */ 4154 4155static void 4156s_ncons (bytes) 4157 int bytes ATTRIBUTE_UNUSED; 4158{ 4159 cons (sparc_arch_size == 32 ? 4 : 8); 4160} 4161 4162#ifdef OBJ_ELF 4163/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4164 global register. 4165 The syntax is: 4166 4167 .register %g[2367],{#scratch|symbolname|#ignore} 4168*/ 4169 4170static void 4171s_register (ignore) 4172 int ignore ATTRIBUTE_UNUSED; 4173{ 4174 char c; 4175 int reg; 4176 int flags; 4177 const char *regname; 4178 4179 if (input_line_pointer[0] != '%' 4180 || input_line_pointer[1] != 'g' 4181 || ((input_line_pointer[2] & ~1) != '2' 4182 && (input_line_pointer[2] & ~1) != '6') 4183 || input_line_pointer[3] != ',') 4184 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4185 reg = input_line_pointer[2] - '0'; 4186 input_line_pointer += 4; 4187 4188 if (*input_line_pointer == '#') 4189 { 4190 ++input_line_pointer; 4191 regname = input_line_pointer; 4192 c = get_symbol_end (); 4193 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4194 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4195 if (regname[0] == 'i') 4196 regname = NULL; 4197 else 4198 regname = ""; 4199 } 4200 else 4201 { 4202 regname = input_line_pointer; 4203 c = get_symbol_end (); 4204 } 4205 if (sparc_arch_size == 64) 4206 { 4207 if (globals[reg]) 4208 { 4209 if ((regname && globals[reg] != (symbolS *) 1 4210 && strcmp (S_GET_NAME (globals[reg]), regname)) 4211 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4212 as_bad (_("redefinition of global register")); 4213 } 4214 else 4215 { 4216 if (regname == NULL) 4217 globals[reg] = (symbolS *) 1; 4218 else 4219 { 4220 if (*regname) 4221 { 4222 if (symbol_find (regname)) 4223 as_bad (_("Register symbol %s already defined."), 4224 regname); 4225 } 4226 globals[reg] = symbol_make (regname); 4227 flags = symbol_get_bfdsym (globals[reg])->flags; 4228 if (! *regname) 4229 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4230 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4231 flags |= BSF_GLOBAL; 4232 symbol_get_bfdsym (globals[reg])->flags = flags; 4233 S_SET_VALUE (globals[reg], (valueT) reg); 4234 S_SET_ALIGN (globals[reg], reg); 4235 S_SET_SIZE (globals[reg], 0); 4236 /* Although we actually want undefined_section here, 4237 we have to use absolute_section, because otherwise 4238 generic as code will make it a COM section. 4239 We fix this up in sparc_adjust_symtab. */ 4240 S_SET_SEGMENT (globals[reg], absolute_section); 4241 S_SET_OTHER (globals[reg], 0); 4242 elf_symbol (symbol_get_bfdsym (globals[reg])) 4243 ->internal_elf_sym.st_info = 4244 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4245 elf_symbol (symbol_get_bfdsym (globals[reg])) 4246 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4247 } 4248 } 4249 } 4250 4251 *input_line_pointer = c; 4252 4253 demand_empty_rest_of_line (); 4254} 4255 4256/* Adjust the symbol table. We set undefined sections for STT_REGISTER 4257 symbols which need it. */ 4258 4259void 4260sparc_adjust_symtab () 4261{ 4262 symbolS *sym; 4263 4264 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4265 { 4266 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4267 ->internal_elf_sym.st_info) != STT_REGISTER) 4268 continue; 4269 4270 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4271 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4272 continue; 4273 4274 S_SET_SEGMENT (sym, undefined_section); 4275 } 4276} 4277#endif 4278 4279/* If the --enforce-aligned-data option is used, we require .word, 4280 et. al., to be aligned correctly. We do it by setting up an 4281 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4282 no unexpected alignment was introduced. 4283 4284 The SunOS and Solaris native assemblers enforce aligned data by 4285 default. We don't want to do that, because gcc can deliberately 4286 generate misaligned data if the packed attribute is used. Instead, 4287 we permit misaligned data by default, and permit the user to set an 4288 option to check for it. */ 4289 4290void 4291sparc_cons_align (nbytes) 4292 int nbytes; 4293{ 4294 int nalign; 4295 char *p; 4296 4297 /* Only do this if we are enforcing aligned data. */ 4298 if (! enforce_aligned_data) 4299 return; 4300 4301 /* Don't align if this is an unaligned pseudo-op. */ 4302 if (sparc_no_align_cons) 4303 return; 4304 4305 nalign = mylog2 (nbytes); 4306 if (nalign == 0) 4307 return; 4308 4309 assert (nalign > 0); 4310 4311 if (now_seg == absolute_section) 4312 { 4313 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4314 as_bad (_("misaligned data")); 4315 return; 4316 } 4317 4318 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4319 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4320 4321 record_alignment (now_seg, nalign); 4322} 4323 4324/* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4325 4326void 4327sparc_handle_align (fragp) 4328 fragS *fragp; 4329{ 4330 int count, fix; 4331 char *p; 4332 4333 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4334 4335 switch (fragp->fr_type) 4336 { 4337 case rs_align_test: 4338 if (count != 0) 4339 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4340 break; 4341 4342 case rs_align_code: 4343 p = fragp->fr_literal + fragp->fr_fix; 4344 fix = 0; 4345 4346 if (count & 3) 4347 { 4348 fix = count & 3; 4349 memset (p, 0, fix); 4350 p += fix; 4351 count -= fix; 4352 } 4353 4354 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4355 { 4356 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4357 if (INSN_BIG_ENDIAN) 4358 number_to_chars_bigendian (p, wval, 4); 4359 else 4360 number_to_chars_littleendian (p, wval, 4); 4361 p += 4; 4362 count -= 4; 4363 fix += 4; 4364 } 4365 4366 if (INSN_BIG_ENDIAN) 4367 number_to_chars_bigendian (p, 0x01000000, 4); 4368 else 4369 number_to_chars_littleendian (p, 0x01000000, 4); 4370 4371 fragp->fr_fix += fix; 4372 fragp->fr_var = 4; 4373 break; 4374 4375 default: 4376 break; 4377 } 4378} 4379 4380#ifdef OBJ_ELF 4381/* Some special processing for a Sparc ELF file. */ 4382 4383void 4384sparc_elf_final_processing () 4385{ 4386 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4387 sort of BFD interface for this. */ 4388 if (sparc_arch_size == 64) 4389 { 4390 switch (sparc_memory_model) 4391 { 4392 case MM_RMO: 4393 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4394 break; 4395 case MM_PSO: 4396 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4397 break; 4398 default: 4399 break; 4400 } 4401 } 4402 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4403 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4404 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4405 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4406 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4407 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4408} 4409 4410void 4411sparc_cons (exp, size) 4412 expressionS *exp; 4413 int size; 4414{ 4415 char *save; 4416 4417 SKIP_WHITESPACE (); 4418 sparc_cons_special_reloc = NULL; 4419 save = input_line_pointer; 4420 if (input_line_pointer[0] == '%' 4421 && input_line_pointer[1] == 'r' 4422 && input_line_pointer[2] == '_') 4423 { 4424 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4425 { 4426 input_line_pointer += 7; 4427 sparc_cons_special_reloc = "disp"; 4428 } 4429 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4430 { 4431 if (size != 4 && size != 8) 4432 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4433 else 4434 { 4435 input_line_pointer += 6; 4436 sparc_cons_special_reloc = "plt"; 4437 } 4438 } 4439 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4440 { 4441 if (size != 4 && size != 8) 4442 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4443 else 4444 { 4445 input_line_pointer += 13; 4446 sparc_cons_special_reloc = "tls_dtpoff"; 4447 } 4448 } 4449 if (sparc_cons_special_reloc) 4450 { 4451 int bad = 0; 4452 4453 switch (size) 4454 { 4455 case 1: 4456 if (*input_line_pointer != '8') 4457 bad = 1; 4458 input_line_pointer--; 4459 break; 4460 case 2: 4461 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4462 bad = 1; 4463 break; 4464 case 4: 4465 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4466 bad = 1; 4467 break; 4468 case 8: 4469 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4470 bad = 1; 4471 break; 4472 default: 4473 bad = 1; 4474 break; 4475 } 4476 4477 if (bad) 4478 { 4479 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4480 sparc_cons_special_reloc, size * 8, size); 4481 } 4482 else 4483 { 4484 input_line_pointer += 2; 4485 if (*input_line_pointer != '(') 4486 { 4487 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4488 sparc_cons_special_reloc, size * 8); 4489 bad = 1; 4490 } 4491 } 4492 4493 if (bad) 4494 { 4495 input_line_pointer = save; 4496 sparc_cons_special_reloc = NULL; 4497 } 4498 else 4499 { 4500 int c; 4501 char *end = ++input_line_pointer; 4502 int npar = 0; 4503 4504 while (! is_end_of_line[(c = *end)]) 4505 { 4506 if (c == '(') 4507 npar++; 4508 else if (c == ')') 4509 { 4510 if (!npar) 4511 break; 4512 npar--; 4513 } 4514 end++; 4515 } 4516 4517 if (c != ')') 4518 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4519 sparc_cons_special_reloc, size * 8); 4520 else 4521 { 4522 *end = '\0'; 4523 expression (exp); 4524 *end = c; 4525 if (input_line_pointer != end) 4526 { 4527 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4528 sparc_cons_special_reloc, size * 8); 4529 } 4530 else 4531 { 4532 input_line_pointer++; 4533 SKIP_WHITESPACE (); 4534 c = *input_line_pointer; 4535 if (! is_end_of_line[c] && c != ',') 4536 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4537 sparc_cons_special_reloc, size * 8); 4538 } 4539 } 4540 } 4541 } 4542 } 4543 if (sparc_cons_special_reloc == NULL) 4544 expression (exp); 4545} 4546 4547#endif 4548 4549/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4550 reloc for a cons. We could use the definition there, except that 4551 we want to handle little endian relocs specially. */ 4552 4553void 4554cons_fix_new_sparc (frag, where, nbytes, exp) 4555 fragS *frag; 4556 int where; 4557 unsigned int nbytes; 4558 expressionS *exp; 4559{ 4560 bfd_reloc_code_real_type r; 4561 4562 r = (nbytes == 1 ? BFD_RELOC_8 : 4563 (nbytes == 2 ? BFD_RELOC_16 : 4564 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4565 4566 if (target_little_endian_data 4567 && nbytes == 4 4568 && now_seg->flags & SEC_ALLOC) 4569 r = BFD_RELOC_SPARC_REV32; 4570 4571 if (sparc_cons_special_reloc) 4572 { 4573 if (*sparc_cons_special_reloc == 'd') 4574 switch (nbytes) 4575 { 4576 case 1: r = BFD_RELOC_8_PCREL; break; 4577 case 2: r = BFD_RELOC_16_PCREL; break; 4578 case 4: r = BFD_RELOC_32_PCREL; break; 4579 case 8: r = BFD_RELOC_64_PCREL; break; 4580 default: abort (); 4581 } 4582 else if (*sparc_cons_special_reloc == 'p') 4583 switch (nbytes) 4584 { 4585 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4586 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4587 } 4588 else 4589 switch (nbytes) 4590 { 4591 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4592 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4593 } 4594 } 4595 else if (sparc_no_align_cons) 4596 { 4597 switch (nbytes) 4598 { 4599 case 2: r = BFD_RELOC_SPARC_UA16; break; 4600 case 4: r = BFD_RELOC_SPARC_UA32; break; 4601 case 8: r = BFD_RELOC_SPARC_UA64; break; 4602 default: abort (); 4603 } 4604 } 4605 4606 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4607 sparc_cons_special_reloc = NULL; 4608} 4609 4610void 4611sparc_cfi_frame_initial_instructions () 4612{ 4613 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4614} 4615 4616int 4617sparc_regname_to_dw2regnum (char *regname) 4618{ 4619 char *p, *q; 4620 4621 if (!regname[0]) 4622 return -1; 4623 4624 q = "goli"; 4625 p = strchr (q, regname[0]); 4626 if (p) 4627 { 4628 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4629 return -1; 4630 return (p - q) * 8 + regname[1] - '0'; 4631 } 4632 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4633 return 14; 4634 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4635 return 30; 4636 if (regname[0] == 'f' || regname[0] == 'r') 4637 { 4638 unsigned int regnum; 4639 4640 regnum = strtoul (regname + 1, &q, 10); 4641 if (p == q || *q) 4642 return -1; 4643 if (regnum >= ((regname[0] == 'f' 4644 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4645 ? 64 : 32)) 4646 return -1; 4647 if (regname[0] == 'f') 4648 { 4649 regnum += 32; 4650 if (regnum >= 64 && (regnum & 1)) 4651 return -1; 4652 } 4653 return regnum; 4654 } 4655 return -1; 4656} 4657 4658void 4659sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 4660{ 4661 sparc_cons_special_reloc = "disp"; 4662 sparc_no_align_cons = 1; 4663 emit_expr (exp, nbytes); 4664 sparc_no_align_cons = 0; 4665 sparc_cons_special_reloc = NULL; 4666} 4667