tc-ia64.c revision 94536
1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. 2 Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22/* 23 TODO: 24 25 - optional operands 26 - directives: 27 .alias 28 .eb 29 .estate 30 .lb 31 .popsection 32 .previous 33 .psr 34 .pushsection 35 - labels are wrong if automatic alignment is introduced 36 (e.g., checkout the second real10 definition in test-data.s) 37 - DV-related stuff: 38 <reg>.safe_across_calls and any other DV-related directives I don't 39 have documentation for. 40 verify mod-sched-brs reads/writes are checked/marked (and other 41 notes) 42 43 */ 44 45#include "as.h" 46#include "safe-ctype.h" 47#include "dwarf2dbg.h" 48#include "subsegs.h" 49 50#include "opcode/ia64.h" 51 52#include "elf/ia64.h" 53 54#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) 55#define MIN(a,b) ((a) < (b) ? (a) : (b)) 56 57#define NUM_SLOTS 4 58#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] 59#define CURR_SLOT md.slot[md.curr_slot] 60 61#define O_pseudo_fixup (O_max + 1) 62 63enum special_section 64 { 65 /* IA-64 ABI section pseudo-ops. */ 66 SPECIAL_SECTION_BSS = 0, 67 SPECIAL_SECTION_SBSS, 68 SPECIAL_SECTION_SDATA, 69 SPECIAL_SECTION_RODATA, 70 SPECIAL_SECTION_COMMENT, 71 SPECIAL_SECTION_UNWIND, 72 SPECIAL_SECTION_UNWIND_INFO, 73 /* HPUX specific section pseudo-ops. */ 74 SPECIAL_SECTION_INIT_ARRAY, 75 SPECIAL_SECTION_FINI_ARRAY, 76 }; 77 78enum reloc_func 79 { 80 FUNC_FPTR_RELATIVE, 81 FUNC_GP_RELATIVE, 82 FUNC_LT_RELATIVE, 83 FUNC_PC_RELATIVE, 84 FUNC_PLT_RELATIVE, 85 FUNC_SEC_RELATIVE, 86 FUNC_SEG_RELATIVE, 87 FUNC_LTV_RELATIVE, 88 FUNC_LT_FPTR_RELATIVE, 89 FUNC_IPLT_RELOC, 90 }; 91 92enum reg_symbol 93 { 94 REG_GR = 0, 95 REG_FR = (REG_GR + 128), 96 REG_AR = (REG_FR + 128), 97 REG_CR = (REG_AR + 128), 98 REG_P = (REG_CR + 128), 99 REG_BR = (REG_P + 64), 100 REG_IP = (REG_BR + 8), 101 REG_CFM, 102 REG_PR, 103 REG_PR_ROT, 104 REG_PSR, 105 REG_PSR_L, 106 REG_PSR_UM, 107 /* The following are pseudo-registers for use by gas only. */ 108 IND_CPUID, 109 IND_DBR, 110 IND_DTR, 111 IND_ITR, 112 IND_IBR, 113 IND_MEM, 114 IND_MSR, 115 IND_PKR, 116 IND_PMC, 117 IND_PMD, 118 IND_RR, 119 /* The following pseudo-registers are used for unwind directives only: */ 120 REG_PSP, 121 REG_PRIUNAT, 122 REG_NUM 123 }; 124 125enum dynreg_type 126 { 127 DYNREG_GR = 0, /* dynamic general purpose register */ 128 DYNREG_FR, /* dynamic floating point register */ 129 DYNREG_PR, /* dynamic predicate register */ 130 DYNREG_NUM_TYPES 131 }; 132 133enum operand_match_result 134 { 135 OPERAND_MATCH, 136 OPERAND_OUT_OF_RANGE, 137 OPERAND_MISMATCH 138 }; 139 140/* On the ia64, we can't know the address of a text label until the 141 instructions are packed into a bundle. To handle this, we keep 142 track of the list of labels that appear in front of each 143 instruction. */ 144struct label_fix 145{ 146 struct label_fix *next; 147 struct symbol *sym; 148}; 149 150extern int target_big_endian; 151 152/* Characters which always start a comment. */ 153const char comment_chars[] = ""; 154 155/* Characters which start a comment at the beginning of a line. */ 156const char line_comment_chars[] = "#"; 157 158/* Characters which may be used to separate multiple commands on a 159 single line. */ 160const char line_separator_chars[] = ";"; 161 162/* Characters which are used to indicate an exponent in a floating 163 point number. */ 164const char EXP_CHARS[] = "eE"; 165 166/* Characters which mean that a number is a floating point constant, 167 as in 0d1.0. */ 168const char FLT_CHARS[] = "rRsSfFdDxXpP"; 169 170/* ia64-specific option processing: */ 171 172const char *md_shortopts = "m:N:x::"; 173 174struct option md_longopts[] = 175 { 176#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) 177 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, 178#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) 179 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} 180 }; 181 182size_t md_longopts_size = sizeof (md_longopts); 183 184static struct 185 { 186 struct hash_control *pseudo_hash; /* pseudo opcode hash table */ 187 struct hash_control *reg_hash; /* register name hash table */ 188 struct hash_control *dynreg_hash; /* dynamic register hash table */ 189 struct hash_control *const_hash; /* constant hash table */ 190 struct hash_control *entry_hash; /* code entry hint hash table */ 191 192 symbolS *regsym[REG_NUM]; 193 194 /* If X_op is != O_absent, the registername for the instruction's 195 qualifying predicate. If NULL, p0 is assumed for instructions 196 that are predicatable. */ 197 expressionS qp; 198 199 unsigned int 200 manual_bundling : 1, 201 debug_dv: 1, 202 detect_dv: 1, 203 explicit_mode : 1, /* which mode we're in */ 204 default_explicit_mode : 1, /* which mode is the default */ 205 mode_explicitly_set : 1, /* was the current mode explicitly set? */ 206 auto_align : 1, 207 keep_pending_output : 1; 208 209 /* Each bundle consists of up to three instructions. We keep 210 track of four most recent instructions so we can correctly set 211 the end_of_insn_group for the last instruction in a bundle. */ 212 int curr_slot; 213 int num_slots_in_use; 214 struct slot 215 { 216 unsigned int 217 end_of_insn_group : 1, 218 manual_bundling_on : 1, 219 manual_bundling_off : 1; 220 signed char user_template; /* user-selected template, if any */ 221 unsigned char qp_regno; /* qualifying predicate */ 222 /* This duplicates a good fraction of "struct fix" but we 223 can't use a "struct fix" instead since we can't call 224 fix_new_exp() until we know the address of the instruction. */ 225 int num_fixups; 226 struct insn_fix 227 { 228 bfd_reloc_code_real_type code; 229 enum ia64_opnd opnd; /* type of operand in need of fix */ 230 unsigned int is_pcrel : 1; /* is operand pc-relative? */ 231 expressionS expr; /* the value to be inserted */ 232 } 233 fixup[2]; /* at most two fixups per insn */ 234 struct ia64_opcode *idesc; 235 struct label_fix *label_fixups; 236 struct label_fix *tag_fixups; 237 struct unw_rec_list *unwind_record; /* Unwind directive. */ 238 expressionS opnd[6]; 239 char *src_file; 240 unsigned int src_line; 241 struct dwarf2_line_info debug_line; 242 } 243 slot[NUM_SLOTS]; 244 245 segT last_text_seg; 246 247 struct dynreg 248 { 249 struct dynreg *next; /* next dynamic register */ 250 const char *name; 251 unsigned short base; /* the base register number */ 252 unsigned short num_regs; /* # of registers in this set */ 253 } 254 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; 255 256 flagword flags; /* ELF-header flags */ 257 258 struct mem_offset { 259 unsigned hint:1; /* is this hint currently valid? */ 260 bfd_vma offset; /* mem.offset offset */ 261 bfd_vma base; /* mem.offset base */ 262 } mem_offset; 263 264 int path; /* number of alt. entry points seen */ 265 const char **entry_labels; /* labels of all alternate paths in 266 the current DV-checking block. */ 267 int maxpaths; /* size currently allocated for 268 entry_labels */ 269 /* Support for hardware errata workarounds. */ 270 271 /* Record data about the last three insn groups. */ 272 struct group 273 { 274 /* B-step workaround. 275 For each predicate register, this is set if the corresponding insn 276 group conditionally sets this register with one of the affected 277 instructions. */ 278 int p_reg_set[64]; 279 /* B-step workaround. 280 For each general register, this is set if the corresponding insn 281 a) is conditional one one of the predicate registers for which 282 P_REG_SET is 1 in the corresponding entry of the previous group, 283 b) sets this general register with one of the affected 284 instructions. */ 285 int g_reg_set_conditionally[128]; 286 } last_groups[3]; 287 int group_idx; 288 289 int pointer_size; /* size in bytes of a pointer */ 290 int pointer_size_shift; /* shift size of a pointer for alignment */ 291 } 292md; 293 294/* application registers: */ 295 296#define AR_K0 0 297#define AR_K7 7 298#define AR_RSC 16 299#define AR_BSP 17 300#define AR_BSPSTORE 18 301#define AR_RNAT 19 302#define AR_UNAT 36 303#define AR_FPSR 40 304#define AR_ITC 44 305#define AR_PFS 64 306#define AR_LC 65 307 308static const struct 309 { 310 const char *name; 311 int regnum; 312 } 313ar[] = 314 { 315 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, 316 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, 317 {"ar.rsc", 16}, {"ar.bsp", 17}, 318 {"ar.bspstore", 18}, {"ar.rnat", 19}, 319 {"ar.fcr", 21}, {"ar.eflag", 24}, 320 {"ar.csd", 25}, {"ar.ssd", 26}, 321 {"ar.cflg", 27}, {"ar.fsr", 28}, 322 {"ar.fir", 29}, {"ar.fdr", 30}, 323 {"ar.ccv", 32}, {"ar.unat", 36}, 324 {"ar.fpsr", 40}, {"ar.itc", 44}, 325 {"ar.pfs", 64}, {"ar.lc", 65}, 326 {"ar.ec", 66}, 327 }; 328 329#define CR_IPSR 16 330#define CR_ISR 17 331#define CR_IIP 19 332#define CR_IFA 20 333#define CR_ITIR 21 334#define CR_IIPA 22 335#define CR_IFS 23 336#define CR_IIM 24 337#define CR_IHA 25 338#define CR_IVR 65 339#define CR_TPR 66 340#define CR_EOI 67 341#define CR_IRR0 68 342#define CR_IRR3 71 343#define CR_LRR0 80 344#define CR_LRR1 81 345 346/* control registers: */ 347static const struct 348 { 349 const char *name; 350 int regnum; 351 } 352cr[] = 353 { 354 {"cr.dcr", 0}, 355 {"cr.itm", 1}, 356 {"cr.iva", 2}, 357 {"cr.pta", 8}, 358 {"cr.gpta", 9}, 359 {"cr.ipsr", 16}, 360 {"cr.isr", 17}, 361 {"cr.iip", 19}, 362 {"cr.ifa", 20}, 363 {"cr.itir", 21}, 364 {"cr.iipa", 22}, 365 {"cr.ifs", 23}, 366 {"cr.iim", 24}, 367 {"cr.iha", 25}, 368 {"cr.lid", 64}, 369 {"cr.ivr", 65}, 370 {"cr.tpr", 66}, 371 {"cr.eoi", 67}, 372 {"cr.irr0", 68}, 373 {"cr.irr1", 69}, 374 {"cr.irr2", 70}, 375 {"cr.irr3", 71}, 376 {"cr.itv", 72}, 377 {"cr.pmv", 73}, 378 {"cr.cmcv", 74}, 379 {"cr.lrr0", 80}, 380 {"cr.lrr1", 81} 381 }; 382 383#define PSR_MFL 4 384#define PSR_IC 13 385#define PSR_DFL 18 386#define PSR_CPL 32 387 388static const struct const_desc 389 { 390 const char *name; 391 valueT value; 392 } 393const_bits[] = 394 { 395 /* PSR constant masks: */ 396 397 /* 0: reserved */ 398 {"psr.be", ((valueT) 1) << 1}, 399 {"psr.up", ((valueT) 1) << 2}, 400 {"psr.ac", ((valueT) 1) << 3}, 401 {"psr.mfl", ((valueT) 1) << 4}, 402 {"psr.mfh", ((valueT) 1) << 5}, 403 /* 6-12: reserved */ 404 {"psr.ic", ((valueT) 1) << 13}, 405 {"psr.i", ((valueT) 1) << 14}, 406 {"psr.pk", ((valueT) 1) << 15}, 407 /* 16: reserved */ 408 {"psr.dt", ((valueT) 1) << 17}, 409 {"psr.dfl", ((valueT) 1) << 18}, 410 {"psr.dfh", ((valueT) 1) << 19}, 411 {"psr.sp", ((valueT) 1) << 20}, 412 {"psr.pp", ((valueT) 1) << 21}, 413 {"psr.di", ((valueT) 1) << 22}, 414 {"psr.si", ((valueT) 1) << 23}, 415 {"psr.db", ((valueT) 1) << 24}, 416 {"psr.lp", ((valueT) 1) << 25}, 417 {"psr.tb", ((valueT) 1) << 26}, 418 {"psr.rt", ((valueT) 1) << 27}, 419 /* 28-31: reserved */ 420 /* 32-33: cpl (current privilege level) */ 421 {"psr.is", ((valueT) 1) << 34}, 422 {"psr.mc", ((valueT) 1) << 35}, 423 {"psr.it", ((valueT) 1) << 36}, 424 {"psr.id", ((valueT) 1) << 37}, 425 {"psr.da", ((valueT) 1) << 38}, 426 {"psr.dd", ((valueT) 1) << 39}, 427 {"psr.ss", ((valueT) 1) << 40}, 428 /* 41-42: ri (restart instruction) */ 429 {"psr.ed", ((valueT) 1) << 43}, 430 {"psr.bn", ((valueT) 1) << 44}, 431 }; 432 433/* indirect register-sets/memory: */ 434 435static const struct 436 { 437 const char *name; 438 int regnum; 439 } 440indirect_reg[] = 441 { 442 { "CPUID", IND_CPUID }, 443 { "cpuid", IND_CPUID }, 444 { "dbr", IND_DBR }, 445 { "dtr", IND_DTR }, 446 { "itr", IND_ITR }, 447 { "ibr", IND_IBR }, 448 { "msr", IND_MSR }, 449 { "pkr", IND_PKR }, 450 { "pmc", IND_PMC }, 451 { "pmd", IND_PMD }, 452 { "rr", IND_RR }, 453 }; 454 455/* Pseudo functions used to indicate relocation types (these functions 456 start with an at sign (@). */ 457static struct 458 { 459 const char *name; 460 enum pseudo_type 461 { 462 PSEUDO_FUNC_NONE, 463 PSEUDO_FUNC_RELOC, 464 PSEUDO_FUNC_CONST, 465 PSEUDO_FUNC_REG, 466 PSEUDO_FUNC_FLOAT 467 } 468 type; 469 union 470 { 471 unsigned long ival; 472 symbolS *sym; 473 } 474 u; 475 } 476pseudo_func[] = 477 { 478 /* reloc pseudo functions (these must come first!): */ 479 { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, 480 { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, 481 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, 482 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, 483 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, 484 { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, 485 { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, 486 { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, 487 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ 488 { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, 489 490 /* mbtype4 constants: */ 491 { "alt", PSEUDO_FUNC_CONST, { 0xa } }, 492 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, 493 { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, 494 { "rev", PSEUDO_FUNC_CONST, { 0xb } }, 495 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, 496 497 /* fclass constants: */ 498 { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, 499 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, 500 { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, 501 { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, 502 { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, 503 { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, 504 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, 505 { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, 506 { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, 507 508 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ 509 510 /* unwind-related constants: */ 511 { "svr4", PSEUDO_FUNC_CONST, { 0 } }, 512 { "hpux", PSEUDO_FUNC_CONST, { 1 } }, 513 { "nt", PSEUDO_FUNC_CONST, { 2 } }, 514 515 /* unwind-related registers: */ 516 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } 517 }; 518 519/* 41-bit nop opcodes (one per unit): */ 520static const bfd_vma nop[IA64_NUM_UNITS] = 521 { 522 0x0000000000LL, /* NIL => break 0 */ 523 0x0008000000LL, /* I-unit nop */ 524 0x0008000000LL, /* M-unit nop */ 525 0x4000000000LL, /* B-unit nop */ 526 0x0008000000LL, /* F-unit nop */ 527 0x0008000000LL, /* L-"unit" nop */ 528 0x0008000000LL, /* X-unit nop */ 529 }; 530 531/* Can't be `const' as it's passed to input routines (which have the 532 habit of setting temporary sentinels. */ 533static char special_section_name[][20] = 534 { 535 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, 536 {".IA_64.unwind"}, {".IA_64.unwind_info"}, 537 {".init_array"}, {".fini_array"} 538 }; 539 540static char *special_linkonce_name[] = 541 { 542 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." 543 }; 544 545/* The best template for a particular sequence of up to three 546 instructions: */ 547#define N IA64_NUM_TYPES 548static unsigned char best_template[N][N][N]; 549#undef N 550 551/* Resource dependencies currently in effect */ 552static struct rsrc { 553 int depind; /* dependency index */ 554 const struct ia64_dependency *dependency; /* actual dependency */ 555 unsigned specific:1, /* is this a specific bit/regno? */ 556 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ 557 int index; /* specific regno/bit within dependency */ 558 int note; /* optional qualifying note (0 if none) */ 559#define STATE_NONE 0 560#define STATE_STOP 1 561#define STATE_SRLZ 2 562 int insn_srlz; /* current insn serialization state */ 563 int data_srlz; /* current data serialization state */ 564 int qp_regno; /* qualifying predicate for this usage */ 565 char *file; /* what file marked this dependency */ 566 unsigned int line; /* what line marked this dependency */ 567 struct mem_offset mem_offset; /* optional memory offset hint */ 568 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ 569 int path; /* corresponding code entry index */ 570} *regdeps = NULL; 571static int regdepslen = 0; 572static int regdepstotlen = 0; 573static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; 574static const char *dv_sem[] = { "none", "implied", "impliedf", 575 "data", "instr", "specific", "stop", "other" }; 576static const char *dv_cmp_type[] = { "none", "OR", "AND" }; 577 578/* Current state of PR mutexation */ 579static struct qpmutex { 580 valueT prmask; 581 int path; 582} *qp_mutexes = NULL; /* QP mutex bitmasks */ 583static int qp_mutexeslen = 0; 584static int qp_mutexestotlen = 0; 585static valueT qp_safe_across_calls = 0; 586 587/* Current state of PR implications */ 588static struct qp_imply { 589 unsigned p1:6; 590 unsigned p2:6; 591 unsigned p2_branched:1; 592 int path; 593} *qp_implies = NULL; 594static int qp_implieslen = 0; 595static int qp_impliestotlen = 0; 596 597/* Keep track of static GR values so that indirect register usage can 598 sometimes be tracked. */ 599static struct gr { 600 unsigned known:1; 601 int path; 602 valueT value; 603} gr_values[128] = {{ 1, 0, 0 }}; 604 605/* These are the routines required to output the various types of 606 unwind records. */ 607 608/* A slot_number is a frag address plus the slot index (0-2). We use the 609 frag address here so that if there is a section switch in the middle of 610 a function, then instructions emitted to a different section are not 611 counted. Since there may be more than one frag for a function, this 612 means we also need to keep track of which frag this address belongs to 613 so we can compute inter-frag distances. This also nicely solves the 614 problem with nops emitted for align directives, which can't easily be 615 counted, but can easily be derived from frag sizes. */ 616 617typedef struct unw_rec_list { 618 unwind_record r; 619 unsigned long slot_number; 620 fragS *slot_frag; 621 struct unw_rec_list *next; 622} unw_rec_list; 623 624#define SLOT_NUM_NOT_SET (unsigned)-1 625 626/* Linked list of saved prologue counts. A very poor 627 implementation of a map from label numbers to prologue counts. */ 628typedef struct label_prologue_count 629{ 630 struct label_prologue_count *next; 631 unsigned long label_number; 632 unsigned int prologue_count; 633} label_prologue_count; 634 635static struct 636{ 637 unsigned long next_slot_number; 638 fragS *next_slot_frag; 639 640 /* Maintain a list of unwind entries for the current function. */ 641 unw_rec_list *list; 642 unw_rec_list *tail; 643 644 /* Any unwind entires that should be attached to the current slot 645 that an insn is being constructed for. */ 646 unw_rec_list *current_entry; 647 648 /* These are used to create the unwind table entry for this function. */ 649 symbolS *proc_start; 650 symbolS *proc_end; 651 symbolS *info; /* pointer to unwind info */ 652 symbolS *personality_routine; 653 segT saved_text_seg; 654 subsegT saved_text_subseg; 655 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ 656 657 /* TRUE if processing unwind directives in a prologue region. */ 658 int prologue; 659 int prologue_mask; 660 unsigned int prologue_count; /* number of .prologues seen so far */ 661 /* Prologue counts at previous .label_state directives. */ 662 struct label_prologue_count * saved_prologue_counts; 663} unwind; 664 665typedef void (*vbyte_func) PARAMS ((int, char *, char *)); 666 667/* Forward delarations: */ 668static int ar_is_in_integer_unit PARAMS ((int regnum)); 669static void set_section PARAMS ((char *name)); 670static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, 671 unsigned int, unsigned int)); 672static void dot_radix PARAMS ((int)); 673static void dot_special_section PARAMS ((int)); 674static void dot_proc PARAMS ((int)); 675static void dot_fframe PARAMS ((int)); 676static void dot_vframe PARAMS ((int)); 677static void dot_vframesp PARAMS ((int)); 678static void dot_vframepsp PARAMS ((int)); 679static void dot_save PARAMS ((int)); 680static void dot_restore PARAMS ((int)); 681static void dot_restorereg PARAMS ((int)); 682static void dot_restorereg_p PARAMS ((int)); 683static void dot_handlerdata PARAMS ((int)); 684static void dot_unwentry PARAMS ((int)); 685static void dot_altrp PARAMS ((int)); 686static void dot_savemem PARAMS ((int)); 687static void dot_saveg PARAMS ((int)); 688static void dot_savef PARAMS ((int)); 689static void dot_saveb PARAMS ((int)); 690static void dot_savegf PARAMS ((int)); 691static void dot_spill PARAMS ((int)); 692static void dot_spillreg PARAMS ((int)); 693static void dot_spillmem PARAMS ((int)); 694static void dot_spillreg_p PARAMS ((int)); 695static void dot_spillmem_p PARAMS ((int)); 696static void dot_label_state PARAMS ((int)); 697static void dot_copy_state PARAMS ((int)); 698static void dot_unwabi PARAMS ((int)); 699static void dot_personality PARAMS ((int)); 700static void dot_body PARAMS ((int)); 701static void dot_prologue PARAMS ((int)); 702static void dot_endp PARAMS ((int)); 703static void dot_template PARAMS ((int)); 704static void dot_regstk PARAMS ((int)); 705static void dot_rot PARAMS ((int)); 706static void dot_byteorder PARAMS ((int)); 707static void dot_psr PARAMS ((int)); 708static void dot_alias PARAMS ((int)); 709static void dot_ln PARAMS ((int)); 710static char *parse_section_name PARAMS ((void)); 711static void dot_xdata PARAMS ((int)); 712static void stmt_float_cons PARAMS ((int)); 713static void stmt_cons_ua PARAMS ((int)); 714static void dot_xfloat_cons PARAMS ((int)); 715static void dot_xstringer PARAMS ((int)); 716static void dot_xdata_ua PARAMS ((int)); 717static void dot_xfloat_cons_ua PARAMS ((int)); 718static void print_prmask PARAMS ((valueT mask)); 719static void dot_pred_rel PARAMS ((int)); 720static void dot_reg_val PARAMS ((int)); 721static void dot_dv_mode PARAMS ((int)); 722static void dot_entry PARAMS ((int)); 723static void dot_mem_offset PARAMS ((int)); 724static void add_unwind_entry PARAMS((unw_rec_list *ptr)); 725static symbolS *declare_register PARAMS ((const char *name, int regnum)); 726static void declare_register_set PARAMS ((const char *, int, int)); 727static unsigned int operand_width PARAMS ((enum ia64_opnd)); 728static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, 729 int index, 730 expressionS *e)); 731static int parse_operand PARAMS ((expressionS *e)); 732static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); 733static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit)); 734static void build_insn PARAMS ((struct slot *, bfd_vma *)); 735static void emit_one_bundle PARAMS ((void)); 736static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); 737static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, 738 bfd_reloc_code_real_type r_type)); 739static void insn_group_break PARAMS ((int, int, int)); 740static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, 741 struct rsrc *, int depind, int path)); 742static void add_qp_mutex PARAMS((valueT mask)); 743static void add_qp_imply PARAMS((int p1, int p2)); 744static void clear_qp_branch_flag PARAMS((valueT mask)); 745static void clear_qp_mutex PARAMS((valueT mask)); 746static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); 747static int has_suffix_p PARAMS((const char *, const char *)); 748static void clear_register_values PARAMS ((void)); 749static void print_dependency PARAMS ((const char *action, int depind)); 750static void instruction_serialization PARAMS ((void)); 751static void data_serialization PARAMS ((void)); 752static void remove_marked_resource PARAMS ((struct rsrc *)); 753static int is_conditional_branch PARAMS ((struct ia64_opcode *)); 754static int is_taken_branch PARAMS ((struct ia64_opcode *)); 755static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); 756static int depends_on PARAMS ((int, struct ia64_opcode *)); 757static int specify_resource PARAMS ((const struct ia64_dependency *, 758 struct ia64_opcode *, int, struct rsrc [], int, int)); 759static int check_dv PARAMS((struct ia64_opcode *idesc)); 760static void check_dependencies PARAMS((struct ia64_opcode *)); 761static void mark_resources PARAMS((struct ia64_opcode *)); 762static void update_dependencies PARAMS((struct ia64_opcode *)); 763static void note_register_values PARAMS((struct ia64_opcode *)); 764static int qp_mutex PARAMS ((int, int, int)); 765static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); 766static void output_vbyte_mem PARAMS ((int, char *, char *)); 767static void count_output PARAMS ((int, char *, char *)); 768static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); 769static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); 770static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 771static void output_P1_format PARAMS ((vbyte_func, int)); 772static void output_P2_format PARAMS ((vbyte_func, int, int)); 773static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); 774static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); 775static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); 776static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); 777static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); 778static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 779static void output_P9_format PARAMS ((vbyte_func, int, int)); 780static void output_P10_format PARAMS ((vbyte_func, int, int)); 781static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 782static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); 783static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); 784static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 785static char format_ab_reg PARAMS ((int, int)); 786static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, 787 unsigned long)); 788static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); 789static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, 790 unsigned long)); 791static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); 792static void free_list_records PARAMS ((unw_rec_list *)); 793static unw_rec_list *output_prologue PARAMS ((void)); 794static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); 795static unw_rec_list *output_body PARAMS ((void)); 796static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); 797static unw_rec_list *output_mem_stack_v PARAMS ((void)); 798static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); 799static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); 800static unw_rec_list *output_rp_when PARAMS ((void)); 801static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); 802static unw_rec_list *output_rp_br PARAMS ((unsigned int)); 803static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); 804static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); 805static unw_rec_list *output_pfs_when PARAMS ((void)); 806static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); 807static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); 808static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); 809static unw_rec_list *output_preds_when PARAMS ((void)); 810static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); 811static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); 812static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); 813static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); 814static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); 815static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); 816static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); 817static unw_rec_list *output_br_mem PARAMS ((unsigned int)); 818static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); 819static unw_rec_list *output_spill_base PARAMS ((unsigned int)); 820static unw_rec_list *output_unat_when PARAMS ((void)); 821static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); 822static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); 823static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); 824static unw_rec_list *output_lc_when PARAMS ((void)); 825static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); 826static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); 827static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); 828static unw_rec_list *output_fpsr_when PARAMS ((void)); 829static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); 830static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); 831static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); 832static unw_rec_list *output_priunat_when_gr PARAMS ((void)); 833static unw_rec_list *output_priunat_when_mem PARAMS ((void)); 834static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); 835static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); 836static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); 837static unw_rec_list *output_bsp_when PARAMS ((void)); 838static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); 839static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); 840static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); 841static unw_rec_list *output_bspstore_when PARAMS ((void)); 842static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); 843static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); 844static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); 845static unw_rec_list *output_rnat_when PARAMS ((void)); 846static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); 847static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); 848static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); 849static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); 850static unw_rec_list *output_epilogue PARAMS ((unsigned long)); 851static unw_rec_list *output_label_state PARAMS ((unsigned long)); 852static unw_rec_list *output_copy_state PARAMS ((unsigned long)); 853static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); 854static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); 855static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, 856 unsigned int)); 857static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, 858 unsigned int)); 859static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, 860 unsigned int)); 861static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, 862 unsigned int, unsigned int)); 863static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); 864static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); 865static int calc_record_size PARAMS ((unw_rec_list *)); 866static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); 867static int count_bits PARAMS ((unsigned long)); 868static unsigned long slot_index PARAMS ((unsigned long, fragS *, 869 unsigned long, fragS *)); 870static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); 871static void fixup_unw_records PARAMS ((unw_rec_list *)); 872static int output_unw_records PARAMS ((unw_rec_list *, void **)); 873static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); 874static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); 875static int generate_unwind_image PARAMS ((const char *)); 876static unsigned int get_saved_prologue_count PARAMS ((unsigned long)); 877static void save_prologue_count PARAMS ((unsigned long, unsigned int)); 878static void free_saved_prologue_counts PARAMS ((void)); 879 880/* Build the unwind section name by appending the (possibly stripped) 881 text section NAME to the unwind PREFIX. The resulting string 882 pointer is assigned to RESULT. The string is allocated on the 883 stack, so this must be a macro... */ 884#define make_unw_section_name(special, text_name, result) \ 885 { \ 886 const char *_prefix = special_section_name[special]; \ 887 const char *_suffix = text_name; \ 888 size_t _prefix_len, _suffix_len; \ 889 char *_result; \ 890 if (strncmp (text_name, ".gnu.linkonce.t.", \ 891 sizeof (".gnu.linkonce.t.") - 1) == 0) \ 892 { \ 893 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \ 894 _suffix += sizeof (".gnu.linkonce.t.") - 1; \ 895 } \ 896 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \ 897 _result = alloca (_prefix_len + _suffix_len + 1); \ 898 memcpy (_result, _prefix, _prefix_len); \ 899 memcpy (_result + _prefix_len, _suffix, _suffix_len); \ 900 _result[_prefix_len + _suffix_len] = '\0'; \ 901 result = _result; \ 902 } \ 903while (0) 904 905/* Determine if application register REGNUM resides in the integer 906 unit (as opposed to the memory unit). */ 907static int 908ar_is_in_integer_unit (reg) 909 int reg; 910{ 911 reg -= REG_AR; 912 913 return (reg == 64 /* pfs */ 914 || reg == 65 /* lc */ 915 || reg == 66 /* ec */ 916 /* ??? ias accepts and puts these in the integer unit. */ 917 || (reg >= 112 && reg <= 127)); 918} 919 920/* Switch to section NAME and create section if necessary. It's 921 rather ugly that we have to manipulate input_line_pointer but I 922 don't see any other way to accomplish the same thing without 923 changing obj-elf.c (which may be the Right Thing, in the end). */ 924static void 925set_section (name) 926 char *name; 927{ 928 char *saved_input_line_pointer; 929 930 saved_input_line_pointer = input_line_pointer; 931 input_line_pointer = name; 932 obj_elf_section (0); 933 input_line_pointer = saved_input_line_pointer; 934} 935 936/* Map 's' to SHF_IA_64_SHORT. */ 937 938int 939ia64_elf_section_letter (letter, ptr_msg) 940 int letter; 941 char **ptr_msg; 942{ 943 if (letter == 's') 944 return SHF_IA_64_SHORT; 945 946 *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S in string"); 947 return 0; 948} 949 950/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ 951 952flagword 953ia64_elf_section_flags (flags, attr, type) 954 flagword flags; 955 int attr, type ATTRIBUTE_UNUSED; 956{ 957 if (attr & SHF_IA_64_SHORT) 958 flags |= SEC_SMALL_DATA; 959 return flags; 960} 961 962int 963ia64_elf_section_type (str, len) 964 const char *str; 965 size_t len; 966{ 967#define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0)) 968 969 if (STREQ (ELF_STRING_ia64_unwind_info)) 970 return SHT_PROGBITS; 971 972 if (STREQ (ELF_STRING_ia64_unwind_info_once)) 973 return SHT_PROGBITS; 974 975 if (STREQ (ELF_STRING_ia64_unwind)) 976 return SHT_IA_64_UNWIND; 977 978 if (STREQ (ELF_STRING_ia64_unwind_once)) 979 return SHT_IA_64_UNWIND; 980 981 if (STREQ ("init_array")) 982 return SHT_INIT_ARRAY; 983 984 if (STREQ ("fini_array")) 985 return SHT_FINI_ARRAY; 986 987 return -1; 988#undef STREQ 989} 990 991static unsigned int 992set_regstack (ins, locs, outs, rots) 993 unsigned int ins, locs, outs, rots; 994{ 995 /* Size of frame. */ 996 unsigned int sof; 997 998 sof = ins + locs + outs; 999 if (sof > 96) 1000 { 1001 as_bad ("Size of frame exceeds maximum of 96 registers"); 1002 return 0; 1003 } 1004 if (rots > sof) 1005 { 1006 as_warn ("Size of rotating registers exceeds frame size"); 1007 return 0; 1008 } 1009 md.in.base = REG_GR + 32; 1010 md.loc.base = md.in.base + ins; 1011 md.out.base = md.loc.base + locs; 1012 1013 md.in.num_regs = ins; 1014 md.loc.num_regs = locs; 1015 md.out.num_regs = outs; 1016 md.rot.num_regs = rots; 1017 return sof; 1018} 1019 1020void 1021ia64_flush_insns () 1022{ 1023 struct label_fix *lfix; 1024 segT saved_seg; 1025 subsegT saved_subseg; 1026 unw_rec_list *ptr; 1027 1028 if (!md.last_text_seg) 1029 return; 1030 1031 saved_seg = now_seg; 1032 saved_subseg = now_subseg; 1033 1034 subseg_set (md.last_text_seg, 0); 1035 1036 while (md.num_slots_in_use > 0) 1037 emit_one_bundle (); /* force out queued instructions */ 1038 1039 /* In case there are labels following the last instruction, resolve 1040 those now: */ 1041 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) 1042 { 1043 S_SET_VALUE (lfix->sym, frag_now_fix ()); 1044 symbol_set_frag (lfix->sym, frag_now); 1045 } 1046 CURR_SLOT.label_fixups = 0; 1047 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) 1048 { 1049 S_SET_VALUE (lfix->sym, frag_now_fix ()); 1050 symbol_set_frag (lfix->sym, frag_now); 1051 } 1052 CURR_SLOT.tag_fixups = 0; 1053 1054 /* In case there are unwind directives following the last instruction, 1055 resolve those now. We only handle body and prologue directives here. 1056 Give an error for others. */ 1057 for (ptr = unwind.current_entry; ptr; ptr = ptr->next) 1058 { 1059 if (ptr->r.type == prologue || ptr->r.type == prologue_gr 1060 || ptr->r.type == body) 1061 { 1062 ptr->slot_number = (unsigned long) frag_more (0); 1063 ptr->slot_frag = frag_now; 1064 } 1065 else 1066 as_bad (_("Unwind directive not followed by an instruction.")); 1067 } 1068 unwind.current_entry = NULL; 1069 1070 subseg_set (saved_seg, saved_subseg); 1071 1072 if (md.qp.X_op == O_register) 1073 as_bad ("qualifying predicate not followed by instruction"); 1074} 1075 1076void 1077ia64_do_align (nbytes) 1078 int nbytes; 1079{ 1080 char *saved_input_line_pointer = input_line_pointer; 1081 1082 input_line_pointer = ""; 1083 s_align_bytes (nbytes); 1084 input_line_pointer = saved_input_line_pointer; 1085} 1086 1087void 1088ia64_cons_align (nbytes) 1089 int nbytes; 1090{ 1091 if (md.auto_align) 1092 { 1093 char *saved_input_line_pointer = input_line_pointer; 1094 input_line_pointer = ""; 1095 s_align_bytes (nbytes); 1096 input_line_pointer = saved_input_line_pointer; 1097 } 1098} 1099 1100/* Output COUNT bytes to a memory location. */ 1101static unsigned char *vbyte_mem_ptr = NULL; 1102 1103void 1104output_vbyte_mem (count, ptr, comment) 1105 int count; 1106 char *ptr; 1107 char *comment ATTRIBUTE_UNUSED; 1108{ 1109 int x; 1110 if (vbyte_mem_ptr == NULL) 1111 abort (); 1112 1113 if (count == 0) 1114 return; 1115 for (x = 0; x < count; x++) 1116 *(vbyte_mem_ptr++) = ptr[x]; 1117} 1118 1119/* Count the number of bytes required for records. */ 1120static int vbyte_count = 0; 1121void 1122count_output (count, ptr, comment) 1123 int count; 1124 char *ptr ATTRIBUTE_UNUSED; 1125 char *comment ATTRIBUTE_UNUSED; 1126{ 1127 vbyte_count += count; 1128} 1129 1130static void 1131output_R1_format (f, rtype, rlen) 1132 vbyte_func f; 1133 unw_record_type rtype; 1134 int rlen; 1135{ 1136 int r = 0; 1137 char byte; 1138 if (rlen > 0x1f) 1139 { 1140 output_R3_format (f, rtype, rlen); 1141 return; 1142 } 1143 1144 if (rtype == body) 1145 r = 1; 1146 else if (rtype != prologue) 1147 as_bad ("record type is not valid"); 1148 1149 byte = UNW_R1 | (r << 5) | (rlen & 0x1f); 1150 (*f) (1, &byte, NULL); 1151} 1152 1153static void 1154output_R2_format (f, mask, grsave, rlen) 1155 vbyte_func f; 1156 int mask, grsave; 1157 unsigned long rlen; 1158{ 1159 char bytes[20]; 1160 int count = 2; 1161 mask = (mask & 0x0f); 1162 grsave = (grsave & 0x7f); 1163 1164 bytes[0] = (UNW_R2 | (mask >> 1)); 1165 bytes[1] = (((mask & 0x01) << 7) | grsave); 1166 count += output_leb128 (bytes + 2, rlen, 0); 1167 (*f) (count, bytes, NULL); 1168} 1169 1170static void 1171output_R3_format (f, rtype, rlen) 1172 vbyte_func f; 1173 unw_record_type rtype; 1174 unsigned long rlen; 1175{ 1176 int r = 0, count; 1177 char bytes[20]; 1178 if (rlen <= 0x1f) 1179 { 1180 output_R1_format (f, rtype, rlen); 1181 return; 1182 } 1183 1184 if (rtype == body) 1185 r = 1; 1186 else if (rtype != prologue) 1187 as_bad ("record type is not valid"); 1188 bytes[0] = (UNW_R3 | r); 1189 count = output_leb128 (bytes + 1, rlen, 0); 1190 (*f) (count + 1, bytes, NULL); 1191} 1192 1193static void 1194output_P1_format (f, brmask) 1195 vbyte_func f; 1196 int brmask; 1197{ 1198 char byte; 1199 byte = UNW_P1 | (brmask & 0x1f); 1200 (*f) (1, &byte, NULL); 1201} 1202 1203static void 1204output_P2_format (f, brmask, gr) 1205 vbyte_func f; 1206 int brmask; 1207 int gr; 1208{ 1209 char bytes[2]; 1210 brmask = (brmask & 0x1f); 1211 bytes[0] = UNW_P2 | (brmask >> 1); 1212 bytes[1] = (((brmask & 1) << 7) | gr); 1213 (*f) (2, bytes, NULL); 1214} 1215 1216static void 1217output_P3_format (f, rtype, reg) 1218 vbyte_func f; 1219 unw_record_type rtype; 1220 int reg; 1221{ 1222 char bytes[2]; 1223 int r = 0; 1224 reg = (reg & 0x7f); 1225 switch (rtype) 1226 { 1227 case psp_gr: 1228 r = 0; 1229 break; 1230 case rp_gr: 1231 r = 1; 1232 break; 1233 case pfs_gr: 1234 r = 2; 1235 break; 1236 case preds_gr: 1237 r = 3; 1238 break; 1239 case unat_gr: 1240 r = 4; 1241 break; 1242 case lc_gr: 1243 r = 5; 1244 break; 1245 case rp_br: 1246 r = 6; 1247 break; 1248 case rnat_gr: 1249 r = 7; 1250 break; 1251 case bsp_gr: 1252 r = 8; 1253 break; 1254 case bspstore_gr: 1255 r = 9; 1256 break; 1257 case fpsr_gr: 1258 r = 10; 1259 break; 1260 case priunat_gr: 1261 r = 11; 1262 break; 1263 default: 1264 as_bad ("Invalid record type for P3 format."); 1265 } 1266 bytes[0] = (UNW_P3 | (r >> 1)); 1267 bytes[1] = (((r & 1) << 7) | reg); 1268 (*f) (2, bytes, NULL); 1269} 1270 1271static void 1272output_P4_format (f, imask, imask_size) 1273 vbyte_func f; 1274 unsigned char *imask; 1275 unsigned long imask_size; 1276{ 1277 imask[0] = UNW_P4; 1278 (*f) (imask_size, imask, NULL); 1279} 1280 1281static void 1282output_P5_format (f, grmask, frmask) 1283 vbyte_func f; 1284 int grmask; 1285 unsigned long frmask; 1286{ 1287 char bytes[4]; 1288 grmask = (grmask & 0x0f); 1289 1290 bytes[0] = UNW_P5; 1291 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); 1292 bytes[2] = ((frmask & 0x0000ff00) >> 8); 1293 bytes[3] = (frmask & 0x000000ff); 1294 (*f) (4, bytes, NULL); 1295} 1296 1297static void 1298output_P6_format (f, rtype, rmask) 1299 vbyte_func f; 1300 unw_record_type rtype; 1301 int rmask; 1302{ 1303 char byte; 1304 int r = 0; 1305 1306 if (rtype == gr_mem) 1307 r = 1; 1308 else if (rtype != fr_mem) 1309 as_bad ("Invalid record type for format P6"); 1310 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); 1311 (*f) (1, &byte, NULL); 1312} 1313 1314static void 1315output_P7_format (f, rtype, w1, w2) 1316 vbyte_func f; 1317 unw_record_type rtype; 1318 unsigned long w1; 1319 unsigned long w2; 1320{ 1321 char bytes[20]; 1322 int count = 1; 1323 int r = 0; 1324 count += output_leb128 (bytes + 1, w1, 0); 1325 switch (rtype) 1326 { 1327 case mem_stack_f: 1328 r = 0; 1329 count += output_leb128 (bytes + count, w2 >> 4, 0); 1330 break; 1331 case mem_stack_v: 1332 r = 1; 1333 break; 1334 case spill_base: 1335 r = 2; 1336 break; 1337 case psp_sprel: 1338 r = 3; 1339 break; 1340 case rp_when: 1341 r = 4; 1342 break; 1343 case rp_psprel: 1344 r = 5; 1345 break; 1346 case pfs_when: 1347 r = 6; 1348 break; 1349 case pfs_psprel: 1350 r = 7; 1351 break; 1352 case preds_when: 1353 r = 8; 1354 break; 1355 case preds_psprel: 1356 r = 9; 1357 break; 1358 case lc_when: 1359 r = 10; 1360 break; 1361 case lc_psprel: 1362 r = 11; 1363 break; 1364 case unat_when: 1365 r = 12; 1366 break; 1367 case unat_psprel: 1368 r = 13; 1369 break; 1370 case fpsr_when: 1371 r = 14; 1372 break; 1373 case fpsr_psprel: 1374 r = 15; 1375 break; 1376 default: 1377 break; 1378 } 1379 bytes[0] = (UNW_P7 | r); 1380 (*f) (count, bytes, NULL); 1381} 1382 1383static void 1384output_P8_format (f, rtype, t) 1385 vbyte_func f; 1386 unw_record_type rtype; 1387 unsigned long t; 1388{ 1389 char bytes[20]; 1390 int r = 0; 1391 int count = 2; 1392 bytes[0] = UNW_P8; 1393 switch (rtype) 1394 { 1395 case rp_sprel: 1396 r = 1; 1397 break; 1398 case pfs_sprel: 1399 r = 2; 1400 break; 1401 case preds_sprel: 1402 r = 3; 1403 break; 1404 case lc_sprel: 1405 r = 4; 1406 break; 1407 case unat_sprel: 1408 r = 5; 1409 break; 1410 case fpsr_sprel: 1411 r = 6; 1412 break; 1413 case bsp_when: 1414 r = 7; 1415 break; 1416 case bsp_psprel: 1417 r = 8; 1418 break; 1419 case bsp_sprel: 1420 r = 9; 1421 break; 1422 case bspstore_when: 1423 r = 10; 1424 break; 1425 case bspstore_psprel: 1426 r = 11; 1427 break; 1428 case bspstore_sprel: 1429 r = 12; 1430 break; 1431 case rnat_when: 1432 r = 13; 1433 break; 1434 case rnat_psprel: 1435 r = 14; 1436 break; 1437 case rnat_sprel: 1438 r = 15; 1439 break; 1440 case priunat_when_gr: 1441 r = 16; 1442 break; 1443 case priunat_psprel: 1444 r = 17; 1445 break; 1446 case priunat_sprel: 1447 r = 18; 1448 break; 1449 case priunat_when_mem: 1450 r = 19; 1451 break; 1452 default: 1453 break; 1454 } 1455 bytes[1] = r; 1456 count += output_leb128 (bytes + 2, t, 0); 1457 (*f) (count, bytes, NULL); 1458} 1459 1460static void 1461output_P9_format (f, grmask, gr) 1462 vbyte_func f; 1463 int grmask; 1464 int gr; 1465{ 1466 char bytes[3]; 1467 bytes[0] = UNW_P9; 1468 bytes[1] = (grmask & 0x0f); 1469 bytes[2] = (gr & 0x7f); 1470 (*f) (3, bytes, NULL); 1471} 1472 1473static void 1474output_P10_format (f, abi, context) 1475 vbyte_func f; 1476 int abi; 1477 int context; 1478{ 1479 char bytes[3]; 1480 bytes[0] = UNW_P10; 1481 bytes[1] = (abi & 0xff); 1482 bytes[2] = (context & 0xff); 1483 (*f) (3, bytes, NULL); 1484} 1485 1486static void 1487output_B1_format (f, rtype, label) 1488 vbyte_func f; 1489 unw_record_type rtype; 1490 unsigned long label; 1491{ 1492 char byte; 1493 int r = 0; 1494 if (label > 0x1f) 1495 { 1496 output_B4_format (f, rtype, label); 1497 return; 1498 } 1499 if (rtype == copy_state) 1500 r = 1; 1501 else if (rtype != label_state) 1502 as_bad ("Invalid record type for format B1"); 1503 1504 byte = (UNW_B1 | (r << 5) | (label & 0x1f)); 1505 (*f) (1, &byte, NULL); 1506} 1507 1508static void 1509output_B2_format (f, ecount, t) 1510 vbyte_func f; 1511 unsigned long ecount; 1512 unsigned long t; 1513{ 1514 char bytes[20]; 1515 int count = 1; 1516 if (ecount > 0x1f) 1517 { 1518 output_B3_format (f, ecount, t); 1519 return; 1520 } 1521 bytes[0] = (UNW_B2 | (ecount & 0x1f)); 1522 count += output_leb128 (bytes + 1, t, 0); 1523 (*f) (count, bytes, NULL); 1524} 1525 1526static void 1527output_B3_format (f, ecount, t) 1528 vbyte_func f; 1529 unsigned long ecount; 1530 unsigned long t; 1531{ 1532 char bytes[20]; 1533 int count = 1; 1534 if (ecount <= 0x1f) 1535 { 1536 output_B2_format (f, ecount, t); 1537 return; 1538 } 1539 bytes[0] = UNW_B3; 1540 count += output_leb128 (bytes + 1, t, 0); 1541 count += output_leb128 (bytes + count, ecount, 0); 1542 (*f) (count, bytes, NULL); 1543} 1544 1545static void 1546output_B4_format (f, rtype, label) 1547 vbyte_func f; 1548 unw_record_type rtype; 1549 unsigned long label; 1550{ 1551 char bytes[20]; 1552 int r = 0; 1553 int count = 1; 1554 if (label <= 0x1f) 1555 { 1556 output_B1_format (f, rtype, label); 1557 return; 1558 } 1559 1560 if (rtype == copy_state) 1561 r = 1; 1562 else if (rtype != label_state) 1563 as_bad ("Invalid record type for format B1"); 1564 1565 bytes[0] = (UNW_B4 | (r << 3)); 1566 count += output_leb128 (bytes + 1, label, 0); 1567 (*f) (count, bytes, NULL); 1568} 1569 1570static char 1571format_ab_reg (ab, reg) 1572 int ab; 1573 int reg; 1574{ 1575 int ret; 1576 ab = (ab & 3); 1577 reg = (reg & 0x1f); 1578 ret = (ab << 5) | reg; 1579 return ret; 1580} 1581 1582static void 1583output_X1_format (f, rtype, ab, reg, t, w1) 1584 vbyte_func f; 1585 unw_record_type rtype; 1586 int ab, reg; 1587 unsigned long t; 1588 unsigned long w1; 1589{ 1590 char bytes[20]; 1591 int r = 0; 1592 int count = 2; 1593 bytes[0] = UNW_X1; 1594 1595 if (rtype == spill_sprel) 1596 r = 1; 1597 else if (rtype != spill_psprel) 1598 as_bad ("Invalid record type for format X1"); 1599 bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); 1600 count += output_leb128 (bytes + 2, t, 0); 1601 count += output_leb128 (bytes + count, w1, 0); 1602 (*f) (count, bytes, NULL); 1603} 1604 1605static void 1606output_X2_format (f, ab, reg, x, y, treg, t) 1607 vbyte_func f; 1608 int ab, reg; 1609 int x, y, treg; 1610 unsigned long t; 1611{ 1612 char bytes[20]; 1613 int count = 3; 1614 bytes[0] = UNW_X2; 1615 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1616 bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); 1617 count += output_leb128 (bytes + 3, t, 0); 1618 (*f) (count, bytes, NULL); 1619} 1620 1621static void 1622output_X3_format (f, rtype, qp, ab, reg, t, w1) 1623 vbyte_func f; 1624 unw_record_type rtype; 1625 int qp; 1626 int ab, reg; 1627 unsigned long t; 1628 unsigned long w1; 1629{ 1630 char bytes[20]; 1631 int r = 0; 1632 int count = 3; 1633 bytes[0] = UNW_X3; 1634 1635 if (rtype == spill_sprel_p) 1636 r = 1; 1637 else if (rtype != spill_psprel_p) 1638 as_bad ("Invalid record type for format X3"); 1639 bytes[1] = ((r << 7) | (qp & 0x3f)); 1640 bytes[2] = format_ab_reg (ab, reg); 1641 count += output_leb128 (bytes + 3, t, 0); 1642 count += output_leb128 (bytes + count, w1, 0); 1643 (*f) (count, bytes, NULL); 1644} 1645 1646static void 1647output_X4_format (f, qp, ab, reg, x, y, treg, t) 1648 vbyte_func f; 1649 int qp; 1650 int ab, reg; 1651 int x, y, treg; 1652 unsigned long t; 1653{ 1654 char bytes[20]; 1655 int count = 4; 1656 bytes[0] = UNW_X4; 1657 bytes[1] = (qp & 0x3f); 1658 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1659 bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); 1660 count += output_leb128 (bytes + 4, t, 0); 1661 (*f) (count, bytes, NULL); 1662} 1663 1664/* This function allocates a record list structure, and initializes fields. */ 1665 1666static unw_rec_list * 1667alloc_record (unw_record_type t) 1668{ 1669 unw_rec_list *ptr; 1670 ptr = xmalloc (sizeof (*ptr)); 1671 ptr->next = NULL; 1672 ptr->slot_number = SLOT_NUM_NOT_SET; 1673 ptr->r.type = t; 1674 return ptr; 1675} 1676 1677/* This function frees an entire list of record structures. */ 1678 1679void 1680free_list_records (unw_rec_list *first) 1681{ 1682 unw_rec_list *ptr; 1683 for (ptr = first; ptr != NULL;) 1684 { 1685 unw_rec_list *tmp = ptr; 1686 1687 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) 1688 && tmp->r.record.r.mask.i) 1689 free (tmp->r.record.r.mask.i); 1690 1691 ptr = ptr->next; 1692 free (tmp); 1693 } 1694} 1695 1696static unw_rec_list * 1697output_prologue () 1698{ 1699 unw_rec_list *ptr = alloc_record (prologue); 1700 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1701 return ptr; 1702} 1703 1704static unw_rec_list * 1705output_prologue_gr (saved_mask, reg) 1706 unsigned int saved_mask; 1707 unsigned int reg; 1708{ 1709 unw_rec_list *ptr = alloc_record (prologue_gr); 1710 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1711 ptr->r.record.r.grmask = saved_mask; 1712 ptr->r.record.r.grsave = reg; 1713 return ptr; 1714} 1715 1716static unw_rec_list * 1717output_body () 1718{ 1719 unw_rec_list *ptr = alloc_record (body); 1720 return ptr; 1721} 1722 1723static unw_rec_list * 1724output_mem_stack_f (size) 1725 unsigned int size; 1726{ 1727 unw_rec_list *ptr = alloc_record (mem_stack_f); 1728 ptr->r.record.p.size = size; 1729 return ptr; 1730} 1731 1732static unw_rec_list * 1733output_mem_stack_v () 1734{ 1735 unw_rec_list *ptr = alloc_record (mem_stack_v); 1736 return ptr; 1737} 1738 1739static unw_rec_list * 1740output_psp_gr (gr) 1741 unsigned int gr; 1742{ 1743 unw_rec_list *ptr = alloc_record (psp_gr); 1744 ptr->r.record.p.gr = gr; 1745 return ptr; 1746} 1747 1748static unw_rec_list * 1749output_psp_sprel (offset) 1750 unsigned int offset; 1751{ 1752 unw_rec_list *ptr = alloc_record (psp_sprel); 1753 ptr->r.record.p.spoff = offset / 4; 1754 return ptr; 1755} 1756 1757static unw_rec_list * 1758output_rp_when () 1759{ 1760 unw_rec_list *ptr = alloc_record (rp_when); 1761 return ptr; 1762} 1763 1764static unw_rec_list * 1765output_rp_gr (gr) 1766 unsigned int gr; 1767{ 1768 unw_rec_list *ptr = alloc_record (rp_gr); 1769 ptr->r.record.p.gr = gr; 1770 return ptr; 1771} 1772 1773static unw_rec_list * 1774output_rp_br (br) 1775 unsigned int br; 1776{ 1777 unw_rec_list *ptr = alloc_record (rp_br); 1778 ptr->r.record.p.br = br; 1779 return ptr; 1780} 1781 1782static unw_rec_list * 1783output_rp_psprel (offset) 1784 unsigned int offset; 1785{ 1786 unw_rec_list *ptr = alloc_record (rp_psprel); 1787 ptr->r.record.p.pspoff = offset / 4; 1788 return ptr; 1789} 1790 1791static unw_rec_list * 1792output_rp_sprel (offset) 1793 unsigned int offset; 1794{ 1795 unw_rec_list *ptr = alloc_record (rp_sprel); 1796 ptr->r.record.p.spoff = offset / 4; 1797 return ptr; 1798} 1799 1800static unw_rec_list * 1801output_pfs_when () 1802{ 1803 unw_rec_list *ptr = alloc_record (pfs_when); 1804 return ptr; 1805} 1806 1807static unw_rec_list * 1808output_pfs_gr (gr) 1809 unsigned int gr; 1810{ 1811 unw_rec_list *ptr = alloc_record (pfs_gr); 1812 ptr->r.record.p.gr = gr; 1813 return ptr; 1814} 1815 1816static unw_rec_list * 1817output_pfs_psprel (offset) 1818 unsigned int offset; 1819{ 1820 unw_rec_list *ptr = alloc_record (pfs_psprel); 1821 ptr->r.record.p.pspoff = offset / 4; 1822 return ptr; 1823} 1824 1825static unw_rec_list * 1826output_pfs_sprel (offset) 1827 unsigned int offset; 1828{ 1829 unw_rec_list *ptr = alloc_record (pfs_sprel); 1830 ptr->r.record.p.spoff = offset / 4; 1831 return ptr; 1832} 1833 1834static unw_rec_list * 1835output_preds_when () 1836{ 1837 unw_rec_list *ptr = alloc_record (preds_when); 1838 return ptr; 1839} 1840 1841static unw_rec_list * 1842output_preds_gr (gr) 1843 unsigned int gr; 1844{ 1845 unw_rec_list *ptr = alloc_record (preds_gr); 1846 ptr->r.record.p.gr = gr; 1847 return ptr; 1848} 1849 1850static unw_rec_list * 1851output_preds_psprel (offset) 1852 unsigned int offset; 1853{ 1854 unw_rec_list *ptr = alloc_record (preds_psprel); 1855 ptr->r.record.p.pspoff = offset / 4; 1856 return ptr; 1857} 1858 1859static unw_rec_list * 1860output_preds_sprel (offset) 1861 unsigned int offset; 1862{ 1863 unw_rec_list *ptr = alloc_record (preds_sprel); 1864 ptr->r.record.p.spoff = offset / 4; 1865 return ptr; 1866} 1867 1868static unw_rec_list * 1869output_fr_mem (mask) 1870 unsigned int mask; 1871{ 1872 unw_rec_list *ptr = alloc_record (fr_mem); 1873 ptr->r.record.p.rmask = mask; 1874 return ptr; 1875} 1876 1877static unw_rec_list * 1878output_frgr_mem (gr_mask, fr_mask) 1879 unsigned int gr_mask; 1880 unsigned int fr_mask; 1881{ 1882 unw_rec_list *ptr = alloc_record (frgr_mem); 1883 ptr->r.record.p.grmask = gr_mask; 1884 ptr->r.record.p.frmask = fr_mask; 1885 return ptr; 1886} 1887 1888static unw_rec_list * 1889output_gr_gr (mask, reg) 1890 unsigned int mask; 1891 unsigned int reg; 1892{ 1893 unw_rec_list *ptr = alloc_record (gr_gr); 1894 ptr->r.record.p.grmask = mask; 1895 ptr->r.record.p.gr = reg; 1896 return ptr; 1897} 1898 1899static unw_rec_list * 1900output_gr_mem (mask) 1901 unsigned int mask; 1902{ 1903 unw_rec_list *ptr = alloc_record (gr_mem); 1904 ptr->r.record.p.rmask = mask; 1905 return ptr; 1906} 1907 1908static unw_rec_list * 1909output_br_mem (unsigned int mask) 1910{ 1911 unw_rec_list *ptr = alloc_record (br_mem); 1912 ptr->r.record.p.brmask = mask; 1913 return ptr; 1914} 1915 1916static unw_rec_list * 1917output_br_gr (save_mask, reg) 1918 unsigned int save_mask; 1919 unsigned int reg; 1920{ 1921 unw_rec_list *ptr = alloc_record (br_gr); 1922 ptr->r.record.p.brmask = save_mask; 1923 ptr->r.record.p.gr = reg; 1924 return ptr; 1925} 1926 1927static unw_rec_list * 1928output_spill_base (offset) 1929 unsigned int offset; 1930{ 1931 unw_rec_list *ptr = alloc_record (spill_base); 1932 ptr->r.record.p.pspoff = offset / 4; 1933 return ptr; 1934} 1935 1936static unw_rec_list * 1937output_unat_when () 1938{ 1939 unw_rec_list *ptr = alloc_record (unat_when); 1940 return ptr; 1941} 1942 1943static unw_rec_list * 1944output_unat_gr (gr) 1945 unsigned int gr; 1946{ 1947 unw_rec_list *ptr = alloc_record (unat_gr); 1948 ptr->r.record.p.gr = gr; 1949 return ptr; 1950} 1951 1952static unw_rec_list * 1953output_unat_psprel (offset) 1954 unsigned int offset; 1955{ 1956 unw_rec_list *ptr = alloc_record (unat_psprel); 1957 ptr->r.record.p.pspoff = offset / 4; 1958 return ptr; 1959} 1960 1961static unw_rec_list * 1962output_unat_sprel (offset) 1963 unsigned int offset; 1964{ 1965 unw_rec_list *ptr = alloc_record (unat_sprel); 1966 ptr->r.record.p.spoff = offset / 4; 1967 return ptr; 1968} 1969 1970static unw_rec_list * 1971output_lc_when () 1972{ 1973 unw_rec_list *ptr = alloc_record (lc_when); 1974 return ptr; 1975} 1976 1977static unw_rec_list * 1978output_lc_gr (gr) 1979 unsigned int gr; 1980{ 1981 unw_rec_list *ptr = alloc_record (lc_gr); 1982 ptr->r.record.p.gr = gr; 1983 return ptr; 1984} 1985 1986static unw_rec_list * 1987output_lc_psprel (offset) 1988 unsigned int offset; 1989{ 1990 unw_rec_list *ptr = alloc_record (lc_psprel); 1991 ptr->r.record.p.pspoff = offset / 4; 1992 return ptr; 1993} 1994 1995static unw_rec_list * 1996output_lc_sprel (offset) 1997 unsigned int offset; 1998{ 1999 unw_rec_list *ptr = alloc_record (lc_sprel); 2000 ptr->r.record.p.spoff = offset / 4; 2001 return ptr; 2002} 2003 2004static unw_rec_list * 2005output_fpsr_when () 2006{ 2007 unw_rec_list *ptr = alloc_record (fpsr_when); 2008 return ptr; 2009} 2010 2011static unw_rec_list * 2012output_fpsr_gr (gr) 2013 unsigned int gr; 2014{ 2015 unw_rec_list *ptr = alloc_record (fpsr_gr); 2016 ptr->r.record.p.gr = gr; 2017 return ptr; 2018} 2019 2020static unw_rec_list * 2021output_fpsr_psprel (offset) 2022 unsigned int offset; 2023{ 2024 unw_rec_list *ptr = alloc_record (fpsr_psprel); 2025 ptr->r.record.p.pspoff = offset / 4; 2026 return ptr; 2027} 2028 2029static unw_rec_list * 2030output_fpsr_sprel (offset) 2031 unsigned int offset; 2032{ 2033 unw_rec_list *ptr = alloc_record (fpsr_sprel); 2034 ptr->r.record.p.spoff = offset / 4; 2035 return ptr; 2036} 2037 2038static unw_rec_list * 2039output_priunat_when_gr () 2040{ 2041 unw_rec_list *ptr = alloc_record (priunat_when_gr); 2042 return ptr; 2043} 2044 2045static unw_rec_list * 2046output_priunat_when_mem () 2047{ 2048 unw_rec_list *ptr = alloc_record (priunat_when_mem); 2049 return ptr; 2050} 2051 2052static unw_rec_list * 2053output_priunat_gr (gr) 2054 unsigned int gr; 2055{ 2056 unw_rec_list *ptr = alloc_record (priunat_gr); 2057 ptr->r.record.p.gr = gr; 2058 return ptr; 2059} 2060 2061static unw_rec_list * 2062output_priunat_psprel (offset) 2063 unsigned int offset; 2064{ 2065 unw_rec_list *ptr = alloc_record (priunat_psprel); 2066 ptr->r.record.p.pspoff = offset / 4; 2067 return ptr; 2068} 2069 2070static unw_rec_list * 2071output_priunat_sprel (offset) 2072 unsigned int offset; 2073{ 2074 unw_rec_list *ptr = alloc_record (priunat_sprel); 2075 ptr->r.record.p.spoff = offset / 4; 2076 return ptr; 2077} 2078 2079static unw_rec_list * 2080output_bsp_when () 2081{ 2082 unw_rec_list *ptr = alloc_record (bsp_when); 2083 return ptr; 2084} 2085 2086static unw_rec_list * 2087output_bsp_gr (gr) 2088 unsigned int gr; 2089{ 2090 unw_rec_list *ptr = alloc_record (bsp_gr); 2091 ptr->r.record.p.gr = gr; 2092 return ptr; 2093} 2094 2095static unw_rec_list * 2096output_bsp_psprel (offset) 2097 unsigned int offset; 2098{ 2099 unw_rec_list *ptr = alloc_record (bsp_psprel); 2100 ptr->r.record.p.pspoff = offset / 4; 2101 return ptr; 2102} 2103 2104static unw_rec_list * 2105output_bsp_sprel (offset) 2106 unsigned int offset; 2107{ 2108 unw_rec_list *ptr = alloc_record (bsp_sprel); 2109 ptr->r.record.p.spoff = offset / 4; 2110 return ptr; 2111} 2112 2113static unw_rec_list * 2114output_bspstore_when () 2115{ 2116 unw_rec_list *ptr = alloc_record (bspstore_when); 2117 return ptr; 2118} 2119 2120static unw_rec_list * 2121output_bspstore_gr (gr) 2122 unsigned int gr; 2123{ 2124 unw_rec_list *ptr = alloc_record (bspstore_gr); 2125 ptr->r.record.p.gr = gr; 2126 return ptr; 2127} 2128 2129static unw_rec_list * 2130output_bspstore_psprel (offset) 2131 unsigned int offset; 2132{ 2133 unw_rec_list *ptr = alloc_record (bspstore_psprel); 2134 ptr->r.record.p.pspoff = offset / 4; 2135 return ptr; 2136} 2137 2138static unw_rec_list * 2139output_bspstore_sprel (offset) 2140 unsigned int offset; 2141{ 2142 unw_rec_list *ptr = alloc_record (bspstore_sprel); 2143 ptr->r.record.p.spoff = offset / 4; 2144 return ptr; 2145} 2146 2147static unw_rec_list * 2148output_rnat_when () 2149{ 2150 unw_rec_list *ptr = alloc_record (rnat_when); 2151 return ptr; 2152} 2153 2154static unw_rec_list * 2155output_rnat_gr (gr) 2156 unsigned int gr; 2157{ 2158 unw_rec_list *ptr = alloc_record (rnat_gr); 2159 ptr->r.record.p.gr = gr; 2160 return ptr; 2161} 2162 2163static unw_rec_list * 2164output_rnat_psprel (offset) 2165 unsigned int offset; 2166{ 2167 unw_rec_list *ptr = alloc_record (rnat_psprel); 2168 ptr->r.record.p.pspoff = offset / 4; 2169 return ptr; 2170} 2171 2172static unw_rec_list * 2173output_rnat_sprel (offset) 2174 unsigned int offset; 2175{ 2176 unw_rec_list *ptr = alloc_record (rnat_sprel); 2177 ptr->r.record.p.spoff = offset / 4; 2178 return ptr; 2179} 2180 2181static unw_rec_list * 2182output_unwabi (abi, context) 2183 unsigned long abi; 2184 unsigned long context; 2185{ 2186 unw_rec_list *ptr = alloc_record (unwabi); 2187 ptr->r.record.p.abi = abi; 2188 ptr->r.record.p.context = context; 2189 return ptr; 2190} 2191 2192static unw_rec_list * 2193output_epilogue (unsigned long ecount) 2194{ 2195 unw_rec_list *ptr = alloc_record (epilogue); 2196 ptr->r.record.b.ecount = ecount; 2197 return ptr; 2198} 2199 2200static unw_rec_list * 2201output_label_state (unsigned long label) 2202{ 2203 unw_rec_list *ptr = alloc_record (label_state); 2204 ptr->r.record.b.label = label; 2205 return ptr; 2206} 2207 2208static unw_rec_list * 2209output_copy_state (unsigned long label) 2210{ 2211 unw_rec_list *ptr = alloc_record (copy_state); 2212 ptr->r.record.b.label = label; 2213 return ptr; 2214} 2215 2216static unw_rec_list * 2217output_spill_psprel (ab, reg, offset) 2218 unsigned int ab; 2219 unsigned int reg; 2220 unsigned int offset; 2221{ 2222 unw_rec_list *ptr = alloc_record (spill_psprel); 2223 ptr->r.record.x.ab = ab; 2224 ptr->r.record.x.reg = reg; 2225 ptr->r.record.x.pspoff = offset / 4; 2226 return ptr; 2227} 2228 2229static unw_rec_list * 2230output_spill_sprel (ab, reg, offset) 2231 unsigned int ab; 2232 unsigned int reg; 2233 unsigned int offset; 2234{ 2235 unw_rec_list *ptr = alloc_record (spill_sprel); 2236 ptr->r.record.x.ab = ab; 2237 ptr->r.record.x.reg = reg; 2238 ptr->r.record.x.spoff = offset / 4; 2239 return ptr; 2240} 2241 2242static unw_rec_list * 2243output_spill_psprel_p (ab, reg, offset, predicate) 2244 unsigned int ab; 2245 unsigned int reg; 2246 unsigned int offset; 2247 unsigned int predicate; 2248{ 2249 unw_rec_list *ptr = alloc_record (spill_psprel_p); 2250 ptr->r.record.x.ab = ab; 2251 ptr->r.record.x.reg = reg; 2252 ptr->r.record.x.pspoff = offset / 4; 2253 ptr->r.record.x.qp = predicate; 2254 return ptr; 2255} 2256 2257static unw_rec_list * 2258output_spill_sprel_p (ab, reg, offset, predicate) 2259 unsigned int ab; 2260 unsigned int reg; 2261 unsigned int offset; 2262 unsigned int predicate; 2263{ 2264 unw_rec_list *ptr = alloc_record (spill_sprel_p); 2265 ptr->r.record.x.ab = ab; 2266 ptr->r.record.x.reg = reg; 2267 ptr->r.record.x.spoff = offset / 4; 2268 ptr->r.record.x.qp = predicate; 2269 return ptr; 2270} 2271 2272static unw_rec_list * 2273output_spill_reg (ab, reg, targ_reg, xy) 2274 unsigned int ab; 2275 unsigned int reg; 2276 unsigned int targ_reg; 2277 unsigned int xy; 2278{ 2279 unw_rec_list *ptr = alloc_record (spill_reg); 2280 ptr->r.record.x.ab = ab; 2281 ptr->r.record.x.reg = reg; 2282 ptr->r.record.x.treg = targ_reg; 2283 ptr->r.record.x.xy = xy; 2284 return ptr; 2285} 2286 2287static unw_rec_list * 2288output_spill_reg_p (ab, reg, targ_reg, xy, predicate) 2289 unsigned int ab; 2290 unsigned int reg; 2291 unsigned int targ_reg; 2292 unsigned int xy; 2293 unsigned int predicate; 2294{ 2295 unw_rec_list *ptr = alloc_record (spill_reg_p); 2296 ptr->r.record.x.ab = ab; 2297 ptr->r.record.x.reg = reg; 2298 ptr->r.record.x.treg = targ_reg; 2299 ptr->r.record.x.xy = xy; 2300 ptr->r.record.x.qp = predicate; 2301 return ptr; 2302} 2303 2304/* Given a unw_rec_list process the correct format with the 2305 specified function. */ 2306 2307static void 2308process_one_record (ptr, f) 2309 unw_rec_list *ptr; 2310 vbyte_func f; 2311{ 2312 unsigned long fr_mask, gr_mask; 2313 2314 switch (ptr->r.type) 2315 { 2316 case gr_mem: 2317 case fr_mem: 2318 case br_mem: 2319 case frgr_mem: 2320 /* These are taken care of by prologue/prologue_gr. */ 2321 break; 2322 2323 case prologue_gr: 2324 case prologue: 2325 if (ptr->r.type == prologue_gr) 2326 output_R2_format (f, ptr->r.record.r.grmask, 2327 ptr->r.record.r.grsave, ptr->r.record.r.rlen); 2328 else 2329 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2330 2331 /* Output descriptor(s) for union of register spills (if any). */ 2332 gr_mask = ptr->r.record.r.mask.gr_mem; 2333 fr_mask = ptr->r.record.r.mask.fr_mem; 2334 if (fr_mask) 2335 { 2336 if ((fr_mask & ~0xfUL) == 0) 2337 output_P6_format (f, fr_mem, fr_mask); 2338 else 2339 { 2340 output_P5_format (f, gr_mask, fr_mask); 2341 gr_mask = 0; 2342 } 2343 } 2344 if (gr_mask) 2345 output_P6_format (f, gr_mem, gr_mask); 2346 if (ptr->r.record.r.mask.br_mem) 2347 output_P1_format (f, ptr->r.record.r.mask.br_mem); 2348 2349 /* output imask descriptor if necessary: */ 2350 if (ptr->r.record.r.mask.i) 2351 output_P4_format (f, ptr->r.record.r.mask.i, 2352 ptr->r.record.r.imask_size); 2353 break; 2354 2355 case body: 2356 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2357 break; 2358 case mem_stack_f: 2359 case mem_stack_v: 2360 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 2361 ptr->r.record.p.size); 2362 break; 2363 case psp_gr: 2364 case rp_gr: 2365 case pfs_gr: 2366 case preds_gr: 2367 case unat_gr: 2368 case lc_gr: 2369 case fpsr_gr: 2370 case priunat_gr: 2371 case bsp_gr: 2372 case bspstore_gr: 2373 case rnat_gr: 2374 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); 2375 break; 2376 case rp_br: 2377 output_P3_format (f, rp_br, ptr->r.record.p.br); 2378 break; 2379 case psp_sprel: 2380 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); 2381 break; 2382 case rp_when: 2383 case pfs_when: 2384 case preds_when: 2385 case unat_when: 2386 case lc_when: 2387 case fpsr_when: 2388 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); 2389 break; 2390 case rp_psprel: 2391 case pfs_psprel: 2392 case preds_psprel: 2393 case unat_psprel: 2394 case lc_psprel: 2395 case fpsr_psprel: 2396 case spill_base: 2397 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); 2398 break; 2399 case rp_sprel: 2400 case pfs_sprel: 2401 case preds_sprel: 2402 case unat_sprel: 2403 case lc_sprel: 2404 case fpsr_sprel: 2405 case priunat_sprel: 2406 case bsp_sprel: 2407 case bspstore_sprel: 2408 case rnat_sprel: 2409 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); 2410 break; 2411 case gr_gr: 2412 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); 2413 break; 2414 case br_gr: 2415 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); 2416 break; 2417 case spill_mask: 2418 as_bad ("spill_mask record unimplemented."); 2419 break; 2420 case priunat_when_gr: 2421 case priunat_when_mem: 2422 case bsp_when: 2423 case bspstore_when: 2424 case rnat_when: 2425 output_P8_format (f, ptr->r.type, ptr->r.record.p.t); 2426 break; 2427 case priunat_psprel: 2428 case bsp_psprel: 2429 case bspstore_psprel: 2430 case rnat_psprel: 2431 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); 2432 break; 2433 case unwabi: 2434 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); 2435 break; 2436 case epilogue: 2437 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); 2438 break; 2439 case label_state: 2440 case copy_state: 2441 output_B4_format (f, ptr->r.type, ptr->r.record.b.label); 2442 break; 2443 case spill_psprel: 2444 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2445 ptr->r.record.x.reg, ptr->r.record.x.t, 2446 ptr->r.record.x.pspoff); 2447 break; 2448 case spill_sprel: 2449 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2450 ptr->r.record.x.reg, ptr->r.record.x.t, 2451 ptr->r.record.x.spoff); 2452 break; 2453 case spill_reg: 2454 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, 2455 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, 2456 ptr->r.record.x.treg, ptr->r.record.x.t); 2457 break; 2458 case spill_psprel_p: 2459 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2460 ptr->r.record.x.ab, ptr->r.record.x.reg, 2461 ptr->r.record.x.t, ptr->r.record.x.pspoff); 2462 break; 2463 case spill_sprel_p: 2464 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2465 ptr->r.record.x.ab, ptr->r.record.x.reg, 2466 ptr->r.record.x.t, ptr->r.record.x.spoff); 2467 break; 2468 case spill_reg_p: 2469 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, 2470 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, 2471 ptr->r.record.x.xy, ptr->r.record.x.treg, 2472 ptr->r.record.x.t); 2473 break; 2474 default: 2475 as_bad ("record_type_not_valid"); 2476 break; 2477 } 2478} 2479 2480/* Given a unw_rec_list list, process all the records with 2481 the specified function. */ 2482static void 2483process_unw_records (list, f) 2484 unw_rec_list *list; 2485 vbyte_func f; 2486{ 2487 unw_rec_list *ptr; 2488 for (ptr = list; ptr; ptr = ptr->next) 2489 process_one_record (ptr, f); 2490} 2491 2492/* Determine the size of a record list in bytes. */ 2493static int 2494calc_record_size (list) 2495 unw_rec_list *list; 2496{ 2497 vbyte_count = 0; 2498 process_unw_records (list, count_output); 2499 return vbyte_count; 2500} 2501 2502/* Update IMASK bitmask to reflect the fact that one or more registers 2503 of type TYPE are saved starting at instruction with index T. If N 2504 bits are set in REGMASK, it is assumed that instructions T through 2505 T+N-1 save these registers. 2506 2507 TYPE values: 2508 0: no save 2509 1: instruction saves next fp reg 2510 2: instruction saves next general reg 2511 3: instruction saves next branch reg */ 2512static void 2513set_imask (region, regmask, t, type) 2514 unw_rec_list *region; 2515 unsigned long regmask; 2516 unsigned long t; 2517 unsigned int type; 2518{ 2519 unsigned char *imask; 2520 unsigned long imask_size; 2521 unsigned int i; 2522 int pos; 2523 2524 imask = region->r.record.r.mask.i; 2525 imask_size = region->r.record.r.imask_size; 2526 if (!imask) 2527 { 2528 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; 2529 imask = xmalloc (imask_size); 2530 memset (imask, 0, imask_size); 2531 2532 region->r.record.r.imask_size = imask_size; 2533 region->r.record.r.mask.i = imask; 2534 } 2535 2536 i = (t / 4) + 1; 2537 pos = 2 * (3 - t % 4); 2538 while (regmask) 2539 { 2540 if (i >= imask_size) 2541 { 2542 as_bad ("Ignoring attempt to spill beyond end of region"); 2543 return; 2544 } 2545 2546 imask[i] |= (type & 0x3) << pos; 2547 2548 regmask &= (regmask - 1); 2549 pos -= 2; 2550 if (pos < 0) 2551 { 2552 pos = 0; 2553 ++i; 2554 } 2555 } 2556} 2557 2558static int 2559count_bits (unsigned long mask) 2560{ 2561 int n = 0; 2562 2563 while (mask) 2564 { 2565 mask &= mask - 1; 2566 ++n; 2567 } 2568 return n; 2569} 2570 2571/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. 2572 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag 2573 containing FIRST_ADDR. */ 2574 2575unsigned long 2576slot_index (slot_addr, slot_frag, first_addr, first_frag) 2577 unsigned long slot_addr; 2578 fragS *slot_frag; 2579 unsigned long first_addr; 2580 fragS *first_frag; 2581{ 2582 unsigned long index = 0; 2583 2584 /* First time we are called, the initial address and frag are invalid. */ 2585 if (first_addr == 0) 2586 return 0; 2587 2588 /* If the two addresses are in different frags, then we need to add in 2589 the remaining size of this frag, and then the entire size of intermediate 2590 frags. */ 2591 while (slot_frag != first_frag) 2592 { 2593 unsigned long start_addr = (unsigned long) &first_frag->fr_literal; 2594 2595 /* Add in the full size of the frag converted to instruction slots. */ 2596 index += 3 * (first_frag->fr_fix >> 4); 2597 /* Subtract away the initial part before first_addr. */ 2598 index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) 2599 + ((first_addr & 0x3) - (start_addr & 0x3))); 2600 2601 /* Move to the beginning of the next frag. */ 2602 first_frag = first_frag->fr_next; 2603 first_addr = (unsigned long) &first_frag->fr_literal; 2604 } 2605 2606 /* Add in the used part of the last frag. */ 2607 index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) 2608 + ((slot_addr & 0x3) - (first_addr & 0x3))); 2609 return index; 2610} 2611 2612/* Optimize unwind record directives. */ 2613 2614static unw_rec_list * 2615optimize_unw_records (list) 2616 unw_rec_list *list; 2617{ 2618 if (!list) 2619 return NULL; 2620 2621 /* If the only unwind record is ".prologue" or ".prologue" followed 2622 by ".body", then we can optimize the unwind directives away. */ 2623 if (list->r.type == prologue 2624 && (list->next == NULL 2625 || (list->next->r.type == body && list->next->next == NULL))) 2626 return NULL; 2627 2628 return list; 2629} 2630 2631/* Given a complete record list, process any records which have 2632 unresolved fields, (ie length counts for a prologue). After 2633 this has been run, all neccessary information should be available 2634 within each record to generate an image. */ 2635 2636static void 2637fixup_unw_records (list) 2638 unw_rec_list *list; 2639{ 2640 unw_rec_list *ptr, *region = 0; 2641 unsigned long first_addr = 0, rlen = 0, t; 2642 fragS *first_frag = 0; 2643 2644 for (ptr = list; ptr; ptr = ptr->next) 2645 { 2646 if (ptr->slot_number == SLOT_NUM_NOT_SET) 2647 as_bad (" Insn slot not set in unwind record."); 2648 t = slot_index (ptr->slot_number, ptr->slot_frag, 2649 first_addr, first_frag); 2650 switch (ptr->r.type) 2651 { 2652 case prologue: 2653 case prologue_gr: 2654 case body: 2655 { 2656 unw_rec_list *last; 2657 int size, dir_len = 0; 2658 unsigned long last_addr; 2659 fragS *last_frag; 2660 2661 first_addr = ptr->slot_number; 2662 first_frag = ptr->slot_frag; 2663 ptr->slot_number = 0; 2664 /* Find either the next body/prologue start, or the end of 2665 the list, and determine the size of the region. */ 2666 last_addr = unwind.next_slot_number; 2667 last_frag = unwind.next_slot_frag; 2668 for (last = ptr->next; last != NULL; last = last->next) 2669 if (last->r.type == prologue || last->r.type == prologue_gr 2670 || last->r.type == body) 2671 { 2672 last_addr = last->slot_number; 2673 last_frag = last->slot_frag; 2674 break; 2675 } 2676 else if (!last->next) 2677 { 2678 /* In the absence of an explicit .body directive, 2679 the prologue ends after the last instruction 2680 covered by an unwind directive. */ 2681 if (ptr->r.type != body) 2682 { 2683 last_addr = last->slot_number; 2684 last_frag = last->slot_frag; 2685 switch (last->r.type) 2686 { 2687 case frgr_mem: 2688 dir_len = (count_bits (last->r.record.p.frmask) 2689 + count_bits (last->r.record.p.grmask)); 2690 break; 2691 case fr_mem: 2692 case gr_mem: 2693 dir_len += count_bits (last->r.record.p.rmask); 2694 break; 2695 case br_mem: 2696 case br_gr: 2697 dir_len += count_bits (last->r.record.p.brmask); 2698 break; 2699 case gr_gr: 2700 dir_len += count_bits (last->r.record.p.grmask); 2701 break; 2702 default: 2703 dir_len = 1; 2704 break; 2705 } 2706 } 2707 break; 2708 } 2709 size = (slot_index (last_addr, last_frag, first_addr, first_frag) 2710 + dir_len); 2711 rlen = ptr->r.record.r.rlen = size; 2712 if (ptr->r.type == body) 2713 /* End of region. */ 2714 region = 0; 2715 else 2716 region = ptr; 2717 break; 2718 } 2719 case epilogue: 2720 ptr->r.record.b.t = rlen - 1 - t; 2721 break; 2722 2723 case mem_stack_f: 2724 case mem_stack_v: 2725 case rp_when: 2726 case pfs_when: 2727 case preds_when: 2728 case unat_when: 2729 case lc_when: 2730 case fpsr_when: 2731 case priunat_when_gr: 2732 case priunat_when_mem: 2733 case bsp_when: 2734 case bspstore_when: 2735 case rnat_when: 2736 ptr->r.record.p.t = t; 2737 break; 2738 2739 case spill_reg: 2740 case spill_sprel: 2741 case spill_psprel: 2742 case spill_reg_p: 2743 case spill_sprel_p: 2744 case spill_psprel_p: 2745 ptr->r.record.x.t = t; 2746 break; 2747 2748 case frgr_mem: 2749 if (!region) 2750 { 2751 as_bad ("frgr_mem record before region record!\n"); 2752 return; 2753 } 2754 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; 2755 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; 2756 set_imask (region, ptr->r.record.p.frmask, t, 1); 2757 set_imask (region, ptr->r.record.p.grmask, t, 2); 2758 break; 2759 case fr_mem: 2760 if (!region) 2761 { 2762 as_bad ("fr_mem record before region record!\n"); 2763 return; 2764 } 2765 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; 2766 set_imask (region, ptr->r.record.p.rmask, t, 1); 2767 break; 2768 case gr_mem: 2769 if (!region) 2770 { 2771 as_bad ("gr_mem record before region record!\n"); 2772 return; 2773 } 2774 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; 2775 set_imask (region, ptr->r.record.p.rmask, t, 2); 2776 break; 2777 case br_mem: 2778 if (!region) 2779 { 2780 as_bad ("br_mem record before region record!\n"); 2781 return; 2782 } 2783 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; 2784 set_imask (region, ptr->r.record.p.brmask, t, 3); 2785 break; 2786 2787 case gr_gr: 2788 if (!region) 2789 { 2790 as_bad ("gr_gr record before region record!\n"); 2791 return; 2792 } 2793 set_imask (region, ptr->r.record.p.grmask, t, 2); 2794 break; 2795 case br_gr: 2796 if (!region) 2797 { 2798 as_bad ("br_gr record before region record!\n"); 2799 return; 2800 } 2801 set_imask (region, ptr->r.record.p.brmask, t, 3); 2802 break; 2803 2804 default: 2805 break; 2806 } 2807 } 2808} 2809 2810/* Helper routine for output_unw_records. Emits the header for the unwind 2811 info. */ 2812 2813static int 2814setup_unwind_header (int size, unsigned char **mem) 2815{ 2816 int x, extra = 0; 2817 valueT flag_value; 2818 2819 /* pad to pointer-size boundry. */ 2820 x = size % md.pointer_size; 2821 if (x != 0) 2822 extra = md.pointer_size - x; 2823 2824 /* Add 8 for the header + a pointer for the 2825 personality offset. */ 2826 *mem = xmalloc (size + extra + 8 + md.pointer_size); 2827 2828 /* Clear the padding area and personality. */ 2829 memset (*mem + 8 + size, 0 , extra + md.pointer_size); 2830 2831 /* Initialize the header area. */ 2832 if (unwind.personality_routine) 2833 { 2834 if (md.flags & EF_IA_64_ABI64) 2835 flag_value = (bfd_vma) 3 << 32; 2836 else 2837 /* 32-bit unwind info block. */ 2838 flag_value = (bfd_vma) 0x1003 << 32; 2839 } 2840 else 2841 flag_value = 0; 2842 2843 md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */ 2844 | flag_value /* U & E handler flags. */ 2845 | ((size + extra) / md.pointer_size)), /* Length. */ 2846 8); 2847 2848 return extra; 2849} 2850 2851/* Generate an unwind image from a record list. Returns the number of 2852 bytes in the resulting image. The memory image itselof is returned 2853 in the 'ptr' parameter. */ 2854static int 2855output_unw_records (list, ptr) 2856 unw_rec_list *list; 2857 void **ptr; 2858{ 2859 int size, extra; 2860 unsigned char *mem; 2861 2862 *ptr = NULL; 2863 2864 list = optimize_unw_records (list); 2865 fixup_unw_records (list); 2866 size = calc_record_size (list); 2867 2868 if (size > 0 || unwind.force_unwind_entry) 2869 { 2870 unwind.force_unwind_entry = 0; 2871 extra = setup_unwind_header (size, &mem); 2872 2873 vbyte_mem_ptr = mem + 8; 2874 process_unw_records (list, output_vbyte_mem); 2875 2876 *ptr = mem; 2877 2878 size += extra + 8 + md.pointer_size; 2879 } 2880 return size; 2881} 2882 2883static int 2884convert_expr_to_ab_reg (e, ab, regp) 2885 expressionS *e; 2886 unsigned int *ab; 2887 unsigned int *regp; 2888{ 2889 unsigned int reg; 2890 2891 if (e->X_op != O_register) 2892 return 0; 2893 2894 reg = e->X_add_number; 2895 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) 2896 { 2897 *ab = 0; 2898 *regp = reg - REG_GR; 2899 } 2900 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) 2901 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) 2902 { 2903 *ab = 1; 2904 *regp = reg - REG_FR; 2905 } 2906 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) 2907 { 2908 *ab = 2; 2909 *regp = reg - REG_BR; 2910 } 2911 else 2912 { 2913 *ab = 3; 2914 switch (reg) 2915 { 2916 case REG_PR: *regp = 0; break; 2917 case REG_PSP: *regp = 1; break; 2918 case REG_PRIUNAT: *regp = 2; break; 2919 case REG_BR + 0: *regp = 3; break; 2920 case REG_AR + AR_BSP: *regp = 4; break; 2921 case REG_AR + AR_BSPSTORE: *regp = 5; break; 2922 case REG_AR + AR_RNAT: *regp = 6; break; 2923 case REG_AR + AR_UNAT: *regp = 7; break; 2924 case REG_AR + AR_FPSR: *regp = 8; break; 2925 case REG_AR + AR_PFS: *regp = 9; break; 2926 case REG_AR + AR_LC: *regp = 10; break; 2927 2928 default: 2929 return 0; 2930 } 2931 } 2932 return 1; 2933} 2934 2935static int 2936convert_expr_to_xy_reg (e, xy, regp) 2937 expressionS *e; 2938 unsigned int *xy; 2939 unsigned int *regp; 2940{ 2941 unsigned int reg; 2942 2943 if (e->X_op != O_register) 2944 return 0; 2945 2946 reg = e->X_add_number; 2947 2948 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) 2949 { 2950 *xy = 0; 2951 *regp = reg - REG_GR; 2952 } 2953 else if (reg >= REG_FR && reg <= (REG_FR + 127)) 2954 { 2955 *xy = 1; 2956 *regp = reg - REG_FR; 2957 } 2958 else if (reg >= REG_BR && reg <= (REG_BR + 7)) 2959 { 2960 *xy = 2; 2961 *regp = reg - REG_BR; 2962 } 2963 else 2964 return -1; 2965 return 1; 2966} 2967 2968static void 2969dot_radix (dummy) 2970 int dummy ATTRIBUTE_UNUSED; 2971{ 2972 int radix; 2973 2974 SKIP_WHITESPACE (); 2975 radix = *input_line_pointer++; 2976 2977 if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) 2978 { 2979 as_bad ("Radix `%c' unsupported", *input_line_pointer); 2980 ignore_rest_of_line (); 2981 return; 2982 } 2983} 2984 2985/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ 2986static void 2987dot_special_section (which) 2988 int which; 2989{ 2990 set_section ((char *) special_section_name[which]); 2991} 2992 2993static void 2994add_unwind_entry (ptr) 2995 unw_rec_list *ptr; 2996{ 2997 if (unwind.tail) 2998 unwind.tail->next = ptr; 2999 else 3000 unwind.list = ptr; 3001 unwind.tail = ptr; 3002 3003 /* The current entry can in fact be a chain of unwind entries. */ 3004 if (unwind.current_entry == NULL) 3005 unwind.current_entry = ptr; 3006} 3007 3008static void 3009dot_fframe (dummy) 3010 int dummy ATTRIBUTE_UNUSED; 3011{ 3012 expressionS e; 3013 3014 parse_operand (&e); 3015 3016 if (e.X_op != O_constant) 3017 as_bad ("Operand to .fframe must be a constant"); 3018 else 3019 add_unwind_entry (output_mem_stack_f (e.X_add_number)); 3020} 3021 3022static void 3023dot_vframe (dummy) 3024 int dummy ATTRIBUTE_UNUSED; 3025{ 3026 expressionS e; 3027 unsigned reg; 3028 3029 parse_operand (&e); 3030 reg = e.X_add_number - REG_GR; 3031 if (e.X_op == O_register && reg < 128) 3032 { 3033 add_unwind_entry (output_mem_stack_v ()); 3034 if (! (unwind.prologue_mask & 2)) 3035 add_unwind_entry (output_psp_gr (reg)); 3036 } 3037 else 3038 as_bad ("First operand to .vframe must be a general register"); 3039} 3040 3041static void 3042dot_vframesp (dummy) 3043 int dummy ATTRIBUTE_UNUSED; 3044{ 3045 expressionS e; 3046 3047 parse_operand (&e); 3048 if (e.X_op == O_constant) 3049 { 3050 add_unwind_entry (output_mem_stack_v ()); 3051 add_unwind_entry (output_psp_sprel (e.X_add_number)); 3052 } 3053 else 3054 as_bad ("First operand to .vframesp must be a general register"); 3055} 3056 3057static void 3058dot_vframepsp (dummy) 3059 int dummy ATTRIBUTE_UNUSED; 3060{ 3061 expressionS e; 3062 3063 parse_operand (&e); 3064 if (e.X_op == O_constant) 3065 { 3066 add_unwind_entry (output_mem_stack_v ()); 3067 add_unwind_entry (output_psp_sprel (e.X_add_number)); 3068 } 3069 else 3070 as_bad ("First operand to .vframepsp must be a general register"); 3071} 3072 3073static void 3074dot_save (dummy) 3075 int dummy ATTRIBUTE_UNUSED; 3076{ 3077 expressionS e1, e2; 3078 int sep; 3079 int reg1, reg2; 3080 3081 sep = parse_operand (&e1); 3082 if (sep != ',') 3083 as_bad ("No second operand to .save"); 3084 sep = parse_operand (&e2); 3085 3086 reg1 = e1.X_add_number; 3087 reg2 = e2.X_add_number - REG_GR; 3088 3089 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3090 if (e1.X_op == O_register) 3091 { 3092 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) 3093 { 3094 switch (reg1) 3095 { 3096 case REG_AR + AR_BSP: 3097 add_unwind_entry (output_bsp_when ()); 3098 add_unwind_entry (output_bsp_gr (reg2)); 3099 break; 3100 case REG_AR + AR_BSPSTORE: 3101 add_unwind_entry (output_bspstore_when ()); 3102 add_unwind_entry (output_bspstore_gr (reg2)); 3103 break; 3104 case REG_AR + AR_RNAT: 3105 add_unwind_entry (output_rnat_when ()); 3106 add_unwind_entry (output_rnat_gr (reg2)); 3107 break; 3108 case REG_AR + AR_UNAT: 3109 add_unwind_entry (output_unat_when ()); 3110 add_unwind_entry (output_unat_gr (reg2)); 3111 break; 3112 case REG_AR + AR_FPSR: 3113 add_unwind_entry (output_fpsr_when ()); 3114 add_unwind_entry (output_fpsr_gr (reg2)); 3115 break; 3116 case REG_AR + AR_PFS: 3117 add_unwind_entry (output_pfs_when ()); 3118 if (! (unwind.prologue_mask & 4)) 3119 add_unwind_entry (output_pfs_gr (reg2)); 3120 break; 3121 case REG_AR + AR_LC: 3122 add_unwind_entry (output_lc_when ()); 3123 add_unwind_entry (output_lc_gr (reg2)); 3124 break; 3125 case REG_BR: 3126 add_unwind_entry (output_rp_when ()); 3127 if (! (unwind.prologue_mask & 8)) 3128 add_unwind_entry (output_rp_gr (reg2)); 3129 break; 3130 case REG_PR: 3131 add_unwind_entry (output_preds_when ()); 3132 if (! (unwind.prologue_mask & 1)) 3133 add_unwind_entry (output_preds_gr (reg2)); 3134 break; 3135 case REG_PRIUNAT: 3136 add_unwind_entry (output_priunat_when_gr ()); 3137 add_unwind_entry (output_priunat_gr (reg2)); 3138 break; 3139 default: 3140 as_bad ("First operand not a valid register"); 3141 } 3142 } 3143 else 3144 as_bad (" Second operand not a valid register"); 3145 } 3146 else 3147 as_bad ("First operand not a register"); 3148} 3149 3150static void 3151dot_restore (dummy) 3152 int dummy ATTRIBUTE_UNUSED; 3153{ 3154 expressionS e1, e2; 3155 unsigned long ecount; /* # of _additional_ regions to pop */ 3156 int sep; 3157 3158 sep = parse_operand (&e1); 3159 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) 3160 { 3161 as_bad ("First operand to .restore must be stack pointer (sp)"); 3162 return; 3163 } 3164 3165 if (sep == ',') 3166 { 3167 parse_operand (&e2); 3168 if (e2.X_op != O_constant || e2.X_add_number < 0) 3169 { 3170 as_bad ("Second operand to .restore must be a constant >= 0"); 3171 return; 3172 } 3173 ecount = e2.X_add_number; 3174 } 3175 else 3176 ecount = unwind.prologue_count - 1; 3177 3178 if (ecount >= unwind.prologue_count) 3179 { 3180 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)", 3181 ecount + 1, unwind.prologue_count); 3182 return; 3183 } 3184 3185 add_unwind_entry (output_epilogue (ecount)); 3186 3187 if (ecount < unwind.prologue_count) 3188 unwind.prologue_count -= ecount + 1; 3189 else 3190 unwind.prologue_count = 0; 3191} 3192 3193static void 3194dot_restorereg (dummy) 3195 int dummy ATTRIBUTE_UNUSED; 3196{ 3197 unsigned int ab, reg; 3198 expressionS e; 3199 3200 parse_operand (&e); 3201 3202 if (!convert_expr_to_ab_reg (&e, &ab, ®)) 3203 { 3204 as_bad ("First operand to .restorereg must be a preserved register"); 3205 return; 3206 } 3207 add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); 3208} 3209 3210static void 3211dot_restorereg_p (dummy) 3212 int dummy ATTRIBUTE_UNUSED; 3213{ 3214 unsigned int qp, ab, reg; 3215 expressionS e1, e2; 3216 int sep; 3217 3218 sep = parse_operand (&e1); 3219 if (sep != ',') 3220 { 3221 as_bad ("No second operand to .restorereg.p"); 3222 return; 3223 } 3224 3225 parse_operand (&e2); 3226 3227 qp = e1.X_add_number - REG_P; 3228 if (e1.X_op != O_register || qp > 63) 3229 { 3230 as_bad ("First operand to .restorereg.p must be a predicate"); 3231 return; 3232 } 3233 3234 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3235 { 3236 as_bad ("Second operand to .restorereg.p must be a preserved register"); 3237 return; 3238 } 3239 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); 3240} 3241 3242static int 3243generate_unwind_image (text_name) 3244 const char *text_name; 3245{ 3246 int size; 3247 unsigned char *unw_rec; 3248 3249 /* Force out pending instructions, to make sure all unwind records have 3250 a valid slot_number field. */ 3251 ia64_flush_insns (); 3252 3253 /* Generate the unwind record. */ 3254 size = output_unw_records (unwind.list, (void **) &unw_rec); 3255 if (size % md.pointer_size != 0) 3256 as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size); 3257 3258 /* If there are unwind records, switch sections, and output the info. */ 3259 if (size != 0) 3260 { 3261 unsigned char *where; 3262 char *sec_name; 3263 expressionS exp; 3264 bfd_reloc_code_real_type reloc; 3265 3266 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); 3267 set_section (sec_name); 3268 bfd_set_section_flags (stdoutput, now_seg, 3269 SEC_LOAD | SEC_ALLOC | SEC_READONLY); 3270 3271 /* Make sure the section has 4 byte alignment for ILP32 and 3272 8 byte alignment for LP64. */ 3273 frag_align (md.pointer_size_shift, 0, 0); 3274 record_alignment (now_seg, md.pointer_size_shift); 3275 3276 /* Set expression which points to start of unwind descriptor area. */ 3277 unwind.info = expr_build_dot (); 3278 3279 where = (unsigned char *) frag_more (size); 3280 3281 /* Issue a label for this address, and keep track of it to put it 3282 in the unwind section. */ 3283 3284 /* Copy the information from the unwind record into this section. The 3285 data is already in the correct byte order. */ 3286 memcpy (where, unw_rec, size); 3287 3288 /* Add the personality address to the image. */ 3289 if (unwind.personality_routine != 0) 3290 { 3291 exp.X_op = O_symbol; 3292 exp.X_add_symbol = unwind.personality_routine; 3293 exp.X_add_number = 0; 3294 3295 if (md.flags & EF_IA_64_BE) 3296 { 3297 if (md.flags & EF_IA_64_ABI64) 3298 reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB; 3299 else 3300 reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB; 3301 } 3302 else 3303 { 3304 if (md.flags & EF_IA_64_ABI64) 3305 reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB; 3306 else 3307 reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB; 3308 } 3309 3310 fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, 3311 md.pointer_size, & exp, 0, reloc); 3312 unwind.personality_routine = 0; 3313 } 3314 } 3315 3316 free_list_records (unwind.list); 3317 free_saved_prologue_counts (); 3318 unwind.list = unwind.tail = unwind.current_entry = NULL; 3319 3320 return size; 3321} 3322 3323static void 3324dot_handlerdata (dummy) 3325 int dummy ATTRIBUTE_UNUSED; 3326{ 3327 const char *text_name = segment_name (now_seg); 3328 3329 /* If text section name starts with ".text" (which it should), 3330 strip this prefix off. */ 3331 if (strcmp (text_name, ".text") == 0) 3332 text_name = ""; 3333 3334 unwind.force_unwind_entry = 1; 3335 3336 /* Remember which segment we're in so we can switch back after .endp */ 3337 unwind.saved_text_seg = now_seg; 3338 unwind.saved_text_subseg = now_subseg; 3339 3340 /* Generate unwind info into unwind-info section and then leave that 3341 section as the currently active one so dataXX directives go into 3342 the language specific data area of the unwind info block. */ 3343 generate_unwind_image (text_name); 3344 demand_empty_rest_of_line (); 3345} 3346 3347static void 3348dot_unwentry (dummy) 3349 int dummy ATTRIBUTE_UNUSED; 3350{ 3351 unwind.force_unwind_entry = 1; 3352 demand_empty_rest_of_line (); 3353} 3354 3355static void 3356dot_altrp (dummy) 3357 int dummy ATTRIBUTE_UNUSED; 3358{ 3359 expressionS e; 3360 unsigned reg; 3361 3362 parse_operand (&e); 3363 reg = e.X_add_number - REG_BR; 3364 if (e.X_op == O_register && reg < 8) 3365 add_unwind_entry (output_rp_br (reg)); 3366 else 3367 as_bad ("First operand not a valid branch register"); 3368} 3369 3370static void 3371dot_savemem (psprel) 3372 int psprel; 3373{ 3374 expressionS e1, e2; 3375 int sep; 3376 int reg1, val; 3377 3378 sep = parse_operand (&e1); 3379 if (sep != ',') 3380 as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); 3381 sep = parse_operand (&e2); 3382 3383 reg1 = e1.X_add_number; 3384 val = e2.X_add_number; 3385 3386 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3387 if (e1.X_op == O_register) 3388 { 3389 if (e2.X_op == O_constant) 3390 { 3391 switch (reg1) 3392 { 3393 case REG_AR + AR_BSP: 3394 add_unwind_entry (output_bsp_when ()); 3395 add_unwind_entry ((psprel 3396 ? output_bsp_psprel 3397 : output_bsp_sprel) (val)); 3398 break; 3399 case REG_AR + AR_BSPSTORE: 3400 add_unwind_entry (output_bspstore_when ()); 3401 add_unwind_entry ((psprel 3402 ? output_bspstore_psprel 3403 : output_bspstore_sprel) (val)); 3404 break; 3405 case REG_AR + AR_RNAT: 3406 add_unwind_entry (output_rnat_when ()); 3407 add_unwind_entry ((psprel 3408 ? output_rnat_psprel 3409 : output_rnat_sprel) (val)); 3410 break; 3411 case REG_AR + AR_UNAT: 3412 add_unwind_entry (output_unat_when ()); 3413 add_unwind_entry ((psprel 3414 ? output_unat_psprel 3415 : output_unat_sprel) (val)); 3416 break; 3417 case REG_AR + AR_FPSR: 3418 add_unwind_entry (output_fpsr_when ()); 3419 add_unwind_entry ((psprel 3420 ? output_fpsr_psprel 3421 : output_fpsr_sprel) (val)); 3422 break; 3423 case REG_AR + AR_PFS: 3424 add_unwind_entry (output_pfs_when ()); 3425 add_unwind_entry ((psprel 3426 ? output_pfs_psprel 3427 : output_pfs_sprel) (val)); 3428 break; 3429 case REG_AR + AR_LC: 3430 add_unwind_entry (output_lc_when ()); 3431 add_unwind_entry ((psprel 3432 ? output_lc_psprel 3433 : output_lc_sprel) (val)); 3434 break; 3435 case REG_BR: 3436 add_unwind_entry (output_rp_when ()); 3437 add_unwind_entry ((psprel 3438 ? output_rp_psprel 3439 : output_rp_sprel) (val)); 3440 break; 3441 case REG_PR: 3442 add_unwind_entry (output_preds_when ()); 3443 add_unwind_entry ((psprel 3444 ? output_preds_psprel 3445 : output_preds_sprel) (val)); 3446 break; 3447 case REG_PRIUNAT: 3448 add_unwind_entry (output_priunat_when_mem ()); 3449 add_unwind_entry ((psprel 3450 ? output_priunat_psprel 3451 : output_priunat_sprel) (val)); 3452 break; 3453 default: 3454 as_bad ("First operand not a valid register"); 3455 } 3456 } 3457 else 3458 as_bad (" Second operand not a valid constant"); 3459 } 3460 else 3461 as_bad ("First operand not a register"); 3462} 3463 3464static void 3465dot_saveg (dummy) 3466 int dummy ATTRIBUTE_UNUSED; 3467{ 3468 expressionS e1, e2; 3469 int sep; 3470 sep = parse_operand (&e1); 3471 if (sep == ',') 3472 parse_operand (&e2); 3473 3474 if (e1.X_op != O_constant) 3475 as_bad ("First operand to .save.g must be a constant."); 3476 else 3477 { 3478 int grmask = e1.X_add_number; 3479 if (sep != ',') 3480 add_unwind_entry (output_gr_mem (grmask)); 3481 else 3482 { 3483 int reg = e2.X_add_number - REG_GR; 3484 if (e2.X_op == O_register && reg >= 0 && reg < 128) 3485 add_unwind_entry (output_gr_gr (grmask, reg)); 3486 else 3487 as_bad ("Second operand is an invalid register."); 3488 } 3489 } 3490} 3491 3492static void 3493dot_savef (dummy) 3494 int dummy ATTRIBUTE_UNUSED; 3495{ 3496 expressionS e1; 3497 int sep; 3498 sep = parse_operand (&e1); 3499 3500 if (e1.X_op != O_constant) 3501 as_bad ("Operand to .save.f must be a constant."); 3502 else 3503 add_unwind_entry (output_fr_mem (e1.X_add_number)); 3504} 3505 3506static void 3507dot_saveb (dummy) 3508 int dummy ATTRIBUTE_UNUSED; 3509{ 3510 expressionS e1, e2; 3511 unsigned int reg; 3512 unsigned char sep; 3513 int brmask; 3514 3515 sep = parse_operand (&e1); 3516 if (e1.X_op != O_constant) 3517 { 3518 as_bad ("First operand to .save.b must be a constant."); 3519 return; 3520 } 3521 brmask = e1.X_add_number; 3522 3523 if (sep == ',') 3524 { 3525 sep = parse_operand (&e2); 3526 reg = e2.X_add_number - REG_GR; 3527 if (e2.X_op != O_register || reg > 127) 3528 { 3529 as_bad ("Second operand to .save.b must be a general register."); 3530 return; 3531 } 3532 add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); 3533 } 3534 else 3535 add_unwind_entry (output_br_mem (brmask)); 3536 3537 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3538 ignore_rest_of_line (); 3539} 3540 3541static void 3542dot_savegf (dummy) 3543 int dummy ATTRIBUTE_UNUSED; 3544{ 3545 expressionS e1, e2; 3546 int sep; 3547 sep = parse_operand (&e1); 3548 if (sep == ',') 3549 parse_operand (&e2); 3550 3551 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) 3552 as_bad ("Both operands of .save.gf must be constants."); 3553 else 3554 { 3555 int grmask = e1.X_add_number; 3556 int frmask = e2.X_add_number; 3557 add_unwind_entry (output_frgr_mem (grmask, frmask)); 3558 } 3559} 3560 3561static void 3562dot_spill (dummy) 3563 int dummy ATTRIBUTE_UNUSED; 3564{ 3565 expressionS e; 3566 unsigned char sep; 3567 3568 sep = parse_operand (&e); 3569 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3570 ignore_rest_of_line (); 3571 3572 if (e.X_op != O_constant) 3573 as_bad ("Operand to .spill must be a constant"); 3574 else 3575 add_unwind_entry (output_spill_base (e.X_add_number)); 3576} 3577 3578static void 3579dot_spillreg (dummy) 3580 int dummy ATTRIBUTE_UNUSED; 3581{ 3582 int sep, ab, xy, reg, treg; 3583 expressionS e1, e2; 3584 3585 sep = parse_operand (&e1); 3586 if (sep != ',') 3587 { 3588 as_bad ("No second operand to .spillreg"); 3589 return; 3590 } 3591 3592 parse_operand (&e2); 3593 3594 if (!convert_expr_to_ab_reg (&e1, &ab, ®)) 3595 { 3596 as_bad ("First operand to .spillreg must be a preserved register"); 3597 return; 3598 } 3599 3600 if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) 3601 { 3602 as_bad ("Second operand to .spillreg must be a register"); 3603 return; 3604 } 3605 3606 add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); 3607} 3608 3609static void 3610dot_spillmem (psprel) 3611 int psprel; 3612{ 3613 expressionS e1, e2; 3614 int sep, ab, reg; 3615 3616 sep = parse_operand (&e1); 3617 if (sep != ',') 3618 { 3619 as_bad ("Second operand missing"); 3620 return; 3621 } 3622 3623 parse_operand (&e2); 3624 3625 if (!convert_expr_to_ab_reg (&e1, &ab, ®)) 3626 { 3627 as_bad ("First operand to .spill%s must be a preserved register", 3628 psprel ? "psp" : "sp"); 3629 return; 3630 } 3631 3632 if (e2.X_op != O_constant) 3633 { 3634 as_bad ("Second operand to .spill%s must be a constant", 3635 psprel ? "psp" : "sp"); 3636 return; 3637 } 3638 3639 if (psprel) 3640 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); 3641 else 3642 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); 3643} 3644 3645static void 3646dot_spillreg_p (dummy) 3647 int dummy ATTRIBUTE_UNUSED; 3648{ 3649 int sep, ab, xy, reg, treg; 3650 expressionS e1, e2, e3; 3651 unsigned int qp; 3652 3653 sep = parse_operand (&e1); 3654 if (sep != ',') 3655 { 3656 as_bad ("No second and third operand to .spillreg.p"); 3657 return; 3658 } 3659 3660 sep = parse_operand (&e2); 3661 if (sep != ',') 3662 { 3663 as_bad ("No third operand to .spillreg.p"); 3664 return; 3665 } 3666 3667 parse_operand (&e3); 3668 3669 qp = e1.X_add_number - REG_P; 3670 3671 if (e1.X_op != O_register || qp > 63) 3672 { 3673 as_bad ("First operand to .spillreg.p must be a predicate"); 3674 return; 3675 } 3676 3677 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3678 { 3679 as_bad ("Second operand to .spillreg.p must be a preserved register"); 3680 return; 3681 } 3682 3683 if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) 3684 { 3685 as_bad ("Third operand to .spillreg.p must be a register"); 3686 return; 3687 } 3688 3689 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); 3690} 3691 3692static void 3693dot_spillmem_p (psprel) 3694 int psprel; 3695{ 3696 expressionS e1, e2, e3; 3697 int sep, ab, reg; 3698 unsigned int qp; 3699 3700 sep = parse_operand (&e1); 3701 if (sep != ',') 3702 { 3703 as_bad ("Second operand missing"); 3704 return; 3705 } 3706 3707 parse_operand (&e2); 3708 if (sep != ',') 3709 { 3710 as_bad ("Second operand missing"); 3711 return; 3712 } 3713 3714 parse_operand (&e3); 3715 3716 qp = e1.X_add_number - REG_P; 3717 if (e1.X_op != O_register || qp > 63) 3718 { 3719 as_bad ("First operand to .spill%s_p must be a predicate", 3720 psprel ? "psp" : "sp"); 3721 return; 3722 } 3723 3724 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3725 { 3726 as_bad ("Second operand to .spill%s_p must be a preserved register", 3727 psprel ? "psp" : "sp"); 3728 return; 3729 } 3730 3731 if (e3.X_op != O_constant) 3732 { 3733 as_bad ("Third operand to .spill%s_p must be a constant", 3734 psprel ? "psp" : "sp"); 3735 return; 3736 } 3737 3738 if (psprel) 3739 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp)); 3740 else 3741 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp)); 3742} 3743 3744static unsigned int 3745get_saved_prologue_count (lbl) 3746 unsigned long lbl; 3747{ 3748 label_prologue_count *lpc = unwind.saved_prologue_counts; 3749 3750 while (lpc != NULL && lpc->label_number != lbl) 3751 lpc = lpc->next; 3752 3753 if (lpc != NULL) 3754 return lpc->prologue_count; 3755 3756 as_bad ("Missing .label_state %ld", lbl); 3757 return 1; 3758} 3759 3760static void 3761save_prologue_count (lbl, count) 3762 unsigned long lbl; 3763 unsigned int count; 3764{ 3765 label_prologue_count *lpc = unwind.saved_prologue_counts; 3766 3767 while (lpc != NULL && lpc->label_number != lbl) 3768 lpc = lpc->next; 3769 3770 if (lpc != NULL) 3771 lpc->prologue_count = count; 3772 else 3773 { 3774 label_prologue_count * new_lpc = xmalloc (sizeof (* new_lpc)); 3775 3776 new_lpc->next = unwind.saved_prologue_counts; 3777 new_lpc->label_number = lbl; 3778 new_lpc->prologue_count = count; 3779 unwind.saved_prologue_counts = new_lpc; 3780 } 3781} 3782 3783static void 3784free_saved_prologue_counts () 3785{ 3786 label_prologue_count * lpc = unwind.saved_prologue_counts; 3787 label_prologue_count * next; 3788 3789 while (lpc != NULL) 3790 { 3791 next = lpc->next; 3792 free (lpc); 3793 lpc = next; 3794 } 3795 3796 unwind.saved_prologue_counts = NULL; 3797} 3798 3799static void 3800dot_label_state (dummy) 3801 int dummy ATTRIBUTE_UNUSED; 3802{ 3803 expressionS e; 3804 3805 parse_operand (&e); 3806 if (e.X_op != O_constant) 3807 { 3808 as_bad ("Operand to .label_state must be a constant"); 3809 return; 3810 } 3811 add_unwind_entry (output_label_state (e.X_add_number)); 3812 save_prologue_count (e.X_add_number, unwind.prologue_count); 3813} 3814 3815static void 3816dot_copy_state (dummy) 3817 int dummy ATTRIBUTE_UNUSED; 3818{ 3819 expressionS e; 3820 3821 parse_operand (&e); 3822 if (e.X_op != O_constant) 3823 { 3824 as_bad ("Operand to .copy_state must be a constant"); 3825 return; 3826 } 3827 add_unwind_entry (output_copy_state (e.X_add_number)); 3828 unwind.prologue_count = get_saved_prologue_count (e.X_add_number); 3829} 3830 3831static void 3832dot_unwabi (dummy) 3833 int dummy ATTRIBUTE_UNUSED; 3834{ 3835 expressionS e1, e2; 3836 unsigned char sep; 3837 3838 sep = parse_operand (&e1); 3839 if (sep != ',') 3840 { 3841 as_bad ("Second operand to .unwabi missing"); 3842 return; 3843 } 3844 sep = parse_operand (&e2); 3845 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3846 ignore_rest_of_line (); 3847 3848 if (e1.X_op != O_constant) 3849 { 3850 as_bad ("First operand to .unwabi must be a constant"); 3851 return; 3852 } 3853 3854 if (e2.X_op != O_constant) 3855 { 3856 as_bad ("Second operand to .unwabi must be a constant"); 3857 return; 3858 } 3859 3860 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); 3861} 3862 3863static void 3864dot_personality (dummy) 3865 int dummy ATTRIBUTE_UNUSED; 3866{ 3867 char *name, *p, c; 3868 SKIP_WHITESPACE (); 3869 name = input_line_pointer; 3870 c = get_symbol_end (); 3871 p = input_line_pointer; 3872 unwind.personality_routine = symbol_find_or_make (name); 3873 unwind.force_unwind_entry = 1; 3874 *p = c; 3875 SKIP_WHITESPACE (); 3876 demand_empty_rest_of_line (); 3877} 3878 3879static void 3880dot_proc (dummy) 3881 int dummy ATTRIBUTE_UNUSED; 3882{ 3883 char *name, *p, c; 3884 symbolS *sym; 3885 3886 unwind.proc_start = expr_build_dot (); 3887 /* Parse names of main and alternate entry points and mark them as 3888 function symbols: */ 3889 while (1) 3890 { 3891 SKIP_WHITESPACE (); 3892 name = input_line_pointer; 3893 c = get_symbol_end (); 3894 p = input_line_pointer; 3895 sym = symbol_find_or_make (name); 3896 if (unwind.proc_start == 0) 3897 { 3898 unwind.proc_start = sym; 3899 } 3900 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; 3901 *p = c; 3902 SKIP_WHITESPACE (); 3903 if (*input_line_pointer != ',') 3904 break; 3905 ++input_line_pointer; 3906 } 3907 demand_empty_rest_of_line (); 3908 ia64_do_align (16); 3909 3910 unwind.prologue_count = 0; 3911 unwind.list = unwind.tail = unwind.current_entry = NULL; 3912 unwind.personality_routine = 0; 3913} 3914 3915static void 3916dot_body (dummy) 3917 int dummy ATTRIBUTE_UNUSED; 3918{ 3919 unwind.prologue = 0; 3920 unwind.prologue_mask = 0; 3921 3922 add_unwind_entry (output_body ()); 3923 demand_empty_rest_of_line (); 3924} 3925 3926static void 3927dot_prologue (dummy) 3928 int dummy ATTRIBUTE_UNUSED; 3929{ 3930 unsigned char sep; 3931 int mask = 0, grsave = 0; 3932 3933 if (!is_it_end_of_statement ()) 3934 { 3935 expressionS e1, e2; 3936 sep = parse_operand (&e1); 3937 if (sep != ',') 3938 as_bad ("No second operand to .prologue"); 3939 sep = parse_operand (&e2); 3940 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3941 ignore_rest_of_line (); 3942 3943 if (e1.X_op == O_constant) 3944 { 3945 mask = e1.X_add_number; 3946 3947 if (e2.X_op == O_constant) 3948 grsave = e2.X_add_number; 3949 else if (e2.X_op == O_register 3950 && (grsave = e2.X_add_number - REG_GR) < 128) 3951 ; 3952 else 3953 as_bad ("Second operand not a constant or general register"); 3954 3955 add_unwind_entry (output_prologue_gr (mask, grsave)); 3956 } 3957 else 3958 as_bad ("First operand not a constant"); 3959 } 3960 else 3961 add_unwind_entry (output_prologue ()); 3962 3963 unwind.prologue = 1; 3964 unwind.prologue_mask = mask; 3965 ++unwind.prologue_count; 3966} 3967 3968static void 3969dot_endp (dummy) 3970 int dummy ATTRIBUTE_UNUSED; 3971{ 3972 expressionS e; 3973 unsigned char *ptr; 3974 int bytes_per_address; 3975 long where; 3976 segT saved_seg; 3977 subsegT saved_subseg; 3978 const char *sec_name, *text_name; 3979 char *name, *p, c; 3980 symbolS *sym; 3981 3982 if (unwind.saved_text_seg) 3983 { 3984 saved_seg = unwind.saved_text_seg; 3985 saved_subseg = unwind.saved_text_subseg; 3986 unwind.saved_text_seg = NULL; 3987 } 3988 else 3989 { 3990 saved_seg = now_seg; 3991 saved_subseg = now_subseg; 3992 } 3993 3994 /* 3995 Use a slightly ugly scheme to derive the unwind section names from 3996 the text section name: 3997 3998 text sect. unwind table sect. 3999 name: name: comments: 4000 ---------- ----------------- -------------------------------- 4001 .text .IA_64.unwind 4002 .text.foo .IA_64.unwind.text.foo 4003 .foo .IA_64.unwind.foo 4004 .gnu.linkonce.t.foo 4005 .gnu.linkonce.ia64unw.foo 4006 _info .IA_64.unwind_info gas issues error message (ditto) 4007 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) 4008 4009 This mapping is done so that: 4010 4011 (a) An object file with unwind info only in .text will use 4012 unwind section names .IA_64.unwind and .IA_64.unwind_info. 4013 This follows the letter of the ABI and also ensures backwards 4014 compatibility with older toolchains. 4015 4016 (b) An object file with unwind info in multiple text sections 4017 will use separate unwind sections for each text section. 4018 This allows us to properly set the "sh_info" and "sh_link" 4019 fields in SHT_IA_64_UNWIND as required by the ABI and also 4020 lets GNU ld support programs with multiple segments 4021 containing unwind info (as might be the case for certain 4022 embedded applications). 4023 4024 (c) An error is issued if there would be a name clash. 4025 */ 4026 text_name = segment_name (saved_seg); 4027 if (strncmp (text_name, "_info", 5) == 0) 4028 { 4029 as_bad ("Illegal section name `%s' (causes unwind section name clash)", 4030 text_name); 4031 ignore_rest_of_line (); 4032 return; 4033 } 4034 if (strcmp (text_name, ".text") == 0) 4035 text_name = ""; 4036 4037 insn_group_break (1, 0, 0); 4038 4039 /* If there wasn't a .handlerdata, we haven't generated an image yet. */ 4040 if (!unwind.info) 4041 generate_unwind_image (text_name); 4042 4043 if (unwind.info || unwind.force_unwind_entry) 4044 { 4045 subseg_set (md.last_text_seg, 0); 4046 unwind.proc_end = expr_build_dot (); 4047 4048 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); 4049 set_section ((char *) sec_name); 4050 bfd_set_section_flags (stdoutput, now_seg, 4051 SEC_LOAD | SEC_ALLOC | SEC_READONLY); 4052 4053 /* Make sure that section has 4 byte alignment for ILP32 and 4054 8 byte alignment for LP64. */ 4055 record_alignment (now_seg, md.pointer_size_shift); 4056 4057 /* Need space for 3 pointers for procedure start, procedure end, 4058 and unwind info. */ 4059 ptr = frag_more (3 * md.pointer_size); 4060 where = frag_now_fix () - (3 * md.pointer_size); 4061 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; 4062 4063 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ 4064 e.X_op = O_pseudo_fixup; 4065 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4066 e.X_add_number = 0; 4067 e.X_add_symbol = unwind.proc_start; 4068 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); 4069 4070 e.X_op = O_pseudo_fixup; 4071 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4072 e.X_add_number = 0; 4073 e.X_add_symbol = unwind.proc_end; 4074 ia64_cons_fix_new (frag_now, where + bytes_per_address, 4075 bytes_per_address, &e); 4076 4077 if (unwind.info) 4078 { 4079 e.X_op = O_pseudo_fixup; 4080 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4081 e.X_add_number = 0; 4082 e.X_add_symbol = unwind.info; 4083 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), 4084 bytes_per_address, &e); 4085 } 4086 else 4087 md_number_to_chars (ptr + (bytes_per_address * 2), 0, 4088 bytes_per_address); 4089 4090 } 4091 subseg_set (saved_seg, saved_subseg); 4092 4093 /* Parse names of main and alternate entry points and set symbol sizes. */ 4094 while (1) 4095 { 4096 SKIP_WHITESPACE (); 4097 name = input_line_pointer; 4098 c = get_symbol_end (); 4099 p = input_line_pointer; 4100 sym = symbol_find (name); 4101 if (sym && unwind.proc_start 4102 && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION) 4103 && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL) 4104 { 4105 fragS *fr = symbol_get_frag (unwind.proc_start); 4106 fragS *frag = symbol_get_frag (sym); 4107 4108 /* Check whether the function label is at or beyond last 4109 .proc directive. */ 4110 while (fr && fr != frag) 4111 fr = fr->fr_next; 4112 if (fr) 4113 { 4114 if (frag == frag_now && SEG_NORMAL (now_seg)) 4115 S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); 4116 else 4117 { 4118 symbol_get_obj (sym)->size = 4119 (expressionS *) xmalloc (sizeof (expressionS)); 4120 symbol_get_obj (sym)->size->X_op = O_subtract; 4121 symbol_get_obj (sym)->size->X_add_symbol 4122 = symbol_new (FAKE_LABEL_NAME, now_seg, 4123 frag_now_fix (), frag_now); 4124 symbol_get_obj (sym)->size->X_op_symbol = sym; 4125 symbol_get_obj (sym)->size->X_add_number = 0; 4126 } 4127 } 4128 } 4129 *p = c; 4130 SKIP_WHITESPACE (); 4131 if (*input_line_pointer != ',') 4132 break; 4133 ++input_line_pointer; 4134 } 4135 demand_empty_rest_of_line (); 4136 unwind.proc_start = unwind.proc_end = unwind.info = 0; 4137} 4138 4139static void 4140dot_template (template) 4141 int template; 4142{ 4143 CURR_SLOT.user_template = template; 4144} 4145 4146static void 4147dot_regstk (dummy) 4148 int dummy ATTRIBUTE_UNUSED; 4149{ 4150 int ins, locs, outs, rots; 4151 4152 if (is_it_end_of_statement ()) 4153 ins = locs = outs = rots = 0; 4154 else 4155 { 4156 ins = get_absolute_expression (); 4157 if (*input_line_pointer++ != ',') 4158 goto err; 4159 locs = get_absolute_expression (); 4160 if (*input_line_pointer++ != ',') 4161 goto err; 4162 outs = get_absolute_expression (); 4163 if (*input_line_pointer++ != ',') 4164 goto err; 4165 rots = get_absolute_expression (); 4166 } 4167 set_regstack (ins, locs, outs, rots); 4168 return; 4169 4170 err: 4171 as_bad ("Comma expected"); 4172 ignore_rest_of_line (); 4173} 4174 4175static void 4176dot_rot (type) 4177 int type; 4178{ 4179 unsigned num_regs, num_alloced = 0; 4180 struct dynreg **drpp, *dr; 4181 int ch, base_reg = 0; 4182 char *name, *start; 4183 size_t len; 4184 4185 switch (type) 4186 { 4187 case DYNREG_GR: base_reg = REG_GR + 32; break; 4188 case DYNREG_FR: base_reg = REG_FR + 32; break; 4189 case DYNREG_PR: base_reg = REG_P + 16; break; 4190 default: break; 4191 } 4192 4193 /* First, remove existing names from hash table. */ 4194 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) 4195 { 4196 hash_delete (md.dynreg_hash, dr->name); 4197 dr->num_regs = 0; 4198 } 4199 4200 drpp = &md.dynreg[type]; 4201 while (1) 4202 { 4203 start = input_line_pointer; 4204 ch = get_symbol_end (); 4205 *input_line_pointer = ch; 4206 len = (input_line_pointer - start); 4207 4208 SKIP_WHITESPACE (); 4209 if (*input_line_pointer != '[') 4210 { 4211 as_bad ("Expected '['"); 4212 goto err; 4213 } 4214 ++input_line_pointer; /* skip '[' */ 4215 4216 num_regs = get_absolute_expression (); 4217 4218 if (*input_line_pointer++ != ']') 4219 { 4220 as_bad ("Expected ']'"); 4221 goto err; 4222 } 4223 SKIP_WHITESPACE (); 4224 4225 num_alloced += num_regs; 4226 switch (type) 4227 { 4228 case DYNREG_GR: 4229 if (num_alloced > md.rot.num_regs) 4230 { 4231 as_bad ("Used more than the declared %d rotating registers", 4232 md.rot.num_regs); 4233 goto err; 4234 } 4235 break; 4236 case DYNREG_FR: 4237 if (num_alloced > 96) 4238 { 4239 as_bad ("Used more than the available 96 rotating registers"); 4240 goto err; 4241 } 4242 break; 4243 case DYNREG_PR: 4244 if (num_alloced > 48) 4245 { 4246 as_bad ("Used more than the available 48 rotating registers"); 4247 goto err; 4248 } 4249 break; 4250 4251 default: 4252 break; 4253 } 4254 4255 name = obstack_alloc (¬es, len + 1); 4256 memcpy (name, start, len); 4257 name[len] = '\0'; 4258 4259 if (!*drpp) 4260 { 4261 *drpp = obstack_alloc (¬es, sizeof (*dr)); 4262 memset (*drpp, 0, sizeof (*dr)); 4263 } 4264 4265 dr = *drpp; 4266 dr->name = name; 4267 dr->num_regs = num_regs; 4268 dr->base = base_reg; 4269 drpp = &dr->next; 4270 base_reg += num_regs; 4271 4272 if (hash_insert (md.dynreg_hash, name, dr)) 4273 { 4274 as_bad ("Attempt to redefine register set `%s'", name); 4275 goto err; 4276 } 4277 4278 if (*input_line_pointer != ',') 4279 break; 4280 ++input_line_pointer; /* skip comma */ 4281 SKIP_WHITESPACE (); 4282 } 4283 demand_empty_rest_of_line (); 4284 return; 4285 4286 err: 4287 ignore_rest_of_line (); 4288} 4289 4290static void 4291dot_byteorder (byteorder) 4292 int byteorder; 4293{ 4294 target_big_endian = byteorder; 4295} 4296 4297static void 4298dot_psr (dummy) 4299 int dummy ATTRIBUTE_UNUSED; 4300{ 4301 char *option; 4302 int ch; 4303 4304 while (1) 4305 { 4306 option = input_line_pointer; 4307 ch = get_symbol_end (); 4308 if (strcmp (option, "lsb") == 0) 4309 md.flags &= ~EF_IA_64_BE; 4310 else if (strcmp (option, "msb") == 0) 4311 md.flags |= EF_IA_64_BE; 4312 else if (strcmp (option, "abi32") == 0) 4313 md.flags &= ~EF_IA_64_ABI64; 4314 else if (strcmp (option, "abi64") == 0) 4315 md.flags |= EF_IA_64_ABI64; 4316 else 4317 as_bad ("Unknown psr option `%s'", option); 4318 *input_line_pointer = ch; 4319 4320 SKIP_WHITESPACE (); 4321 if (*input_line_pointer != ',') 4322 break; 4323 4324 ++input_line_pointer; 4325 SKIP_WHITESPACE (); 4326 } 4327 demand_empty_rest_of_line (); 4328} 4329 4330static void 4331dot_alias (dummy) 4332 int dummy ATTRIBUTE_UNUSED; 4333{ 4334 as_bad (".alias not implemented yet"); 4335} 4336 4337static void 4338dot_ln (dummy) 4339 int dummy ATTRIBUTE_UNUSED; 4340{ 4341 new_logical_line (0, get_absolute_expression ()); 4342 demand_empty_rest_of_line (); 4343} 4344 4345static char * 4346parse_section_name () 4347{ 4348 char *name; 4349 int len; 4350 4351 SKIP_WHITESPACE (); 4352 if (*input_line_pointer != '"') 4353 { 4354 as_bad ("Missing section name"); 4355 ignore_rest_of_line (); 4356 return 0; 4357 } 4358 name = demand_copy_C_string (&len); 4359 if (!name) 4360 { 4361 ignore_rest_of_line (); 4362 return 0; 4363 } 4364 SKIP_WHITESPACE (); 4365 if (*input_line_pointer != ',') 4366 { 4367 as_bad ("Comma expected after section name"); 4368 ignore_rest_of_line (); 4369 return 0; 4370 } 4371 ++input_line_pointer; /* skip comma */ 4372 return name; 4373} 4374 4375static void 4376dot_xdata (size) 4377 int size; 4378{ 4379 char *name = parse_section_name (); 4380 if (!name) 4381 return; 4382 4383 md.keep_pending_output = 1; 4384 set_section (name); 4385 cons (size); 4386 obj_elf_previous (0); 4387 md.keep_pending_output = 0; 4388} 4389 4390/* Why doesn't float_cons() call md_cons_align() the way cons() does? */ 4391 4392static void 4393stmt_float_cons (kind) 4394 int kind; 4395{ 4396 size_t size; 4397 4398 switch (kind) 4399 { 4400 case 'd': size = 8; break; 4401 case 'x': size = 10; break; 4402 4403 case 'f': 4404 default: 4405 size = 4; 4406 break; 4407 } 4408 ia64_do_align (size); 4409 float_cons (kind); 4410} 4411 4412static void 4413stmt_cons_ua (size) 4414 int size; 4415{ 4416 int saved_auto_align = md.auto_align; 4417 4418 md.auto_align = 0; 4419 cons (size); 4420 md.auto_align = saved_auto_align; 4421} 4422 4423static void 4424dot_xfloat_cons (kind) 4425 int kind; 4426{ 4427 char *name = parse_section_name (); 4428 if (!name) 4429 return; 4430 4431 md.keep_pending_output = 1; 4432 set_section (name); 4433 stmt_float_cons (kind); 4434 obj_elf_previous (0); 4435 md.keep_pending_output = 0; 4436} 4437 4438static void 4439dot_xstringer (zero) 4440 int zero; 4441{ 4442 char *name = parse_section_name (); 4443 if (!name) 4444 return; 4445 4446 md.keep_pending_output = 1; 4447 set_section (name); 4448 stringer (zero); 4449 obj_elf_previous (0); 4450 md.keep_pending_output = 0; 4451} 4452 4453static void 4454dot_xdata_ua (size) 4455 int size; 4456{ 4457 int saved_auto_align = md.auto_align; 4458 char *name = parse_section_name (); 4459 if (!name) 4460 return; 4461 4462 md.keep_pending_output = 1; 4463 set_section (name); 4464 md.auto_align = 0; 4465 cons (size); 4466 md.auto_align = saved_auto_align; 4467 obj_elf_previous (0); 4468 md.keep_pending_output = 0; 4469} 4470 4471static void 4472dot_xfloat_cons_ua (kind) 4473 int kind; 4474{ 4475 int saved_auto_align = md.auto_align; 4476 char *name = parse_section_name (); 4477 if (!name) 4478 return; 4479 4480 md.keep_pending_output = 1; 4481 set_section (name); 4482 md.auto_align = 0; 4483 stmt_float_cons (kind); 4484 md.auto_align = saved_auto_align; 4485 obj_elf_previous (0); 4486 md.keep_pending_output = 0; 4487} 4488 4489/* .reg.val <regname>,value */ 4490 4491static void 4492dot_reg_val (dummy) 4493 int dummy ATTRIBUTE_UNUSED; 4494{ 4495 expressionS reg; 4496 4497 expression (®); 4498 if (reg.X_op != O_register) 4499 { 4500 as_bad (_("Register name expected")); 4501 ignore_rest_of_line (); 4502 } 4503 else if (*input_line_pointer++ != ',') 4504 { 4505 as_bad (_("Comma expected")); 4506 ignore_rest_of_line (); 4507 } 4508 else 4509 { 4510 valueT value = get_absolute_expression (); 4511 int regno = reg.X_add_number; 4512 if (regno < REG_GR || regno > REG_GR + 128) 4513 as_warn (_("Register value annotation ignored")); 4514 else 4515 { 4516 gr_values[regno - REG_GR].known = 1; 4517 gr_values[regno - REG_GR].value = value; 4518 gr_values[regno - REG_GR].path = md.path; 4519 } 4520 } 4521 demand_empty_rest_of_line (); 4522} 4523 4524/* select dv checking mode 4525 .auto 4526 .explicit 4527 .default 4528 4529 A stop is inserted when changing modes 4530 */ 4531 4532static void 4533dot_dv_mode (type) 4534 int type; 4535{ 4536 if (md.manual_bundling) 4537 as_warn (_("Directive invalid within a bundle")); 4538 4539 if (type == 'E' || type == 'A') 4540 md.mode_explicitly_set = 0; 4541 else 4542 md.mode_explicitly_set = 1; 4543 4544 md.detect_dv = 1; 4545 switch (type) 4546 { 4547 case 'A': 4548 case 'a': 4549 if (md.explicit_mode) 4550 insn_group_break (1, 0, 0); 4551 md.explicit_mode = 0; 4552 break; 4553 case 'E': 4554 case 'e': 4555 if (!md.explicit_mode) 4556 insn_group_break (1, 0, 0); 4557 md.explicit_mode = 1; 4558 break; 4559 default: 4560 case 'd': 4561 if (md.explicit_mode != md.default_explicit_mode) 4562 insn_group_break (1, 0, 0); 4563 md.explicit_mode = md.default_explicit_mode; 4564 md.mode_explicitly_set = 0; 4565 break; 4566 } 4567} 4568 4569static void 4570print_prmask (mask) 4571 valueT mask; 4572{ 4573 int regno; 4574 char *comma = ""; 4575 for (regno = 0; regno < 64; regno++) 4576 { 4577 if (mask & ((valueT) 1 << regno)) 4578 { 4579 fprintf (stderr, "%s p%d", comma, regno); 4580 comma = ","; 4581 } 4582 } 4583} 4584 4585/* 4586 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") 4587 .pred.rel.imply p1, p2 (also .pred.rel "imply") 4588 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") 4589 .pred.safe_across_calls p1 [, p2 [,...]] 4590 */ 4591 4592static void 4593dot_pred_rel (type) 4594 int type; 4595{ 4596 valueT mask = 0; 4597 int count = 0; 4598 int p1 = -1, p2 = -1; 4599 4600 if (type == 0) 4601 { 4602 if (*input_line_pointer != '"') 4603 { 4604 as_bad (_("Missing predicate relation type")); 4605 ignore_rest_of_line (); 4606 return; 4607 } 4608 else 4609 { 4610 int len; 4611 char *form = demand_copy_C_string (&len); 4612 if (strcmp (form, "mutex") == 0) 4613 type = 'm'; 4614 else if (strcmp (form, "clear") == 0) 4615 type = 'c'; 4616 else if (strcmp (form, "imply") == 0) 4617 type = 'i'; 4618 else 4619 { 4620 as_bad (_("Unrecognized predicate relation type")); 4621 ignore_rest_of_line (); 4622 return; 4623 } 4624 } 4625 if (*input_line_pointer == ',') 4626 ++input_line_pointer; 4627 SKIP_WHITESPACE (); 4628 } 4629 4630 SKIP_WHITESPACE (); 4631 while (1) 4632 { 4633 valueT bit = 1; 4634 int regno; 4635 4636 if (TOUPPER (*input_line_pointer) != 'P' 4637 || (regno = atoi (++input_line_pointer)) < 0 4638 || regno > 63) 4639 { 4640 as_bad (_("Predicate register expected")); 4641 ignore_rest_of_line (); 4642 return; 4643 } 4644 while (ISDIGIT (*input_line_pointer)) 4645 ++input_line_pointer; 4646 if (p1 == -1) 4647 p1 = regno; 4648 else if (p2 == -1) 4649 p2 = regno; 4650 bit <<= regno; 4651 if (mask & bit) 4652 as_warn (_("Duplicate predicate register ignored")); 4653 mask |= bit; 4654 count++; 4655 /* See if it's a range. */ 4656 if (*input_line_pointer == '-') 4657 { 4658 valueT stop = 1; 4659 ++input_line_pointer; 4660 4661 if (TOUPPER (*input_line_pointer) != 'P' 4662 || (regno = atoi (++input_line_pointer)) < 0 4663 || regno > 63) 4664 { 4665 as_bad (_("Predicate register expected")); 4666 ignore_rest_of_line (); 4667 return; 4668 } 4669 while (ISDIGIT (*input_line_pointer)) 4670 ++input_line_pointer; 4671 stop <<= regno; 4672 if (bit >= stop) 4673 { 4674 as_bad (_("Bad register range")); 4675 ignore_rest_of_line (); 4676 return; 4677 } 4678 while (bit < stop) 4679 { 4680 bit <<= 1; 4681 mask |= bit; 4682 count++; 4683 } 4684 SKIP_WHITESPACE (); 4685 } 4686 if (*input_line_pointer != ',') 4687 break; 4688 ++input_line_pointer; 4689 SKIP_WHITESPACE (); 4690 } 4691 4692 switch (type) 4693 { 4694 case 'c': 4695 if (count == 0) 4696 mask = ~(valueT) 0; 4697 clear_qp_mutex (mask); 4698 clear_qp_implies (mask, (valueT) 0); 4699 break; 4700 case 'i': 4701 if (count != 2 || p1 == -1 || p2 == -1) 4702 as_bad (_("Predicate source and target required")); 4703 else if (p1 == 0 || p2 == 0) 4704 as_bad (_("Use of p0 is not valid in this context")); 4705 else 4706 add_qp_imply (p1, p2); 4707 break; 4708 case 'm': 4709 if (count < 2) 4710 { 4711 as_bad (_("At least two PR arguments expected")); 4712 break; 4713 } 4714 else if (mask & 1) 4715 { 4716 as_bad (_("Use of p0 is not valid in this context")); 4717 break; 4718 } 4719 add_qp_mutex (mask); 4720 break; 4721 case 's': 4722 /* note that we don't override any existing relations */ 4723 if (count == 0) 4724 { 4725 as_bad (_("At least one PR argument expected")); 4726 break; 4727 } 4728 if (md.debug_dv) 4729 { 4730 fprintf (stderr, "Safe across calls: "); 4731 print_prmask (mask); 4732 fprintf (stderr, "\n"); 4733 } 4734 qp_safe_across_calls = mask; 4735 break; 4736 } 4737 demand_empty_rest_of_line (); 4738} 4739 4740/* .entry label [, label [, ...]] 4741 Hint to DV code that the given labels are to be considered entry points. 4742 Otherwise, only global labels are considered entry points. */ 4743 4744static void 4745dot_entry (dummy) 4746 int dummy ATTRIBUTE_UNUSED; 4747{ 4748 const char *err; 4749 char *name; 4750 int c; 4751 symbolS *symbolP; 4752 4753 do 4754 { 4755 name = input_line_pointer; 4756 c = get_symbol_end (); 4757 symbolP = symbol_find_or_make (name); 4758 4759 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); 4760 if (err) 4761 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), 4762 name, err); 4763 4764 *input_line_pointer = c; 4765 SKIP_WHITESPACE (); 4766 c = *input_line_pointer; 4767 if (c == ',') 4768 { 4769 input_line_pointer++; 4770 SKIP_WHITESPACE (); 4771 if (*input_line_pointer == '\n') 4772 c = '\n'; 4773 } 4774 } 4775 while (c == ','); 4776 4777 demand_empty_rest_of_line (); 4778} 4779 4780/* .mem.offset offset, base 4781 "base" is used to distinguish between offsets from a different base. */ 4782 4783static void 4784dot_mem_offset (dummy) 4785 int dummy ATTRIBUTE_UNUSED; 4786{ 4787 md.mem_offset.hint = 1; 4788 md.mem_offset.offset = get_absolute_expression (); 4789 if (*input_line_pointer != ',') 4790 { 4791 as_bad (_("Comma expected")); 4792 ignore_rest_of_line (); 4793 return; 4794 } 4795 ++input_line_pointer; 4796 md.mem_offset.base = get_absolute_expression (); 4797 demand_empty_rest_of_line (); 4798} 4799 4800/* ia64-specific pseudo-ops: */ 4801const pseudo_typeS md_pseudo_table[] = 4802 { 4803 { "radix", dot_radix, 0 }, 4804 { "lcomm", s_lcomm_bytes, 1 }, 4805 { "bss", dot_special_section, SPECIAL_SECTION_BSS }, 4806 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, 4807 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, 4808 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, 4809 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, 4810 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, 4811 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, 4812 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, 4813 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, 4814 { "proc", dot_proc, 0 }, 4815 { "body", dot_body, 0 }, 4816 { "prologue", dot_prologue, 0 }, 4817 { "endp", dot_endp, 0 }, 4818 { "file", dwarf2_directive_file, 0 }, 4819 { "loc", dwarf2_directive_loc, 0 }, 4820 4821 { "fframe", dot_fframe, 0 }, 4822 { "vframe", dot_vframe, 0 }, 4823 { "vframesp", dot_vframesp, 0 }, 4824 { "vframepsp", dot_vframepsp, 0 }, 4825 { "save", dot_save, 0 }, 4826 { "restore", dot_restore, 0 }, 4827 { "restorereg", dot_restorereg, 0 }, 4828 { "restorereg.p", dot_restorereg_p, 0 }, 4829 { "handlerdata", dot_handlerdata, 0 }, 4830 { "unwentry", dot_unwentry, 0 }, 4831 { "altrp", dot_altrp, 0 }, 4832 { "savesp", dot_savemem, 0 }, 4833 { "savepsp", dot_savemem, 1 }, 4834 { "save.g", dot_saveg, 0 }, 4835 { "save.f", dot_savef, 0 }, 4836 { "save.b", dot_saveb, 0 }, 4837 { "save.gf", dot_savegf, 0 }, 4838 { "spill", dot_spill, 0 }, 4839 { "spillreg", dot_spillreg, 0 }, 4840 { "spillsp", dot_spillmem, 0 }, 4841 { "spillpsp", dot_spillmem, 1 }, 4842 { "spillreg.p", dot_spillreg_p, 0 }, 4843 { "spillsp.p", dot_spillmem_p, 0 }, 4844 { "spillpsp.p", dot_spillmem_p, 1 }, 4845 { "label_state", dot_label_state, 0 }, 4846 { "copy_state", dot_copy_state, 0 }, 4847 { "unwabi", dot_unwabi, 0 }, 4848 { "personality", dot_personality, 0 }, 4849#if 0 4850 { "estate", dot_estate, 0 }, 4851#endif 4852 { "mii", dot_template, 0x0 }, 4853 { "mli", dot_template, 0x2 }, /* old format, for compatibility */ 4854 { "mlx", dot_template, 0x2 }, 4855 { "mmi", dot_template, 0x4 }, 4856 { "mfi", dot_template, 0x6 }, 4857 { "mmf", dot_template, 0x7 }, 4858 { "mib", dot_template, 0x8 }, 4859 { "mbb", dot_template, 0x9 }, 4860 { "bbb", dot_template, 0xb }, 4861 { "mmb", dot_template, 0xc }, 4862 { "mfb", dot_template, 0xe }, 4863#if 0 4864 { "lb", dot_scope, 0 }, 4865 { "le", dot_scope, 1 }, 4866#endif 4867 { "align", s_align_bytes, 0 }, 4868 { "regstk", dot_regstk, 0 }, 4869 { "rotr", dot_rot, DYNREG_GR }, 4870 { "rotf", dot_rot, DYNREG_FR }, 4871 { "rotp", dot_rot, DYNREG_PR }, 4872 { "lsb", dot_byteorder, 0 }, 4873 { "msb", dot_byteorder, 1 }, 4874 { "psr", dot_psr, 0 }, 4875 { "alias", dot_alias, 0 }, 4876 { "ln", dot_ln, 0 }, /* source line info (for debugging) */ 4877 4878 { "xdata1", dot_xdata, 1 }, 4879 { "xdata2", dot_xdata, 2 }, 4880 { "xdata4", dot_xdata, 4 }, 4881 { "xdata8", dot_xdata, 8 }, 4882 { "xreal4", dot_xfloat_cons, 'f' }, 4883 { "xreal8", dot_xfloat_cons, 'd' }, 4884 { "xreal10", dot_xfloat_cons, 'x' }, 4885 { "xstring", dot_xstringer, 0 }, 4886 { "xstringz", dot_xstringer, 1 }, 4887 4888 /* unaligned versions: */ 4889 { "xdata2.ua", dot_xdata_ua, 2 }, 4890 { "xdata4.ua", dot_xdata_ua, 4 }, 4891 { "xdata8.ua", dot_xdata_ua, 8 }, 4892 { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, 4893 { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, 4894 { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, 4895 4896 /* annotations/DV checking support */ 4897 { "entry", dot_entry, 0 }, 4898 { "mem.offset", dot_mem_offset, 0 }, 4899 { "pred.rel", dot_pred_rel, 0 }, 4900 { "pred.rel.clear", dot_pred_rel, 'c' }, 4901 { "pred.rel.imply", dot_pred_rel, 'i' }, 4902 { "pred.rel.mutex", dot_pred_rel, 'm' }, 4903 { "pred.safe_across_calls", dot_pred_rel, 's' }, 4904 { "reg.val", dot_reg_val, 0 }, 4905 { "auto", dot_dv_mode, 'a' }, 4906 { "explicit", dot_dv_mode, 'e' }, 4907 { "default", dot_dv_mode, 'd' }, 4908 4909 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. 4910 IA-64 aligns data allocation pseudo-ops by default, so we have to 4911 tell it that these ones are supposed to be unaligned. Long term, 4912 should rewrite so that only IA-64 specific data allocation pseudo-ops 4913 are aligned by default. */ 4914 {"2byte", stmt_cons_ua, 2}, 4915 {"4byte", stmt_cons_ua, 4}, 4916 {"8byte", stmt_cons_ua, 8}, 4917 4918 { NULL, 0, 0 } 4919 }; 4920 4921static const struct pseudo_opcode 4922 { 4923 const char *name; 4924 void (*handler) (int); 4925 int arg; 4926 } 4927pseudo_opcode[] = 4928 { 4929 /* these are more like pseudo-ops, but don't start with a dot */ 4930 { "data1", cons, 1 }, 4931 { "data2", cons, 2 }, 4932 { "data4", cons, 4 }, 4933 { "data8", cons, 8 }, 4934 { "data16", cons, 16 }, 4935 { "real4", stmt_float_cons, 'f' }, 4936 { "real8", stmt_float_cons, 'd' }, 4937 { "real10", stmt_float_cons, 'x' }, 4938 { "string", stringer, 0 }, 4939 { "stringz", stringer, 1 }, 4940 4941 /* unaligned versions: */ 4942 { "data2.ua", stmt_cons_ua, 2 }, 4943 { "data4.ua", stmt_cons_ua, 4 }, 4944 { "data8.ua", stmt_cons_ua, 8 }, 4945 { "data16.ua", stmt_cons_ua, 16 }, 4946 { "real4.ua", float_cons, 'f' }, 4947 { "real8.ua", float_cons, 'd' }, 4948 { "real10.ua", float_cons, 'x' }, 4949 }; 4950 4951/* Declare a register by creating a symbol for it and entering it in 4952 the symbol table. */ 4953 4954static symbolS * 4955declare_register (name, regnum) 4956 const char *name; 4957 int regnum; 4958{ 4959 const char *err; 4960 symbolS *sym; 4961 4962 sym = symbol_new (name, reg_section, regnum, &zero_address_frag); 4963 4964 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); 4965 if (err) 4966 as_fatal ("Inserting \"%s\" into register table failed: %s", 4967 name, err); 4968 4969 return sym; 4970} 4971 4972static void 4973declare_register_set (prefix, num_regs, base_regnum) 4974 const char *prefix; 4975 int num_regs; 4976 int base_regnum; 4977{ 4978 char name[8]; 4979 int i; 4980 4981 for (i = 0; i < num_regs; ++i) 4982 { 4983 sprintf (name, "%s%u", prefix, i); 4984 declare_register (name, base_regnum + i); 4985 } 4986} 4987 4988static unsigned int 4989operand_width (opnd) 4990 enum ia64_opnd opnd; 4991{ 4992 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; 4993 unsigned int bits = 0; 4994 int i; 4995 4996 bits = 0; 4997 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) 4998 bits += odesc->field[i].bits; 4999 5000 return bits; 5001} 5002 5003static enum operand_match_result 5004operand_match (idesc, index, e) 5005 const struct ia64_opcode *idesc; 5006 int index; 5007 expressionS *e; 5008{ 5009 enum ia64_opnd opnd = idesc->operands[index]; 5010 int bits, relocatable = 0; 5011 struct insn_fix *fix; 5012 bfd_signed_vma val; 5013 5014 switch (opnd) 5015 { 5016 /* constants: */ 5017 5018 case IA64_OPND_AR_CCV: 5019 if (e->X_op == O_register && e->X_add_number == REG_AR + 32) 5020 return OPERAND_MATCH; 5021 break; 5022 5023 case IA64_OPND_AR_PFS: 5024 if (e->X_op == O_register && e->X_add_number == REG_AR + 64) 5025 return OPERAND_MATCH; 5026 break; 5027 5028 case IA64_OPND_GR0: 5029 if (e->X_op == O_register && e->X_add_number == REG_GR + 0) 5030 return OPERAND_MATCH; 5031 break; 5032 5033 case IA64_OPND_IP: 5034 if (e->X_op == O_register && e->X_add_number == REG_IP) 5035 return OPERAND_MATCH; 5036 break; 5037 5038 case IA64_OPND_PR: 5039 if (e->X_op == O_register && e->X_add_number == REG_PR) 5040 return OPERAND_MATCH; 5041 break; 5042 5043 case IA64_OPND_PR_ROT: 5044 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) 5045 return OPERAND_MATCH; 5046 break; 5047 5048 case IA64_OPND_PSR: 5049 if (e->X_op == O_register && e->X_add_number == REG_PSR) 5050 return OPERAND_MATCH; 5051 break; 5052 5053 case IA64_OPND_PSR_L: 5054 if (e->X_op == O_register && e->X_add_number == REG_PSR_L) 5055 return OPERAND_MATCH; 5056 break; 5057 5058 case IA64_OPND_PSR_UM: 5059 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) 5060 return OPERAND_MATCH; 5061 break; 5062 5063 case IA64_OPND_C1: 5064 if (e->X_op == O_constant) 5065 { 5066 if (e->X_add_number == 1) 5067 return OPERAND_MATCH; 5068 else 5069 return OPERAND_OUT_OF_RANGE; 5070 } 5071 break; 5072 5073 case IA64_OPND_C8: 5074 if (e->X_op == O_constant) 5075 { 5076 if (e->X_add_number == 8) 5077 return OPERAND_MATCH; 5078 else 5079 return OPERAND_OUT_OF_RANGE; 5080 } 5081 break; 5082 5083 case IA64_OPND_C16: 5084 if (e->X_op == O_constant) 5085 { 5086 if (e->X_add_number == 16) 5087 return OPERAND_MATCH; 5088 else 5089 return OPERAND_OUT_OF_RANGE; 5090 } 5091 break; 5092 5093 /* register operands: */ 5094 5095 case IA64_OPND_AR3: 5096 if (e->X_op == O_register && e->X_add_number >= REG_AR 5097 && e->X_add_number < REG_AR + 128) 5098 return OPERAND_MATCH; 5099 break; 5100 5101 case IA64_OPND_B1: 5102 case IA64_OPND_B2: 5103 if (e->X_op == O_register && e->X_add_number >= REG_BR 5104 && e->X_add_number < REG_BR + 8) 5105 return OPERAND_MATCH; 5106 break; 5107 5108 case IA64_OPND_CR3: 5109 if (e->X_op == O_register && e->X_add_number >= REG_CR 5110 && e->X_add_number < REG_CR + 128) 5111 return OPERAND_MATCH; 5112 break; 5113 5114 case IA64_OPND_F1: 5115 case IA64_OPND_F2: 5116 case IA64_OPND_F3: 5117 case IA64_OPND_F4: 5118 if (e->X_op == O_register && e->X_add_number >= REG_FR 5119 && e->X_add_number < REG_FR + 128) 5120 return OPERAND_MATCH; 5121 break; 5122 5123 case IA64_OPND_P1: 5124 case IA64_OPND_P2: 5125 if (e->X_op == O_register && e->X_add_number >= REG_P 5126 && e->X_add_number < REG_P + 64) 5127 return OPERAND_MATCH; 5128 break; 5129 5130 case IA64_OPND_R1: 5131 case IA64_OPND_R2: 5132 case IA64_OPND_R3: 5133 if (e->X_op == O_register && e->X_add_number >= REG_GR 5134 && e->X_add_number < REG_GR + 128) 5135 return OPERAND_MATCH; 5136 break; 5137 5138 case IA64_OPND_R3_2: 5139 if (e->X_op == O_register && e->X_add_number >= REG_GR) 5140 { 5141 if (e->X_add_number < REG_GR + 4) 5142 return OPERAND_MATCH; 5143 else if (e->X_add_number < REG_GR + 128) 5144 return OPERAND_OUT_OF_RANGE; 5145 } 5146 break; 5147 5148 /* indirect operands: */ 5149 case IA64_OPND_CPUID_R3: 5150 case IA64_OPND_DBR_R3: 5151 case IA64_OPND_DTR_R3: 5152 case IA64_OPND_ITR_R3: 5153 case IA64_OPND_IBR_R3: 5154 case IA64_OPND_MSR_R3: 5155 case IA64_OPND_PKR_R3: 5156 case IA64_OPND_PMC_R3: 5157 case IA64_OPND_PMD_R3: 5158 case IA64_OPND_RR_R3: 5159 if (e->X_op == O_index && e->X_op_symbol 5160 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID 5161 == opnd - IA64_OPND_CPUID_R3)) 5162 return OPERAND_MATCH; 5163 break; 5164 5165 case IA64_OPND_MR3: 5166 if (e->X_op == O_index && !e->X_op_symbol) 5167 return OPERAND_MATCH; 5168 break; 5169 5170 /* immediate operands: */ 5171 case IA64_OPND_CNT2a: 5172 case IA64_OPND_LEN4: 5173 case IA64_OPND_LEN6: 5174 bits = operand_width (idesc->operands[index]); 5175 if (e->X_op == O_constant) 5176 { 5177 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) 5178 return OPERAND_MATCH; 5179 else 5180 return OPERAND_OUT_OF_RANGE; 5181 } 5182 break; 5183 5184 case IA64_OPND_CNT2b: 5185 if (e->X_op == O_constant) 5186 { 5187 if ((bfd_vma) (e->X_add_number - 1) < 3) 5188 return OPERAND_MATCH; 5189 else 5190 return OPERAND_OUT_OF_RANGE; 5191 } 5192 break; 5193 5194 case IA64_OPND_CNT2c: 5195 val = e->X_add_number; 5196 if (e->X_op == O_constant) 5197 { 5198 if ((val == 0 || val == 7 || val == 15 || val == 16)) 5199 return OPERAND_MATCH; 5200 else 5201 return OPERAND_OUT_OF_RANGE; 5202 } 5203 break; 5204 5205 case IA64_OPND_SOR: 5206 /* SOR must be an integer multiple of 8 */ 5207 if (e->X_op == O_constant && e->X_add_number & 0x7) 5208 return OPERAND_OUT_OF_RANGE; 5209 case IA64_OPND_SOF: 5210 case IA64_OPND_SOL: 5211 if (e->X_op == O_constant) 5212 { 5213 if ((bfd_vma) e->X_add_number <= 96) 5214 return OPERAND_MATCH; 5215 else 5216 return OPERAND_OUT_OF_RANGE; 5217 } 5218 break; 5219 5220 case IA64_OPND_IMMU62: 5221 if (e->X_op == O_constant) 5222 { 5223 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) 5224 return OPERAND_MATCH; 5225 else 5226 return OPERAND_OUT_OF_RANGE; 5227 } 5228 else 5229 { 5230 /* FIXME -- need 62-bit relocation type */ 5231 as_bad (_("62-bit relocation not yet implemented")); 5232 } 5233 break; 5234 5235 case IA64_OPND_IMMU64: 5236 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup 5237 || e->X_op == O_subtract) 5238 { 5239 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5240 fix->code = BFD_RELOC_IA64_IMM64; 5241 if (e->X_op != O_subtract) 5242 { 5243 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5244 if (e->X_op == O_pseudo_fixup) 5245 e->X_op = O_symbol; 5246 } 5247 5248 fix->opnd = idesc->operands[index]; 5249 fix->expr = *e; 5250 fix->is_pcrel = 0; 5251 ++CURR_SLOT.num_fixups; 5252 return OPERAND_MATCH; 5253 } 5254 else if (e->X_op == O_constant) 5255 return OPERAND_MATCH; 5256 break; 5257 5258 case IA64_OPND_CCNT5: 5259 case IA64_OPND_CNT5: 5260 case IA64_OPND_CNT6: 5261 case IA64_OPND_CPOS6a: 5262 case IA64_OPND_CPOS6b: 5263 case IA64_OPND_CPOS6c: 5264 case IA64_OPND_IMMU2: 5265 case IA64_OPND_IMMU7a: 5266 case IA64_OPND_IMMU7b: 5267 case IA64_OPND_IMMU21: 5268 case IA64_OPND_IMMU24: 5269 case IA64_OPND_MBTYPE4: 5270 case IA64_OPND_MHTYPE8: 5271 case IA64_OPND_POS6: 5272 bits = operand_width (idesc->operands[index]); 5273 if (e->X_op == O_constant) 5274 { 5275 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5276 return OPERAND_MATCH; 5277 else 5278 return OPERAND_OUT_OF_RANGE; 5279 } 5280 break; 5281 5282 case IA64_OPND_IMMU9: 5283 bits = operand_width (idesc->operands[index]); 5284 if (e->X_op == O_constant) 5285 { 5286 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5287 { 5288 int lobits = e->X_add_number & 0x3; 5289 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) 5290 e->X_add_number |= (bfd_vma) 0x3; 5291 return OPERAND_MATCH; 5292 } 5293 else 5294 return OPERAND_OUT_OF_RANGE; 5295 } 5296 break; 5297 5298 case IA64_OPND_IMM44: 5299 /* least 16 bits must be zero */ 5300 if ((e->X_add_number & 0xffff) != 0) 5301 /* XXX technically, this is wrong: we should not be issuing warning 5302 messages until we're sure this instruction pattern is going to 5303 be used! */ 5304 as_warn (_("lower 16 bits of mask ignored")); 5305 5306 if (e->X_op == O_constant) 5307 { 5308 if (((e->X_add_number >= 0 5309 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) 5310 || (e->X_add_number < 0 5311 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) 5312 { 5313 /* sign-extend */ 5314 if (e->X_add_number >= 0 5315 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) 5316 { 5317 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); 5318 } 5319 return OPERAND_MATCH; 5320 } 5321 else 5322 return OPERAND_OUT_OF_RANGE; 5323 } 5324 break; 5325 5326 case IA64_OPND_IMM17: 5327 /* bit 0 is a don't care (pr0 is hardwired to 1) */ 5328 if (e->X_op == O_constant) 5329 { 5330 if (((e->X_add_number >= 0 5331 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) 5332 || (e->X_add_number < 0 5333 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) 5334 { 5335 /* sign-extend */ 5336 if (e->X_add_number >= 0 5337 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) 5338 { 5339 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); 5340 } 5341 return OPERAND_MATCH; 5342 } 5343 else 5344 return OPERAND_OUT_OF_RANGE; 5345 } 5346 break; 5347 5348 case IA64_OPND_IMM14: 5349 case IA64_OPND_IMM22: 5350 relocatable = 1; 5351 case IA64_OPND_IMM1: 5352 case IA64_OPND_IMM8: 5353 case IA64_OPND_IMM8U4: 5354 case IA64_OPND_IMM8M1: 5355 case IA64_OPND_IMM8M1U4: 5356 case IA64_OPND_IMM8M1U8: 5357 case IA64_OPND_IMM9a: 5358 case IA64_OPND_IMM9b: 5359 bits = operand_width (idesc->operands[index]); 5360 if (relocatable && (e->X_op == O_symbol 5361 || e->X_op == O_subtract 5362 || e->X_op == O_pseudo_fixup)) 5363 { 5364 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5365 5366 if (idesc->operands[index] == IA64_OPND_IMM14) 5367 fix->code = BFD_RELOC_IA64_IMM14; 5368 else 5369 fix->code = BFD_RELOC_IA64_IMM22; 5370 5371 if (e->X_op != O_subtract) 5372 { 5373 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5374 if (e->X_op == O_pseudo_fixup) 5375 e->X_op = O_symbol; 5376 } 5377 5378 fix->opnd = idesc->operands[index]; 5379 fix->expr = *e; 5380 fix->is_pcrel = 0; 5381 ++CURR_SLOT.num_fixups; 5382 return OPERAND_MATCH; 5383 } 5384 else if (e->X_op != O_constant 5385 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) 5386 return OPERAND_MISMATCH; 5387 5388 if (opnd == IA64_OPND_IMM8M1U4) 5389 { 5390 /* Zero is not valid for unsigned compares that take an adjusted 5391 constant immediate range. */ 5392 if (e->X_add_number == 0) 5393 return OPERAND_OUT_OF_RANGE; 5394 5395 /* Sign-extend 32-bit unsigned numbers, so that the following range 5396 checks will work. */ 5397 val = e->X_add_number; 5398 if (((val & (~(bfd_vma) 0 << 32)) == 0) 5399 && ((val & ((bfd_vma) 1 << 31)) != 0)) 5400 val = ((val << 32) >> 32); 5401 5402 /* Check for 0x100000000. This is valid because 5403 0x100000000-1 is the same as ((uint32_t) -1). */ 5404 if (val == ((bfd_signed_vma) 1 << 32)) 5405 return OPERAND_MATCH; 5406 5407 val = val - 1; 5408 } 5409 else if (opnd == IA64_OPND_IMM8M1U8) 5410 { 5411 /* Zero is not valid for unsigned compares that take an adjusted 5412 constant immediate range. */ 5413 if (e->X_add_number == 0) 5414 return OPERAND_OUT_OF_RANGE; 5415 5416 /* Check for 0x10000000000000000. */ 5417 if (e->X_op == O_big) 5418 { 5419 if (generic_bignum[0] == 0 5420 && generic_bignum[1] == 0 5421 && generic_bignum[2] == 0 5422 && generic_bignum[3] == 0 5423 && generic_bignum[4] == 1) 5424 return OPERAND_MATCH; 5425 else 5426 return OPERAND_OUT_OF_RANGE; 5427 } 5428 else 5429 val = e->X_add_number - 1; 5430 } 5431 else if (opnd == IA64_OPND_IMM8M1) 5432 val = e->X_add_number - 1; 5433 else if (opnd == IA64_OPND_IMM8U4) 5434 { 5435 /* Sign-extend 32-bit unsigned numbers, so that the following range 5436 checks will work. */ 5437 val = e->X_add_number; 5438 if (((val & (~(bfd_vma) 0 << 32)) == 0) 5439 && ((val & ((bfd_vma) 1 << 31)) != 0)) 5440 val = ((val << 32) >> 32); 5441 } 5442 else 5443 val = e->X_add_number; 5444 5445 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) 5446 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) 5447 return OPERAND_MATCH; 5448 else 5449 return OPERAND_OUT_OF_RANGE; 5450 5451 case IA64_OPND_INC3: 5452 /* +/- 1, 4, 8, 16 */ 5453 val = e->X_add_number; 5454 if (val < 0) 5455 val = -val; 5456 if (e->X_op == O_constant) 5457 { 5458 if ((val == 1 || val == 4 || val == 8 || val == 16)) 5459 return OPERAND_MATCH; 5460 else 5461 return OPERAND_OUT_OF_RANGE; 5462 } 5463 break; 5464 5465 case IA64_OPND_TGT25: 5466 case IA64_OPND_TGT25b: 5467 case IA64_OPND_TGT25c: 5468 case IA64_OPND_TGT64: 5469 if (e->X_op == O_symbol) 5470 { 5471 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5472 if (opnd == IA64_OPND_TGT25) 5473 fix->code = BFD_RELOC_IA64_PCREL21F; 5474 else if (opnd == IA64_OPND_TGT25b) 5475 fix->code = BFD_RELOC_IA64_PCREL21M; 5476 else if (opnd == IA64_OPND_TGT25c) 5477 fix->code = BFD_RELOC_IA64_PCREL21B; 5478 else if (opnd == IA64_OPND_TGT64) 5479 fix->code = BFD_RELOC_IA64_PCREL60B; 5480 else 5481 abort (); 5482 5483 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5484 fix->opnd = idesc->operands[index]; 5485 fix->expr = *e; 5486 fix->is_pcrel = 1; 5487 ++CURR_SLOT.num_fixups; 5488 return OPERAND_MATCH; 5489 } 5490 case IA64_OPND_TAG13: 5491 case IA64_OPND_TAG13b: 5492 switch (e->X_op) 5493 { 5494 case O_constant: 5495 return OPERAND_MATCH; 5496 5497 case O_symbol: 5498 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5499 /* There are no external relocs for TAG13/TAG13b fields, so we 5500 create a dummy reloc. This will not live past md_apply_fix3. */ 5501 fix->code = BFD_RELOC_UNUSED; 5502 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5503 fix->opnd = idesc->operands[index]; 5504 fix->expr = *e; 5505 fix->is_pcrel = 1; 5506 ++CURR_SLOT.num_fixups; 5507 return OPERAND_MATCH; 5508 5509 default: 5510 break; 5511 } 5512 break; 5513 5514 default: 5515 break; 5516 } 5517 return OPERAND_MISMATCH; 5518} 5519 5520static int 5521parse_operand (e) 5522 expressionS *e; 5523{ 5524 int sep = '\0'; 5525 5526 memset (e, 0, sizeof (*e)); 5527 e->X_op = O_absent; 5528 SKIP_WHITESPACE (); 5529 if (*input_line_pointer != '}') 5530 expression (e); 5531 sep = *input_line_pointer++; 5532 5533 if (sep == '}') 5534 { 5535 if (!md.manual_bundling) 5536 as_warn ("Found '}' when manual bundling is off"); 5537 else 5538 CURR_SLOT.manual_bundling_off = 1; 5539 md.manual_bundling = 0; 5540 sep = '\0'; 5541 } 5542 return sep; 5543} 5544 5545/* Returns the next entry in the opcode table that matches the one in 5546 IDESC, and frees the entry in IDESC. If no matching entry is 5547 found, NULL is returned instead. */ 5548 5549static struct ia64_opcode * 5550get_next_opcode (struct ia64_opcode *idesc) 5551{ 5552 struct ia64_opcode *next = ia64_find_next_opcode (idesc); 5553 ia64_free_opcode (idesc); 5554 return next; 5555} 5556 5557/* Parse the operands for the opcode and find the opcode variant that 5558 matches the specified operands, or NULL if no match is possible. */ 5559 5560static struct ia64_opcode * 5561parse_operands (idesc) 5562 struct ia64_opcode *idesc; 5563{ 5564 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; 5565 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; 5566 enum ia64_opnd expected_operand = IA64_OPND_NIL; 5567 enum operand_match_result result; 5568 char mnemonic[129]; 5569 char *first_arg = 0, *end, *saved_input_pointer; 5570 unsigned int sof; 5571 5572 assert (strlen (idesc->name) <= 128); 5573 5574 strcpy (mnemonic, idesc->name); 5575 if (idesc->operands[2] == IA64_OPND_SOF) 5576 { 5577 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we 5578 can't parse the first operand until we have parsed the 5579 remaining operands of the "alloc" instruction. */ 5580 SKIP_WHITESPACE (); 5581 first_arg = input_line_pointer; 5582 end = strchr (input_line_pointer, '='); 5583 if (!end) 5584 { 5585 as_bad ("Expected separator `='"); 5586 return 0; 5587 } 5588 input_line_pointer = end + 1; 5589 ++i; 5590 ++num_outputs; 5591 } 5592 5593 for (; i < NELEMS (CURR_SLOT.opnd); ++i) 5594 { 5595 sep = parse_operand (CURR_SLOT.opnd + i); 5596 if (CURR_SLOT.opnd[i].X_op == O_absent) 5597 break; 5598 5599 ++num_operands; 5600 5601 if (sep != '=' && sep != ',') 5602 break; 5603 5604 if (sep == '=') 5605 { 5606 if (num_outputs > 0) 5607 as_bad ("Duplicate equal sign (=) in instruction"); 5608 else 5609 num_outputs = i + 1; 5610 } 5611 } 5612 if (sep != '\0') 5613 { 5614 as_bad ("Illegal operand separator `%c'", sep); 5615 return 0; 5616 } 5617 5618 if (idesc->operands[2] == IA64_OPND_SOF) 5619 { 5620 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ 5621 know (strcmp (idesc->name, "alloc") == 0); 5622 if (num_operands == 5 /* first_arg not included in this count! */ 5623 && CURR_SLOT.opnd[2].X_op == O_constant 5624 && CURR_SLOT.opnd[3].X_op == O_constant 5625 && CURR_SLOT.opnd[4].X_op == O_constant 5626 && CURR_SLOT.opnd[5].X_op == O_constant) 5627 { 5628 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, 5629 CURR_SLOT.opnd[3].X_add_number, 5630 CURR_SLOT.opnd[4].X_add_number, 5631 CURR_SLOT.opnd[5].X_add_number); 5632 5633 /* now we can parse the first arg: */ 5634 saved_input_pointer = input_line_pointer; 5635 input_line_pointer = first_arg; 5636 sep = parse_operand (CURR_SLOT.opnd + 0); 5637 if (sep != '=') 5638 --num_outputs; /* force error */ 5639 input_line_pointer = saved_input_pointer; 5640 5641 CURR_SLOT.opnd[2].X_add_number = sof; 5642 CURR_SLOT.opnd[3].X_add_number 5643 = sof - CURR_SLOT.opnd[4].X_add_number; 5644 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; 5645 } 5646 } 5647 5648 highest_unmatched_operand = 0; 5649 curr_out_of_range_pos = -1; 5650 error_pos = 0; 5651 expected_operand = idesc->operands[0]; 5652 for (; idesc; idesc = get_next_opcode (idesc)) 5653 { 5654 if (num_outputs != idesc->num_outputs) 5655 continue; /* mismatch in # of outputs */ 5656 5657 CURR_SLOT.num_fixups = 0; 5658 5659 /* Try to match all operands. If we see an out-of-range operand, 5660 then continue trying to match the rest of the operands, since if 5661 the rest match, then this idesc will give the best error message. */ 5662 5663 out_of_range_pos = -1; 5664 for (i = 0; i < num_operands && idesc->operands[i]; ++i) 5665 { 5666 result = operand_match (idesc, i, CURR_SLOT.opnd + i); 5667 if (result != OPERAND_MATCH) 5668 { 5669 if (result != OPERAND_OUT_OF_RANGE) 5670 break; 5671 if (out_of_range_pos < 0) 5672 /* remember position of the first out-of-range operand: */ 5673 out_of_range_pos = i; 5674 } 5675 } 5676 5677 /* If we did not match all operands, or if at least one operand was 5678 out-of-range, then this idesc does not match. Keep track of which 5679 idesc matched the most operands before failing. If we have two 5680 idescs that failed at the same position, and one had an out-of-range 5681 operand, then prefer the out-of-range operand. Thus if we have 5682 "add r0=0x1000000,r1" we get an error saying the constant is out 5683 of range instead of an error saying that the constant should have been 5684 a register. */ 5685 5686 if (i != num_operands || out_of_range_pos >= 0) 5687 { 5688 if (i > highest_unmatched_operand 5689 || (i == highest_unmatched_operand 5690 && out_of_range_pos > curr_out_of_range_pos)) 5691 { 5692 highest_unmatched_operand = i; 5693 if (out_of_range_pos >= 0) 5694 { 5695 expected_operand = idesc->operands[out_of_range_pos]; 5696 error_pos = out_of_range_pos; 5697 } 5698 else 5699 { 5700 expected_operand = idesc->operands[i]; 5701 error_pos = i; 5702 } 5703 curr_out_of_range_pos = out_of_range_pos; 5704 } 5705 continue; 5706 } 5707 5708 if (num_operands < NELEMS (idesc->operands) 5709 && idesc->operands[num_operands]) 5710 continue; /* mismatch in number of arguments */ 5711 5712 break; 5713 } 5714 if (!idesc) 5715 { 5716 if (expected_operand) 5717 as_bad ("Operand %u of `%s' should be %s", 5718 error_pos + 1, mnemonic, 5719 elf64_ia64_operands[expected_operand].desc); 5720 else 5721 as_bad ("Operand mismatch"); 5722 return 0; 5723 } 5724 return idesc; 5725} 5726 5727/* Keep track of state necessary to determine whether a NOP is necessary 5728 to avoid an erratum in A and B step Itanium chips, and return 1 if we 5729 detect a case where additional NOPs may be necessary. */ 5730static int 5731errata_nop_necessary_p (slot, insn_unit) 5732 struct slot *slot; 5733 enum ia64_unit insn_unit; 5734{ 5735 int i; 5736 struct group *this_group = md.last_groups + md.group_idx; 5737 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; 5738 struct ia64_opcode *idesc = slot->idesc; 5739 5740 /* Test whether this could be the first insn in a problematic sequence. */ 5741 if (insn_unit == IA64_UNIT_F) 5742 { 5743 for (i = 0; i < idesc->num_outputs; i++) 5744 if (idesc->operands[i] == IA64_OPND_P1 5745 || idesc->operands[i] == IA64_OPND_P2) 5746 { 5747 int regno = slot->opnd[i].X_add_number - REG_P; 5748 /* Ignore invalid operands; they generate errors elsewhere. */ 5749 if (regno >= 64) 5750 return 0; 5751 this_group->p_reg_set[regno] = 1; 5752 } 5753 } 5754 5755 /* Test whether this could be the second insn in a problematic sequence. */ 5756 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 5757 && prev_group->p_reg_set[slot->qp_regno]) 5758 { 5759 for (i = 0; i < idesc->num_outputs; i++) 5760 if (idesc->operands[i] == IA64_OPND_R1 5761 || idesc->operands[i] == IA64_OPND_R2 5762 || idesc->operands[i] == IA64_OPND_R3) 5763 { 5764 int regno = slot->opnd[i].X_add_number - REG_GR; 5765 /* Ignore invalid operands; they generate errors elsewhere. */ 5766 if (regno >= 128) 5767 return 0; 5768 if (strncmp (idesc->name, "add", 3) != 0 5769 && strncmp (idesc->name, "sub", 3) != 0 5770 && strncmp (idesc->name, "shladd", 6) != 0 5771 && (idesc->flags & IA64_OPCODE_POSTINC) == 0) 5772 this_group->g_reg_set_conditionally[regno] = 1; 5773 } 5774 } 5775 5776 /* Test whether this could be the third insn in a problematic sequence. */ 5777 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) 5778 { 5779 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ 5780 idesc->operands[i] == IA64_OPND_R3 5781 /* For mov indirect. */ 5782 || idesc->operands[i] == IA64_OPND_RR_R3 5783 || idesc->operands[i] == IA64_OPND_DBR_R3 5784 || idesc->operands[i] == IA64_OPND_IBR_R3 5785 || idesc->operands[i] == IA64_OPND_PKR_R3 5786 || idesc->operands[i] == IA64_OPND_PMC_R3 5787 || idesc->operands[i] == IA64_OPND_PMD_R3 5788 || idesc->operands[i] == IA64_OPND_MSR_R3 5789 || idesc->operands[i] == IA64_OPND_CPUID_R3 5790 /* For itr. */ 5791 || idesc->operands[i] == IA64_OPND_ITR_R3 5792 || idesc->operands[i] == IA64_OPND_DTR_R3 5793 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ 5794 || idesc->operands[i] == IA64_OPND_MR3) 5795 { 5796 int regno = slot->opnd[i].X_add_number - REG_GR; 5797 /* Ignore invalid operands; they generate errors elsewhere. */ 5798 if (regno >= 128) 5799 return 0; 5800 if (idesc->operands[i] == IA64_OPND_R3) 5801 { 5802 if (strcmp (idesc->name, "fc") != 0 5803 && strcmp (idesc->name, "tak") != 0 5804 && strcmp (idesc->name, "thash") != 0 5805 && strcmp (idesc->name, "tpa") != 0 5806 && strcmp (idesc->name, "ttag") != 0 5807 && strncmp (idesc->name, "ptr", 3) != 0 5808 && strncmp (idesc->name, "ptc", 3) != 0 5809 && strncmp (idesc->name, "probe", 5) != 0) 5810 return 0; 5811 } 5812 if (prev_group->g_reg_set_conditionally[regno]) 5813 return 1; 5814 } 5815 } 5816 return 0; 5817} 5818 5819static void 5820build_insn (slot, insnp) 5821 struct slot *slot; 5822 bfd_vma *insnp; 5823{ 5824 const struct ia64_operand *odesc, *o2desc; 5825 struct ia64_opcode *idesc = slot->idesc; 5826 bfd_signed_vma insn, val; 5827 const char *err; 5828 int i; 5829 5830 insn = idesc->opcode | slot->qp_regno; 5831 5832 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) 5833 { 5834 if (slot->opnd[i].X_op == O_register 5835 || slot->opnd[i].X_op == O_constant 5836 || slot->opnd[i].X_op == O_index) 5837 val = slot->opnd[i].X_add_number; 5838 else if (slot->opnd[i].X_op == O_big) 5839 { 5840 /* This must be the value 0x10000000000000000. */ 5841 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); 5842 val = 0; 5843 } 5844 else 5845 val = 0; 5846 5847 switch (idesc->operands[i]) 5848 { 5849 case IA64_OPND_IMMU64: 5850 *insnp++ = (val >> 22) & 0x1ffffffffffLL; 5851 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) 5852 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) 5853 | (((val >> 63) & 0x1) << 36)); 5854 continue; 5855 5856 case IA64_OPND_IMMU62: 5857 val &= 0x3fffffffffffffffULL; 5858 if (val != slot->opnd[i].X_add_number) 5859 as_warn (_("Value truncated to 62 bits")); 5860 *insnp++ = (val >> 21) & 0x1ffffffffffLL; 5861 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); 5862 continue; 5863 5864 case IA64_OPND_TGT64: 5865 val >>= 4; 5866 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; 5867 insn |= ((((val >> 59) & 0x1) << 36) 5868 | (((val >> 0) & 0xfffff) << 13)); 5869 continue; 5870 5871 case IA64_OPND_AR3: 5872 val -= REG_AR; 5873 break; 5874 5875 case IA64_OPND_B1: 5876 case IA64_OPND_B2: 5877 val -= REG_BR; 5878 break; 5879 5880 case IA64_OPND_CR3: 5881 val -= REG_CR; 5882 break; 5883 5884 case IA64_OPND_F1: 5885 case IA64_OPND_F2: 5886 case IA64_OPND_F3: 5887 case IA64_OPND_F4: 5888 val -= REG_FR; 5889 break; 5890 5891 case IA64_OPND_P1: 5892 case IA64_OPND_P2: 5893 val -= REG_P; 5894 break; 5895 5896 case IA64_OPND_R1: 5897 case IA64_OPND_R2: 5898 case IA64_OPND_R3: 5899 case IA64_OPND_R3_2: 5900 case IA64_OPND_CPUID_R3: 5901 case IA64_OPND_DBR_R3: 5902 case IA64_OPND_DTR_R3: 5903 case IA64_OPND_ITR_R3: 5904 case IA64_OPND_IBR_R3: 5905 case IA64_OPND_MR3: 5906 case IA64_OPND_MSR_R3: 5907 case IA64_OPND_PKR_R3: 5908 case IA64_OPND_PMC_R3: 5909 case IA64_OPND_PMD_R3: 5910 case IA64_OPND_RR_R3: 5911 val -= REG_GR; 5912 break; 5913 5914 default: 5915 break; 5916 } 5917 5918 odesc = elf64_ia64_operands + idesc->operands[i]; 5919 err = (*odesc->insert) (odesc, val, &insn); 5920 if (err) 5921 as_bad_where (slot->src_file, slot->src_line, 5922 "Bad operand value: %s", err); 5923 if (idesc->flags & IA64_OPCODE_PSEUDO) 5924 { 5925 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) 5926 && odesc == elf64_ia64_operands + IA64_OPND_F3) 5927 { 5928 o2desc = elf64_ia64_operands + IA64_OPND_F2; 5929 (*o2desc->insert) (o2desc, val, &insn); 5930 } 5931 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) 5932 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a 5933 || odesc == elf64_ia64_operands + IA64_OPND_POS6)) 5934 { 5935 o2desc = elf64_ia64_operands + IA64_OPND_LEN6; 5936 (*o2desc->insert) (o2desc, 64 - val, &insn); 5937 } 5938 } 5939 } 5940 *insnp = insn; 5941} 5942 5943static void 5944emit_one_bundle () 5945{ 5946 unsigned int manual_bundling_on = 0, manual_bundling_off = 0; 5947 unsigned int manual_bundling = 0; 5948 enum ia64_unit required_unit, insn_unit = 0; 5949 enum ia64_insn_type type[3], insn_type; 5950 unsigned int template, orig_template; 5951 bfd_vma insn[3] = { -1, -1, -1 }; 5952 struct ia64_opcode *idesc; 5953 int end_of_insn_group = 0, user_template = -1; 5954 int n, i, j, first, curr; 5955 unw_rec_list *ptr; 5956 bfd_vma t0 = 0, t1 = 0; 5957 struct label_fix *lfix; 5958 struct insn_fix *ifix; 5959 char mnemonic[16]; 5960 fixS *fix; 5961 char *f; 5962 5963 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; 5964 know (first >= 0 & first < NUM_SLOTS); 5965 n = MIN (3, md.num_slots_in_use); 5966 5967 /* Determine template: user user_template if specified, best match 5968 otherwise: */ 5969 5970 if (md.slot[first].user_template >= 0) 5971 user_template = template = md.slot[first].user_template; 5972 else 5973 { 5974 /* Auto select appropriate template. */ 5975 memset (type, 0, sizeof (type)); 5976 curr = first; 5977 for (i = 0; i < n; ++i) 5978 { 5979 if (md.slot[curr].label_fixups && i != 0) 5980 break; 5981 type[i] = md.slot[curr].idesc->type; 5982 curr = (curr + 1) % NUM_SLOTS; 5983 } 5984 template = best_template[type[0]][type[1]][type[2]]; 5985 } 5986 5987 /* initialize instructions with appropriate nops: */ 5988 for (i = 0; i < 3; ++i) 5989 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; 5990 5991 f = frag_more (16); 5992 5993 /* now fill in slots with as many insns as possible: */ 5994 curr = first; 5995 idesc = md.slot[curr].idesc; 5996 end_of_insn_group = 0; 5997 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) 5998 { 5999 /* Set the slot number for prologue/body records now as those 6000 refer to the current point, not the point after the 6001 instruction has been issued: */ 6002 /* Don't try to delete prologue/body records here, as that will cause 6003 them to also be deleted from the master list of unwind records. */ 6004 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) 6005 if (ptr->r.type == prologue || ptr->r.type == prologue_gr 6006 || ptr->r.type == body) 6007 { 6008 ptr->slot_number = (unsigned long) f + i; 6009 ptr->slot_frag = frag_now; 6010 } 6011 6012 if (idesc->flags & IA64_OPCODE_SLOT2) 6013 { 6014 if (manual_bundling && i != 2) 6015 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6016 "`%s' must be last in bundle", idesc->name); 6017 else 6018 i = 2; 6019 } 6020 if (idesc->flags & IA64_OPCODE_LAST) 6021 { 6022 int required_slot; 6023 unsigned int required_template; 6024 6025 /* If we need a stop bit after an M slot, our only choice is 6026 template 5 (M;;MI). If we need a stop bit after a B 6027 slot, our only choice is to place it at the end of the 6028 bundle, because the only available templates are MIB, 6029 MBB, BBB, MMB, and MFB. We don't handle anything other 6030 than M and B slots because these are the only kind of 6031 instructions that can have the IA64_OPCODE_LAST bit set. */ 6032 required_template = template; 6033 switch (idesc->type) 6034 { 6035 case IA64_TYPE_M: 6036 required_slot = 0; 6037 required_template = 5; 6038 break; 6039 6040 case IA64_TYPE_B: 6041 required_slot = 2; 6042 break; 6043 6044 default: 6045 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6046 "Internal error: don't know how to force %s to end" 6047 "of instruction group", idesc->name); 6048 required_slot = i; 6049 break; 6050 } 6051 if (manual_bundling && i != required_slot) 6052 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6053 "`%s' must be last in instruction group", 6054 idesc->name); 6055 if (required_slot < i) 6056 /* Can't fit this instruction. */ 6057 break; 6058 6059 i = required_slot; 6060 if (required_template != template) 6061 { 6062 /* If we switch the template, we need to reset the NOPs 6063 after slot i. The slot-types of the instructions ahead 6064 of i never change, so we don't need to worry about 6065 changing NOPs in front of this slot. */ 6066 for (j = i; j < 3; ++j) 6067 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; 6068 } 6069 template = required_template; 6070 } 6071 if (curr != first && md.slot[curr].label_fixups) 6072 { 6073 if (manual_bundling_on) 6074 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6075 "Label must be first in a bundle"); 6076 /* This insn must go into the first slot of a bundle. */ 6077 break; 6078 } 6079 6080 manual_bundling_on = md.slot[curr].manual_bundling_on; 6081 manual_bundling_off = md.slot[curr].manual_bundling_off; 6082 6083 if (manual_bundling_on) 6084 { 6085 if (curr == first) 6086 manual_bundling = 1; 6087 else 6088 break; /* need to start a new bundle */ 6089 } 6090 6091 if (end_of_insn_group && md.num_slots_in_use >= 1) 6092 { 6093 /* We need an instruction group boundary in the middle of a 6094 bundle. See if we can switch to an other template with 6095 an appropriate boundary. */ 6096 6097 orig_template = template; 6098 if (i == 1 && (user_template == 4 6099 || (user_template < 0 6100 && (ia64_templ_desc[template].exec_unit[0] 6101 == IA64_UNIT_M)))) 6102 { 6103 template = 5; 6104 end_of_insn_group = 0; 6105 } 6106 else if (i == 2 && (user_template == 0 6107 || (user_template < 0 6108 && (ia64_templ_desc[template].exec_unit[1] 6109 == IA64_UNIT_I))) 6110 /* This test makes sure we don't switch the template if 6111 the next instruction is one that needs to be first in 6112 an instruction group. Since all those instructions are 6113 in the M group, there is no way such an instruction can 6114 fit in this bundle even if we switch the template. The 6115 reason we have to check for this is that otherwise we 6116 may end up generating "MI;;I M.." which has the deadly 6117 effect that the second M instruction is no longer the 6118 first in the bundle! --davidm 99/12/16 */ 6119 && (idesc->flags & IA64_OPCODE_FIRST) == 0) 6120 { 6121 template = 1; 6122 end_of_insn_group = 0; 6123 } 6124 else if (curr != first) 6125 /* can't fit this insn */ 6126 break; 6127 6128 if (template != orig_template) 6129 /* if we switch the template, we need to reset the NOPs 6130 after slot i. The slot-types of the instructions ahead 6131 of i never change, so we don't need to worry about 6132 changing NOPs in front of this slot. */ 6133 for (j = i; j < 3; ++j) 6134 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; 6135 } 6136 required_unit = ia64_templ_desc[template].exec_unit[i]; 6137 6138 /* resolve dynamic opcodes such as "break" and "nop": */ 6139 if (idesc->type == IA64_TYPE_DYN) 6140 { 6141 if ((strcmp (idesc->name, "nop") == 0) 6142 || (strcmp (idesc->name, "break") == 0)) 6143 insn_unit = required_unit; 6144 else if (strcmp (idesc->name, "chk.s") == 0) 6145 { 6146 insn_unit = IA64_UNIT_M; 6147 if (required_unit == IA64_UNIT_I) 6148 insn_unit = IA64_UNIT_I; 6149 } 6150 else 6151 as_fatal ("emit_one_bundle: unexpected dynamic op"); 6152 6153 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); 6154 ia64_free_opcode (idesc); 6155 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); 6156#if 0 6157 know (!idesc->next); /* no resolved dynamic ops have collisions */ 6158#endif 6159 } 6160 else 6161 { 6162 insn_type = idesc->type; 6163 insn_unit = IA64_UNIT_NIL; 6164 switch (insn_type) 6165 { 6166 case IA64_TYPE_A: 6167 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) 6168 insn_unit = required_unit; 6169 break; 6170 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; 6171 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; 6172 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; 6173 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; 6174 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; 6175 default: break; 6176 } 6177 } 6178 6179 if (insn_unit != required_unit) 6180 { 6181 if (required_unit == IA64_UNIT_L 6182 && insn_unit == IA64_UNIT_I 6183 && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) 6184 { 6185 /* we got ourselves an MLX template but the current 6186 instruction isn't an X-unit, or an I-unit instruction 6187 that can go into the X slot of an MLX template. Duh. */ 6188 if (md.num_slots_in_use >= NUM_SLOTS) 6189 { 6190 as_bad_where (md.slot[curr].src_file, 6191 md.slot[curr].src_line, 6192 "`%s' can't go in X slot of " 6193 "MLX template", idesc->name); 6194 /* drop this insn so we don't livelock: */ 6195 --md.num_slots_in_use; 6196 } 6197 break; 6198 } 6199 continue; /* try next slot */ 6200 } 6201 6202 { 6203 bfd_vma addr; 6204 6205 addr = frag_now->fr_address + frag_now_fix () - 16 + i; 6206 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); 6207 } 6208 6209 if (errata_nop_necessary_p (md.slot + curr, insn_unit)) 6210 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); 6211 6212 build_insn (md.slot + curr, insn + i); 6213 6214 /* Set slot counts for non prologue/body unwind records. */ 6215 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) 6216 if (ptr->r.type != prologue && ptr->r.type != prologue_gr 6217 && ptr->r.type != body) 6218 { 6219 ptr->slot_number = (unsigned long) f + i; 6220 ptr->slot_frag = frag_now; 6221 } 6222 md.slot[curr].unwind_record = NULL; 6223 6224 if (required_unit == IA64_UNIT_L) 6225 { 6226 know (i == 1); 6227 /* skip one slot for long/X-unit instructions */ 6228 ++i; 6229 } 6230 --md.num_slots_in_use; 6231 6232 /* now is a good time to fix up the labels for this insn: */ 6233 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) 6234 { 6235 S_SET_VALUE (lfix->sym, frag_now_fix () - 16); 6236 symbol_set_frag (lfix->sym, frag_now); 6237 } 6238 /* and fix up the tags also. */ 6239 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) 6240 { 6241 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); 6242 symbol_set_frag (lfix->sym, frag_now); 6243 } 6244 6245 for (j = 0; j < md.slot[curr].num_fixups; ++j) 6246 { 6247 ifix = md.slot[curr].fixup + j; 6248 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, 6249 &ifix->expr, ifix->is_pcrel, ifix->code); 6250 fix->tc_fix_data.opnd = ifix->opnd; 6251 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); 6252 fix->fx_file = md.slot[curr].src_file; 6253 fix->fx_line = md.slot[curr].src_line; 6254 } 6255 6256 end_of_insn_group = md.slot[curr].end_of_insn_group; 6257 6258 if (end_of_insn_group) 6259 { 6260 md.group_idx = (md.group_idx + 1) % 3; 6261 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); 6262 } 6263 6264 /* clear slot: */ 6265 ia64_free_opcode (md.slot[curr].idesc); 6266 memset (md.slot + curr, 0, sizeof (md.slot[curr])); 6267 md.slot[curr].user_template = -1; 6268 6269 if (manual_bundling_off) 6270 { 6271 manual_bundling = 0; 6272 break; 6273 } 6274 curr = (curr + 1) % NUM_SLOTS; 6275 idesc = md.slot[curr].idesc; 6276 } 6277 if (manual_bundling) 6278 { 6279 if (md.num_slots_in_use > 0) 6280 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6281 "`%s' does not fit into %s template", 6282 idesc->name, ia64_templ_desc[template].name); 6283 else 6284 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6285 "Missing '}' at end of file"); 6286 } 6287 know (md.num_slots_in_use < NUM_SLOTS); 6288 6289 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); 6290 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 6291 6292 number_to_chars_littleendian (f + 0, t0, 8); 6293 number_to_chars_littleendian (f + 8, t1, 8); 6294 6295 unwind.next_slot_number = (unsigned long) f + 16; 6296 unwind.next_slot_frag = frag_now; 6297} 6298 6299int 6300md_parse_option (c, arg) 6301 int c; 6302 char *arg; 6303{ 6304 6305 switch (c) 6306 { 6307 /* Switches from the Intel assembler. */ 6308 case 'm': 6309 if (strcmp (arg, "ilp64") == 0 6310 || strcmp (arg, "lp64") == 0 6311 || strcmp (arg, "p64") == 0) 6312 { 6313 md.flags |= EF_IA_64_ABI64; 6314 } 6315 else if (strcmp (arg, "ilp32") == 0) 6316 { 6317 md.flags &= ~EF_IA_64_ABI64; 6318 } 6319 else if (strcmp (arg, "le") == 0) 6320 { 6321 md.flags &= ~EF_IA_64_BE; 6322 } 6323 else if (strcmp (arg, "be") == 0) 6324 { 6325 md.flags |= EF_IA_64_BE; 6326 } 6327 else 6328 return 0; 6329 break; 6330 6331 case 'N': 6332 if (strcmp (arg, "so") == 0) 6333 { 6334 /* Suppress signon message. */ 6335 } 6336 else if (strcmp (arg, "pi") == 0) 6337 { 6338 /* Reject privileged instructions. FIXME */ 6339 } 6340 else if (strcmp (arg, "us") == 0) 6341 { 6342 /* Allow union of signed and unsigned range. FIXME */ 6343 } 6344 else if (strcmp (arg, "close_fcalls") == 0) 6345 { 6346 /* Do not resolve global function calls. */ 6347 } 6348 else 6349 return 0; 6350 break; 6351 6352 case 'C': 6353 /* temp[="prefix"] Insert temporary labels into the object file 6354 symbol table prefixed by "prefix". 6355 Default prefix is ":temp:". 6356 */ 6357 break; 6358 6359 case 'a': 6360 /* indirect=<tgt> Assume unannotated indirect branches behavior 6361 according to <tgt> -- 6362 exit: branch out from the current context (default) 6363 labels: all labels in context may be branch targets 6364 */ 6365 if (strncmp (arg, "indirect=", 9) != 0) 6366 return 0; 6367 break; 6368 6369 case 'x': 6370 /* -X conflicts with an ignored option, use -x instead */ 6371 md.detect_dv = 1; 6372 if (!arg || strcmp (arg, "explicit") == 0) 6373 { 6374 /* set default mode to explicit */ 6375 md.default_explicit_mode = 1; 6376 break; 6377 } 6378 else if (strcmp (arg, "auto") == 0) 6379 { 6380 md.default_explicit_mode = 0; 6381 } 6382 else if (strcmp (arg, "debug") == 0) 6383 { 6384 md.debug_dv = 1; 6385 } 6386 else if (strcmp (arg, "debugx") == 0) 6387 { 6388 md.default_explicit_mode = 1; 6389 md.debug_dv = 1; 6390 } 6391 else 6392 { 6393 as_bad (_("Unrecognized option '-x%s'"), arg); 6394 } 6395 break; 6396 6397 case 'S': 6398 /* nops Print nops statistics. */ 6399 break; 6400 6401 /* GNU specific switches for gcc. */ 6402 case OPTION_MCONSTANT_GP: 6403 md.flags |= EF_IA_64_CONS_GP; 6404 break; 6405 6406 case OPTION_MAUTO_PIC: 6407 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; 6408 break; 6409 6410 default: 6411 return 0; 6412 } 6413 6414 return 1; 6415} 6416 6417void 6418md_show_usage (stream) 6419 FILE *stream; 6420{ 6421 fputs (_("\ 6422IA-64 options:\n\ 6423 --mconstant-gp mark output file as using the constant-GP model\n\ 6424 (sets ELF header flag EF_IA_64_CONS_GP)\n\ 6425 --mauto-pic mark output file as using the constant-GP model\n\ 6426 without function descriptors (sets ELF header flag\n\ 6427 EF_IA_64_NOFUNCDESC_CONS_GP)\n\ 6428 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ 6429 -mle | -mbe select little- or big-endian byte order (default -mle)\n\ 6430 -x | -xexplicit turn on dependency violation checking (default)\n\ 6431 -xauto automagically remove dependency violations\n\ 6432 -xdebug debug dependency violation checker\n"), 6433 stream); 6434} 6435 6436void 6437ia64_after_parse_args () 6438{ 6439 if (debug_type == DEBUG_STABS) 6440 as_fatal (_("--gstabs is not supported for ia64")); 6441} 6442 6443/* Return true if TYPE fits in TEMPL at SLOT. */ 6444 6445static int 6446match (int templ, int type, int slot) 6447{ 6448 enum ia64_unit unit; 6449 int result; 6450 6451 unit = ia64_templ_desc[templ].exec_unit[slot]; 6452 switch (type) 6453 { 6454 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ 6455 case IA64_TYPE_A: 6456 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); 6457 break; 6458 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; 6459 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; 6460 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; 6461 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; 6462 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; 6463 default: result = 0; break; 6464 } 6465 return result; 6466} 6467 6468/* Add a bit of extra goodness if a nop of type F or B would fit 6469 in TEMPL at SLOT. */ 6470 6471static inline int 6472extra_goodness (int templ, int slot) 6473{ 6474 if (slot == 1 && match (templ, IA64_TYPE_F, slot)) 6475 return 2; 6476 if (slot == 2 && match (templ, IA64_TYPE_B, slot)) 6477 return 1; 6478 return 0; 6479} 6480 6481/* This function is called once, at assembler startup time. It sets 6482 up all the tables, etc. that the MD part of the assembler will need 6483 that can be determined before arguments are parsed. */ 6484void 6485md_begin () 6486{ 6487 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; 6488 const char *err; 6489 char name[8]; 6490 6491 md.auto_align = 1; 6492 md.explicit_mode = md.default_explicit_mode; 6493 6494 bfd_set_section_alignment (stdoutput, text_section, 4); 6495 6496 target_big_endian = TARGET_BYTES_BIG_ENDIAN; 6497 pseudo_func[FUNC_FPTR_RELATIVE].u.sym = 6498 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, 6499 &zero_address_frag); 6500 6501 pseudo_func[FUNC_GP_RELATIVE].u.sym = 6502 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, 6503 &zero_address_frag); 6504 6505 pseudo_func[FUNC_LT_RELATIVE].u.sym = 6506 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, 6507 &zero_address_frag); 6508 6509 pseudo_func[FUNC_PC_RELATIVE].u.sym = 6510 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, 6511 &zero_address_frag); 6512 6513 pseudo_func[FUNC_PLT_RELATIVE].u.sym = 6514 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, 6515 &zero_address_frag); 6516 6517 pseudo_func[FUNC_SEC_RELATIVE].u.sym = 6518 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, 6519 &zero_address_frag); 6520 6521 pseudo_func[FUNC_SEG_RELATIVE].u.sym = 6522 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, 6523 &zero_address_frag); 6524 6525 pseudo_func[FUNC_LTV_RELATIVE].u.sym = 6526 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, 6527 &zero_address_frag); 6528 6529 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = 6530 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, 6531 &zero_address_frag); 6532 6533 pseudo_func[FUNC_IPLT_RELOC].u.sym = 6534 symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC, 6535 &zero_address_frag); 6536 6537 /* Compute the table of best templates. We compute goodness as a 6538 base 4 value, in which each match counts for 3, each F counts 6539 for 2, each B counts for 1. This should maximize the number of 6540 F and B nops in the chosen bundles, which is good because these 6541 pipelines are least likely to be overcommitted. */ 6542 for (i = 0; i < IA64_NUM_TYPES; ++i) 6543 for (j = 0; j < IA64_NUM_TYPES; ++j) 6544 for (k = 0; k < IA64_NUM_TYPES; ++k) 6545 { 6546 best = 0; 6547 for (t = 0; t < NELEMS (ia64_templ_desc); ++t) 6548 { 6549 goodness = 0; 6550 if (match (t, i, 0)) 6551 { 6552 if (match (t, j, 1)) 6553 { 6554 if (match (t, k, 2)) 6555 goodness = 3 + 3 + 3; 6556 else 6557 goodness = 3 + 3 + extra_goodness (t, 2); 6558 } 6559 else if (match (t, j, 2)) 6560 goodness = 3 + 3 + extra_goodness (t, 1); 6561 else 6562 { 6563 goodness = 3; 6564 goodness += extra_goodness (t, 1); 6565 goodness += extra_goodness (t, 2); 6566 } 6567 } 6568 else if (match (t, i, 1)) 6569 { 6570 if (match (t, j, 2)) 6571 goodness = 3 + 3; 6572 else 6573 goodness = 3 + extra_goodness (t, 2); 6574 } 6575 else if (match (t, i, 2)) 6576 goodness = 3 + extra_goodness (t, 1); 6577 6578 if (goodness > best) 6579 { 6580 best = goodness; 6581 best_template[i][j][k] = t; 6582 } 6583 } 6584 } 6585 6586 for (i = 0; i < NUM_SLOTS; ++i) 6587 md.slot[i].user_template = -1; 6588 6589 md.pseudo_hash = hash_new (); 6590 for (i = 0; i < NELEMS (pseudo_opcode); ++i) 6591 { 6592 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, 6593 (void *) (pseudo_opcode + i)); 6594 if (err) 6595 as_fatal ("ia64.md_begin: can't hash `%s': %s", 6596 pseudo_opcode[i].name, err); 6597 } 6598 6599 md.reg_hash = hash_new (); 6600 md.dynreg_hash = hash_new (); 6601 md.const_hash = hash_new (); 6602 md.entry_hash = hash_new (); 6603 6604 /* general registers: */ 6605 6606 total = 128; 6607 for (i = 0; i < total; ++i) 6608 { 6609 sprintf (name, "r%d", i - REG_GR); 6610 md.regsym[i] = declare_register (name, i); 6611 } 6612 6613 /* floating point registers: */ 6614 total += 128; 6615 for (; i < total; ++i) 6616 { 6617 sprintf (name, "f%d", i - REG_FR); 6618 md.regsym[i] = declare_register (name, i); 6619 } 6620 6621 /* application registers: */ 6622 total += 128; 6623 ar_base = i; 6624 for (; i < total; ++i) 6625 { 6626 sprintf (name, "ar%d", i - REG_AR); 6627 md.regsym[i] = declare_register (name, i); 6628 } 6629 6630 /* control registers: */ 6631 total += 128; 6632 cr_base = i; 6633 for (; i < total; ++i) 6634 { 6635 sprintf (name, "cr%d", i - REG_CR); 6636 md.regsym[i] = declare_register (name, i); 6637 } 6638 6639 /* predicate registers: */ 6640 total += 64; 6641 for (; i < total; ++i) 6642 { 6643 sprintf (name, "p%d", i - REG_P); 6644 md.regsym[i] = declare_register (name, i); 6645 } 6646 6647 /* branch registers: */ 6648 total += 8; 6649 for (; i < total; ++i) 6650 { 6651 sprintf (name, "b%d", i - REG_BR); 6652 md.regsym[i] = declare_register (name, i); 6653 } 6654 6655 md.regsym[REG_IP] = declare_register ("ip", REG_IP); 6656 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); 6657 md.regsym[REG_PR] = declare_register ("pr", REG_PR); 6658 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); 6659 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); 6660 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); 6661 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); 6662 6663 for (i = 0; i < NELEMS (indirect_reg); ++i) 6664 { 6665 regnum = indirect_reg[i].regnum; 6666 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); 6667 } 6668 6669 /* define synonyms for application registers: */ 6670 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) 6671 md.regsym[i] = declare_register (ar[i - REG_AR].name, 6672 REG_AR + ar[i - REG_AR].regnum); 6673 6674 /* define synonyms for control registers: */ 6675 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) 6676 md.regsym[i] = declare_register (cr[i - REG_CR].name, 6677 REG_CR + cr[i - REG_CR].regnum); 6678 6679 declare_register ("gp", REG_GR + 1); 6680 declare_register ("sp", REG_GR + 12); 6681 declare_register ("rp", REG_BR + 0); 6682 6683 /* pseudo-registers used to specify unwind info: */ 6684 declare_register ("psp", REG_PSP); 6685 6686 declare_register_set ("ret", 4, REG_GR + 8); 6687 declare_register_set ("farg", 8, REG_FR + 8); 6688 declare_register_set ("fret", 8, REG_FR + 8); 6689 6690 for (i = 0; i < NELEMS (const_bits); ++i) 6691 { 6692 err = hash_insert (md.const_hash, const_bits[i].name, 6693 (PTR) (const_bits + i)); 6694 if (err) 6695 as_fatal ("Inserting \"%s\" into constant hash table failed: %s", 6696 name, err); 6697 } 6698 6699 /* Set the architecture and machine depending on defaults and command line 6700 options. */ 6701 if (md.flags & EF_IA_64_ABI64) 6702 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); 6703 else 6704 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); 6705 6706 if (! ok) 6707 as_warn (_("Could not set architecture and machine")); 6708 6709 /* Set the pointer size and pointer shift size depending on md.flags */ 6710 6711 if (md.flags & EF_IA_64_ABI64) 6712 { 6713 md.pointer_size = 8; /* pointers are 8 bytes */ 6714 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */ 6715 } 6716 else 6717 { 6718 md.pointer_size = 4; /* pointers are 4 bytes */ 6719 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */ 6720 } 6721 6722 md.mem_offset.hint = 0; 6723 md.path = 0; 6724 md.maxpaths = 0; 6725 md.entry_labels = NULL; 6726} 6727 6728/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin 6729 because that is called after md_parse_option which is where we do the 6730 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the 6731 default endianness. */ 6732 6733void 6734ia64_init (argc, argv) 6735 int argc ATTRIBUTE_UNUSED; 6736 char **argv ATTRIBUTE_UNUSED; 6737{ 6738 md.flags = MD_FLAGS_DEFAULT; 6739} 6740 6741/* Return a string for the target object file format. */ 6742 6743const char * 6744ia64_target_format () 6745{ 6746 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 6747 { 6748 if (md.flags & EF_IA_64_BE) 6749 { 6750 if (md.flags & EF_IA_64_ABI64) 6751#if defined(TE_AIX50) 6752 return "elf64-ia64-aix-big"; 6753#elif defined(TE_HPUX) 6754 return "elf64-ia64-hpux-big"; 6755#else 6756 return "elf64-ia64-big"; 6757#endif 6758 else 6759#if defined(TE_AIX50) 6760 return "elf32-ia64-aix-big"; 6761#elif defined(TE_HPUX) 6762 return "elf32-ia64-hpux-big"; 6763#else 6764 return "elf32-ia64-big"; 6765#endif 6766 } 6767 else 6768 { 6769 if (md.flags & EF_IA_64_ABI64) 6770#ifdef TE_AIX50 6771 return "elf64-ia64-aix-little"; 6772#else 6773 return "elf64-ia64-little"; 6774#endif 6775 else 6776#ifdef TE_AIX50 6777 return "elf32-ia64-aix-little"; 6778#else 6779 return "elf32-ia64-little"; 6780#endif 6781 } 6782 } 6783 else 6784 return "unknown-format"; 6785} 6786 6787void 6788ia64_end_of_source () 6789{ 6790 /* terminate insn group upon reaching end of file: */ 6791 insn_group_break (1, 0, 0); 6792 6793 /* emits slots we haven't written yet: */ 6794 ia64_flush_insns (); 6795 6796 bfd_set_private_flags (stdoutput, md.flags); 6797 6798 md.mem_offset.hint = 0; 6799} 6800 6801void 6802ia64_start_line () 6803{ 6804 if (md.qp.X_op == O_register) 6805 as_bad ("qualifying predicate not followed by instruction"); 6806 md.qp.X_op = O_absent; 6807 6808 if (ignore_input ()) 6809 return; 6810 6811 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') 6812 { 6813 if (md.detect_dv && !md.explicit_mode) 6814 as_warn (_("Explicit stops are ignored in auto mode")); 6815 else 6816 insn_group_break (1, 0, 0); 6817 } 6818} 6819 6820/* This is a hook for ia64_frob_label, so that it can distinguish tags from 6821 labels. */ 6822static int defining_tag = 0; 6823 6824int 6825ia64_unrecognized_line (ch) 6826 int ch; 6827{ 6828 switch (ch) 6829 { 6830 case '(': 6831 expression (&md.qp); 6832 if (*input_line_pointer++ != ')') 6833 { 6834 as_bad ("Expected ')'"); 6835 return 0; 6836 } 6837 if (md.qp.X_op != O_register) 6838 { 6839 as_bad ("Qualifying predicate expected"); 6840 return 0; 6841 } 6842 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) 6843 { 6844 as_bad ("Predicate register expected"); 6845 return 0; 6846 } 6847 return 1; 6848 6849 case '{': 6850 if (md.manual_bundling) 6851 as_warn ("Found '{' when manual bundling is already turned on"); 6852 else 6853 CURR_SLOT.manual_bundling_on = 1; 6854 md.manual_bundling = 1; 6855 6856 /* Bundling is only acceptable in explicit mode 6857 or when in default automatic mode. */ 6858 if (md.detect_dv && !md.explicit_mode) 6859 { 6860 if (!md.mode_explicitly_set 6861 && !md.default_explicit_mode) 6862 dot_dv_mode ('E'); 6863 else 6864 as_warn (_("Found '{' after explicit switch to automatic mode")); 6865 } 6866 return 1; 6867 6868 case '}': 6869 if (!md.manual_bundling) 6870 as_warn ("Found '}' when manual bundling is off"); 6871 else 6872 PREV_SLOT.manual_bundling_off = 1; 6873 md.manual_bundling = 0; 6874 6875 /* switch back to automatic mode, if applicable */ 6876 if (md.detect_dv 6877 && md.explicit_mode 6878 && !md.mode_explicitly_set 6879 && !md.default_explicit_mode) 6880 dot_dv_mode ('A'); 6881 6882 /* Allow '{' to follow on the same line. We also allow ";;", but that 6883 happens automatically because ';' is an end of line marker. */ 6884 SKIP_WHITESPACE (); 6885 if (input_line_pointer[0] == '{') 6886 { 6887 input_line_pointer++; 6888 return ia64_unrecognized_line ('{'); 6889 } 6890 6891 demand_empty_rest_of_line (); 6892 return 1; 6893 6894 case '[': 6895 { 6896 char *s; 6897 char c; 6898 symbolS *tag; 6899 int temp; 6900 6901 if (md.qp.X_op == O_register) 6902 { 6903 as_bad ("Tag must come before qualifying predicate."); 6904 return 0; 6905 } 6906 6907 /* This implements just enough of read_a_source_file in read.c to 6908 recognize labels. */ 6909 if (is_name_beginner (*input_line_pointer)) 6910 { 6911 s = input_line_pointer; 6912 c = get_symbol_end (); 6913 } 6914 else if (LOCAL_LABELS_FB 6915 && ISDIGIT (*input_line_pointer)) 6916 { 6917 temp = 0; 6918 while (ISDIGIT (*input_line_pointer)) 6919 temp = (temp * 10) + *input_line_pointer++ - '0'; 6920 fb_label_instance_inc (temp); 6921 s = fb_label_name (temp, 0); 6922 c = *input_line_pointer; 6923 } 6924 else 6925 { 6926 s = NULL; 6927 c = '\0'; 6928 } 6929 if (c != ':') 6930 { 6931 /* Put ':' back for error messages' sake. */ 6932 *input_line_pointer++ = ':'; 6933 as_bad ("Expected ':'"); 6934 return 0; 6935 } 6936 6937 defining_tag = 1; 6938 tag = colon (s); 6939 defining_tag = 0; 6940 /* Put ':' back for error messages' sake. */ 6941 *input_line_pointer++ = ':'; 6942 if (*input_line_pointer++ != ']') 6943 { 6944 as_bad ("Expected ']'"); 6945 return 0; 6946 } 6947 if (! tag) 6948 { 6949 as_bad ("Tag name expected"); 6950 return 0; 6951 } 6952 return 1; 6953 } 6954 6955 default: 6956 break; 6957 } 6958 6959 /* Not a valid line. */ 6960 return 0; 6961} 6962 6963void 6964ia64_frob_label (sym) 6965 struct symbol *sym; 6966{ 6967 struct label_fix *fix; 6968 6969 /* Tags need special handling since they are not bundle breaks like 6970 labels. */ 6971 if (defining_tag) 6972 { 6973 fix = obstack_alloc (¬es, sizeof (*fix)); 6974 fix->sym = sym; 6975 fix->next = CURR_SLOT.tag_fixups; 6976 CURR_SLOT.tag_fixups = fix; 6977 6978 return; 6979 } 6980 6981 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) 6982 { 6983 md.last_text_seg = now_seg; 6984 fix = obstack_alloc (¬es, sizeof (*fix)); 6985 fix->sym = sym; 6986 fix->next = CURR_SLOT.label_fixups; 6987 CURR_SLOT.label_fixups = fix; 6988 6989 /* Keep track of how many code entry points we've seen. */ 6990 if (md.path == md.maxpaths) 6991 { 6992 md.maxpaths += 20; 6993 md.entry_labels = (const char **) 6994 xrealloc ((void *) md.entry_labels, 6995 md.maxpaths * sizeof (char *)); 6996 } 6997 md.entry_labels[md.path++] = S_GET_NAME (sym); 6998 } 6999} 7000 7001void 7002ia64_flush_pending_output () 7003{ 7004 if (!md.keep_pending_output 7005 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) 7006 { 7007 /* ??? This causes many unnecessary stop bits to be emitted. 7008 Unfortunately, it isn't clear if it is safe to remove this. */ 7009 insn_group_break (1, 0, 0); 7010 ia64_flush_insns (); 7011 } 7012} 7013 7014/* Do ia64-specific expression optimization. All that's done here is 7015 to transform index expressions that are either due to the indexing 7016 of rotating registers or due to the indexing of indirect register 7017 sets. */ 7018int 7019ia64_optimize_expr (l, op, r) 7020 expressionS *l; 7021 operatorT op; 7022 expressionS *r; 7023{ 7024 unsigned num_regs; 7025 7026 if (op == O_index) 7027 { 7028 if (l->X_op == O_register && r->X_op == O_constant) 7029 { 7030 num_regs = (l->X_add_number >> 16); 7031 if ((unsigned) r->X_add_number >= num_regs) 7032 { 7033 if (!num_regs) 7034 as_bad ("No current frame"); 7035 else 7036 as_bad ("Index out of range 0..%u", num_regs - 1); 7037 r->X_add_number = 0; 7038 } 7039 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; 7040 return 1; 7041 } 7042 else if (l->X_op == O_register && r->X_op == O_register) 7043 { 7044 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR 7045 || l->X_add_number == IND_MEM) 7046 { 7047 as_bad ("Indirect register set name expected"); 7048 l->X_add_number = IND_CPUID; 7049 } 7050 l->X_op = O_index; 7051 l->X_op_symbol = md.regsym[l->X_add_number]; 7052 l->X_add_number = r->X_add_number; 7053 return 1; 7054 } 7055 } 7056 return 0; 7057} 7058 7059int 7060ia64_parse_name (name, e) 7061 char *name; 7062 expressionS *e; 7063{ 7064 struct const_desc *cdesc; 7065 struct dynreg *dr = 0; 7066 unsigned int regnum; 7067 struct symbol *sym; 7068 char *end; 7069 7070 /* first see if NAME is a known register name: */ 7071 sym = hash_find (md.reg_hash, name); 7072 if (sym) 7073 { 7074 e->X_op = O_register; 7075 e->X_add_number = S_GET_VALUE (sym); 7076 return 1; 7077 } 7078 7079 cdesc = hash_find (md.const_hash, name); 7080 if (cdesc) 7081 { 7082 e->X_op = O_constant; 7083 e->X_add_number = cdesc->value; 7084 return 1; 7085 } 7086 7087 /* check for inN, locN, or outN: */ 7088 switch (name[0]) 7089 { 7090 case 'i': 7091 if (name[1] == 'n' && ISDIGIT (name[2])) 7092 { 7093 dr = &md.in; 7094 name += 2; 7095 } 7096 break; 7097 7098 case 'l': 7099 if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3])) 7100 { 7101 dr = &md.loc; 7102 name += 3; 7103 } 7104 break; 7105 7106 case 'o': 7107 if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3])) 7108 { 7109 dr = &md.out; 7110 name += 3; 7111 } 7112 break; 7113 7114 default: 7115 break; 7116 } 7117 7118 if (dr) 7119 { 7120 /* The name is inN, locN, or outN; parse the register number. */ 7121 regnum = strtoul (name, &end, 10); 7122 if (end > name && *end == '\0') 7123 { 7124 if ((unsigned) regnum >= dr->num_regs) 7125 { 7126 if (!dr->num_regs) 7127 as_bad ("No current frame"); 7128 else 7129 as_bad ("Register number out of range 0..%u", 7130 dr->num_regs - 1); 7131 regnum = 0; 7132 } 7133 e->X_op = O_register; 7134 e->X_add_number = dr->base + regnum; 7135 return 1; 7136 } 7137 } 7138 7139 if ((dr = hash_find (md.dynreg_hash, name))) 7140 { 7141 /* We've got ourselves the name of a rotating register set. 7142 Store the base register number in the low 16 bits of 7143 X_add_number and the size of the register set in the top 16 7144 bits. */ 7145 e->X_op = O_register; 7146 e->X_add_number = dr->base | (dr->num_regs << 16); 7147 return 1; 7148 } 7149 return 0; 7150} 7151 7152/* Remove the '#' suffix that indicates a symbol as opposed to a register. */ 7153 7154char * 7155ia64_canonicalize_symbol_name (name) 7156 char *name; 7157{ 7158 size_t len = strlen (name); 7159 if (len > 1 && name[len - 1] == '#') 7160 name[len - 1] = '\0'; 7161 return name; 7162} 7163 7164/* Return true if idesc is a conditional branch instruction. This excludes 7165 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded 7166 because they always read/write resources regardless of the value of the 7167 qualifying predicate. br.ia must always use p0, and hence is always 7168 taken. Thus this function returns true for branches which can fall 7169 through, and which use no resources if they do fall through. */ 7170 7171static int 7172is_conditional_branch (idesc) 7173 struct ia64_opcode *idesc; 7174{ 7175 /* br is a conditional branch. Everything that starts with br. except 7176 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch. 7177 Everything that starts with brl is a conditional branch. */ 7178 return (idesc->name[0] == 'b' && idesc->name[1] == 'r' 7179 && (idesc->name[2] == '\0' 7180 || (idesc->name[2] == '.' && idesc->name[3] != 'i' 7181 && idesc->name[3] != 'c' && idesc->name[3] != 'w') 7182 || idesc->name[2] == 'l' 7183 /* br.cond, br.call, br.clr */ 7184 || (idesc->name[2] == '.' && idesc->name[3] == 'c' 7185 && (idesc->name[4] == 'a' || idesc->name[4] == 'o' 7186 || (idesc->name[4] == 'l' && idesc->name[5] == 'r'))))); 7187} 7188 7189/* Return whether the given opcode is a taken branch. If there's any doubt, 7190 returns zero. */ 7191 7192static int 7193is_taken_branch (idesc) 7194 struct ia64_opcode *idesc; 7195{ 7196 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) 7197 || strncmp (idesc->name, "br.ia", 5) == 0); 7198} 7199 7200/* Return whether the given opcode is an interruption or rfi. If there's any 7201 doubt, returns zero. */ 7202 7203static int 7204is_interruption_or_rfi (idesc) 7205 struct ia64_opcode *idesc; 7206{ 7207 if (strcmp (idesc->name, "rfi") == 0) 7208 return 1; 7209 return 0; 7210} 7211 7212/* Returns the index of the given dependency in the opcode's list of chks, or 7213 -1 if there is no dependency. */ 7214 7215static int 7216depends_on (depind, idesc) 7217 int depind; 7218 struct ia64_opcode *idesc; 7219{ 7220 int i; 7221 const struct ia64_opcode_dependency *dep = idesc->dependencies; 7222 for (i = 0; i < dep->nchks; i++) 7223 { 7224 if (depind == DEP (dep->chks[i])) 7225 return i; 7226 } 7227 return -1; 7228} 7229 7230/* Determine a set of specific resources used for a particular resource 7231 class. Returns the number of specific resources identified For those 7232 cases which are not determinable statically, the resource returned is 7233 marked nonspecific. 7234 7235 Meanings of value in 'NOTE': 7236 1) only read/write when the register number is explicitly encoded in the 7237 insn. 7238 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only 7239 accesses CFM when qualifying predicate is in the rotating region. 7240 3) general register value is used to specify an indirect register; not 7241 determinable statically. 7242 4) only read the given resource when bits 7:0 of the indirect index 7243 register value does not match the register number of the resource; not 7244 determinable statically. 7245 5) all rules are implementation specific. 7246 6) only when both the index specified by the reader and the index specified 7247 by the writer have the same value in bits 63:61; not determinable 7248 statically. 7249 7) only access the specified resource when the corresponding mask bit is 7250 set 7251 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is 7252 only read when these insns reference FR2-31 7253 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only 7254 written when these insns write FR32-127 7255 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the 7256 instruction 7257 11) The target predicates are written independently of PR[qp], but source 7258 registers are only read if PR[qp] is true. Since the state of PR[qp] 7259 cannot statically be determined, all source registers are marked used. 7260 12) This insn only reads the specified predicate register when that 7261 register is the PR[qp]. 7262 13) This reference to ld-c only applies to teh GR whose value is loaded 7263 with data returned from memory, not the post-incremented address register. 7264 14) The RSE resource includes the implementation-specific RSE internal 7265 state resources. At least one (and possibly more) of these resources are 7266 read by each instruction listed in IC:rse-readers. At least one (and 7267 possibly more) of these resources are written by each insn listed in 7268 IC:rse-writers. 7269 15+16) Represents reserved instructions, which the assembler does not 7270 generate. 7271 7272 Memory resources (i.e. locations in memory) are *not* marked or tracked by 7273 this code; there are no dependency violations based on memory access. 7274*/ 7275 7276#define MAX_SPECS 256 7277#define DV_CHK 1 7278#define DV_REG 0 7279 7280static int 7281specify_resource (dep, idesc, type, specs, note, path) 7282 const struct ia64_dependency *dep; 7283 struct ia64_opcode *idesc; 7284 int type; /* is this a DV chk or a DV reg? */ 7285 struct rsrc specs[MAX_SPECS]; /* returned specific resources */ 7286 int note; /* resource note for this insn's usage */ 7287 int path; /* which execution path to examine */ 7288{ 7289 int count = 0; 7290 int i; 7291 int rsrc_write = 0; 7292 struct rsrc tmpl; 7293 7294 if (dep->mode == IA64_DV_WAW 7295 || (dep->mode == IA64_DV_RAW && type == DV_REG) 7296 || (dep->mode == IA64_DV_WAR && type == DV_CHK)) 7297 rsrc_write = 1; 7298 7299 /* template for any resources we identify */ 7300 tmpl.dependency = dep; 7301 tmpl.note = note; 7302 tmpl.insn_srlz = tmpl.data_srlz = 0; 7303 tmpl.qp_regno = CURR_SLOT.qp_regno; 7304 tmpl.link_to_qp_branch = 1; 7305 tmpl.mem_offset.hint = 0; 7306 tmpl.specific = 1; 7307 tmpl.index = 0; 7308 tmpl.cmp_type = CMP_NONE; 7309 7310#define UNHANDLED \ 7311as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ 7312dep->name, idesc->name, (rsrc_write?"write":"read"), note) 7313#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) 7314 7315 /* we don't need to track these */ 7316 if (dep->semantics == IA64_DVS_NONE) 7317 return 0; 7318 7319 switch (dep->specifier) 7320 { 7321 case IA64_RS_AR_K: 7322 if (note == 1) 7323 { 7324 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7325 { 7326 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7327 if (regno >= 0 && regno <= 7) 7328 { 7329 specs[count] = tmpl; 7330 specs[count++].index = regno; 7331 } 7332 } 7333 } 7334 else if (note == 0) 7335 { 7336 for (i = 0; i < 8; i++) 7337 { 7338 specs[count] = tmpl; 7339 specs[count++].index = i; 7340 } 7341 } 7342 else 7343 { 7344 UNHANDLED; 7345 } 7346 break; 7347 7348 case IA64_RS_AR_UNAT: 7349 /* This is a mov =AR or mov AR= instruction. */ 7350 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7351 { 7352 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7353 if (regno == AR_UNAT) 7354 { 7355 specs[count++] = tmpl; 7356 } 7357 } 7358 else 7359 { 7360 /* This is a spill/fill, or other instruction that modifies the 7361 unat register. */ 7362 7363 /* Unless we can determine the specific bits used, mark the whole 7364 thing; bits 8:3 of the memory address indicate the bit used in 7365 UNAT. The .mem.offset hint may be used to eliminate a small 7366 subset of conflicts. */ 7367 specs[count] = tmpl; 7368 if (md.mem_offset.hint) 7369 { 7370 if (md.debug_dv) 7371 fprintf (stderr, " Using hint for spill/fill\n"); 7372 /* The index isn't actually used, just set it to something 7373 approximating the bit index. */ 7374 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; 7375 specs[count].mem_offset.hint = 1; 7376 specs[count].mem_offset.offset = md.mem_offset.offset; 7377 specs[count++].mem_offset.base = md.mem_offset.base; 7378 } 7379 else 7380 { 7381 specs[count++].specific = 0; 7382 } 7383 } 7384 break; 7385 7386 case IA64_RS_AR: 7387 if (note == 1) 7388 { 7389 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7390 { 7391 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7392 if ((regno >= 8 && regno <= 15) 7393 || (regno >= 20 && regno <= 23) 7394 || (regno >= 31 && regno <= 39) 7395 || (regno >= 41 && regno <= 47) 7396 || (regno >= 67 && regno <= 111)) 7397 { 7398 specs[count] = tmpl; 7399 specs[count++].index = regno; 7400 } 7401 } 7402 } 7403 else 7404 { 7405 UNHANDLED; 7406 } 7407 break; 7408 7409 case IA64_RS_ARb: 7410 if (note == 1) 7411 { 7412 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7413 { 7414 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7415 if ((regno >= 48 && regno <= 63) 7416 || (regno >= 112 && regno <= 127)) 7417 { 7418 specs[count] = tmpl; 7419 specs[count++].index = regno; 7420 } 7421 } 7422 } 7423 else if (note == 0) 7424 { 7425 for (i = 48; i < 64; i++) 7426 { 7427 specs[count] = tmpl; 7428 specs[count++].index = i; 7429 } 7430 for (i = 112; i < 128; i++) 7431 { 7432 specs[count] = tmpl; 7433 specs[count++].index = i; 7434 } 7435 } 7436 else 7437 { 7438 UNHANDLED; 7439 } 7440 break; 7441 7442 case IA64_RS_BR: 7443 if (note != 1) 7444 { 7445 UNHANDLED; 7446 } 7447 else 7448 { 7449 if (rsrc_write) 7450 { 7451 for (i = 0; i < idesc->num_outputs; i++) 7452 if (idesc->operands[i] == IA64_OPND_B1 7453 || idesc->operands[i] == IA64_OPND_B2) 7454 { 7455 specs[count] = tmpl; 7456 specs[count++].index = 7457 CURR_SLOT.opnd[i].X_add_number - REG_BR; 7458 } 7459 } 7460 else 7461 { 7462 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++) 7463 if (idesc->operands[i] == IA64_OPND_B1 7464 || idesc->operands[i] == IA64_OPND_B2) 7465 { 7466 specs[count] = tmpl; 7467 specs[count++].index = 7468 CURR_SLOT.opnd[i].X_add_number - REG_BR; 7469 } 7470 } 7471 } 7472 break; 7473 7474 case IA64_RS_CPUID: /* four or more registers */ 7475 if (note == 3) 7476 { 7477 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) 7478 { 7479 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7480 if (regno >= 0 && regno < NELEMS (gr_values) 7481 && KNOWN (regno)) 7482 { 7483 specs[count] = tmpl; 7484 specs[count++].index = gr_values[regno].value & 0xFF; 7485 } 7486 else 7487 { 7488 specs[count] = tmpl; 7489 specs[count++].specific = 0; 7490 } 7491 } 7492 } 7493 else 7494 { 7495 UNHANDLED; 7496 } 7497 break; 7498 7499 case IA64_RS_DBR: /* four or more registers */ 7500 if (note == 3) 7501 { 7502 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) 7503 { 7504 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7505 if (regno >= 0 && regno < NELEMS (gr_values) 7506 && KNOWN (regno)) 7507 { 7508 specs[count] = tmpl; 7509 specs[count++].index = gr_values[regno].value & 0xFF; 7510 } 7511 else 7512 { 7513 specs[count] = tmpl; 7514 specs[count++].specific = 0; 7515 } 7516 } 7517 } 7518 else if (note == 0 && !rsrc_write) 7519 { 7520 specs[count] = tmpl; 7521 specs[count++].specific = 0; 7522 } 7523 else 7524 { 7525 UNHANDLED; 7526 } 7527 break; 7528 7529 case IA64_RS_IBR: /* four or more registers */ 7530 if (note == 3) 7531 { 7532 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) 7533 { 7534 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7535 if (regno >= 0 && regno < NELEMS (gr_values) 7536 && KNOWN (regno)) 7537 { 7538 specs[count] = tmpl; 7539 specs[count++].index = gr_values[regno].value & 0xFF; 7540 } 7541 else 7542 { 7543 specs[count] = tmpl; 7544 specs[count++].specific = 0; 7545 } 7546 } 7547 } 7548 else 7549 { 7550 UNHANDLED; 7551 } 7552 break; 7553 7554 case IA64_RS_MSR: 7555 if (note == 5) 7556 { 7557 /* These are implementation specific. Force all references to 7558 conflict with all other references. */ 7559 specs[count] = tmpl; 7560 specs[count++].specific = 0; 7561 } 7562 else 7563 { 7564 UNHANDLED; 7565 } 7566 break; 7567 7568 case IA64_RS_PKR: /* 16 or more registers */ 7569 if (note == 3 || note == 4) 7570 { 7571 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) 7572 { 7573 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7574 if (regno >= 0 && regno < NELEMS (gr_values) 7575 && KNOWN (regno)) 7576 { 7577 if (note == 3) 7578 { 7579 specs[count] = tmpl; 7580 specs[count++].index = gr_values[regno].value & 0xFF; 7581 } 7582 else 7583 for (i = 0; i < NELEMS (gr_values); i++) 7584 { 7585 /* Uses all registers *except* the one in R3. */ 7586 if ((unsigned)i != (gr_values[regno].value & 0xFF)) 7587 { 7588 specs[count] = tmpl; 7589 specs[count++].index = i; 7590 } 7591 } 7592 } 7593 else 7594 { 7595 specs[count] = tmpl; 7596 specs[count++].specific = 0; 7597 } 7598 } 7599 } 7600 else if (note == 0) 7601 { 7602 /* probe et al. */ 7603 specs[count] = tmpl; 7604 specs[count++].specific = 0; 7605 } 7606 break; 7607 7608 case IA64_RS_PMC: /* four or more registers */ 7609 if (note == 3) 7610 { 7611 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 7612 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) 7613 7614 { 7615 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) 7616 ? 1 : !rsrc_write); 7617 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; 7618 if (regno >= 0 && regno < NELEMS (gr_values) 7619 && KNOWN (regno)) 7620 { 7621 specs[count] = tmpl; 7622 specs[count++].index = gr_values[regno].value & 0xFF; 7623 } 7624 else 7625 { 7626 specs[count] = tmpl; 7627 specs[count++].specific = 0; 7628 } 7629 } 7630 } 7631 else 7632 { 7633 UNHANDLED; 7634 } 7635 break; 7636 7637 case IA64_RS_PMD: /* four or more registers */ 7638 if (note == 3) 7639 { 7640 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) 7641 { 7642 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7643 if (regno >= 0 && regno < NELEMS (gr_values) 7644 && KNOWN (regno)) 7645 { 7646 specs[count] = tmpl; 7647 specs[count++].index = gr_values[regno].value & 0xFF; 7648 } 7649 else 7650 { 7651 specs[count] = tmpl; 7652 specs[count++].specific = 0; 7653 } 7654 } 7655 } 7656 else 7657 { 7658 UNHANDLED; 7659 } 7660 break; 7661 7662 case IA64_RS_RR: /* eight registers */ 7663 if (note == 6) 7664 { 7665 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) 7666 { 7667 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7668 if (regno >= 0 && regno < NELEMS (gr_values) 7669 && KNOWN (regno)) 7670 { 7671 specs[count] = tmpl; 7672 specs[count++].index = (gr_values[regno].value >> 61) & 0x7; 7673 } 7674 else 7675 { 7676 specs[count] = tmpl; 7677 specs[count++].specific = 0; 7678 } 7679 } 7680 } 7681 else if (note == 0 && !rsrc_write) 7682 { 7683 specs[count] = tmpl; 7684 specs[count++].specific = 0; 7685 } 7686 else 7687 { 7688 UNHANDLED; 7689 } 7690 break; 7691 7692 case IA64_RS_CR_IRR: 7693 if (note == 0) 7694 { 7695 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ 7696 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; 7697 if (rsrc_write 7698 && idesc->operands[1] == IA64_OPND_CR3 7699 && regno == CR_IVR) 7700 { 7701 for (i = 0; i < 4; i++) 7702 { 7703 specs[count] = tmpl; 7704 specs[count++].index = CR_IRR0 + i; 7705 } 7706 } 7707 } 7708 else if (note == 1) 7709 { 7710 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7711 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 7712 && regno >= CR_IRR0 7713 && regno <= CR_IRR3) 7714 { 7715 specs[count] = tmpl; 7716 specs[count++].index = regno; 7717 } 7718 } 7719 else 7720 { 7721 UNHANDLED; 7722 } 7723 break; 7724 7725 case IA64_RS_CR_LRR: 7726 if (note != 1) 7727 { 7728 UNHANDLED; 7729 } 7730 else 7731 { 7732 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7733 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 7734 && (regno == CR_LRR0 || regno == CR_LRR1)) 7735 { 7736 specs[count] = tmpl; 7737 specs[count++].index = regno; 7738 } 7739 } 7740 break; 7741 7742 case IA64_RS_CR: 7743 if (note == 1) 7744 { 7745 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 7746 { 7747 specs[count] = tmpl; 7748 specs[count++].index = 7749 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7750 } 7751 } 7752 else 7753 { 7754 UNHANDLED; 7755 } 7756 break; 7757 7758 case IA64_RS_FR: 7759 case IA64_RS_FRb: 7760 if (note != 1) 7761 { 7762 UNHANDLED; 7763 } 7764 else if (rsrc_write) 7765 { 7766 if (dep->specifier == IA64_RS_FRb 7767 && idesc->operands[0] == IA64_OPND_F1) 7768 { 7769 specs[count] = tmpl; 7770 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; 7771 } 7772 } 7773 else 7774 { 7775 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) 7776 { 7777 if (idesc->operands[i] == IA64_OPND_F2 7778 || idesc->operands[i] == IA64_OPND_F3 7779 || idesc->operands[i] == IA64_OPND_F4) 7780 { 7781 specs[count] = tmpl; 7782 specs[count++].index = 7783 CURR_SLOT.opnd[i].X_add_number - REG_FR; 7784 } 7785 } 7786 } 7787 break; 7788 7789 case IA64_RS_GR: 7790 if (note == 13) 7791 { 7792 /* This reference applies only to the GR whose value is loaded with 7793 data returned from memory. */ 7794 specs[count] = tmpl; 7795 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; 7796 } 7797 else if (note == 1) 7798 { 7799 if (rsrc_write) 7800 { 7801 for (i = 0; i < idesc->num_outputs; i++) 7802 if (idesc->operands[i] == IA64_OPND_R1 7803 || idesc->operands[i] == IA64_OPND_R2 7804 || idesc->operands[i] == IA64_OPND_R3) 7805 { 7806 specs[count] = tmpl; 7807 specs[count++].index = 7808 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7809 } 7810 if (idesc->flags & IA64_OPCODE_POSTINC) 7811 for (i = 0; i < NELEMS (idesc->operands); i++) 7812 if (idesc->operands[i] == IA64_OPND_MR3) 7813 { 7814 specs[count] = tmpl; 7815 specs[count++].index = 7816 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7817 } 7818 } 7819 else 7820 { 7821 /* Look for anything that reads a GR. */ 7822 for (i = 0; i < NELEMS (idesc->operands); i++) 7823 { 7824 if (idesc->operands[i] == IA64_OPND_MR3 7825 || idesc->operands[i] == IA64_OPND_CPUID_R3 7826 || idesc->operands[i] == IA64_OPND_DBR_R3 7827 || idesc->operands[i] == IA64_OPND_IBR_R3 7828 || idesc->operands[i] == IA64_OPND_MSR_R3 7829 || idesc->operands[i] == IA64_OPND_PKR_R3 7830 || idesc->operands[i] == IA64_OPND_PMC_R3 7831 || idesc->operands[i] == IA64_OPND_PMD_R3 7832 || idesc->operands[i] == IA64_OPND_RR_R3 7833 || ((i >= idesc->num_outputs) 7834 && (idesc->operands[i] == IA64_OPND_R1 7835 || idesc->operands[i] == IA64_OPND_R2 7836 || idesc->operands[i] == IA64_OPND_R3 7837 /* addl source register. */ 7838 || idesc->operands[i] == IA64_OPND_R3_2))) 7839 { 7840 specs[count] = tmpl; 7841 specs[count++].index = 7842 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7843 } 7844 } 7845 } 7846 } 7847 else 7848 { 7849 UNHANDLED; 7850 } 7851 break; 7852 7853 /* This is the same as IA64_RS_PRr, except that the register range is 7854 from 1 - 15, and there are no rotating register reads/writes here. */ 7855 case IA64_RS_PR: 7856 if (note == 0) 7857 { 7858 for (i = 1; i < 16; i++) 7859 { 7860 specs[count] = tmpl; 7861 specs[count++].index = i; 7862 } 7863 } 7864 else if (note == 7) 7865 { 7866 valueT mask = 0; 7867 /* Mark only those registers indicated by the mask. */ 7868 if (rsrc_write) 7869 { 7870 mask = CURR_SLOT.opnd[2].X_add_number; 7871 for (i = 1; i < 16; i++) 7872 if (mask & ((valueT) 1 << i)) 7873 { 7874 specs[count] = tmpl; 7875 specs[count++].index = i; 7876 } 7877 } 7878 else 7879 { 7880 UNHANDLED; 7881 } 7882 } 7883 else if (note == 11) /* note 11 implies note 1 as well */ 7884 { 7885 if (rsrc_write) 7886 { 7887 for (i = 0; i < idesc->num_outputs; i++) 7888 { 7889 if (idesc->operands[i] == IA64_OPND_P1 7890 || idesc->operands[i] == IA64_OPND_P2) 7891 { 7892 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 7893 if (regno >= 1 && regno < 16) 7894 { 7895 specs[count] = tmpl; 7896 specs[count++].index = regno; 7897 } 7898 } 7899 } 7900 } 7901 else 7902 { 7903 UNHANDLED; 7904 } 7905 } 7906 else if (note == 12) 7907 { 7908 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 7909 { 7910 specs[count] = tmpl; 7911 specs[count++].index = CURR_SLOT.qp_regno; 7912 } 7913 } 7914 else if (note == 1) 7915 { 7916 if (rsrc_write) 7917 { 7918 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 7919 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 7920 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 7921 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 7922 7923 if ((idesc->operands[0] == IA64_OPND_P1 7924 || idesc->operands[0] == IA64_OPND_P2) 7925 && p1 >= 1 && p1 < 16) 7926 { 7927 specs[count] = tmpl; 7928 specs[count].cmp_type = 7929 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 7930 specs[count++].index = p1; 7931 } 7932 if ((idesc->operands[1] == IA64_OPND_P1 7933 || idesc->operands[1] == IA64_OPND_P2) 7934 && p2 >= 1 && p2 < 16) 7935 { 7936 specs[count] = tmpl; 7937 specs[count].cmp_type = 7938 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 7939 specs[count++].index = p2; 7940 } 7941 } 7942 else 7943 { 7944 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 7945 { 7946 specs[count] = tmpl; 7947 specs[count++].index = CURR_SLOT.qp_regno; 7948 } 7949 if (idesc->operands[1] == IA64_OPND_PR) 7950 { 7951 for (i = 1; i < 16; i++) 7952 { 7953 specs[count] = tmpl; 7954 specs[count++].index = i; 7955 } 7956 } 7957 } 7958 } 7959 else 7960 { 7961 UNHANDLED; 7962 } 7963 break; 7964 7965 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are 7966 simplified cases of this. */ 7967 case IA64_RS_PRr: 7968 if (note == 0) 7969 { 7970 for (i = 16; i < 63; i++) 7971 { 7972 specs[count] = tmpl; 7973 specs[count++].index = i; 7974 } 7975 } 7976 else if (note == 7) 7977 { 7978 valueT mask = 0; 7979 /* Mark only those registers indicated by the mask. */ 7980 if (rsrc_write 7981 && idesc->operands[0] == IA64_OPND_PR) 7982 { 7983 mask = CURR_SLOT.opnd[2].X_add_number; 7984 if (mask & ((valueT) 1<<16)) 7985 for (i = 16; i < 63; i++) 7986 { 7987 specs[count] = tmpl; 7988 specs[count++].index = i; 7989 } 7990 } 7991 else if (rsrc_write 7992 && idesc->operands[0] == IA64_OPND_PR_ROT) 7993 { 7994 for (i = 16; i < 63; i++) 7995 { 7996 specs[count] = tmpl; 7997 specs[count++].index = i; 7998 } 7999 } 8000 else 8001 { 8002 UNHANDLED; 8003 } 8004 } 8005 else if (note == 11) /* note 11 implies note 1 as well */ 8006 { 8007 if (rsrc_write) 8008 { 8009 for (i = 0; i < idesc->num_outputs; i++) 8010 { 8011 if (idesc->operands[i] == IA64_OPND_P1 8012 || idesc->operands[i] == IA64_OPND_P2) 8013 { 8014 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 8015 if (regno >= 16 && regno < 63) 8016 { 8017 specs[count] = tmpl; 8018 specs[count++].index = regno; 8019 } 8020 } 8021 } 8022 } 8023 else 8024 { 8025 UNHANDLED; 8026 } 8027 } 8028 else if (note == 12) 8029 { 8030 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 8031 { 8032 specs[count] = tmpl; 8033 specs[count++].index = CURR_SLOT.qp_regno; 8034 } 8035 } 8036 else if (note == 1) 8037 { 8038 if (rsrc_write) 8039 { 8040 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8041 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8042 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 8043 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 8044 8045 if ((idesc->operands[0] == IA64_OPND_P1 8046 || idesc->operands[0] == IA64_OPND_P2) 8047 && p1 >= 16 && p1 < 63) 8048 { 8049 specs[count] = tmpl; 8050 specs[count].cmp_type = 8051 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 8052 specs[count++].index = p1; 8053 } 8054 if ((idesc->operands[1] == IA64_OPND_P1 8055 || idesc->operands[1] == IA64_OPND_P2) 8056 && p2 >= 16 && p2 < 63) 8057 { 8058 specs[count] = tmpl; 8059 specs[count].cmp_type = 8060 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 8061 specs[count++].index = p2; 8062 } 8063 } 8064 else 8065 { 8066 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 8067 { 8068 specs[count] = tmpl; 8069 specs[count++].index = CURR_SLOT.qp_regno; 8070 } 8071 if (idesc->operands[1] == IA64_OPND_PR) 8072 { 8073 for (i = 16; i < 63; i++) 8074 { 8075 specs[count] = tmpl; 8076 specs[count++].index = i; 8077 } 8078 } 8079 } 8080 } 8081 else 8082 { 8083 UNHANDLED; 8084 } 8085 break; 8086 8087 case IA64_RS_PSR: 8088 /* Verify that the instruction is using the PSR bit indicated in 8089 dep->regindex. */ 8090 if (note == 0) 8091 { 8092 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) 8093 { 8094 if (dep->regindex < 6) 8095 { 8096 specs[count++] = tmpl; 8097 } 8098 } 8099 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) 8100 { 8101 if (dep->regindex < 32 8102 || dep->regindex == 35 8103 || dep->regindex == 36 8104 || (!rsrc_write && dep->regindex == PSR_CPL)) 8105 { 8106 specs[count++] = tmpl; 8107 } 8108 } 8109 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) 8110 { 8111 if (dep->regindex < 32 8112 || dep->regindex == 35 8113 || dep->regindex == 36 8114 || (rsrc_write && dep->regindex == PSR_CPL)) 8115 { 8116 specs[count++] = tmpl; 8117 } 8118 } 8119 else 8120 { 8121 /* Several PSR bits have very specific dependencies. */ 8122 switch (dep->regindex) 8123 { 8124 default: 8125 specs[count++] = tmpl; 8126 break; 8127 case PSR_IC: 8128 if (rsrc_write) 8129 { 8130 specs[count++] = tmpl; 8131 } 8132 else 8133 { 8134 /* Only certain CR accesses use PSR.ic */ 8135 if (idesc->operands[0] == IA64_OPND_CR3 8136 || idesc->operands[1] == IA64_OPND_CR3) 8137 { 8138 int index = 8139 ((idesc->operands[0] == IA64_OPND_CR3) 8140 ? 0 : 1); 8141 int regno = 8142 CURR_SLOT.opnd[index].X_add_number - REG_CR; 8143 8144 switch (regno) 8145 { 8146 default: 8147 break; 8148 case CR_ITIR: 8149 case CR_IFS: 8150 case CR_IIM: 8151 case CR_IIP: 8152 case CR_IPSR: 8153 case CR_ISR: 8154 case CR_IFA: 8155 case CR_IHA: 8156 case CR_IIPA: 8157 specs[count++] = tmpl; 8158 break; 8159 } 8160 } 8161 } 8162 break; 8163 case PSR_CPL: 8164 if (rsrc_write) 8165 { 8166 specs[count++] = tmpl; 8167 } 8168 else 8169 { 8170 /* Only some AR accesses use cpl */ 8171 if (idesc->operands[0] == IA64_OPND_AR3 8172 || idesc->operands[1] == IA64_OPND_AR3) 8173 { 8174 int index = 8175 ((idesc->operands[0] == IA64_OPND_AR3) 8176 ? 0 : 1); 8177 int regno = 8178 CURR_SLOT.opnd[index].X_add_number - REG_AR; 8179 8180 if (regno == AR_ITC 8181 || (index == 0 8182 && (regno == AR_ITC 8183 || regno == AR_RSC 8184 || (regno >= AR_K0 8185 && regno <= AR_K7)))) 8186 { 8187 specs[count++] = tmpl; 8188 } 8189 } 8190 else 8191 { 8192 specs[count++] = tmpl; 8193 } 8194 break; 8195 } 8196 } 8197 } 8198 } 8199 else if (note == 7) 8200 { 8201 valueT mask = 0; 8202 if (idesc->operands[0] == IA64_OPND_IMMU24) 8203 { 8204 mask = CURR_SLOT.opnd[0].X_add_number; 8205 } 8206 else 8207 { 8208 UNHANDLED; 8209 } 8210 if (mask & ((valueT) 1 << dep->regindex)) 8211 { 8212 specs[count++] = tmpl; 8213 } 8214 } 8215 else if (note == 8) 8216 { 8217 int min = dep->regindex == PSR_DFL ? 2 : 32; 8218 int max = dep->regindex == PSR_DFL ? 31 : 127; 8219 /* dfh is read on FR32-127; dfl is read on FR2-31 */ 8220 for (i = 0; i < NELEMS (idesc->operands); i++) 8221 { 8222 if (idesc->operands[i] == IA64_OPND_F1 8223 || idesc->operands[i] == IA64_OPND_F2 8224 || idesc->operands[i] == IA64_OPND_F3 8225 || idesc->operands[i] == IA64_OPND_F4) 8226 { 8227 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8228 if (reg >= min && reg <= max) 8229 { 8230 specs[count++] = tmpl; 8231 } 8232 } 8233 } 8234 } 8235 else if (note == 9) 8236 { 8237 int min = dep->regindex == PSR_MFL ? 2 : 32; 8238 int max = dep->regindex == PSR_MFL ? 31 : 127; 8239 /* mfh is read on writes to FR32-127; mfl is read on writes to 8240 FR2-31 */ 8241 for (i = 0; i < idesc->num_outputs; i++) 8242 { 8243 if (idesc->operands[i] == IA64_OPND_F1) 8244 { 8245 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8246 if (reg >= min && reg <= max) 8247 { 8248 specs[count++] = tmpl; 8249 } 8250 } 8251 } 8252 } 8253 else if (note == 10) 8254 { 8255 for (i = 0; i < NELEMS (idesc->operands); i++) 8256 { 8257 if (idesc->operands[i] == IA64_OPND_R1 8258 || idesc->operands[i] == IA64_OPND_R2 8259 || idesc->operands[i] == IA64_OPND_R3) 8260 { 8261 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8262 if (regno >= 16 && regno <= 31) 8263 { 8264 specs[count++] = tmpl; 8265 } 8266 } 8267 } 8268 } 8269 else 8270 { 8271 UNHANDLED; 8272 } 8273 break; 8274 8275 case IA64_RS_AR_FPSR: 8276 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 8277 { 8278 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8279 if (regno == AR_FPSR) 8280 { 8281 specs[count++] = tmpl; 8282 } 8283 } 8284 else 8285 { 8286 specs[count++] = tmpl; 8287 } 8288 break; 8289 8290 case IA64_RS_ARX: 8291 /* Handle all AR[REG] resources */ 8292 if (note == 0 || note == 1) 8293 { 8294 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8295 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 8296 && regno == dep->regindex) 8297 { 8298 specs[count++] = tmpl; 8299 } 8300 /* other AR[REG] resources may be affected by AR accesses */ 8301 else if (idesc->operands[0] == IA64_OPND_AR3) 8302 { 8303 /* AR[] writes */ 8304 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; 8305 switch (dep->regindex) 8306 { 8307 default: 8308 break; 8309 case AR_BSP: 8310 case AR_RNAT: 8311 if (regno == AR_BSPSTORE) 8312 { 8313 specs[count++] = tmpl; 8314 } 8315 case AR_RSC: 8316 if (!rsrc_write && 8317 (regno == AR_BSPSTORE 8318 || regno == AR_RNAT)) 8319 { 8320 specs[count++] = tmpl; 8321 } 8322 break; 8323 } 8324 } 8325 else if (idesc->operands[1] == IA64_OPND_AR3) 8326 { 8327 /* AR[] reads */ 8328 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; 8329 switch (dep->regindex) 8330 { 8331 default: 8332 break; 8333 case AR_RSC: 8334 if (regno == AR_BSPSTORE || regno == AR_RNAT) 8335 { 8336 specs[count++] = tmpl; 8337 } 8338 break; 8339 } 8340 } 8341 else 8342 { 8343 specs[count++] = tmpl; 8344 } 8345 } 8346 else 8347 { 8348 UNHANDLED; 8349 } 8350 break; 8351 8352 case IA64_RS_CRX: 8353 /* Handle all CR[REG] resources */ 8354 if (note == 0 || note == 1) 8355 { 8356 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 8357 { 8358 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 8359 if (regno == dep->regindex) 8360 { 8361 specs[count++] = tmpl; 8362 } 8363 else if (!rsrc_write) 8364 { 8365 /* Reads from CR[IVR] affect other resources. */ 8366 if (regno == CR_IVR) 8367 { 8368 if ((dep->regindex >= CR_IRR0 8369 && dep->regindex <= CR_IRR3) 8370 || dep->regindex == CR_TPR) 8371 { 8372 specs[count++] = tmpl; 8373 } 8374 } 8375 } 8376 } 8377 else 8378 { 8379 specs[count++] = tmpl; 8380 } 8381 } 8382 else 8383 { 8384 UNHANDLED; 8385 } 8386 break; 8387 8388 case IA64_RS_INSERVICE: 8389 /* look for write of EOI (67) or read of IVR (65) */ 8390 if ((idesc->operands[0] == IA64_OPND_CR3 8391 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) 8392 || (idesc->operands[1] == IA64_OPND_CR3 8393 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) 8394 { 8395 specs[count++] = tmpl; 8396 } 8397 break; 8398 8399 case IA64_RS_GR0: 8400 if (note == 1) 8401 { 8402 specs[count++] = tmpl; 8403 } 8404 else 8405 { 8406 UNHANDLED; 8407 } 8408 break; 8409 8410 case IA64_RS_CFM: 8411 if (note != 2) 8412 { 8413 specs[count++] = tmpl; 8414 } 8415 else 8416 { 8417 /* Check if any of the registers accessed are in the rotating region. 8418 mov to/from pr accesses CFM only when qp_regno is in the rotating 8419 region */ 8420 for (i = 0; i < NELEMS (idesc->operands); i++) 8421 { 8422 if (idesc->operands[i] == IA64_OPND_R1 8423 || idesc->operands[i] == IA64_OPND_R2 8424 || idesc->operands[i] == IA64_OPND_R3) 8425 { 8426 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8427 /* Assumes that md.rot.num_regs is always valid */ 8428 if (md.rot.num_regs > 0 8429 && num > 31 8430 && num < 31 + md.rot.num_regs) 8431 { 8432 specs[count] = tmpl; 8433 specs[count++].specific = 0; 8434 } 8435 } 8436 else if (idesc->operands[i] == IA64_OPND_F1 8437 || idesc->operands[i] == IA64_OPND_F2 8438 || idesc->operands[i] == IA64_OPND_F3 8439 || idesc->operands[i] == IA64_OPND_F4) 8440 { 8441 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8442 if (num > 31) 8443 { 8444 specs[count] = tmpl; 8445 specs[count++].specific = 0; 8446 } 8447 } 8448 else if (idesc->operands[i] == IA64_OPND_P1 8449 || idesc->operands[i] == IA64_OPND_P2) 8450 { 8451 int num = CURR_SLOT.opnd[i].X_add_number - REG_P; 8452 if (num > 15) 8453 { 8454 specs[count] = tmpl; 8455 specs[count++].specific = 0; 8456 } 8457 } 8458 } 8459 if (CURR_SLOT.qp_regno > 15) 8460 { 8461 specs[count] = tmpl; 8462 specs[count++].specific = 0; 8463 } 8464 } 8465 break; 8466 8467 /* This is the same as IA64_RS_PRr, except simplified to account for 8468 the fact that there is only one register. */ 8469 case IA64_RS_PR63: 8470 if (note == 0) 8471 { 8472 specs[count++] = tmpl; 8473 } 8474 else if (note == 7) 8475 { 8476 valueT mask = 0; 8477 if (idesc->operands[2] == IA64_OPND_IMM17) 8478 mask = CURR_SLOT.opnd[2].X_add_number; 8479 if (mask & ((valueT) 1 << 63)) 8480 specs[count++] = tmpl; 8481 } 8482 else if (note == 11) 8483 { 8484 if ((idesc->operands[0] == IA64_OPND_P1 8485 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) 8486 || (idesc->operands[1] == IA64_OPND_P2 8487 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) 8488 { 8489 specs[count++] = tmpl; 8490 } 8491 } 8492 else if (note == 12) 8493 { 8494 if (CURR_SLOT.qp_regno == 63) 8495 { 8496 specs[count++] = tmpl; 8497 } 8498 } 8499 else if (note == 1) 8500 { 8501 if (rsrc_write) 8502 { 8503 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8504 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8505 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 8506 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 8507 8508 if (p1 == 63 8509 && (idesc->operands[0] == IA64_OPND_P1 8510 || idesc->operands[0] == IA64_OPND_P2)) 8511 { 8512 specs[count] = tmpl; 8513 specs[count++].cmp_type = 8514 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 8515 } 8516 if (p2 == 63 8517 && (idesc->operands[1] == IA64_OPND_P1 8518 || idesc->operands[1] == IA64_OPND_P2)) 8519 { 8520 specs[count] = tmpl; 8521 specs[count++].cmp_type = 8522 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 8523 } 8524 } 8525 else 8526 { 8527 if (CURR_SLOT.qp_regno == 63) 8528 { 8529 specs[count++] = tmpl; 8530 } 8531 } 8532 } 8533 else 8534 { 8535 UNHANDLED; 8536 } 8537 break; 8538 8539 case IA64_RS_RSE: 8540 /* FIXME we can identify some individual RSE written resources, but RSE 8541 read resources have not yet been completely identified, so for now 8542 treat RSE as a single resource */ 8543 if (strncmp (idesc->name, "mov", 3) == 0) 8544 { 8545 if (rsrc_write) 8546 { 8547 if (idesc->operands[0] == IA64_OPND_AR3 8548 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) 8549 { 8550 specs[count] = tmpl; 8551 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ 8552 } 8553 } 8554 else 8555 { 8556 if (idesc->operands[0] == IA64_OPND_AR3) 8557 { 8558 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE 8559 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) 8560 { 8561 specs[count++] = tmpl; 8562 } 8563 } 8564 else if (idesc->operands[1] == IA64_OPND_AR3) 8565 { 8566 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP 8567 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE 8568 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) 8569 { 8570 specs[count++] = tmpl; 8571 } 8572 } 8573 } 8574 } 8575 else 8576 { 8577 specs[count++] = tmpl; 8578 } 8579 break; 8580 8581 case IA64_RS_ANY: 8582 /* FIXME -- do any of these need to be non-specific? */ 8583 specs[count++] = tmpl; 8584 break; 8585 8586 default: 8587 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); 8588 break; 8589 } 8590 8591 return count; 8592} 8593 8594/* Clear branch flags on marked resources. This breaks the link between the 8595 QP of the marking instruction and a subsequent branch on the same QP. */ 8596 8597static void 8598clear_qp_branch_flag (mask) 8599 valueT mask; 8600{ 8601 int i; 8602 for (i = 0; i < regdepslen; i++) 8603 { 8604 valueT bit = ((valueT) 1 << regdeps[i].qp_regno); 8605 if ((bit & mask) != 0) 8606 { 8607 regdeps[i].link_to_qp_branch = 0; 8608 } 8609 } 8610} 8611 8612/* Remove any mutexes which contain any of the PRs indicated in the mask. 8613 8614 Any changes to a PR clears the mutex relations which include that PR. */ 8615 8616static void 8617clear_qp_mutex (mask) 8618 valueT mask; 8619{ 8620 int i; 8621 8622 i = 0; 8623 while (i < qp_mutexeslen) 8624 { 8625 if ((qp_mutexes[i].prmask & mask) != 0) 8626 { 8627 if (md.debug_dv) 8628 { 8629 fprintf (stderr, " Clearing mutex relation"); 8630 print_prmask (qp_mutexes[i].prmask); 8631 fprintf (stderr, "\n"); 8632 } 8633 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; 8634 } 8635 else 8636 ++i; 8637 } 8638} 8639 8640/* Clear implies relations which contain PRs in the given masks. 8641 P1_MASK indicates the source of the implies relation, while P2_MASK 8642 indicates the implied PR. */ 8643 8644static void 8645clear_qp_implies (p1_mask, p2_mask) 8646 valueT p1_mask; 8647 valueT p2_mask; 8648{ 8649 int i; 8650 8651 i = 0; 8652 while (i < qp_implieslen) 8653 { 8654 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 8655 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) 8656 { 8657 if (md.debug_dv) 8658 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", 8659 qp_implies[i].p1, qp_implies[i].p2); 8660 qp_implies[i] = qp_implies[--qp_implieslen]; 8661 } 8662 else 8663 ++i; 8664 } 8665} 8666 8667/* Add the PRs specified to the list of implied relations. */ 8668 8669static void 8670add_qp_imply (p1, p2) 8671 int p1, p2; 8672{ 8673 valueT mask; 8674 valueT bit; 8675 int i; 8676 8677 /* p0 is not meaningful here. */ 8678 if (p1 == 0 || p2 == 0) 8679 abort (); 8680 8681 if (p1 == p2) 8682 return; 8683 8684 /* If it exists already, ignore it. */ 8685 for (i = 0; i < qp_implieslen; i++) 8686 { 8687 if (qp_implies[i].p1 == p1 8688 && qp_implies[i].p2 == p2 8689 && qp_implies[i].path == md.path 8690 && !qp_implies[i].p2_branched) 8691 return; 8692 } 8693 8694 if (qp_implieslen == qp_impliestotlen) 8695 { 8696 qp_impliestotlen += 20; 8697 qp_implies = (struct qp_imply *) 8698 xrealloc ((void *) qp_implies, 8699 qp_impliestotlen * sizeof (struct qp_imply)); 8700 } 8701 if (md.debug_dv) 8702 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); 8703 qp_implies[qp_implieslen].p1 = p1; 8704 qp_implies[qp_implieslen].p2 = p2; 8705 qp_implies[qp_implieslen].path = md.path; 8706 qp_implies[qp_implieslen++].p2_branched = 0; 8707 8708 /* Add in the implied transitive relations; for everything that p2 implies, 8709 make p1 imply that, too; for everything that implies p1, make it imply p2 8710 as well. */ 8711 for (i = 0; i < qp_implieslen; i++) 8712 { 8713 if (qp_implies[i].p1 == p2) 8714 add_qp_imply (p1, qp_implies[i].p2); 8715 if (qp_implies[i].p2 == p1) 8716 add_qp_imply (qp_implies[i].p1, p2); 8717 } 8718 /* Add in mutex relations implied by this implies relation; for each mutex 8719 relation containing p2, duplicate it and replace p2 with p1. */ 8720 bit = (valueT) 1 << p1; 8721 mask = (valueT) 1 << p2; 8722 for (i = 0; i < qp_mutexeslen; i++) 8723 { 8724 if (qp_mutexes[i].prmask & mask) 8725 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); 8726 } 8727} 8728 8729/* Add the PRs specified in the mask to the mutex list; this means that only 8730 one of the PRs can be true at any time. PR0 should never be included in 8731 the mask. */ 8732 8733static void 8734add_qp_mutex (mask) 8735 valueT mask; 8736{ 8737 if (mask & 0x1) 8738 abort (); 8739 8740 if (qp_mutexeslen == qp_mutexestotlen) 8741 { 8742 qp_mutexestotlen += 20; 8743 qp_mutexes = (struct qpmutex *) 8744 xrealloc ((void *) qp_mutexes, 8745 qp_mutexestotlen * sizeof (struct qpmutex)); 8746 } 8747 if (md.debug_dv) 8748 { 8749 fprintf (stderr, " Registering mutex on"); 8750 print_prmask (mask); 8751 fprintf (stderr, "\n"); 8752 } 8753 qp_mutexes[qp_mutexeslen].path = md.path; 8754 qp_mutexes[qp_mutexeslen++].prmask = mask; 8755} 8756 8757static int 8758has_suffix_p (name, suffix) 8759 const char *name; 8760 const char *suffix; 8761{ 8762 size_t namelen = strlen (name); 8763 size_t sufflen = strlen (suffix); 8764 8765 if (namelen <= sufflen) 8766 return 0; 8767 return strcmp (name + namelen - sufflen, suffix) == 0; 8768} 8769 8770static void 8771clear_register_values () 8772{ 8773 int i; 8774 if (md.debug_dv) 8775 fprintf (stderr, " Clearing register values\n"); 8776 for (i = 1; i < NELEMS (gr_values); i++) 8777 gr_values[i].known = 0; 8778} 8779 8780/* Keep track of register values/changes which affect DV tracking. 8781 8782 optimization note: should add a flag to classes of insns where otherwise we 8783 have to examine a group of strings to identify them. */ 8784 8785static void 8786note_register_values (idesc) 8787 struct ia64_opcode *idesc; 8788{ 8789 valueT qp_changemask = 0; 8790 int i; 8791 8792 /* Invalidate values for registers being written to. */ 8793 for (i = 0; i < idesc->num_outputs; i++) 8794 { 8795 if (idesc->operands[i] == IA64_OPND_R1 8796 || idesc->operands[i] == IA64_OPND_R2 8797 || idesc->operands[i] == IA64_OPND_R3) 8798 { 8799 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8800 if (regno > 0 && regno < NELEMS (gr_values)) 8801 gr_values[regno].known = 0; 8802 } 8803 else if (idesc->operands[i] == IA64_OPND_R3_2) 8804 { 8805 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8806 if (regno > 0 && regno < 4) 8807 gr_values[regno].known = 0; 8808 } 8809 else if (idesc->operands[i] == IA64_OPND_P1 8810 || idesc->operands[i] == IA64_OPND_P2) 8811 { 8812 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 8813 qp_changemask |= (valueT) 1 << regno; 8814 } 8815 else if (idesc->operands[i] == IA64_OPND_PR) 8816 { 8817 if (idesc->operands[2] & (valueT) 0x10000) 8818 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; 8819 else 8820 qp_changemask = idesc->operands[2]; 8821 break; 8822 } 8823 else if (idesc->operands[i] == IA64_OPND_PR_ROT) 8824 { 8825 if (idesc->operands[1] & ((valueT) 1 << 43)) 8826 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; 8827 else 8828 qp_changemask = idesc->operands[1]; 8829 qp_changemask &= ~(valueT) 0xFFFF; 8830 break; 8831 } 8832 } 8833 8834 /* Always clear qp branch flags on any PR change. */ 8835 /* FIXME there may be exceptions for certain compares. */ 8836 clear_qp_branch_flag (qp_changemask); 8837 8838 /* Invalidate rotating registers on insns which affect RRBs in CFM. */ 8839 if (idesc->flags & IA64_OPCODE_MOD_RRBS) 8840 { 8841 qp_changemask |= ~(valueT) 0xFFFF; 8842 if (strcmp (idesc->name, "clrrrb.pr") != 0) 8843 { 8844 for (i = 32; i < 32 + md.rot.num_regs; i++) 8845 gr_values[i].known = 0; 8846 } 8847 clear_qp_mutex (qp_changemask); 8848 clear_qp_implies (qp_changemask, qp_changemask); 8849 } 8850 /* After a call, all register values are undefined, except those marked 8851 as "safe". */ 8852 else if (strncmp (idesc->name, "br.call", 6) == 0 8853 || strncmp (idesc->name, "brl.call", 7) == 0) 8854 { 8855 /* FIXME keep GR values which are marked as "safe_across_calls" */ 8856 clear_register_values (); 8857 clear_qp_mutex (~qp_safe_across_calls); 8858 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); 8859 clear_qp_branch_flag (~qp_safe_across_calls); 8860 } 8861 else if (is_interruption_or_rfi (idesc) 8862 || is_taken_branch (idesc)) 8863 { 8864 clear_register_values (); 8865 clear_qp_mutex (~(valueT) 0); 8866 clear_qp_implies (~(valueT) 0, ~(valueT) 0); 8867 } 8868 /* Look for mutex and implies relations. */ 8869 else if ((idesc->operands[0] == IA64_OPND_P1 8870 || idesc->operands[0] == IA64_OPND_P2) 8871 && (idesc->operands[1] == IA64_OPND_P1 8872 || idesc->operands[1] == IA64_OPND_P2)) 8873 { 8874 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8875 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8876 valueT p1mask = (valueT) 1 << p1; 8877 valueT p2mask = (valueT) 1 << p2; 8878 8879 /* If one of the PRs is PR0, we can't really do anything. */ 8880 if (p1 == 0 || p2 == 0) 8881 { 8882 if (md.debug_dv) 8883 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); 8884 } 8885 /* In general, clear mutexes and implies which include P1 or P2, 8886 with the following exceptions. */ 8887 else if (has_suffix_p (idesc->name, ".or.andcm") 8888 || has_suffix_p (idesc->name, ".and.orcm")) 8889 { 8890 add_qp_mutex (p1mask | p2mask); 8891 clear_qp_implies (p2mask, p1mask); 8892 } 8893 else if (has_suffix_p (idesc->name, ".andcm") 8894 || has_suffix_p (idesc->name, ".and")) 8895 { 8896 clear_qp_implies (0, p1mask | p2mask); 8897 } 8898 else if (has_suffix_p (idesc->name, ".orcm") 8899 || has_suffix_p (idesc->name, ".or")) 8900 { 8901 clear_qp_mutex (p1mask | p2mask); 8902 clear_qp_implies (p1mask | p2mask, 0); 8903 } 8904 else 8905 { 8906 clear_qp_implies (p1mask | p2mask, p1mask | p2mask); 8907 if (has_suffix_p (idesc->name, ".unc")) 8908 { 8909 add_qp_mutex (p1mask | p2mask); 8910 if (CURR_SLOT.qp_regno != 0) 8911 { 8912 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, 8913 CURR_SLOT.qp_regno); 8914 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, 8915 CURR_SLOT.qp_regno); 8916 } 8917 } 8918 else if (CURR_SLOT.qp_regno == 0) 8919 { 8920 add_qp_mutex (p1mask | p2mask); 8921 } 8922 else 8923 { 8924 clear_qp_mutex (p1mask | p2mask); 8925 } 8926 } 8927 } 8928 /* Look for mov imm insns into GRs. */ 8929 else if (idesc->operands[0] == IA64_OPND_R1 8930 && (idesc->operands[1] == IA64_OPND_IMM22 8931 || idesc->operands[1] == IA64_OPND_IMMU64) 8932 && (strcmp (idesc->name, "mov") == 0 8933 || strcmp (idesc->name, "movl") == 0)) 8934 { 8935 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; 8936 if (regno > 0 && regno < NELEMS (gr_values)) 8937 { 8938 gr_values[regno].known = 1; 8939 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; 8940 gr_values[regno].path = md.path; 8941 if (md.debug_dv) 8942 { 8943 fprintf (stderr, " Know gr%d = ", regno); 8944 fprintf_vma (stderr, gr_values[regno].value); 8945 fputs ("\n", stderr); 8946 } 8947 } 8948 } 8949 else 8950 { 8951 clear_qp_mutex (qp_changemask); 8952 clear_qp_implies (qp_changemask, qp_changemask); 8953 } 8954} 8955 8956/* Return whether the given predicate registers are currently mutex. */ 8957 8958static int 8959qp_mutex (p1, p2, path) 8960 int p1; 8961 int p2; 8962 int path; 8963{ 8964 int i; 8965 valueT mask; 8966 8967 if (p1 != p2) 8968 { 8969 mask = ((valueT) 1 << p1) | (valueT) 1 << p2; 8970 for (i = 0; i < qp_mutexeslen; i++) 8971 { 8972 if (qp_mutexes[i].path >= path 8973 && (qp_mutexes[i].prmask & mask) == mask) 8974 return 1; 8975 } 8976 } 8977 return 0; 8978} 8979 8980/* Return whether the given resource is in the given insn's list of chks 8981 Return 1 if the conflict is absolutely determined, 2 if it's a potential 8982 conflict. */ 8983 8984static int 8985resources_match (rs, idesc, note, qp_regno, path) 8986 struct rsrc *rs; 8987 struct ia64_opcode *idesc; 8988 int note; 8989 int qp_regno; 8990 int path; 8991{ 8992 struct rsrc specs[MAX_SPECS]; 8993 int count; 8994 8995 /* If the marked resource's qp_regno and the given qp_regno are mutex, 8996 we don't need to check. One exception is note 11, which indicates that 8997 target predicates are written regardless of PR[qp]. */ 8998 if (qp_mutex (rs->qp_regno, qp_regno, path) 8999 && note != 11) 9000 return 0; 9001 9002 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); 9003 while (count-- > 0) 9004 { 9005 /* UNAT checking is a bit more specific than other resources */ 9006 if (rs->dependency->specifier == IA64_RS_AR_UNAT 9007 && specs[count].mem_offset.hint 9008 && rs->mem_offset.hint) 9009 { 9010 if (rs->mem_offset.base == specs[count].mem_offset.base) 9011 { 9012 if (((rs->mem_offset.offset >> 3) & 0x3F) == 9013 ((specs[count].mem_offset.offset >> 3) & 0x3F)) 9014 return 1; 9015 else 9016 continue; 9017 } 9018 } 9019 9020 /* Skip apparent PR write conflicts where both writes are an AND or both 9021 writes are an OR. */ 9022 if (rs->dependency->specifier == IA64_RS_PR 9023 || rs->dependency->specifier == IA64_RS_PRr 9024 || rs->dependency->specifier == IA64_RS_PR63) 9025 { 9026 if (specs[count].cmp_type != CMP_NONE 9027 && specs[count].cmp_type == rs->cmp_type) 9028 { 9029 if (md.debug_dv) 9030 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", 9031 dv_mode[rs->dependency->mode], 9032 rs->dependency->specifier != IA64_RS_PR63 ? 9033 specs[count].index : 63); 9034 continue; 9035 } 9036 if (md.debug_dv) 9037 fprintf (stderr, 9038 " %s on parallel compare conflict %s vs %s on PR%d\n", 9039 dv_mode[rs->dependency->mode], 9040 dv_cmp_type[rs->cmp_type], 9041 dv_cmp_type[specs[count].cmp_type], 9042 rs->dependency->specifier != IA64_RS_PR63 ? 9043 specs[count].index : 63); 9044 9045 } 9046 9047 /* If either resource is not specific, conservatively assume a conflict 9048 */ 9049 if (!specs[count].specific || !rs->specific) 9050 return 2; 9051 else if (specs[count].index == rs->index) 9052 return 1; 9053 } 9054#if 0 9055 if (md.debug_dv) 9056 fprintf (stderr, " No %s conflicts\n", rs->dependency->name); 9057#endif 9058 9059 return 0; 9060} 9061 9062/* Indicate an instruction group break; if INSERT_STOP is non-zero, then 9063 insert a stop to create the break. Update all resource dependencies 9064 appropriately. If QP_REGNO is non-zero, only apply the break to resources 9065 which use the same QP_REGNO and have the link_to_qp_branch flag set. 9066 If SAVE_CURRENT is non-zero, don't affect resources marked by the current 9067 instruction. */ 9068 9069static void 9070insn_group_break (insert_stop, qp_regno, save_current) 9071 int insert_stop; 9072 int qp_regno; 9073 int save_current; 9074{ 9075 int i; 9076 9077 if (insert_stop && md.num_slots_in_use > 0) 9078 PREV_SLOT.end_of_insn_group = 1; 9079 9080 if (md.debug_dv) 9081 { 9082 fprintf (stderr, " Insn group break%s", 9083 (insert_stop ? " (w/stop)" : "")); 9084 if (qp_regno != 0) 9085 fprintf (stderr, " effective for QP=%d", qp_regno); 9086 fprintf (stderr, "\n"); 9087 } 9088 9089 i = 0; 9090 while (i < regdepslen) 9091 { 9092 const struct ia64_dependency *dep = regdeps[i].dependency; 9093 9094 if (qp_regno != 0 9095 && regdeps[i].qp_regno != qp_regno) 9096 { 9097 ++i; 9098 continue; 9099 } 9100 9101 if (save_current 9102 && CURR_SLOT.src_file == regdeps[i].file 9103 && CURR_SLOT.src_line == regdeps[i].line) 9104 { 9105 ++i; 9106 continue; 9107 } 9108 9109 /* clear dependencies which are automatically cleared by a stop, or 9110 those that have reached the appropriate state of insn serialization */ 9111 if (dep->semantics == IA64_DVS_IMPLIED 9112 || dep->semantics == IA64_DVS_IMPLIEDF 9113 || regdeps[i].insn_srlz == STATE_SRLZ) 9114 { 9115 print_dependency ("Removing", i); 9116 regdeps[i] = regdeps[--regdepslen]; 9117 } 9118 else 9119 { 9120 if (dep->semantics == IA64_DVS_DATA 9121 || dep->semantics == IA64_DVS_INSTR 9122 || dep->semantics == IA64_DVS_SPECIFIC) 9123 { 9124 if (regdeps[i].insn_srlz == STATE_NONE) 9125 regdeps[i].insn_srlz = STATE_STOP; 9126 if (regdeps[i].data_srlz == STATE_NONE) 9127 regdeps[i].data_srlz = STATE_STOP; 9128 } 9129 ++i; 9130 } 9131 } 9132} 9133 9134/* Add the given resource usage spec to the list of active dependencies. */ 9135 9136static void 9137mark_resource (idesc, dep, spec, depind, path) 9138 struct ia64_opcode *idesc ATTRIBUTE_UNUSED; 9139 const struct ia64_dependency *dep ATTRIBUTE_UNUSED; 9140 struct rsrc *spec; 9141 int depind; 9142 int path; 9143{ 9144 if (regdepslen == regdepstotlen) 9145 { 9146 regdepstotlen += 20; 9147 regdeps = (struct rsrc *) 9148 xrealloc ((void *) regdeps, 9149 regdepstotlen * sizeof (struct rsrc)); 9150 } 9151 9152 regdeps[regdepslen] = *spec; 9153 regdeps[regdepslen].depind = depind; 9154 regdeps[regdepslen].path = path; 9155 regdeps[regdepslen].file = CURR_SLOT.src_file; 9156 regdeps[regdepslen].line = CURR_SLOT.src_line; 9157 9158 print_dependency ("Adding", regdepslen); 9159 9160 ++regdepslen; 9161} 9162 9163static void 9164print_dependency (action, depind) 9165 const char *action; 9166 int depind; 9167{ 9168 if (md.debug_dv) 9169 { 9170 fprintf (stderr, " %s %s '%s'", 9171 action, dv_mode[(regdeps[depind].dependency)->mode], 9172 (regdeps[depind].dependency)->name); 9173 if (regdeps[depind].specific && regdeps[depind].index != 0) 9174 fprintf (stderr, " (%d)", regdeps[depind].index); 9175 if (regdeps[depind].mem_offset.hint) 9176 { 9177 fputs (" ", stderr); 9178 fprintf_vma (stderr, regdeps[depind].mem_offset.base); 9179 fputs ("+", stderr); 9180 fprintf_vma (stderr, regdeps[depind].mem_offset.offset); 9181 } 9182 fprintf (stderr, "\n"); 9183 } 9184} 9185 9186static void 9187instruction_serialization () 9188{ 9189 int i; 9190 if (md.debug_dv) 9191 fprintf (stderr, " Instruction serialization\n"); 9192 for (i = 0; i < regdepslen; i++) 9193 if (regdeps[i].insn_srlz == STATE_STOP) 9194 regdeps[i].insn_srlz = STATE_SRLZ; 9195} 9196 9197static void 9198data_serialization () 9199{ 9200 int i = 0; 9201 if (md.debug_dv) 9202 fprintf (stderr, " Data serialization\n"); 9203 while (i < regdepslen) 9204 { 9205 if (regdeps[i].data_srlz == STATE_STOP 9206 /* Note: as of 991210, all "other" dependencies are cleared by a 9207 data serialization. This might change with new tables */ 9208 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) 9209 { 9210 print_dependency ("Removing", i); 9211 regdeps[i] = regdeps[--regdepslen]; 9212 } 9213 else 9214 ++i; 9215 } 9216} 9217 9218/* Insert stops and serializations as needed to avoid DVs. */ 9219 9220static void 9221remove_marked_resource (rs) 9222 struct rsrc *rs; 9223{ 9224 switch (rs->dependency->semantics) 9225 { 9226 case IA64_DVS_SPECIFIC: 9227 if (md.debug_dv) 9228 fprintf (stderr, "Implementation-specific, assume worst case...\n"); 9229 /* ...fall through... */ 9230 case IA64_DVS_INSTR: 9231 if (md.debug_dv) 9232 fprintf (stderr, "Inserting instr serialization\n"); 9233 if (rs->insn_srlz < STATE_STOP) 9234 insn_group_break (1, 0, 0); 9235 if (rs->insn_srlz < STATE_SRLZ) 9236 { 9237 int oldqp = CURR_SLOT.qp_regno; 9238 struct ia64_opcode *oldidesc = CURR_SLOT.idesc; 9239 /* Manually jam a srlz.i insn into the stream */ 9240 CURR_SLOT.qp_regno = 0; 9241 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); 9242 instruction_serialization (); 9243 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9244 if (++md.num_slots_in_use >= NUM_SLOTS) 9245 emit_one_bundle (); 9246 CURR_SLOT.qp_regno = oldqp; 9247 CURR_SLOT.idesc = oldidesc; 9248 } 9249 insn_group_break (1, 0, 0); 9250 break; 9251 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all 9252 "other" types of DV are eliminated 9253 by a data serialization */ 9254 case IA64_DVS_DATA: 9255 if (md.debug_dv) 9256 fprintf (stderr, "Inserting data serialization\n"); 9257 if (rs->data_srlz < STATE_STOP) 9258 insn_group_break (1, 0, 0); 9259 { 9260 int oldqp = CURR_SLOT.qp_regno; 9261 struct ia64_opcode *oldidesc = CURR_SLOT.idesc; 9262 /* Manually jam a srlz.d insn into the stream */ 9263 CURR_SLOT.qp_regno = 0; 9264 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); 9265 data_serialization (); 9266 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9267 if (++md.num_slots_in_use >= NUM_SLOTS) 9268 emit_one_bundle (); 9269 CURR_SLOT.qp_regno = oldqp; 9270 CURR_SLOT.idesc = oldidesc; 9271 } 9272 break; 9273 case IA64_DVS_IMPLIED: 9274 case IA64_DVS_IMPLIEDF: 9275 if (md.debug_dv) 9276 fprintf (stderr, "Inserting stop\n"); 9277 insn_group_break (1, 0, 0); 9278 break; 9279 default: 9280 break; 9281 } 9282} 9283 9284/* Check the resources used by the given opcode against the current dependency 9285 list. 9286 9287 The check is run once for each execution path encountered. In this case, 9288 a unique execution path is the sequence of instructions following a code 9289 entry point, e.g. the following has three execution paths, one starting 9290 at L0, one at L1, and one at L2. 9291 9292 L0: nop 9293 L1: add 9294 L2: add 9295 br.ret 9296*/ 9297 9298static void 9299check_dependencies (idesc) 9300 struct ia64_opcode *idesc; 9301{ 9302 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 9303 int path; 9304 int i; 9305 9306 /* Note that the number of marked resources may change within the 9307 loop if in auto mode. */ 9308 i = 0; 9309 while (i < regdepslen) 9310 { 9311 struct rsrc *rs = ®deps[i]; 9312 const struct ia64_dependency *dep = rs->dependency; 9313 int chkind; 9314 int note; 9315 int start_over = 0; 9316 9317 if (dep->semantics == IA64_DVS_NONE 9318 || (chkind = depends_on (rs->depind, idesc)) == -1) 9319 { 9320 ++i; 9321 continue; 9322 } 9323 9324 note = NOTE (opdeps->chks[chkind]); 9325 9326 /* Check this resource against each execution path seen thus far. */ 9327 for (path = 0; path <= md.path; path++) 9328 { 9329 int matchtype; 9330 9331 /* If the dependency wasn't on the path being checked, ignore it. */ 9332 if (rs->path < path) 9333 continue; 9334 9335 /* If the QP for this insn implies a QP which has branched, don't 9336 bother checking. Ed. NOTE: I don't think this check is terribly 9337 useful; what's the point of generating code which will only be 9338 reached if its QP is zero? 9339 This code was specifically inserted to handle the following code, 9340 based on notes from Intel's DV checking code, where p1 implies p2. 9341 9342 mov r4 = 2 9343 (p2) br.cond L 9344 (p1) mov r4 = 7 9345 */ 9346 if (CURR_SLOT.qp_regno != 0) 9347 { 9348 int skip = 0; 9349 int implies; 9350 for (implies = 0; implies < qp_implieslen; implies++) 9351 { 9352 if (qp_implies[implies].path >= path 9353 && qp_implies[implies].p1 == CURR_SLOT.qp_regno 9354 && qp_implies[implies].p2_branched) 9355 { 9356 skip = 1; 9357 break; 9358 } 9359 } 9360 if (skip) 9361 continue; 9362 } 9363 9364 if ((matchtype = resources_match (rs, idesc, note, 9365 CURR_SLOT.qp_regno, path)) != 0) 9366 { 9367 char msg[1024]; 9368 char pathmsg[256] = ""; 9369 char indexmsg[256] = ""; 9370 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); 9371 9372 if (path != 0) 9373 sprintf (pathmsg, " when entry is at label '%s'", 9374 md.entry_labels[path - 1]); 9375 if (rs->specific && rs->index != 0) 9376 sprintf (indexmsg, ", specific resource number is %d", 9377 rs->index); 9378 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", 9379 idesc->name, 9380 (certain ? "violates" : "may violate"), 9381 dv_mode[dep->mode], dep->name, 9382 dv_sem[dep->semantics], 9383 pathmsg, indexmsg); 9384 9385 if (md.explicit_mode) 9386 { 9387 as_warn ("%s", msg); 9388 if (path < md.path) 9389 as_warn (_("Only the first path encountering the conflict " 9390 "is reported")); 9391 as_warn_where (rs->file, rs->line, 9392 _("This is the location of the " 9393 "conflicting usage")); 9394 /* Don't bother checking other paths, to avoid duplicating 9395 the same warning */ 9396 break; 9397 } 9398 else 9399 { 9400 if (md.debug_dv) 9401 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); 9402 9403 remove_marked_resource (rs); 9404 9405 /* since the set of dependencies has changed, start over */ 9406 /* FIXME -- since we're removing dvs as we go, we 9407 probably don't really need to start over... */ 9408 start_over = 1; 9409 break; 9410 } 9411 } 9412 } 9413 if (start_over) 9414 i = 0; 9415 else 9416 ++i; 9417 } 9418} 9419 9420/* Register new dependencies based on the given opcode. */ 9421 9422static void 9423mark_resources (idesc) 9424 struct ia64_opcode *idesc; 9425{ 9426 int i; 9427 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 9428 int add_only_qp_reads = 0; 9429 9430 /* A conditional branch only uses its resources if it is taken; if it is 9431 taken, we stop following that path. The other branch types effectively 9432 *always* write their resources. If it's not taken, register only QP 9433 reads. */ 9434 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) 9435 { 9436 add_only_qp_reads = 1; 9437 } 9438 9439 if (md.debug_dv) 9440 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); 9441 9442 for (i = 0; i < opdeps->nregs; i++) 9443 { 9444 const struct ia64_dependency *dep; 9445 struct rsrc specs[MAX_SPECS]; 9446 int note; 9447 int path; 9448 int count; 9449 9450 dep = ia64_find_dependency (opdeps->regs[i]); 9451 note = NOTE (opdeps->regs[i]); 9452 9453 if (add_only_qp_reads 9454 && !(dep->mode == IA64_DV_WAR 9455 && (dep->specifier == IA64_RS_PR 9456 || dep->specifier == IA64_RS_PRr 9457 || dep->specifier == IA64_RS_PR63))) 9458 continue; 9459 9460 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); 9461 9462#if 0 9463 if (md.debug_dv && !count) 9464 fprintf (stderr, " No %s %s usage found (path %d)\n", 9465 dv_mode[dep->mode], dep->name, md.path); 9466#endif 9467 9468 while (count-- > 0) 9469 { 9470 mark_resource (idesc, dep, &specs[count], 9471 DEP (opdeps->regs[i]), md.path); 9472 } 9473 9474 /* The execution path may affect register values, which may in turn 9475 affect which indirect-access resources are accessed. */ 9476 switch (dep->specifier) 9477 { 9478 default: 9479 break; 9480 case IA64_RS_CPUID: 9481 case IA64_RS_DBR: 9482 case IA64_RS_IBR: 9483 case IA64_RS_MSR: 9484 case IA64_RS_PKR: 9485 case IA64_RS_PMC: 9486 case IA64_RS_PMD: 9487 case IA64_RS_RR: 9488 for (path = 0; path < md.path; path++) 9489 { 9490 count = specify_resource (dep, idesc, DV_REG, specs, note, path); 9491 while (count-- > 0) 9492 mark_resource (idesc, dep, &specs[count], 9493 DEP (opdeps->regs[i]), path); 9494 } 9495 break; 9496 } 9497 } 9498} 9499 9500/* Remove dependencies when they no longer apply. */ 9501 9502static void 9503update_dependencies (idesc) 9504 struct ia64_opcode *idesc; 9505{ 9506 int i; 9507 9508 if (strcmp (idesc->name, "srlz.i") == 0) 9509 { 9510 instruction_serialization (); 9511 } 9512 else if (strcmp (idesc->name, "srlz.d") == 0) 9513 { 9514 data_serialization (); 9515 } 9516 else if (is_interruption_or_rfi (idesc) 9517 || is_taken_branch (idesc)) 9518 { 9519 /* Although technically the taken branch doesn't clear dependencies 9520 which require a srlz.[id], we don't follow the branch; the next 9521 instruction is assumed to start with a clean slate. */ 9522 regdepslen = 0; 9523 md.path = 0; 9524 } 9525 else if (is_conditional_branch (idesc) 9526 && CURR_SLOT.qp_regno != 0) 9527 { 9528 int is_call = strstr (idesc->name, ".call") != NULL; 9529 9530 for (i = 0; i < qp_implieslen; i++) 9531 { 9532 /* If the conditional branch's predicate is implied by the predicate 9533 in an existing dependency, remove that dependency. */ 9534 if (qp_implies[i].p2 == CURR_SLOT.qp_regno) 9535 { 9536 int depind = 0; 9537 /* Note that this implied predicate takes a branch so that if 9538 a later insn generates a DV but its predicate implies this 9539 one, we can avoid the false DV warning. */ 9540 qp_implies[i].p2_branched = 1; 9541 while (depind < regdepslen) 9542 { 9543 if (regdeps[depind].qp_regno == qp_implies[i].p1) 9544 { 9545 print_dependency ("Removing", depind); 9546 regdeps[depind] = regdeps[--regdepslen]; 9547 } 9548 else 9549 ++depind; 9550 } 9551 } 9552 } 9553 /* Any marked resources which have this same predicate should be 9554 cleared, provided that the QP hasn't been modified between the 9555 marking instruction and the branch. */ 9556 if (is_call) 9557 { 9558 insn_group_break (0, CURR_SLOT.qp_regno, 1); 9559 } 9560 else 9561 { 9562 i = 0; 9563 while (i < regdepslen) 9564 { 9565 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno 9566 && regdeps[i].link_to_qp_branch 9567 && (regdeps[i].file != CURR_SLOT.src_file 9568 || regdeps[i].line != CURR_SLOT.src_line)) 9569 { 9570 /* Treat like a taken branch */ 9571 print_dependency ("Removing", i); 9572 regdeps[i] = regdeps[--regdepslen]; 9573 } 9574 else 9575 ++i; 9576 } 9577 } 9578 } 9579} 9580 9581/* Examine the current instruction for dependency violations. */ 9582 9583static int 9584check_dv (idesc) 9585 struct ia64_opcode *idesc; 9586{ 9587 if (md.debug_dv) 9588 { 9589 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", 9590 idesc->name, CURR_SLOT.src_line, 9591 idesc->dependencies->nchks, 9592 idesc->dependencies->nregs); 9593 } 9594 9595 /* Look through the list of currently marked resources; if the current 9596 instruction has the dependency in its chks list which uses that resource, 9597 check against the specific resources used. */ 9598 check_dependencies (idesc); 9599 9600 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), 9601 then add them to the list of marked resources. */ 9602 mark_resources (idesc); 9603 9604 /* There are several types of dependency semantics, and each has its own 9605 requirements for being cleared 9606 9607 Instruction serialization (insns separated by interruption, rfi, or 9608 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. 9609 9610 Data serialization (instruction serialization, or writer + srlz.d + 9611 reader, where writer and srlz.d are in separate groups) clears 9612 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to 9613 always be the case). 9614 9615 Instruction group break (groups separated by stop, taken branch, 9616 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. 9617 */ 9618 update_dependencies (idesc); 9619 9620 /* Sometimes, knowing a register value allows us to avoid giving a false DV 9621 warning. Keep track of as many as possible that are useful. */ 9622 note_register_values (idesc); 9623 9624 /* We don't need or want this anymore. */ 9625 md.mem_offset.hint = 0; 9626 9627 return 0; 9628} 9629 9630/* Translate one line of assembly. Pseudo ops and labels do not show 9631 here. */ 9632void 9633md_assemble (str) 9634 char *str; 9635{ 9636 char *saved_input_line_pointer, *mnemonic; 9637 const struct pseudo_opcode *pdesc; 9638 struct ia64_opcode *idesc; 9639 unsigned char qp_regno; 9640 unsigned int flags; 9641 int ch; 9642 9643 saved_input_line_pointer = input_line_pointer; 9644 input_line_pointer = str; 9645 9646 /* extract the opcode (mnemonic): */ 9647 9648 mnemonic = input_line_pointer; 9649 ch = get_symbol_end (); 9650 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); 9651 if (pdesc) 9652 { 9653 *input_line_pointer = ch; 9654 (*pdesc->handler) (pdesc->arg); 9655 goto done; 9656 } 9657 9658 /* Find the instruction descriptor matching the arguments. */ 9659 9660 idesc = ia64_find_opcode (mnemonic); 9661 *input_line_pointer = ch; 9662 if (!idesc) 9663 { 9664 as_bad ("Unknown opcode `%s'", mnemonic); 9665 goto done; 9666 } 9667 9668 idesc = parse_operands (idesc); 9669 if (!idesc) 9670 goto done; 9671 9672 /* Handle the dynamic ops we can handle now: */ 9673 if (idesc->type == IA64_TYPE_DYN) 9674 { 9675 if (strcmp (idesc->name, "add") == 0) 9676 { 9677 if (CURR_SLOT.opnd[2].X_op == O_register 9678 && CURR_SLOT.opnd[2].X_add_number < 4) 9679 mnemonic = "addl"; 9680 else 9681 mnemonic = "adds"; 9682 ia64_free_opcode (idesc); 9683 idesc = ia64_find_opcode (mnemonic); 9684#if 0 9685 know (!idesc->next); 9686#endif 9687 } 9688 else if (strcmp (idesc->name, "mov") == 0) 9689 { 9690 enum ia64_opnd opnd1, opnd2; 9691 int rop; 9692 9693 opnd1 = idesc->operands[0]; 9694 opnd2 = idesc->operands[1]; 9695 if (opnd1 == IA64_OPND_AR3) 9696 rop = 0; 9697 else if (opnd2 == IA64_OPND_AR3) 9698 rop = 1; 9699 else 9700 abort (); 9701 if (CURR_SLOT.opnd[rop].X_op == O_register 9702 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) 9703 mnemonic = "mov.i"; 9704 else 9705 mnemonic = "mov.m"; 9706 ia64_free_opcode (idesc); 9707 idesc = ia64_find_opcode (mnemonic); 9708 while (idesc != NULL 9709 && (idesc->operands[0] != opnd1 9710 || idesc->operands[1] != opnd2)) 9711 idesc = get_next_opcode (idesc); 9712 } 9713 } 9714 9715 qp_regno = 0; 9716 if (md.qp.X_op == O_register) 9717 { 9718 qp_regno = md.qp.X_add_number - REG_P; 9719 md.qp.X_op = O_absent; 9720 } 9721 9722 flags = idesc->flags; 9723 9724 if ((flags & IA64_OPCODE_FIRST) != 0) 9725 insn_group_break (1, 0, 0); 9726 9727 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) 9728 { 9729 as_bad ("`%s' cannot be predicated", idesc->name); 9730 goto done; 9731 } 9732 9733 /* Build the instruction. */ 9734 CURR_SLOT.qp_regno = qp_regno; 9735 CURR_SLOT.idesc = idesc; 9736 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); 9737 dwarf2_where (&CURR_SLOT.debug_line); 9738 9739 /* Add unwind entry, if there is one. */ 9740 if (unwind.current_entry) 9741 { 9742 CURR_SLOT.unwind_record = unwind.current_entry; 9743 unwind.current_entry = NULL; 9744 } 9745 9746 /* Check for dependency violations. */ 9747 if (md.detect_dv) 9748 check_dv (idesc); 9749 9750 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9751 if (++md.num_slots_in_use >= NUM_SLOTS) 9752 emit_one_bundle (); 9753 9754 if ((flags & IA64_OPCODE_LAST) != 0) 9755 insn_group_break (1, 0, 0); 9756 9757 md.last_text_seg = now_seg; 9758 9759 done: 9760 input_line_pointer = saved_input_line_pointer; 9761} 9762 9763/* Called when symbol NAME cannot be found in the symbol table. 9764 Should be used for dynamic valued symbols only. */ 9765 9766symbolS * 9767md_undefined_symbol (name) 9768 char *name ATTRIBUTE_UNUSED; 9769{ 9770 return 0; 9771} 9772 9773/* Called for any expression that can not be recognized. When the 9774 function is called, `input_line_pointer' will point to the start of 9775 the expression. */ 9776 9777void 9778md_operand (e) 9779 expressionS *e; 9780{ 9781 enum pseudo_type pseudo_type; 9782 const char *name; 9783 size_t len; 9784 int ch, i; 9785 9786 switch (*input_line_pointer) 9787 { 9788 case '@': 9789 /* Find what relocation pseudo-function we're dealing with. */ 9790 pseudo_type = 0; 9791 ch = *++input_line_pointer; 9792 for (i = 0; i < NELEMS (pseudo_func); ++i) 9793 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) 9794 { 9795 len = strlen (pseudo_func[i].name); 9796 if (strncmp (pseudo_func[i].name + 1, 9797 input_line_pointer + 1, len - 1) == 0 9798 && !is_part_of_name (input_line_pointer[len])) 9799 { 9800 input_line_pointer += len; 9801 pseudo_type = pseudo_func[i].type; 9802 break; 9803 } 9804 } 9805 switch (pseudo_type) 9806 { 9807 case PSEUDO_FUNC_RELOC: 9808 SKIP_WHITESPACE (); 9809 if (*input_line_pointer != '(') 9810 { 9811 as_bad ("Expected '('"); 9812 goto err; 9813 } 9814 /* Skip '('. */ 9815 ++input_line_pointer; 9816 expression (e); 9817 if (*input_line_pointer++ != ')') 9818 { 9819 as_bad ("Missing ')'"); 9820 goto err; 9821 } 9822 if (e->X_op != O_symbol) 9823 { 9824 if (e->X_op != O_pseudo_fixup) 9825 { 9826 as_bad ("Not a symbolic expression"); 9827 goto err; 9828 } 9829 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE 9830 && i == FUNC_LT_RELATIVE) 9831 i = FUNC_LT_FPTR_RELATIVE; 9832 else 9833 { 9834 as_bad ("Illegal combination of relocation functions"); 9835 goto err; 9836 } 9837 } 9838 /* Make sure gas doesn't get rid of local symbols that are used 9839 in relocs. */ 9840 e->X_op = O_pseudo_fixup; 9841 e->X_op_symbol = pseudo_func[i].u.sym; 9842 break; 9843 9844 case PSEUDO_FUNC_CONST: 9845 e->X_op = O_constant; 9846 e->X_add_number = pseudo_func[i].u.ival; 9847 break; 9848 9849 case PSEUDO_FUNC_REG: 9850 e->X_op = O_register; 9851 e->X_add_number = pseudo_func[i].u.ival; 9852 break; 9853 9854 default: 9855 name = input_line_pointer - 1; 9856 get_symbol_end (); 9857 as_bad ("Unknown pseudo function `%s'", name); 9858 goto err; 9859 } 9860 break; 9861 9862 case '[': 9863 ++input_line_pointer; 9864 expression (e); 9865 if (*input_line_pointer != ']') 9866 { 9867 as_bad ("Closing bracket misssing"); 9868 goto err; 9869 } 9870 else 9871 { 9872 if (e->X_op != O_register) 9873 as_bad ("Register expected as index"); 9874 9875 ++input_line_pointer; 9876 e->X_op = O_index; 9877 } 9878 break; 9879 9880 default: 9881 break; 9882 } 9883 return; 9884 9885 err: 9886 ignore_rest_of_line (); 9887} 9888 9889/* Return 1 if it's OK to adjust a reloc by replacing the symbol with 9890 a section symbol plus some offset. For relocs involving @fptr(), 9891 directives we don't want such adjustments since we need to have the 9892 original symbol's name in the reloc. */ 9893int 9894ia64_fix_adjustable (fix) 9895 fixS *fix; 9896{ 9897 /* Prevent all adjustments to global symbols */ 9898 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) 9899 return 0; 9900 9901 switch (fix->fx_r_type) 9902 { 9903 case BFD_RELOC_IA64_FPTR64I: 9904 case BFD_RELOC_IA64_FPTR32MSB: 9905 case BFD_RELOC_IA64_FPTR32LSB: 9906 case BFD_RELOC_IA64_FPTR64MSB: 9907 case BFD_RELOC_IA64_FPTR64LSB: 9908 case BFD_RELOC_IA64_LTOFF_FPTR22: 9909 case BFD_RELOC_IA64_LTOFF_FPTR64I: 9910 return 0; 9911 default: 9912 break; 9913 } 9914 9915 return 1; 9916} 9917 9918int 9919ia64_force_relocation (fix) 9920 fixS *fix; 9921{ 9922 switch (fix->fx_r_type) 9923 { 9924 case BFD_RELOC_IA64_FPTR64I: 9925 case BFD_RELOC_IA64_FPTR32MSB: 9926 case BFD_RELOC_IA64_FPTR32LSB: 9927 case BFD_RELOC_IA64_FPTR64MSB: 9928 case BFD_RELOC_IA64_FPTR64LSB: 9929 9930 case BFD_RELOC_IA64_LTOFF22: 9931 case BFD_RELOC_IA64_LTOFF64I: 9932 case BFD_RELOC_IA64_LTOFF_FPTR22: 9933 case BFD_RELOC_IA64_LTOFF_FPTR64I: 9934 case BFD_RELOC_IA64_PLTOFF22: 9935 case BFD_RELOC_IA64_PLTOFF64I: 9936 case BFD_RELOC_IA64_PLTOFF64MSB: 9937 case BFD_RELOC_IA64_PLTOFF64LSB: 9938 return 1; 9939 9940 default: 9941 return 0; 9942 } 9943 return 0; 9944} 9945 9946/* Decide from what point a pc-relative relocation is relative to, 9947 relative to the pc-relative fixup. Er, relatively speaking. */ 9948long 9949ia64_pcrel_from_section (fix, sec) 9950 fixS *fix; 9951 segT sec; 9952{ 9953 unsigned long off = fix->fx_frag->fr_address + fix->fx_where; 9954 9955 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) 9956 off &= ~0xfUL; 9957 9958 return off; 9959} 9960 9961/* This is called whenever some data item (not an instruction) needs a 9962 fixup. We pick the right reloc code depending on the byteorder 9963 currently in effect. */ 9964void 9965ia64_cons_fix_new (f, where, nbytes, exp) 9966 fragS *f; 9967 int where; 9968 int nbytes; 9969 expressionS *exp; 9970{ 9971 bfd_reloc_code_real_type code; 9972 fixS *fix; 9973 9974 switch (nbytes) 9975 { 9976 /* There are no reloc for 8 and 16 bit quantities, but we allow 9977 them here since they will work fine as long as the expression 9978 is fully defined at the end of the pass over the source file. */ 9979 case 1: code = BFD_RELOC_8; break; 9980 case 2: code = BFD_RELOC_16; break; 9981 case 4: 9982 if (target_big_endian) 9983 code = BFD_RELOC_IA64_DIR32MSB; 9984 else 9985 code = BFD_RELOC_IA64_DIR32LSB; 9986 break; 9987 9988 case 8: 9989 /* In 32-bit mode, data8 could mean function descriptors too. */ 9990 if (exp->X_op == O_pseudo_fixup 9991 && exp->X_op_symbol 9992 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC 9993 && !(md.flags & EF_IA_64_ABI64)) 9994 { 9995 if (target_big_endian) 9996 code = BFD_RELOC_IA64_IPLTMSB; 9997 else 9998 code = BFD_RELOC_IA64_IPLTLSB; 9999 exp->X_op = O_symbol; 10000 break; 10001 } 10002 else { 10003 if (target_big_endian) 10004 code = BFD_RELOC_IA64_DIR64MSB; 10005 else 10006 code = BFD_RELOC_IA64_DIR64LSB; 10007 break; 10008 } 10009 10010 case 16: 10011 if (exp->X_op == O_pseudo_fixup 10012 && exp->X_op_symbol 10013 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC) 10014 { 10015 if (target_big_endian) 10016 code = BFD_RELOC_IA64_IPLTMSB; 10017 else 10018 code = BFD_RELOC_IA64_IPLTLSB; 10019 10020 exp->X_op = O_symbol; 10021 break; 10022 } 10023 /* FALLTHRU */ 10024 10025 default: 10026 as_bad ("Unsupported fixup size %d", nbytes); 10027 ignore_rest_of_line (); 10028 return; 10029 } 10030 if (exp->X_op == O_pseudo_fixup) 10031 { 10032 /* ??? */ 10033 exp->X_op = O_symbol; 10034 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); 10035 } 10036 10037 fix = fix_new_exp (f, where, nbytes, exp, 0, code); 10038 /* We need to store the byte order in effect in case we're going 10039 to fix an 8 or 16 bit relocation (for which there no real 10040 relocs available). See md_apply_fix3(). */ 10041 fix->tc_fix_data.bigendian = target_big_endian; 10042} 10043 10044/* Return the actual relocation we wish to associate with the pseudo 10045 reloc described by SYM and R_TYPE. SYM should be one of the 10046 symbols in the pseudo_func array, or NULL. */ 10047 10048static bfd_reloc_code_real_type 10049ia64_gen_real_reloc_type (sym, r_type) 10050 struct symbol *sym; 10051 bfd_reloc_code_real_type r_type; 10052{ 10053 bfd_reloc_code_real_type new = 0; 10054 10055 if (sym == NULL) 10056 { 10057 return r_type; 10058 } 10059 10060 switch (S_GET_VALUE (sym)) 10061 { 10062 case FUNC_FPTR_RELATIVE: 10063 switch (r_type) 10064 { 10065 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; 10066 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; 10067 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; 10068 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; 10069 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; 10070 default: break; 10071 } 10072 break; 10073 10074 case FUNC_GP_RELATIVE: 10075 switch (r_type) 10076 { 10077 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; 10078 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; 10079 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; 10080 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; 10081 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; 10082 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; 10083 default: break; 10084 } 10085 break; 10086 10087 case FUNC_LT_RELATIVE: 10088 switch (r_type) 10089 { 10090 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; 10091 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; 10092 default: break; 10093 } 10094 break; 10095 10096 case FUNC_PC_RELATIVE: 10097 switch (r_type) 10098 { 10099 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; 10100 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; 10101 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; 10102 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; 10103 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; 10104 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; 10105 default: break; 10106 } 10107 break; 10108 10109 case FUNC_PLT_RELATIVE: 10110 switch (r_type) 10111 { 10112 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; 10113 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; 10114 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; 10115 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; 10116 default: break; 10117 } 10118 break; 10119 10120 case FUNC_SEC_RELATIVE: 10121 switch (r_type) 10122 { 10123 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; 10124 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; 10125 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; 10126 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; 10127 default: break; 10128 } 10129 break; 10130 10131 case FUNC_SEG_RELATIVE: 10132 switch (r_type) 10133 { 10134 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; 10135 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; 10136 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; 10137 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; 10138 default: break; 10139 } 10140 break; 10141 10142 case FUNC_LTV_RELATIVE: 10143 switch (r_type) 10144 { 10145 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; 10146 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; 10147 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; 10148 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; 10149 default: break; 10150 } 10151 break; 10152 10153 case FUNC_LT_FPTR_RELATIVE: 10154 switch (r_type) 10155 { 10156 case BFD_RELOC_IA64_IMM22: 10157 new = BFD_RELOC_IA64_LTOFF_FPTR22; break; 10158 case BFD_RELOC_IA64_IMM64: 10159 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; 10160 default: 10161 break; 10162 } 10163 break; 10164 10165 case FUNC_IPLT_RELOC: 10166 break; 10167 10168 default: 10169 abort (); 10170 } 10171 /* Hmmmm. Should this ever occur? */ 10172 if (new) 10173 return new; 10174 else 10175 return r_type; 10176} 10177 10178/* Here is where generate the appropriate reloc for pseudo relocation 10179 functions. */ 10180void 10181ia64_validate_fix (fix) 10182 fixS *fix; 10183{ 10184 switch (fix->fx_r_type) 10185 { 10186 case BFD_RELOC_IA64_FPTR64I: 10187 case BFD_RELOC_IA64_FPTR32MSB: 10188 case BFD_RELOC_IA64_FPTR64LSB: 10189 case BFD_RELOC_IA64_LTOFF_FPTR22: 10190 case BFD_RELOC_IA64_LTOFF_FPTR64I: 10191 if (fix->fx_offset != 0) 10192 as_bad_where (fix->fx_file, fix->fx_line, 10193 "No addend allowed in @fptr() relocation"); 10194 break; 10195 default: 10196 break; 10197 } 10198 10199 return; 10200} 10201 10202static void 10203fix_insn (fix, odesc, value) 10204 fixS *fix; 10205 const struct ia64_operand *odesc; 10206 valueT value; 10207{ 10208 bfd_vma insn[3], t0, t1, control_bits; 10209 const char *err; 10210 char *fixpos; 10211 long slot; 10212 10213 slot = fix->fx_where & 0x3; 10214 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); 10215 10216 /* Bundles are always in little-endian byte order */ 10217 t0 = bfd_getl64 (fixpos); 10218 t1 = bfd_getl64 (fixpos + 8); 10219 control_bits = t0 & 0x1f; 10220 insn[0] = (t0 >> 5) & 0x1ffffffffffLL; 10221 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); 10222 insn[2] = (t1 >> 23) & 0x1ffffffffffLL; 10223 10224 err = NULL; 10225 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) 10226 { 10227 insn[1] = (value >> 22) & 0x1ffffffffffLL; 10228 insn[2] |= (((value & 0x7f) << 13) 10229 | (((value >> 7) & 0x1ff) << 27) 10230 | (((value >> 16) & 0x1f) << 22) 10231 | (((value >> 21) & 0x1) << 21) 10232 | (((value >> 63) & 0x1) << 36)); 10233 } 10234 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) 10235 { 10236 if (value & ~0x3fffffffffffffffULL) 10237 err = "integer operand out of range"; 10238 insn[1] = (value >> 21) & 0x1ffffffffffLL; 10239 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); 10240 } 10241 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) 10242 { 10243 value >>= 4; 10244 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; 10245 insn[2] |= ((((value >> 59) & 0x1) << 36) 10246 | (((value >> 0) & 0xfffff) << 13)); 10247 } 10248 else 10249 err = (*odesc->insert) (odesc, value, insn + slot); 10250 10251 if (err) 10252 as_bad_where (fix->fx_file, fix->fx_line, err); 10253 10254 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); 10255 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 10256 number_to_chars_littleendian (fixpos + 0, t0, 8); 10257 number_to_chars_littleendian (fixpos + 8, t1, 8); 10258} 10259 10260/* Attempt to simplify or even eliminate a fixup. The return value is 10261 ignored; perhaps it was once meaningful, but now it is historical. 10262 To indicate that a fixup has been eliminated, set FIXP->FX_DONE. 10263 10264 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry 10265 (if possible). */ 10266 10267void 10268md_apply_fix3 (fix, valP, seg) 10269 fixS *fix; 10270 valueT * valP; 10271 segT seg ATTRIBUTE_UNUSED; 10272{ 10273 char *fixpos; 10274 valueT value = * valP; 10275 int adjust = 0; 10276 10277 fixpos = fix->fx_frag->fr_literal + fix->fx_where; 10278 10279 if (fix->fx_pcrel) 10280 { 10281 switch (fix->fx_r_type) 10282 { 10283 case BFD_RELOC_IA64_DIR32MSB: 10284 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; 10285 adjust = 1; 10286 break; 10287 10288 case BFD_RELOC_IA64_DIR32LSB: 10289 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; 10290 adjust = 1; 10291 break; 10292 10293 case BFD_RELOC_IA64_DIR64MSB: 10294 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; 10295 adjust = 1; 10296 break; 10297 10298 case BFD_RELOC_IA64_DIR64LSB: 10299 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; 10300 adjust = 1; 10301 break; 10302 10303 default: 10304 break; 10305 } 10306 } 10307 if (fix->fx_addsy) 10308 { 10309 if (fix->fx_r_type == (int) BFD_RELOC_UNUSED) 10310 { 10311 /* This must be a TAG13 or TAG13b operand. There are no external 10312 relocs defined for them, so we must give an error. */ 10313 as_bad_where (fix->fx_file, fix->fx_line, 10314 "%s must have a constant value", 10315 elf64_ia64_operands[fix->tc_fix_data.opnd].desc); 10316 fix->fx_done = 1; 10317 return; 10318 } 10319 10320 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs 10321 work. There should be a better way to handle this. */ 10322 if (adjust) 10323 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; 10324 } 10325 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) 10326 { 10327 if (fix->tc_fix_data.bigendian) 10328 number_to_chars_bigendian (fixpos, value, fix->fx_size); 10329 else 10330 number_to_chars_littleendian (fixpos, value, fix->fx_size); 10331 fix->fx_done = 1; 10332 } 10333 else 10334 { 10335 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); 10336 fix->fx_done = 1; 10337 } 10338} 10339 10340/* Generate the BFD reloc to be stuck in the object file from the 10341 fixup used internally in the assembler. */ 10342 10343arelent * 10344tc_gen_reloc (sec, fixp) 10345 asection *sec ATTRIBUTE_UNUSED; 10346 fixS *fixp; 10347{ 10348 arelent *reloc; 10349 10350 reloc = xmalloc (sizeof (*reloc)); 10351 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 10352 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 10353 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 10354 reloc->addend = fixp->fx_offset; 10355 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 10356 10357 if (!reloc->howto) 10358 { 10359 as_bad_where (fixp->fx_file, fixp->fx_line, 10360 "Cannot represent %s relocation in object file", 10361 bfd_get_reloc_code_name (fixp->fx_r_type)); 10362 } 10363 return reloc; 10364} 10365 10366/* Turn a string in input_line_pointer into a floating point constant 10367 of type TYPE, and store the appropriate bytes in *LIT. The number 10368 of LITTLENUMS emitted is stored in *SIZE. An error message is 10369 returned, or NULL on OK. */ 10370 10371#define MAX_LITTLENUMS 5 10372 10373char * 10374md_atof (type, lit, size) 10375 int type; 10376 char *lit; 10377 int *size; 10378{ 10379 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 10380 LITTLENUM_TYPE *word; 10381 char *t; 10382 int prec; 10383 10384 switch (type) 10385 { 10386 /* IEEE floats */ 10387 case 'f': 10388 case 'F': 10389 case 's': 10390 case 'S': 10391 prec = 2; 10392 break; 10393 10394 case 'd': 10395 case 'D': 10396 case 'r': 10397 case 'R': 10398 prec = 4; 10399 break; 10400 10401 case 'x': 10402 case 'X': 10403 case 'p': 10404 case 'P': 10405 prec = 5; 10406 break; 10407 10408 default: 10409 *size = 0; 10410 return "Bad call to MD_ATOF()"; 10411 } 10412 t = atof_ieee (input_line_pointer, type, words); 10413 if (t) 10414 input_line_pointer = t; 10415 *size = prec * sizeof (LITTLENUM_TYPE); 10416 10417 for (word = words + prec - 1; prec--;) 10418 { 10419 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); 10420 lit += sizeof (LITTLENUM_TYPE); 10421 } 10422 return 0; 10423} 10424 10425/* Round up a section's size to the appropriate boundary. */ 10426valueT 10427md_section_align (seg, size) 10428 segT seg; 10429 valueT size; 10430{ 10431 int align = bfd_get_section_alignment (stdoutput, seg); 10432 valueT mask = ((valueT) 1 << align) - 1; 10433 10434 return (size + mask) & ~mask; 10435} 10436 10437/* Handle ia64 specific semantics of the align directive. */ 10438 10439void 10440ia64_md_do_align (n, fill, len, max) 10441 int n ATTRIBUTE_UNUSED; 10442 const char *fill ATTRIBUTE_UNUSED; 10443 int len ATTRIBUTE_UNUSED; 10444 int max ATTRIBUTE_UNUSED; 10445{ 10446 if (subseg_text_p (now_seg)) 10447 ia64_flush_insns (); 10448} 10449 10450/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 10451 of an rs_align_code fragment. */ 10452 10453void 10454ia64_handle_align (fragp) 10455 fragS *fragp; 10456{ 10457 /* Use mfi bundle of nops with no stop bits. */ 10458 static const unsigned char be_nop[] 10459 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 10460 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; 10461 static const unsigned char le_nop[] 10462 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 10463 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; 10464 10465 int bytes; 10466 char *p; 10467 10468 if (fragp->fr_type != rs_align_code) 10469 return; 10470 10471 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 10472 p = fragp->fr_literal + fragp->fr_fix; 10473 10474 /* Make sure we are on a 16-byte boundary, in case someone has been 10475 putting data into a text section. */ 10476 if (bytes & 15) 10477 { 10478 int fix = bytes & 15; 10479 memset (p, 0, fix); 10480 p += fix; 10481 bytes -= fix; 10482 fragp->fr_fix += fix; 10483 } 10484 10485 memcpy (p, (target_big_endian ? be_nop : le_nop), 16); 10486 fragp->fr_var = 16; 10487} 10488