tc-ia64.c revision 92828
1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. 2 Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22/* 23 TODO: 24 25 - optional operands 26 - directives: 27 .alias 28 .eb 29 .estate 30 .lb 31 .popsection 32 .previous 33 .psr 34 .pushsection 35 - labels are wrong if automatic alignment is introduced 36 (e.g., checkout the second real10 definition in test-data.s) 37 - DV-related stuff: 38 <reg>.safe_across_calls and any other DV-related directives I don't 39 have documentation for. 40 verify mod-sched-brs reads/writes are checked/marked (and other 41 notes) 42 43 */ 44 45#include "as.h" 46#include "safe-ctype.h" 47#include "dwarf2dbg.h" 48#include "subsegs.h" 49 50#include "opcode/ia64.h" 51 52#include "elf/ia64.h" 53 54#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) 55#define MIN(a,b) ((a) < (b) ? (a) : (b)) 56 57#define NUM_SLOTS 4 58#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] 59#define CURR_SLOT md.slot[md.curr_slot] 60 61#define O_pseudo_fixup (O_max + 1) 62 63enum special_section 64 { 65 /* IA-64 ABI section pseudo-ops. */ 66 SPECIAL_SECTION_BSS = 0, 67 SPECIAL_SECTION_SBSS, 68 SPECIAL_SECTION_SDATA, 69 SPECIAL_SECTION_RODATA, 70 SPECIAL_SECTION_COMMENT, 71 SPECIAL_SECTION_UNWIND, 72 SPECIAL_SECTION_UNWIND_INFO, 73 /* HPUX specific section pseudo-ops. */ 74 SPECIAL_SECTION_INIT_ARRAY, 75 SPECIAL_SECTION_FINI_ARRAY, 76 }; 77 78enum reloc_func 79 { 80 FUNC_FPTR_RELATIVE, 81 FUNC_GP_RELATIVE, 82 FUNC_LT_RELATIVE, 83 FUNC_PC_RELATIVE, 84 FUNC_PLT_RELATIVE, 85 FUNC_SEC_RELATIVE, 86 FUNC_SEG_RELATIVE, 87 FUNC_LTV_RELATIVE, 88 FUNC_LT_FPTR_RELATIVE, 89 FUNC_IPLT_RELOC, 90 }; 91 92enum reg_symbol 93 { 94 REG_GR = 0, 95 REG_FR = (REG_GR + 128), 96 REG_AR = (REG_FR + 128), 97 REG_CR = (REG_AR + 128), 98 REG_P = (REG_CR + 128), 99 REG_BR = (REG_P + 64), 100 REG_IP = (REG_BR + 8), 101 REG_CFM, 102 REG_PR, 103 REG_PR_ROT, 104 REG_PSR, 105 REG_PSR_L, 106 REG_PSR_UM, 107 /* The following are pseudo-registers for use by gas only. */ 108 IND_CPUID, 109 IND_DBR, 110 IND_DTR, 111 IND_ITR, 112 IND_IBR, 113 IND_MEM, 114 IND_MSR, 115 IND_PKR, 116 IND_PMC, 117 IND_PMD, 118 IND_RR, 119 /* The following pseudo-registers are used for unwind directives only: */ 120 REG_PSP, 121 REG_PRIUNAT, 122 REG_NUM 123 }; 124 125enum dynreg_type 126 { 127 DYNREG_GR = 0, /* dynamic general purpose register */ 128 DYNREG_FR, /* dynamic floating point register */ 129 DYNREG_PR, /* dynamic predicate register */ 130 DYNREG_NUM_TYPES 131 }; 132 133enum operand_match_result 134 { 135 OPERAND_MATCH, 136 OPERAND_OUT_OF_RANGE, 137 OPERAND_MISMATCH 138 }; 139 140/* On the ia64, we can't know the address of a text label until the 141 instructions are packed into a bundle. To handle this, we keep 142 track of the list of labels that appear in front of each 143 instruction. */ 144struct label_fix 145{ 146 struct label_fix *next; 147 struct symbol *sym; 148}; 149 150extern int target_big_endian; 151 152/* Characters which always start a comment. */ 153const char comment_chars[] = ""; 154 155/* Characters which start a comment at the beginning of a line. */ 156const char line_comment_chars[] = "#"; 157 158/* Characters which may be used to separate multiple commands on a 159 single line. */ 160const char line_separator_chars[] = ";"; 161 162/* Characters which are used to indicate an exponent in a floating 163 point number. */ 164const char EXP_CHARS[] = "eE"; 165 166/* Characters which mean that a number is a floating point constant, 167 as in 0d1.0. */ 168const char FLT_CHARS[] = "rRsSfFdDxXpP"; 169 170/* ia64-specific option processing: */ 171 172const char *md_shortopts = "m:N:x::"; 173 174struct option md_longopts[] = 175 { 176#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) 177 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, 178#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) 179 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} 180 }; 181 182size_t md_longopts_size = sizeof (md_longopts); 183 184static struct 185 { 186 struct hash_control *pseudo_hash; /* pseudo opcode hash table */ 187 struct hash_control *reg_hash; /* register name hash table */ 188 struct hash_control *dynreg_hash; /* dynamic register hash table */ 189 struct hash_control *const_hash; /* constant hash table */ 190 struct hash_control *entry_hash; /* code entry hint hash table */ 191 192 symbolS *regsym[REG_NUM]; 193 194 /* If X_op is != O_absent, the registername for the instruction's 195 qualifying predicate. If NULL, p0 is assumed for instructions 196 that are predicatable. */ 197 expressionS qp; 198 199 unsigned int 200 manual_bundling : 1, 201 debug_dv: 1, 202 detect_dv: 1, 203 explicit_mode : 1, /* which mode we're in */ 204 default_explicit_mode : 1, /* which mode is the default */ 205 mode_explicitly_set : 1, /* was the current mode explicitly set? */ 206 auto_align : 1, 207 keep_pending_output : 1; 208 209 /* Each bundle consists of up to three instructions. We keep 210 track of four most recent instructions so we can correctly set 211 the end_of_insn_group for the last instruction in a bundle. */ 212 int curr_slot; 213 int num_slots_in_use; 214 struct slot 215 { 216 unsigned int 217 end_of_insn_group : 1, 218 manual_bundling_on : 1, 219 manual_bundling_off : 1; 220 signed char user_template; /* user-selected template, if any */ 221 unsigned char qp_regno; /* qualifying predicate */ 222 /* This duplicates a good fraction of "struct fix" but we 223 can't use a "struct fix" instead since we can't call 224 fix_new_exp() until we know the address of the instruction. */ 225 int num_fixups; 226 struct insn_fix 227 { 228 bfd_reloc_code_real_type code; 229 enum ia64_opnd opnd; /* type of operand in need of fix */ 230 unsigned int is_pcrel : 1; /* is operand pc-relative? */ 231 expressionS expr; /* the value to be inserted */ 232 } 233 fixup[2]; /* at most two fixups per insn */ 234 struct ia64_opcode *idesc; 235 struct label_fix *label_fixups; 236 struct label_fix *tag_fixups; 237 struct unw_rec_list *unwind_record; /* Unwind directive. */ 238 expressionS opnd[6]; 239 char *src_file; 240 unsigned int src_line; 241 struct dwarf2_line_info debug_line; 242 } 243 slot[NUM_SLOTS]; 244 245 segT last_text_seg; 246 247 struct dynreg 248 { 249 struct dynreg *next; /* next dynamic register */ 250 const char *name; 251 unsigned short base; /* the base register number */ 252 unsigned short num_regs; /* # of registers in this set */ 253 } 254 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; 255 256 flagword flags; /* ELF-header flags */ 257 258 struct mem_offset { 259 unsigned hint:1; /* is this hint currently valid? */ 260 bfd_vma offset; /* mem.offset offset */ 261 bfd_vma base; /* mem.offset base */ 262 } mem_offset; 263 264 int path; /* number of alt. entry points seen */ 265 const char **entry_labels; /* labels of all alternate paths in 266 the current DV-checking block. */ 267 int maxpaths; /* size currently allocated for 268 entry_labels */ 269 /* Support for hardware errata workarounds. */ 270 271 /* Record data about the last three insn groups. */ 272 struct group 273 { 274 /* B-step workaround. 275 For each predicate register, this is set if the corresponding insn 276 group conditionally sets this register with one of the affected 277 instructions. */ 278 int p_reg_set[64]; 279 /* B-step workaround. 280 For each general register, this is set if the corresponding insn 281 a) is conditional one one of the predicate registers for which 282 P_REG_SET is 1 in the corresponding entry of the previous group, 283 b) sets this general register with one of the affected 284 instructions. */ 285 int g_reg_set_conditionally[128]; 286 } last_groups[3]; 287 int group_idx; 288 289 int pointer_size; /* size in bytes of a pointer */ 290 int pointer_size_shift; /* shift size of a pointer for alignment */ 291 } 292md; 293 294/* application registers: */ 295 296#define AR_K0 0 297#define AR_K7 7 298#define AR_RSC 16 299#define AR_BSP 17 300#define AR_BSPSTORE 18 301#define AR_RNAT 19 302#define AR_UNAT 36 303#define AR_FPSR 40 304#define AR_ITC 44 305#define AR_PFS 64 306#define AR_LC 65 307 308static const struct 309 { 310 const char *name; 311 int regnum; 312 } 313ar[] = 314 { 315 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, 316 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, 317 {"ar.rsc", 16}, {"ar.bsp", 17}, 318 {"ar.bspstore", 18}, {"ar.rnat", 19}, 319 {"ar.fcr", 21}, {"ar.eflag", 24}, 320 {"ar.csd", 25}, {"ar.ssd", 26}, 321 {"ar.cflg", 27}, {"ar.fsr", 28}, 322 {"ar.fir", 29}, {"ar.fdr", 30}, 323 {"ar.ccv", 32}, {"ar.unat", 36}, 324 {"ar.fpsr", 40}, {"ar.itc", 44}, 325 {"ar.pfs", 64}, {"ar.lc", 65}, 326 {"ar.ec", 66}, 327 }; 328 329#define CR_IPSR 16 330#define CR_ISR 17 331#define CR_IIP 19 332#define CR_IFA 20 333#define CR_ITIR 21 334#define CR_IIPA 22 335#define CR_IFS 23 336#define CR_IIM 24 337#define CR_IHA 25 338#define CR_IVR 65 339#define CR_TPR 66 340#define CR_EOI 67 341#define CR_IRR0 68 342#define CR_IRR3 71 343#define CR_LRR0 80 344#define CR_LRR1 81 345 346/* control registers: */ 347static const struct 348 { 349 const char *name; 350 int regnum; 351 } 352cr[] = 353 { 354 {"cr.dcr", 0}, 355 {"cr.itm", 1}, 356 {"cr.iva", 2}, 357 {"cr.pta", 8}, 358 {"cr.gpta", 9}, 359 {"cr.ipsr", 16}, 360 {"cr.isr", 17}, 361 {"cr.iip", 19}, 362 {"cr.ifa", 20}, 363 {"cr.itir", 21}, 364 {"cr.iipa", 22}, 365 {"cr.ifs", 23}, 366 {"cr.iim", 24}, 367 {"cr.iha", 25}, 368 {"cr.lid", 64}, 369 {"cr.ivr", 65}, 370 {"cr.tpr", 66}, 371 {"cr.eoi", 67}, 372 {"cr.irr0", 68}, 373 {"cr.irr1", 69}, 374 {"cr.irr2", 70}, 375 {"cr.irr3", 71}, 376 {"cr.itv", 72}, 377 {"cr.pmv", 73}, 378 {"cr.cmcv", 74}, 379 {"cr.lrr0", 80}, 380 {"cr.lrr1", 81} 381 }; 382 383#define PSR_MFL 4 384#define PSR_IC 13 385#define PSR_DFL 18 386#define PSR_CPL 32 387 388static const struct const_desc 389 { 390 const char *name; 391 valueT value; 392 } 393const_bits[] = 394 { 395 /* PSR constant masks: */ 396 397 /* 0: reserved */ 398 {"psr.be", ((valueT) 1) << 1}, 399 {"psr.up", ((valueT) 1) << 2}, 400 {"psr.ac", ((valueT) 1) << 3}, 401 {"psr.mfl", ((valueT) 1) << 4}, 402 {"psr.mfh", ((valueT) 1) << 5}, 403 /* 6-12: reserved */ 404 {"psr.ic", ((valueT) 1) << 13}, 405 {"psr.i", ((valueT) 1) << 14}, 406 {"psr.pk", ((valueT) 1) << 15}, 407 /* 16: reserved */ 408 {"psr.dt", ((valueT) 1) << 17}, 409 {"psr.dfl", ((valueT) 1) << 18}, 410 {"psr.dfh", ((valueT) 1) << 19}, 411 {"psr.sp", ((valueT) 1) << 20}, 412 {"psr.pp", ((valueT) 1) << 21}, 413 {"psr.di", ((valueT) 1) << 22}, 414 {"psr.si", ((valueT) 1) << 23}, 415 {"psr.db", ((valueT) 1) << 24}, 416 {"psr.lp", ((valueT) 1) << 25}, 417 {"psr.tb", ((valueT) 1) << 26}, 418 {"psr.rt", ((valueT) 1) << 27}, 419 /* 28-31: reserved */ 420 /* 32-33: cpl (current privilege level) */ 421 {"psr.is", ((valueT) 1) << 34}, 422 {"psr.mc", ((valueT) 1) << 35}, 423 {"psr.it", ((valueT) 1) << 36}, 424 {"psr.id", ((valueT) 1) << 37}, 425 {"psr.da", ((valueT) 1) << 38}, 426 {"psr.dd", ((valueT) 1) << 39}, 427 {"psr.ss", ((valueT) 1) << 40}, 428 /* 41-42: ri (restart instruction) */ 429 {"psr.ed", ((valueT) 1) << 43}, 430 {"psr.bn", ((valueT) 1) << 44}, 431 }; 432 433/* indirect register-sets/memory: */ 434 435static const struct 436 { 437 const char *name; 438 int regnum; 439 } 440indirect_reg[] = 441 { 442 { "CPUID", IND_CPUID }, 443 { "cpuid", IND_CPUID }, 444 { "dbr", IND_DBR }, 445 { "dtr", IND_DTR }, 446 { "itr", IND_ITR }, 447 { "ibr", IND_IBR }, 448 { "msr", IND_MSR }, 449 { "pkr", IND_PKR }, 450 { "pmc", IND_PMC }, 451 { "pmd", IND_PMD }, 452 { "rr", IND_RR }, 453 }; 454 455/* Pseudo functions used to indicate relocation types (these functions 456 start with an at sign (@). */ 457static struct 458 { 459 const char *name; 460 enum pseudo_type 461 { 462 PSEUDO_FUNC_NONE, 463 PSEUDO_FUNC_RELOC, 464 PSEUDO_FUNC_CONST, 465 PSEUDO_FUNC_REG, 466 PSEUDO_FUNC_FLOAT 467 } 468 type; 469 union 470 { 471 unsigned long ival; 472 symbolS *sym; 473 } 474 u; 475 } 476pseudo_func[] = 477 { 478 /* reloc pseudo functions (these must come first!): */ 479 { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, 480 { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, 481 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, 482 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, 483 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, 484 { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, 485 { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, 486 { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, 487 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ 488 { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, 489 490 /* mbtype4 constants: */ 491 { "alt", PSEUDO_FUNC_CONST, { 0xa } }, 492 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, 493 { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, 494 { "rev", PSEUDO_FUNC_CONST, { 0xb } }, 495 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, 496 497 /* fclass constants: */ 498 { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, 499 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, 500 { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, 501 { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, 502 { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, 503 { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, 504 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, 505 { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, 506 { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, 507 508 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ 509 510 /* unwind-related constants: */ 511 { "svr4", PSEUDO_FUNC_CONST, { 0 } }, 512 { "hpux", PSEUDO_FUNC_CONST, { 1 } }, 513 { "nt", PSEUDO_FUNC_CONST, { 2 } }, 514 515 /* unwind-related registers: */ 516 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } 517 }; 518 519/* 41-bit nop opcodes (one per unit): */ 520static const bfd_vma nop[IA64_NUM_UNITS] = 521 { 522 0x0000000000LL, /* NIL => break 0 */ 523 0x0008000000LL, /* I-unit nop */ 524 0x0008000000LL, /* M-unit nop */ 525 0x4000000000LL, /* B-unit nop */ 526 0x0008000000LL, /* F-unit nop */ 527 0x0008000000LL, /* L-"unit" nop */ 528 0x0008000000LL, /* X-unit nop */ 529 }; 530 531/* Can't be `const' as it's passed to input routines (which have the 532 habit of setting temporary sentinels. */ 533static char special_section_name[][20] = 534 { 535 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, 536 {".IA_64.unwind"}, {".IA_64.unwind_info"}, 537 {".init_array"}, {".fini_array"} 538 }; 539 540static char *special_linkonce_name[] = 541 { 542 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." 543 }; 544 545/* The best template for a particular sequence of up to three 546 instructions: */ 547#define N IA64_NUM_TYPES 548static unsigned char best_template[N][N][N]; 549#undef N 550 551/* Resource dependencies currently in effect */ 552static struct rsrc { 553 int depind; /* dependency index */ 554 const struct ia64_dependency *dependency; /* actual dependency */ 555 unsigned specific:1, /* is this a specific bit/regno? */ 556 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ 557 int index; /* specific regno/bit within dependency */ 558 int note; /* optional qualifying note (0 if none) */ 559#define STATE_NONE 0 560#define STATE_STOP 1 561#define STATE_SRLZ 2 562 int insn_srlz; /* current insn serialization state */ 563 int data_srlz; /* current data serialization state */ 564 int qp_regno; /* qualifying predicate for this usage */ 565 char *file; /* what file marked this dependency */ 566 unsigned int line; /* what line marked this dependency */ 567 struct mem_offset mem_offset; /* optional memory offset hint */ 568 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ 569 int path; /* corresponding code entry index */ 570} *regdeps = NULL; 571static int regdepslen = 0; 572static int regdepstotlen = 0; 573static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; 574static const char *dv_sem[] = { "none", "implied", "impliedf", 575 "data", "instr", "specific", "stop", "other" }; 576static const char *dv_cmp_type[] = { "none", "OR", "AND" }; 577 578/* Current state of PR mutexation */ 579static struct qpmutex { 580 valueT prmask; 581 int path; 582} *qp_mutexes = NULL; /* QP mutex bitmasks */ 583static int qp_mutexeslen = 0; 584static int qp_mutexestotlen = 0; 585static valueT qp_safe_across_calls = 0; 586 587/* Current state of PR implications */ 588static struct qp_imply { 589 unsigned p1:6; 590 unsigned p2:6; 591 unsigned p2_branched:1; 592 int path; 593} *qp_implies = NULL; 594static int qp_implieslen = 0; 595static int qp_impliestotlen = 0; 596 597/* Keep track of static GR values so that indirect register usage can 598 sometimes be tracked. */ 599static struct gr { 600 unsigned known:1; 601 int path; 602 valueT value; 603} gr_values[128] = {{ 1, 0, 0 }}; 604 605/* These are the routines required to output the various types of 606 unwind records. */ 607 608/* A slot_number is a frag address plus the slot index (0-2). We use the 609 frag address here so that if there is a section switch in the middle of 610 a function, then instructions emitted to a different section are not 611 counted. Since there may be more than one frag for a function, this 612 means we also need to keep track of which frag this address belongs to 613 so we can compute inter-frag distances. This also nicely solves the 614 problem with nops emitted for align directives, which can't easily be 615 counted, but can easily be derived from frag sizes. */ 616 617typedef struct unw_rec_list { 618 unwind_record r; 619 unsigned long slot_number; 620 fragS *slot_frag; 621 struct unw_rec_list *next; 622} unw_rec_list; 623 624#define SLOT_NUM_NOT_SET (unsigned)-1 625 626/* Linked list of saved prologue counts. A very poor 627 implementation of a map from label numbers to prologue counts. */ 628typedef struct label_prologue_count 629{ 630 struct label_prologue_count *next; 631 unsigned long label_number; 632 unsigned int prologue_count; 633} label_prologue_count; 634 635static struct 636{ 637 unsigned long next_slot_number; 638 fragS *next_slot_frag; 639 640 /* Maintain a list of unwind entries for the current function. */ 641 unw_rec_list *list; 642 unw_rec_list *tail; 643 644 /* Any unwind entires that should be attached to the current slot 645 that an insn is being constructed for. */ 646 unw_rec_list *current_entry; 647 648 /* These are used to create the unwind table entry for this function. */ 649 symbolS *proc_start; 650 symbolS *proc_end; 651 symbolS *info; /* pointer to unwind info */ 652 symbolS *personality_routine; 653 segT saved_text_seg; 654 subsegT saved_text_subseg; 655 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ 656 657 /* TRUE if processing unwind directives in a prologue region. */ 658 int prologue; 659 int prologue_mask; 660 unsigned int prologue_count; /* number of .prologues seen so far */ 661 /* Prologue counts at previous .label_state directives. */ 662 struct label_prologue_count * saved_prologue_counts; 663} unwind; 664 665typedef void (*vbyte_func) PARAMS ((int, char *, char *)); 666 667/* Forward delarations: */ 668static int ar_is_in_integer_unit PARAMS ((int regnum)); 669static void set_section PARAMS ((char *name)); 670static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, 671 unsigned int, unsigned int)); 672static void dot_radix PARAMS ((int)); 673static void dot_special_section PARAMS ((int)); 674static void dot_proc PARAMS ((int)); 675static void dot_fframe PARAMS ((int)); 676static void dot_vframe PARAMS ((int)); 677static void dot_vframesp PARAMS ((int)); 678static void dot_vframepsp PARAMS ((int)); 679static void dot_save PARAMS ((int)); 680static void dot_restore PARAMS ((int)); 681static void dot_restorereg PARAMS ((int)); 682static void dot_restorereg_p PARAMS ((int)); 683static void dot_handlerdata PARAMS ((int)); 684static void dot_unwentry PARAMS ((int)); 685static void dot_altrp PARAMS ((int)); 686static void dot_savemem PARAMS ((int)); 687static void dot_saveg PARAMS ((int)); 688static void dot_savef PARAMS ((int)); 689static void dot_saveb PARAMS ((int)); 690static void dot_savegf PARAMS ((int)); 691static void dot_spill PARAMS ((int)); 692static void dot_spillreg PARAMS ((int)); 693static void dot_spillmem PARAMS ((int)); 694static void dot_spillreg_p PARAMS ((int)); 695static void dot_spillmem_p PARAMS ((int)); 696static void dot_label_state PARAMS ((int)); 697static void dot_copy_state PARAMS ((int)); 698static void dot_unwabi PARAMS ((int)); 699static void dot_personality PARAMS ((int)); 700static void dot_body PARAMS ((int)); 701static void dot_prologue PARAMS ((int)); 702static void dot_endp PARAMS ((int)); 703static void dot_template PARAMS ((int)); 704static void dot_regstk PARAMS ((int)); 705static void dot_rot PARAMS ((int)); 706static void dot_byteorder PARAMS ((int)); 707static void dot_psr PARAMS ((int)); 708static void dot_alias PARAMS ((int)); 709static void dot_ln PARAMS ((int)); 710static char *parse_section_name PARAMS ((void)); 711static void dot_xdata PARAMS ((int)); 712static void stmt_float_cons PARAMS ((int)); 713static void stmt_cons_ua PARAMS ((int)); 714static void dot_xfloat_cons PARAMS ((int)); 715static void dot_xstringer PARAMS ((int)); 716static void dot_xdata_ua PARAMS ((int)); 717static void dot_xfloat_cons_ua PARAMS ((int)); 718static void print_prmask PARAMS ((valueT mask)); 719static void dot_pred_rel PARAMS ((int)); 720static void dot_reg_val PARAMS ((int)); 721static void dot_dv_mode PARAMS ((int)); 722static void dot_entry PARAMS ((int)); 723static void dot_mem_offset PARAMS ((int)); 724static void add_unwind_entry PARAMS((unw_rec_list *ptr)); 725static symbolS *declare_register PARAMS ((const char *name, int regnum)); 726static void declare_register_set PARAMS ((const char *, int, int)); 727static unsigned int operand_width PARAMS ((enum ia64_opnd)); 728static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, 729 int index, 730 expressionS *e)); 731static int parse_operand PARAMS ((expressionS *e)); 732static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); 733static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit)); 734static void build_insn PARAMS ((struct slot *, bfd_vma *)); 735static void emit_one_bundle PARAMS ((void)); 736static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); 737static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, 738 bfd_reloc_code_real_type r_type)); 739static void insn_group_break PARAMS ((int, int, int)); 740static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, 741 struct rsrc *, int depind, int path)); 742static void add_qp_mutex PARAMS((valueT mask)); 743static void add_qp_imply PARAMS((int p1, int p2)); 744static void clear_qp_branch_flag PARAMS((valueT mask)); 745static void clear_qp_mutex PARAMS((valueT mask)); 746static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); 747static int has_suffix_p PARAMS((const char *, const char *)); 748static void clear_register_values PARAMS ((void)); 749static void print_dependency PARAMS ((const char *action, int depind)); 750static void instruction_serialization PARAMS ((void)); 751static void data_serialization PARAMS ((void)); 752static void remove_marked_resource PARAMS ((struct rsrc *)); 753static int is_conditional_branch PARAMS ((struct ia64_opcode *)); 754static int is_taken_branch PARAMS ((struct ia64_opcode *)); 755static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); 756static int depends_on PARAMS ((int, struct ia64_opcode *)); 757static int specify_resource PARAMS ((const struct ia64_dependency *, 758 struct ia64_opcode *, int, struct rsrc [], int, int)); 759static int check_dv PARAMS((struct ia64_opcode *idesc)); 760static void check_dependencies PARAMS((struct ia64_opcode *)); 761static void mark_resources PARAMS((struct ia64_opcode *)); 762static void update_dependencies PARAMS((struct ia64_opcode *)); 763static void note_register_values PARAMS((struct ia64_opcode *)); 764static int qp_mutex PARAMS ((int, int, int)); 765static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); 766static void output_vbyte_mem PARAMS ((int, char *, char *)); 767static void count_output PARAMS ((int, char *, char *)); 768static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); 769static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); 770static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 771static void output_P1_format PARAMS ((vbyte_func, int)); 772static void output_P2_format PARAMS ((vbyte_func, int, int)); 773static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); 774static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); 775static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); 776static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); 777static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); 778static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 779static void output_P9_format PARAMS ((vbyte_func, int, int)); 780static void output_P10_format PARAMS ((vbyte_func, int, int)); 781static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 782static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); 783static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); 784static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 785static char format_ab_reg PARAMS ((int, int)); 786static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, 787 unsigned long)); 788static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); 789static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, 790 unsigned long)); 791static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); 792static void free_list_records PARAMS ((unw_rec_list *)); 793static unw_rec_list *output_prologue PARAMS ((void)); 794static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); 795static unw_rec_list *output_body PARAMS ((void)); 796static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); 797static unw_rec_list *output_mem_stack_v PARAMS ((void)); 798static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); 799static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); 800static unw_rec_list *output_rp_when PARAMS ((void)); 801static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); 802static unw_rec_list *output_rp_br PARAMS ((unsigned int)); 803static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); 804static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); 805static unw_rec_list *output_pfs_when PARAMS ((void)); 806static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); 807static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); 808static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); 809static unw_rec_list *output_preds_when PARAMS ((void)); 810static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); 811static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); 812static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); 813static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); 814static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); 815static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); 816static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); 817static unw_rec_list *output_br_mem PARAMS ((unsigned int)); 818static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); 819static unw_rec_list *output_spill_base PARAMS ((unsigned int)); 820static unw_rec_list *output_unat_when PARAMS ((void)); 821static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); 822static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); 823static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); 824static unw_rec_list *output_lc_when PARAMS ((void)); 825static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); 826static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); 827static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); 828static unw_rec_list *output_fpsr_when PARAMS ((void)); 829static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); 830static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); 831static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); 832static unw_rec_list *output_priunat_when_gr PARAMS ((void)); 833static unw_rec_list *output_priunat_when_mem PARAMS ((void)); 834static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); 835static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); 836static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); 837static unw_rec_list *output_bsp_when PARAMS ((void)); 838static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); 839static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); 840static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); 841static unw_rec_list *output_bspstore_when PARAMS ((void)); 842static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); 843static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); 844static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); 845static unw_rec_list *output_rnat_when PARAMS ((void)); 846static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); 847static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); 848static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); 849static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); 850static unw_rec_list *output_epilogue PARAMS ((unsigned long)); 851static unw_rec_list *output_label_state PARAMS ((unsigned long)); 852static unw_rec_list *output_copy_state PARAMS ((unsigned long)); 853static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); 854static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); 855static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, 856 unsigned int)); 857static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, 858 unsigned int)); 859static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, 860 unsigned int)); 861static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, 862 unsigned int, unsigned int)); 863static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); 864static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); 865static int calc_record_size PARAMS ((unw_rec_list *)); 866static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); 867static int count_bits PARAMS ((unsigned long)); 868static unsigned long slot_index PARAMS ((unsigned long, fragS *, 869 unsigned long, fragS *)); 870static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); 871static void fixup_unw_records PARAMS ((unw_rec_list *)); 872static int output_unw_records PARAMS ((unw_rec_list *, void **)); 873static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); 874static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); 875static int generate_unwind_image PARAMS ((const char *)); 876static unsigned int get_saved_prologue_count PARAMS ((unsigned long)); 877static void save_prologue_count PARAMS ((unsigned long, unsigned int)); 878static void free_saved_prologue_counts PARAMS ((void)); 879 880/* Build the unwind section name by appending the (possibly stripped) 881 text section NAME to the unwind PREFIX. The resulting string 882 pointer is assigned to RESULT. The string is allocated on the 883 stack, so this must be a macro... */ 884#define make_unw_section_name(special, text_name, result) \ 885 { \ 886 const char *_prefix = special_section_name[special]; \ 887 const char *_suffix = text_name; \ 888 size_t _prefix_len, _suffix_len; \ 889 char *_result; \ 890 if (strncmp (text_name, ".gnu.linkonce.t.", \ 891 sizeof (".gnu.linkonce.t.") - 1) == 0) \ 892 { \ 893 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \ 894 _suffix += sizeof (".gnu.linkonce.t.") - 1; \ 895 } \ 896 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \ 897 _result = alloca (_prefix_len + _suffix_len + 1); \ 898 memcpy (_result, _prefix, _prefix_len); \ 899 memcpy (_result + _prefix_len, _suffix, _suffix_len); \ 900 _result[_prefix_len + _suffix_len] = '\0'; \ 901 result = _result; \ 902 } \ 903while (0) 904 905/* Determine if application register REGNUM resides in the integer 906 unit (as opposed to the memory unit). */ 907static int 908ar_is_in_integer_unit (reg) 909 int reg; 910{ 911 reg -= REG_AR; 912 913 return (reg == 64 /* pfs */ 914 || reg == 65 /* lc */ 915 || reg == 66 /* ec */ 916 /* ??? ias accepts and puts these in the integer unit. */ 917 || (reg >= 112 && reg <= 127)); 918} 919 920/* Switch to section NAME and create section if necessary. It's 921 rather ugly that we have to manipulate input_line_pointer but I 922 don't see any other way to accomplish the same thing without 923 changing obj-elf.c (which may be the Right Thing, in the end). */ 924static void 925set_section (name) 926 char *name; 927{ 928 char *saved_input_line_pointer; 929 930 saved_input_line_pointer = input_line_pointer; 931 input_line_pointer = name; 932 obj_elf_section (0); 933 input_line_pointer = saved_input_line_pointer; 934} 935 936/* Map 's' to SHF_IA_64_SHORT. */ 937 938int 939ia64_elf_section_letter (letter, ptr_msg) 940 int letter; 941 char **ptr_msg; 942{ 943 if (letter == 's') 944 return SHF_IA_64_SHORT; 945 946 *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S in string"); 947 return 0; 948} 949 950/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ 951 952flagword 953ia64_elf_section_flags (flags, attr, type) 954 flagword flags; 955 int attr, type ATTRIBUTE_UNUSED; 956{ 957 if (attr & SHF_IA_64_SHORT) 958 flags |= SEC_SMALL_DATA; 959 return flags; 960} 961 962int 963ia64_elf_section_type (str, len) 964 const char *str; 965 size_t len; 966{ 967#define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0)) 968 969 if (STREQ (ELF_STRING_ia64_unwind_info)) 970 return SHT_PROGBITS; 971 972 if (STREQ (ELF_STRING_ia64_unwind_info_once)) 973 return SHT_PROGBITS; 974 975 if (STREQ (ELF_STRING_ia64_unwind)) 976 return SHT_IA_64_UNWIND; 977 978 if (STREQ (ELF_STRING_ia64_unwind_once)) 979 return SHT_IA_64_UNWIND; 980 981 if (STREQ ("init_array")) 982 return SHT_INIT_ARRAY; 983 984 if (STREQ ("fini_array")) 985 return SHT_FINI_ARRAY; 986 987 return -1; 988#undef STREQ 989} 990 991static unsigned int 992set_regstack (ins, locs, outs, rots) 993 unsigned int ins, locs, outs, rots; 994{ 995 /* Size of frame. */ 996 unsigned int sof; 997 998 sof = ins + locs + outs; 999 if (sof > 96) 1000 { 1001 as_bad ("Size of frame exceeds maximum of 96 registers"); 1002 return 0; 1003 } 1004 if (rots > sof) 1005 { 1006 as_warn ("Size of rotating registers exceeds frame size"); 1007 return 0; 1008 } 1009 md.in.base = REG_GR + 32; 1010 md.loc.base = md.in.base + ins; 1011 md.out.base = md.loc.base + locs; 1012 1013 md.in.num_regs = ins; 1014 md.loc.num_regs = locs; 1015 md.out.num_regs = outs; 1016 md.rot.num_regs = rots; 1017 return sof; 1018} 1019 1020void 1021ia64_flush_insns () 1022{ 1023 struct label_fix *lfix; 1024 segT saved_seg; 1025 subsegT saved_subseg; 1026 unw_rec_list *ptr; 1027 1028 if (!md.last_text_seg) 1029 return; 1030 1031 saved_seg = now_seg; 1032 saved_subseg = now_subseg; 1033 1034 subseg_set (md.last_text_seg, 0); 1035 1036 while (md.num_slots_in_use > 0) 1037 emit_one_bundle (); /* force out queued instructions */ 1038 1039 /* In case there are labels following the last instruction, resolve 1040 those now: */ 1041 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) 1042 { 1043 S_SET_VALUE (lfix->sym, frag_now_fix ()); 1044 symbol_set_frag (lfix->sym, frag_now); 1045 } 1046 CURR_SLOT.label_fixups = 0; 1047 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) 1048 { 1049 S_SET_VALUE (lfix->sym, frag_now_fix ()); 1050 symbol_set_frag (lfix->sym, frag_now); 1051 } 1052 CURR_SLOT.tag_fixups = 0; 1053 1054 /* In case there are unwind directives following the last instruction, 1055 resolve those now. We only handle body and prologue directives here. 1056 Give an error for others. */ 1057 for (ptr = unwind.current_entry; ptr; ptr = ptr->next) 1058 { 1059 if (ptr->r.type == prologue || ptr->r.type == prologue_gr 1060 || ptr->r.type == body) 1061 { 1062 ptr->slot_number = (unsigned long) frag_more (0); 1063 ptr->slot_frag = frag_now; 1064 } 1065 else 1066 as_bad (_("Unwind directive not followed by an instruction.")); 1067 } 1068 unwind.current_entry = NULL; 1069 1070 subseg_set (saved_seg, saved_subseg); 1071 1072 if (md.qp.X_op == O_register) 1073 as_bad ("qualifying predicate not followed by instruction"); 1074} 1075 1076void 1077ia64_do_align (nbytes) 1078 int nbytes; 1079{ 1080 char *saved_input_line_pointer = input_line_pointer; 1081 1082 input_line_pointer = ""; 1083 s_align_bytes (nbytes); 1084 input_line_pointer = saved_input_line_pointer; 1085} 1086 1087void 1088ia64_cons_align (nbytes) 1089 int nbytes; 1090{ 1091 if (md.auto_align) 1092 { 1093 char *saved_input_line_pointer = input_line_pointer; 1094 input_line_pointer = ""; 1095 s_align_bytes (nbytes); 1096 input_line_pointer = saved_input_line_pointer; 1097 } 1098} 1099 1100/* Output COUNT bytes to a memory location. */ 1101static unsigned char *vbyte_mem_ptr = NULL; 1102 1103void 1104output_vbyte_mem (count, ptr, comment) 1105 int count; 1106 char *ptr; 1107 char *comment ATTRIBUTE_UNUSED; 1108{ 1109 int x; 1110 if (vbyte_mem_ptr == NULL) 1111 abort (); 1112 1113 if (count == 0) 1114 return; 1115 for (x = 0; x < count; x++) 1116 *(vbyte_mem_ptr++) = ptr[x]; 1117} 1118 1119/* Count the number of bytes required for records. */ 1120static int vbyte_count = 0; 1121void 1122count_output (count, ptr, comment) 1123 int count; 1124 char *ptr ATTRIBUTE_UNUSED; 1125 char *comment ATTRIBUTE_UNUSED; 1126{ 1127 vbyte_count += count; 1128} 1129 1130static void 1131output_R1_format (f, rtype, rlen) 1132 vbyte_func f; 1133 unw_record_type rtype; 1134 int rlen; 1135{ 1136 int r = 0; 1137 char byte; 1138 if (rlen > 0x1f) 1139 { 1140 output_R3_format (f, rtype, rlen); 1141 return; 1142 } 1143 1144 if (rtype == body) 1145 r = 1; 1146 else if (rtype != prologue) 1147 as_bad ("record type is not valid"); 1148 1149 byte = UNW_R1 | (r << 5) | (rlen & 0x1f); 1150 (*f) (1, &byte, NULL); 1151} 1152 1153static void 1154output_R2_format (f, mask, grsave, rlen) 1155 vbyte_func f; 1156 int mask, grsave; 1157 unsigned long rlen; 1158{ 1159 char bytes[20]; 1160 int count = 2; 1161 mask = (mask & 0x0f); 1162 grsave = (grsave & 0x7f); 1163 1164 bytes[0] = (UNW_R2 | (mask >> 1)); 1165 bytes[1] = (((mask & 0x01) << 7) | grsave); 1166 count += output_leb128 (bytes + 2, rlen, 0); 1167 (*f) (count, bytes, NULL); 1168} 1169 1170static void 1171output_R3_format (f, rtype, rlen) 1172 vbyte_func f; 1173 unw_record_type rtype; 1174 unsigned long rlen; 1175{ 1176 int r = 0, count; 1177 char bytes[20]; 1178 if (rlen <= 0x1f) 1179 { 1180 output_R1_format (f, rtype, rlen); 1181 return; 1182 } 1183 1184 if (rtype == body) 1185 r = 1; 1186 else if (rtype != prologue) 1187 as_bad ("record type is not valid"); 1188 bytes[0] = (UNW_R3 | r); 1189 count = output_leb128 (bytes + 1, rlen, 0); 1190 (*f) (count + 1, bytes, NULL); 1191} 1192 1193static void 1194output_P1_format (f, brmask) 1195 vbyte_func f; 1196 int brmask; 1197{ 1198 char byte; 1199 byte = UNW_P1 | (brmask & 0x1f); 1200 (*f) (1, &byte, NULL); 1201} 1202 1203static void 1204output_P2_format (f, brmask, gr) 1205 vbyte_func f; 1206 int brmask; 1207 int gr; 1208{ 1209 char bytes[2]; 1210 brmask = (brmask & 0x1f); 1211 bytes[0] = UNW_P2 | (brmask >> 1); 1212 bytes[1] = (((brmask & 1) << 7) | gr); 1213 (*f) (2, bytes, NULL); 1214} 1215 1216static void 1217output_P3_format (f, rtype, reg) 1218 vbyte_func f; 1219 unw_record_type rtype; 1220 int reg; 1221{ 1222 char bytes[2]; 1223 int r = 0; 1224 reg = (reg & 0x7f); 1225 switch (rtype) 1226 { 1227 case psp_gr: 1228 r = 0; 1229 break; 1230 case rp_gr: 1231 r = 1; 1232 break; 1233 case pfs_gr: 1234 r = 2; 1235 break; 1236 case preds_gr: 1237 r = 3; 1238 break; 1239 case unat_gr: 1240 r = 4; 1241 break; 1242 case lc_gr: 1243 r = 5; 1244 break; 1245 case rp_br: 1246 r = 6; 1247 break; 1248 case rnat_gr: 1249 r = 7; 1250 break; 1251 case bsp_gr: 1252 r = 8; 1253 break; 1254 case bspstore_gr: 1255 r = 9; 1256 break; 1257 case fpsr_gr: 1258 r = 10; 1259 break; 1260 case priunat_gr: 1261 r = 11; 1262 break; 1263 default: 1264 as_bad ("Invalid record type for P3 format."); 1265 } 1266 bytes[0] = (UNW_P3 | (r >> 1)); 1267 bytes[1] = (((r & 1) << 7) | reg); 1268 (*f) (2, bytes, NULL); 1269} 1270 1271static void 1272output_P4_format (f, imask, imask_size) 1273 vbyte_func f; 1274 unsigned char *imask; 1275 unsigned long imask_size; 1276{ 1277 imask[0] = UNW_P4; 1278 (*f) (imask_size, imask, NULL); 1279} 1280 1281static void 1282output_P5_format (f, grmask, frmask) 1283 vbyte_func f; 1284 int grmask; 1285 unsigned long frmask; 1286{ 1287 char bytes[4]; 1288 grmask = (grmask & 0x0f); 1289 1290 bytes[0] = UNW_P5; 1291 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); 1292 bytes[2] = ((frmask & 0x0000ff00) >> 8); 1293 bytes[3] = (frmask & 0x000000ff); 1294 (*f) (4, bytes, NULL); 1295} 1296 1297static void 1298output_P6_format (f, rtype, rmask) 1299 vbyte_func f; 1300 unw_record_type rtype; 1301 int rmask; 1302{ 1303 char byte; 1304 int r = 0; 1305 1306 if (rtype == gr_mem) 1307 r = 1; 1308 else if (rtype != fr_mem) 1309 as_bad ("Invalid record type for format P6"); 1310 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); 1311 (*f) (1, &byte, NULL); 1312} 1313 1314static void 1315output_P7_format (f, rtype, w1, w2) 1316 vbyte_func f; 1317 unw_record_type rtype; 1318 unsigned long w1; 1319 unsigned long w2; 1320{ 1321 char bytes[20]; 1322 int count = 1; 1323 int r = 0; 1324 count += output_leb128 (bytes + 1, w1, 0); 1325 switch (rtype) 1326 { 1327 case mem_stack_f: 1328 r = 0; 1329 count += output_leb128 (bytes + count, w2 >> 4, 0); 1330 break; 1331 case mem_stack_v: 1332 r = 1; 1333 break; 1334 case spill_base: 1335 r = 2; 1336 break; 1337 case psp_sprel: 1338 r = 3; 1339 break; 1340 case rp_when: 1341 r = 4; 1342 break; 1343 case rp_psprel: 1344 r = 5; 1345 break; 1346 case pfs_when: 1347 r = 6; 1348 break; 1349 case pfs_psprel: 1350 r = 7; 1351 break; 1352 case preds_when: 1353 r = 8; 1354 break; 1355 case preds_psprel: 1356 r = 9; 1357 break; 1358 case lc_when: 1359 r = 10; 1360 break; 1361 case lc_psprel: 1362 r = 11; 1363 break; 1364 case unat_when: 1365 r = 12; 1366 break; 1367 case unat_psprel: 1368 r = 13; 1369 break; 1370 case fpsr_when: 1371 r = 14; 1372 break; 1373 case fpsr_psprel: 1374 r = 15; 1375 break; 1376 default: 1377 break; 1378 } 1379 bytes[0] = (UNW_P7 | r); 1380 (*f) (count, bytes, NULL); 1381} 1382 1383static void 1384output_P8_format (f, rtype, t) 1385 vbyte_func f; 1386 unw_record_type rtype; 1387 unsigned long t; 1388{ 1389 char bytes[20]; 1390 int r = 0; 1391 int count = 2; 1392 bytes[0] = UNW_P8; 1393 switch (rtype) 1394 { 1395 case rp_sprel: 1396 r = 1; 1397 break; 1398 case pfs_sprel: 1399 r = 2; 1400 break; 1401 case preds_sprel: 1402 r = 3; 1403 break; 1404 case lc_sprel: 1405 r = 4; 1406 break; 1407 case unat_sprel: 1408 r = 5; 1409 break; 1410 case fpsr_sprel: 1411 r = 6; 1412 break; 1413 case bsp_when: 1414 r = 7; 1415 break; 1416 case bsp_psprel: 1417 r = 8; 1418 break; 1419 case bsp_sprel: 1420 r = 9; 1421 break; 1422 case bspstore_when: 1423 r = 10; 1424 break; 1425 case bspstore_psprel: 1426 r = 11; 1427 break; 1428 case bspstore_sprel: 1429 r = 12; 1430 break; 1431 case rnat_when: 1432 r = 13; 1433 break; 1434 case rnat_psprel: 1435 r = 14; 1436 break; 1437 case rnat_sprel: 1438 r = 15; 1439 break; 1440 case priunat_when_gr: 1441 r = 16; 1442 break; 1443 case priunat_psprel: 1444 r = 17; 1445 break; 1446 case priunat_sprel: 1447 r = 18; 1448 break; 1449 case priunat_when_mem: 1450 r = 19; 1451 break; 1452 default: 1453 break; 1454 } 1455 bytes[1] = r; 1456 count += output_leb128 (bytes + 2, t, 0); 1457 (*f) (count, bytes, NULL); 1458} 1459 1460static void 1461output_P9_format (f, grmask, gr) 1462 vbyte_func f; 1463 int grmask; 1464 int gr; 1465{ 1466 char bytes[3]; 1467 bytes[0] = UNW_P9; 1468 bytes[1] = (grmask & 0x0f); 1469 bytes[2] = (gr & 0x7f); 1470 (*f) (3, bytes, NULL); 1471} 1472 1473static void 1474output_P10_format (f, abi, context) 1475 vbyte_func f; 1476 int abi; 1477 int context; 1478{ 1479 char bytes[3]; 1480 bytes[0] = UNW_P10; 1481 bytes[1] = (abi & 0xff); 1482 bytes[2] = (context & 0xff); 1483 (*f) (3, bytes, NULL); 1484} 1485 1486static void 1487output_B1_format (f, rtype, label) 1488 vbyte_func f; 1489 unw_record_type rtype; 1490 unsigned long label; 1491{ 1492 char byte; 1493 int r = 0; 1494 if (label > 0x1f) 1495 { 1496 output_B4_format (f, rtype, label); 1497 return; 1498 } 1499 if (rtype == copy_state) 1500 r = 1; 1501 else if (rtype != label_state) 1502 as_bad ("Invalid record type for format B1"); 1503 1504 byte = (UNW_B1 | (r << 5) | (label & 0x1f)); 1505 (*f) (1, &byte, NULL); 1506} 1507 1508static void 1509output_B2_format (f, ecount, t) 1510 vbyte_func f; 1511 unsigned long ecount; 1512 unsigned long t; 1513{ 1514 char bytes[20]; 1515 int count = 1; 1516 if (ecount > 0x1f) 1517 { 1518 output_B3_format (f, ecount, t); 1519 return; 1520 } 1521 bytes[0] = (UNW_B2 | (ecount & 0x1f)); 1522 count += output_leb128 (bytes + 1, t, 0); 1523 (*f) (count, bytes, NULL); 1524} 1525 1526static void 1527output_B3_format (f, ecount, t) 1528 vbyte_func f; 1529 unsigned long ecount; 1530 unsigned long t; 1531{ 1532 char bytes[20]; 1533 int count = 1; 1534 if (ecount <= 0x1f) 1535 { 1536 output_B2_format (f, ecount, t); 1537 return; 1538 } 1539 bytes[0] = UNW_B3; 1540 count += output_leb128 (bytes + 1, t, 0); 1541 count += output_leb128 (bytes + count, ecount, 0); 1542 (*f) (count, bytes, NULL); 1543} 1544 1545static void 1546output_B4_format (f, rtype, label) 1547 vbyte_func f; 1548 unw_record_type rtype; 1549 unsigned long label; 1550{ 1551 char bytes[20]; 1552 int r = 0; 1553 int count = 1; 1554 if (label <= 0x1f) 1555 { 1556 output_B1_format (f, rtype, label); 1557 return; 1558 } 1559 1560 if (rtype == copy_state) 1561 r = 1; 1562 else if (rtype != label_state) 1563 as_bad ("Invalid record type for format B1"); 1564 1565 bytes[0] = (UNW_B4 | (r << 3)); 1566 count += output_leb128 (bytes + 1, label, 0); 1567 (*f) (count, bytes, NULL); 1568} 1569 1570static char 1571format_ab_reg (ab, reg) 1572 int ab; 1573 int reg; 1574{ 1575 int ret; 1576 ab = (ab & 3); 1577 reg = (reg & 0x1f); 1578 ret = (ab << 5) | reg; 1579 return ret; 1580} 1581 1582static void 1583output_X1_format (f, rtype, ab, reg, t, w1) 1584 vbyte_func f; 1585 unw_record_type rtype; 1586 int ab, reg; 1587 unsigned long t; 1588 unsigned long w1; 1589{ 1590 char bytes[20]; 1591 int r = 0; 1592 int count = 2; 1593 bytes[0] = UNW_X1; 1594 1595 if (rtype == spill_sprel) 1596 r = 1; 1597 else if (rtype != spill_psprel) 1598 as_bad ("Invalid record type for format X1"); 1599 bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); 1600 count += output_leb128 (bytes + 2, t, 0); 1601 count += output_leb128 (bytes + count, w1, 0); 1602 (*f) (count, bytes, NULL); 1603} 1604 1605static void 1606output_X2_format (f, ab, reg, x, y, treg, t) 1607 vbyte_func f; 1608 int ab, reg; 1609 int x, y, treg; 1610 unsigned long t; 1611{ 1612 char bytes[20]; 1613 int count = 3; 1614 bytes[0] = UNW_X2; 1615 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1616 bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); 1617 count += output_leb128 (bytes + 3, t, 0); 1618 (*f) (count, bytes, NULL); 1619} 1620 1621static void 1622output_X3_format (f, rtype, qp, ab, reg, t, w1) 1623 vbyte_func f; 1624 unw_record_type rtype; 1625 int qp; 1626 int ab, reg; 1627 unsigned long t; 1628 unsigned long w1; 1629{ 1630 char bytes[20]; 1631 int r = 0; 1632 int count = 3; 1633 bytes[0] = UNW_X3; 1634 1635 if (rtype == spill_sprel_p) 1636 r = 1; 1637 else if (rtype != spill_psprel_p) 1638 as_bad ("Invalid record type for format X3"); 1639 bytes[1] = ((r << 7) | (qp & 0x3f)); 1640 bytes[2] = format_ab_reg (ab, reg); 1641 count += output_leb128 (bytes + 3, t, 0); 1642 count += output_leb128 (bytes + count, w1, 0); 1643 (*f) (count, bytes, NULL); 1644} 1645 1646static void 1647output_X4_format (f, qp, ab, reg, x, y, treg, t) 1648 vbyte_func f; 1649 int qp; 1650 int ab, reg; 1651 int x, y, treg; 1652 unsigned long t; 1653{ 1654 char bytes[20]; 1655 int count = 4; 1656 bytes[0] = UNW_X4; 1657 bytes[1] = (qp & 0x3f); 1658 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1659 bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); 1660 count += output_leb128 (bytes + 4, t, 0); 1661 (*f) (count, bytes, NULL); 1662} 1663 1664/* This function allocates a record list structure, and initializes fields. */ 1665 1666static unw_rec_list * 1667alloc_record (unw_record_type t) 1668{ 1669 unw_rec_list *ptr; 1670 ptr = xmalloc (sizeof (*ptr)); 1671 ptr->next = NULL; 1672 ptr->slot_number = SLOT_NUM_NOT_SET; 1673 ptr->r.type = t; 1674 return ptr; 1675} 1676 1677/* This function frees an entire list of record structures. */ 1678 1679void 1680free_list_records (unw_rec_list *first) 1681{ 1682 unw_rec_list *ptr; 1683 for (ptr = first; ptr != NULL;) 1684 { 1685 unw_rec_list *tmp = ptr; 1686 1687 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) 1688 && tmp->r.record.r.mask.i) 1689 free (tmp->r.record.r.mask.i); 1690 1691 ptr = ptr->next; 1692 free (tmp); 1693 } 1694} 1695 1696static unw_rec_list * 1697output_prologue () 1698{ 1699 unw_rec_list *ptr = alloc_record (prologue); 1700 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1701 return ptr; 1702} 1703 1704static unw_rec_list * 1705output_prologue_gr (saved_mask, reg) 1706 unsigned int saved_mask; 1707 unsigned int reg; 1708{ 1709 unw_rec_list *ptr = alloc_record (prologue_gr); 1710 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1711 ptr->r.record.r.grmask = saved_mask; 1712 ptr->r.record.r.grsave = reg; 1713 return ptr; 1714} 1715 1716static unw_rec_list * 1717output_body () 1718{ 1719 unw_rec_list *ptr = alloc_record (body); 1720 return ptr; 1721} 1722 1723static unw_rec_list * 1724output_mem_stack_f (size) 1725 unsigned int size; 1726{ 1727 unw_rec_list *ptr = alloc_record (mem_stack_f); 1728 ptr->r.record.p.size = size; 1729 return ptr; 1730} 1731 1732static unw_rec_list * 1733output_mem_stack_v () 1734{ 1735 unw_rec_list *ptr = alloc_record (mem_stack_v); 1736 return ptr; 1737} 1738 1739static unw_rec_list * 1740output_psp_gr (gr) 1741 unsigned int gr; 1742{ 1743 unw_rec_list *ptr = alloc_record (psp_gr); 1744 ptr->r.record.p.gr = gr; 1745 return ptr; 1746} 1747 1748static unw_rec_list * 1749output_psp_sprel (offset) 1750 unsigned int offset; 1751{ 1752 unw_rec_list *ptr = alloc_record (psp_sprel); 1753 ptr->r.record.p.spoff = offset / 4; 1754 return ptr; 1755} 1756 1757static unw_rec_list * 1758output_rp_when () 1759{ 1760 unw_rec_list *ptr = alloc_record (rp_when); 1761 return ptr; 1762} 1763 1764static unw_rec_list * 1765output_rp_gr (gr) 1766 unsigned int gr; 1767{ 1768 unw_rec_list *ptr = alloc_record (rp_gr); 1769 ptr->r.record.p.gr = gr; 1770 return ptr; 1771} 1772 1773static unw_rec_list * 1774output_rp_br (br) 1775 unsigned int br; 1776{ 1777 unw_rec_list *ptr = alloc_record (rp_br); 1778 ptr->r.record.p.br = br; 1779 return ptr; 1780} 1781 1782static unw_rec_list * 1783output_rp_psprel (offset) 1784 unsigned int offset; 1785{ 1786 unw_rec_list *ptr = alloc_record (rp_psprel); 1787 ptr->r.record.p.pspoff = offset / 4; 1788 return ptr; 1789} 1790 1791static unw_rec_list * 1792output_rp_sprel (offset) 1793 unsigned int offset; 1794{ 1795 unw_rec_list *ptr = alloc_record (rp_sprel); 1796 ptr->r.record.p.spoff = offset / 4; 1797 return ptr; 1798} 1799 1800static unw_rec_list * 1801output_pfs_when () 1802{ 1803 unw_rec_list *ptr = alloc_record (pfs_when); 1804 return ptr; 1805} 1806 1807static unw_rec_list * 1808output_pfs_gr (gr) 1809 unsigned int gr; 1810{ 1811 unw_rec_list *ptr = alloc_record (pfs_gr); 1812 ptr->r.record.p.gr = gr; 1813 return ptr; 1814} 1815 1816static unw_rec_list * 1817output_pfs_psprel (offset) 1818 unsigned int offset; 1819{ 1820 unw_rec_list *ptr = alloc_record (pfs_psprel); 1821 ptr->r.record.p.pspoff = offset / 4; 1822 return ptr; 1823} 1824 1825static unw_rec_list * 1826output_pfs_sprel (offset) 1827 unsigned int offset; 1828{ 1829 unw_rec_list *ptr = alloc_record (pfs_sprel); 1830 ptr->r.record.p.spoff = offset / 4; 1831 return ptr; 1832} 1833 1834static unw_rec_list * 1835output_preds_when () 1836{ 1837 unw_rec_list *ptr = alloc_record (preds_when); 1838 return ptr; 1839} 1840 1841static unw_rec_list * 1842output_preds_gr (gr) 1843 unsigned int gr; 1844{ 1845 unw_rec_list *ptr = alloc_record (preds_gr); 1846 ptr->r.record.p.gr = gr; 1847 return ptr; 1848} 1849 1850static unw_rec_list * 1851output_preds_psprel (offset) 1852 unsigned int offset; 1853{ 1854 unw_rec_list *ptr = alloc_record (preds_psprel); 1855 ptr->r.record.p.pspoff = offset / 4; 1856 return ptr; 1857} 1858 1859static unw_rec_list * 1860output_preds_sprel (offset) 1861 unsigned int offset; 1862{ 1863 unw_rec_list *ptr = alloc_record (preds_sprel); 1864 ptr->r.record.p.spoff = offset / 4; 1865 return ptr; 1866} 1867 1868static unw_rec_list * 1869output_fr_mem (mask) 1870 unsigned int mask; 1871{ 1872 unw_rec_list *ptr = alloc_record (fr_mem); 1873 ptr->r.record.p.rmask = mask; 1874 return ptr; 1875} 1876 1877static unw_rec_list * 1878output_frgr_mem (gr_mask, fr_mask) 1879 unsigned int gr_mask; 1880 unsigned int fr_mask; 1881{ 1882 unw_rec_list *ptr = alloc_record (frgr_mem); 1883 ptr->r.record.p.grmask = gr_mask; 1884 ptr->r.record.p.frmask = fr_mask; 1885 return ptr; 1886} 1887 1888static unw_rec_list * 1889output_gr_gr (mask, reg) 1890 unsigned int mask; 1891 unsigned int reg; 1892{ 1893 unw_rec_list *ptr = alloc_record (gr_gr); 1894 ptr->r.record.p.grmask = mask; 1895 ptr->r.record.p.gr = reg; 1896 return ptr; 1897} 1898 1899static unw_rec_list * 1900output_gr_mem (mask) 1901 unsigned int mask; 1902{ 1903 unw_rec_list *ptr = alloc_record (gr_mem); 1904 ptr->r.record.p.rmask = mask; 1905 return ptr; 1906} 1907 1908static unw_rec_list * 1909output_br_mem (unsigned int mask) 1910{ 1911 unw_rec_list *ptr = alloc_record (br_mem); 1912 ptr->r.record.p.brmask = mask; 1913 return ptr; 1914} 1915 1916static unw_rec_list * 1917output_br_gr (save_mask, reg) 1918 unsigned int save_mask; 1919 unsigned int reg; 1920{ 1921 unw_rec_list *ptr = alloc_record (br_gr); 1922 ptr->r.record.p.brmask = save_mask; 1923 ptr->r.record.p.gr = reg; 1924 return ptr; 1925} 1926 1927static unw_rec_list * 1928output_spill_base (offset) 1929 unsigned int offset; 1930{ 1931 unw_rec_list *ptr = alloc_record (spill_base); 1932 ptr->r.record.p.pspoff = offset / 4; 1933 return ptr; 1934} 1935 1936static unw_rec_list * 1937output_unat_when () 1938{ 1939 unw_rec_list *ptr = alloc_record (unat_when); 1940 return ptr; 1941} 1942 1943static unw_rec_list * 1944output_unat_gr (gr) 1945 unsigned int gr; 1946{ 1947 unw_rec_list *ptr = alloc_record (unat_gr); 1948 ptr->r.record.p.gr = gr; 1949 return ptr; 1950} 1951 1952static unw_rec_list * 1953output_unat_psprel (offset) 1954 unsigned int offset; 1955{ 1956 unw_rec_list *ptr = alloc_record (unat_psprel); 1957 ptr->r.record.p.pspoff = offset / 4; 1958 return ptr; 1959} 1960 1961static unw_rec_list * 1962output_unat_sprel (offset) 1963 unsigned int offset; 1964{ 1965 unw_rec_list *ptr = alloc_record (unat_sprel); 1966 ptr->r.record.p.spoff = offset / 4; 1967 return ptr; 1968} 1969 1970static unw_rec_list * 1971output_lc_when () 1972{ 1973 unw_rec_list *ptr = alloc_record (lc_when); 1974 return ptr; 1975} 1976 1977static unw_rec_list * 1978output_lc_gr (gr) 1979 unsigned int gr; 1980{ 1981 unw_rec_list *ptr = alloc_record (lc_gr); 1982 ptr->r.record.p.gr = gr; 1983 return ptr; 1984} 1985 1986static unw_rec_list * 1987output_lc_psprel (offset) 1988 unsigned int offset; 1989{ 1990 unw_rec_list *ptr = alloc_record (lc_psprel); 1991 ptr->r.record.p.pspoff = offset / 4; 1992 return ptr; 1993} 1994 1995static unw_rec_list * 1996output_lc_sprel (offset) 1997 unsigned int offset; 1998{ 1999 unw_rec_list *ptr = alloc_record (lc_sprel); 2000 ptr->r.record.p.spoff = offset / 4; 2001 return ptr; 2002} 2003 2004static unw_rec_list * 2005output_fpsr_when () 2006{ 2007 unw_rec_list *ptr = alloc_record (fpsr_when); 2008 return ptr; 2009} 2010 2011static unw_rec_list * 2012output_fpsr_gr (gr) 2013 unsigned int gr; 2014{ 2015 unw_rec_list *ptr = alloc_record (fpsr_gr); 2016 ptr->r.record.p.gr = gr; 2017 return ptr; 2018} 2019 2020static unw_rec_list * 2021output_fpsr_psprel (offset) 2022 unsigned int offset; 2023{ 2024 unw_rec_list *ptr = alloc_record (fpsr_psprel); 2025 ptr->r.record.p.pspoff = offset / 4; 2026 return ptr; 2027} 2028 2029static unw_rec_list * 2030output_fpsr_sprel (offset) 2031 unsigned int offset; 2032{ 2033 unw_rec_list *ptr = alloc_record (fpsr_sprel); 2034 ptr->r.record.p.spoff = offset / 4; 2035 return ptr; 2036} 2037 2038static unw_rec_list * 2039output_priunat_when_gr () 2040{ 2041 unw_rec_list *ptr = alloc_record (priunat_when_gr); 2042 return ptr; 2043} 2044 2045static unw_rec_list * 2046output_priunat_when_mem () 2047{ 2048 unw_rec_list *ptr = alloc_record (priunat_when_mem); 2049 return ptr; 2050} 2051 2052static unw_rec_list * 2053output_priunat_gr (gr) 2054 unsigned int gr; 2055{ 2056 unw_rec_list *ptr = alloc_record (priunat_gr); 2057 ptr->r.record.p.gr = gr; 2058 return ptr; 2059} 2060 2061static unw_rec_list * 2062output_priunat_psprel (offset) 2063 unsigned int offset; 2064{ 2065 unw_rec_list *ptr = alloc_record (priunat_psprel); 2066 ptr->r.record.p.pspoff = offset / 4; 2067 return ptr; 2068} 2069 2070static unw_rec_list * 2071output_priunat_sprel (offset) 2072 unsigned int offset; 2073{ 2074 unw_rec_list *ptr = alloc_record (priunat_sprel); 2075 ptr->r.record.p.spoff = offset / 4; 2076 return ptr; 2077} 2078 2079static unw_rec_list * 2080output_bsp_when () 2081{ 2082 unw_rec_list *ptr = alloc_record (bsp_when); 2083 return ptr; 2084} 2085 2086static unw_rec_list * 2087output_bsp_gr (gr) 2088 unsigned int gr; 2089{ 2090 unw_rec_list *ptr = alloc_record (bsp_gr); 2091 ptr->r.record.p.gr = gr; 2092 return ptr; 2093} 2094 2095static unw_rec_list * 2096output_bsp_psprel (offset) 2097 unsigned int offset; 2098{ 2099 unw_rec_list *ptr = alloc_record (bsp_psprel); 2100 ptr->r.record.p.pspoff = offset / 4; 2101 return ptr; 2102} 2103 2104static unw_rec_list * 2105output_bsp_sprel (offset) 2106 unsigned int offset; 2107{ 2108 unw_rec_list *ptr = alloc_record (bsp_sprel); 2109 ptr->r.record.p.spoff = offset / 4; 2110 return ptr; 2111} 2112 2113static unw_rec_list * 2114output_bspstore_when () 2115{ 2116 unw_rec_list *ptr = alloc_record (bspstore_when); 2117 return ptr; 2118} 2119 2120static unw_rec_list * 2121output_bspstore_gr (gr) 2122 unsigned int gr; 2123{ 2124 unw_rec_list *ptr = alloc_record (bspstore_gr); 2125 ptr->r.record.p.gr = gr; 2126 return ptr; 2127} 2128 2129static unw_rec_list * 2130output_bspstore_psprel (offset) 2131 unsigned int offset; 2132{ 2133 unw_rec_list *ptr = alloc_record (bspstore_psprel); 2134 ptr->r.record.p.pspoff = offset / 4; 2135 return ptr; 2136} 2137 2138static unw_rec_list * 2139output_bspstore_sprel (offset) 2140 unsigned int offset; 2141{ 2142 unw_rec_list *ptr = alloc_record (bspstore_sprel); 2143 ptr->r.record.p.spoff = offset / 4; 2144 return ptr; 2145} 2146 2147static unw_rec_list * 2148output_rnat_when () 2149{ 2150 unw_rec_list *ptr = alloc_record (rnat_when); 2151 return ptr; 2152} 2153 2154static unw_rec_list * 2155output_rnat_gr (gr) 2156 unsigned int gr; 2157{ 2158 unw_rec_list *ptr = alloc_record (rnat_gr); 2159 ptr->r.record.p.gr = gr; 2160 return ptr; 2161} 2162 2163static unw_rec_list * 2164output_rnat_psprel (offset) 2165 unsigned int offset; 2166{ 2167 unw_rec_list *ptr = alloc_record (rnat_psprel); 2168 ptr->r.record.p.pspoff = offset / 4; 2169 return ptr; 2170} 2171 2172static unw_rec_list * 2173output_rnat_sprel (offset) 2174 unsigned int offset; 2175{ 2176 unw_rec_list *ptr = alloc_record (rnat_sprel); 2177 ptr->r.record.p.spoff = offset / 4; 2178 return ptr; 2179} 2180 2181static unw_rec_list * 2182output_unwabi (abi, context) 2183 unsigned long abi; 2184 unsigned long context; 2185{ 2186 unw_rec_list *ptr = alloc_record (unwabi); 2187 ptr->r.record.p.abi = abi; 2188 ptr->r.record.p.context = context; 2189 return ptr; 2190} 2191 2192static unw_rec_list * 2193output_epilogue (unsigned long ecount) 2194{ 2195 unw_rec_list *ptr = alloc_record (epilogue); 2196 ptr->r.record.b.ecount = ecount; 2197 return ptr; 2198} 2199 2200static unw_rec_list * 2201output_label_state (unsigned long label) 2202{ 2203 unw_rec_list *ptr = alloc_record (label_state); 2204 ptr->r.record.b.label = label; 2205 return ptr; 2206} 2207 2208static unw_rec_list * 2209output_copy_state (unsigned long label) 2210{ 2211 unw_rec_list *ptr = alloc_record (copy_state); 2212 ptr->r.record.b.label = label; 2213 return ptr; 2214} 2215 2216static unw_rec_list * 2217output_spill_psprel (ab, reg, offset) 2218 unsigned int ab; 2219 unsigned int reg; 2220 unsigned int offset; 2221{ 2222 unw_rec_list *ptr = alloc_record (spill_psprel); 2223 ptr->r.record.x.ab = ab; 2224 ptr->r.record.x.reg = reg; 2225 ptr->r.record.x.pspoff = offset / 4; 2226 return ptr; 2227} 2228 2229static unw_rec_list * 2230output_spill_sprel (ab, reg, offset) 2231 unsigned int ab; 2232 unsigned int reg; 2233 unsigned int offset; 2234{ 2235 unw_rec_list *ptr = alloc_record (spill_sprel); 2236 ptr->r.record.x.ab = ab; 2237 ptr->r.record.x.reg = reg; 2238 ptr->r.record.x.spoff = offset / 4; 2239 return ptr; 2240} 2241 2242static unw_rec_list * 2243output_spill_psprel_p (ab, reg, offset, predicate) 2244 unsigned int ab; 2245 unsigned int reg; 2246 unsigned int offset; 2247 unsigned int predicate; 2248{ 2249 unw_rec_list *ptr = alloc_record (spill_psprel_p); 2250 ptr->r.record.x.ab = ab; 2251 ptr->r.record.x.reg = reg; 2252 ptr->r.record.x.pspoff = offset / 4; 2253 ptr->r.record.x.qp = predicate; 2254 return ptr; 2255} 2256 2257static unw_rec_list * 2258output_spill_sprel_p (ab, reg, offset, predicate) 2259 unsigned int ab; 2260 unsigned int reg; 2261 unsigned int offset; 2262 unsigned int predicate; 2263{ 2264 unw_rec_list *ptr = alloc_record (spill_sprel_p); 2265 ptr->r.record.x.ab = ab; 2266 ptr->r.record.x.reg = reg; 2267 ptr->r.record.x.spoff = offset / 4; 2268 ptr->r.record.x.qp = predicate; 2269 return ptr; 2270} 2271 2272static unw_rec_list * 2273output_spill_reg (ab, reg, targ_reg, xy) 2274 unsigned int ab; 2275 unsigned int reg; 2276 unsigned int targ_reg; 2277 unsigned int xy; 2278{ 2279 unw_rec_list *ptr = alloc_record (spill_reg); 2280 ptr->r.record.x.ab = ab; 2281 ptr->r.record.x.reg = reg; 2282 ptr->r.record.x.treg = targ_reg; 2283 ptr->r.record.x.xy = xy; 2284 return ptr; 2285} 2286 2287static unw_rec_list * 2288output_spill_reg_p (ab, reg, targ_reg, xy, predicate) 2289 unsigned int ab; 2290 unsigned int reg; 2291 unsigned int targ_reg; 2292 unsigned int xy; 2293 unsigned int predicate; 2294{ 2295 unw_rec_list *ptr = alloc_record (spill_reg_p); 2296 ptr->r.record.x.ab = ab; 2297 ptr->r.record.x.reg = reg; 2298 ptr->r.record.x.treg = targ_reg; 2299 ptr->r.record.x.xy = xy; 2300 ptr->r.record.x.qp = predicate; 2301 return ptr; 2302} 2303 2304/* Given a unw_rec_list process the correct format with the 2305 specified function. */ 2306 2307static void 2308process_one_record (ptr, f) 2309 unw_rec_list *ptr; 2310 vbyte_func f; 2311{ 2312 unsigned long fr_mask, gr_mask; 2313 2314 switch (ptr->r.type) 2315 { 2316 case gr_mem: 2317 case fr_mem: 2318 case br_mem: 2319 case frgr_mem: 2320 /* These are taken care of by prologue/prologue_gr. */ 2321 break; 2322 2323 case prologue_gr: 2324 case prologue: 2325 if (ptr->r.type == prologue_gr) 2326 output_R2_format (f, ptr->r.record.r.grmask, 2327 ptr->r.record.r.grsave, ptr->r.record.r.rlen); 2328 else 2329 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2330 2331 /* Output descriptor(s) for union of register spills (if any). */ 2332 gr_mask = ptr->r.record.r.mask.gr_mem; 2333 fr_mask = ptr->r.record.r.mask.fr_mem; 2334 if (fr_mask) 2335 { 2336 if ((fr_mask & ~0xfUL) == 0) 2337 output_P6_format (f, fr_mem, fr_mask); 2338 else 2339 { 2340 output_P5_format (f, gr_mask, fr_mask); 2341 gr_mask = 0; 2342 } 2343 } 2344 if (gr_mask) 2345 output_P6_format (f, gr_mem, gr_mask); 2346 if (ptr->r.record.r.mask.br_mem) 2347 output_P1_format (f, ptr->r.record.r.mask.br_mem); 2348 2349 /* output imask descriptor if necessary: */ 2350 if (ptr->r.record.r.mask.i) 2351 output_P4_format (f, ptr->r.record.r.mask.i, 2352 ptr->r.record.r.imask_size); 2353 break; 2354 2355 case body: 2356 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2357 break; 2358 case mem_stack_f: 2359 case mem_stack_v: 2360 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 2361 ptr->r.record.p.size); 2362 break; 2363 case psp_gr: 2364 case rp_gr: 2365 case pfs_gr: 2366 case preds_gr: 2367 case unat_gr: 2368 case lc_gr: 2369 case fpsr_gr: 2370 case priunat_gr: 2371 case bsp_gr: 2372 case bspstore_gr: 2373 case rnat_gr: 2374 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); 2375 break; 2376 case rp_br: 2377 output_P3_format (f, rp_br, ptr->r.record.p.br); 2378 break; 2379 case psp_sprel: 2380 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); 2381 break; 2382 case rp_when: 2383 case pfs_when: 2384 case preds_when: 2385 case unat_when: 2386 case lc_when: 2387 case fpsr_when: 2388 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); 2389 break; 2390 case rp_psprel: 2391 case pfs_psprel: 2392 case preds_psprel: 2393 case unat_psprel: 2394 case lc_psprel: 2395 case fpsr_psprel: 2396 case spill_base: 2397 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); 2398 break; 2399 case rp_sprel: 2400 case pfs_sprel: 2401 case preds_sprel: 2402 case unat_sprel: 2403 case lc_sprel: 2404 case fpsr_sprel: 2405 case priunat_sprel: 2406 case bsp_sprel: 2407 case bspstore_sprel: 2408 case rnat_sprel: 2409 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); 2410 break; 2411 case gr_gr: 2412 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); 2413 break; 2414 case br_gr: 2415 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); 2416 break; 2417 case spill_mask: 2418 as_bad ("spill_mask record unimplemented."); 2419 break; 2420 case priunat_when_gr: 2421 case priunat_when_mem: 2422 case bsp_when: 2423 case bspstore_when: 2424 case rnat_when: 2425 output_P8_format (f, ptr->r.type, ptr->r.record.p.t); 2426 break; 2427 case priunat_psprel: 2428 case bsp_psprel: 2429 case bspstore_psprel: 2430 case rnat_psprel: 2431 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); 2432 break; 2433 case unwabi: 2434 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); 2435 break; 2436 case epilogue: 2437 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); 2438 break; 2439 case label_state: 2440 case copy_state: 2441 output_B4_format (f, ptr->r.type, ptr->r.record.b.label); 2442 break; 2443 case spill_psprel: 2444 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2445 ptr->r.record.x.reg, ptr->r.record.x.t, 2446 ptr->r.record.x.pspoff); 2447 break; 2448 case spill_sprel: 2449 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2450 ptr->r.record.x.reg, ptr->r.record.x.t, 2451 ptr->r.record.x.spoff); 2452 break; 2453 case spill_reg: 2454 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, 2455 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, 2456 ptr->r.record.x.treg, ptr->r.record.x.t); 2457 break; 2458 case spill_psprel_p: 2459 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2460 ptr->r.record.x.ab, ptr->r.record.x.reg, 2461 ptr->r.record.x.t, ptr->r.record.x.pspoff); 2462 break; 2463 case spill_sprel_p: 2464 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2465 ptr->r.record.x.ab, ptr->r.record.x.reg, 2466 ptr->r.record.x.t, ptr->r.record.x.spoff); 2467 break; 2468 case spill_reg_p: 2469 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, 2470 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, 2471 ptr->r.record.x.xy, ptr->r.record.x.treg, 2472 ptr->r.record.x.t); 2473 break; 2474 default: 2475 as_bad ("record_type_not_valid"); 2476 break; 2477 } 2478} 2479 2480/* Given a unw_rec_list list, process all the records with 2481 the specified function. */ 2482static void 2483process_unw_records (list, f) 2484 unw_rec_list *list; 2485 vbyte_func f; 2486{ 2487 unw_rec_list *ptr; 2488 for (ptr = list; ptr; ptr = ptr->next) 2489 process_one_record (ptr, f); 2490} 2491 2492/* Determine the size of a record list in bytes. */ 2493static int 2494calc_record_size (list) 2495 unw_rec_list *list; 2496{ 2497 vbyte_count = 0; 2498 process_unw_records (list, count_output); 2499 return vbyte_count; 2500} 2501 2502/* Update IMASK bitmask to reflect the fact that one or more registers 2503 of type TYPE are saved starting at instruction with index T. If N 2504 bits are set in REGMASK, it is assumed that instructions T through 2505 T+N-1 save these registers. 2506 2507 TYPE values: 2508 0: no save 2509 1: instruction saves next fp reg 2510 2: instruction saves next general reg 2511 3: instruction saves next branch reg */ 2512static void 2513set_imask (region, regmask, t, type) 2514 unw_rec_list *region; 2515 unsigned long regmask; 2516 unsigned long t; 2517 unsigned int type; 2518{ 2519 unsigned char *imask; 2520 unsigned long imask_size; 2521 unsigned int i; 2522 int pos; 2523 2524 imask = region->r.record.r.mask.i; 2525 imask_size = region->r.record.r.imask_size; 2526 if (!imask) 2527 { 2528 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; 2529 imask = xmalloc (imask_size); 2530 memset (imask, 0, imask_size); 2531 2532 region->r.record.r.imask_size = imask_size; 2533 region->r.record.r.mask.i = imask; 2534 } 2535 2536 i = (t / 4) + 1; 2537 pos = 2 * (3 - t % 4); 2538 while (regmask) 2539 { 2540 if (i >= imask_size) 2541 { 2542 as_bad ("Ignoring attempt to spill beyond end of region"); 2543 return; 2544 } 2545 2546 imask[i] |= (type & 0x3) << pos; 2547 2548 regmask &= (regmask - 1); 2549 pos -= 2; 2550 if (pos < 0) 2551 { 2552 pos = 0; 2553 ++i; 2554 } 2555 } 2556} 2557 2558static int 2559count_bits (unsigned long mask) 2560{ 2561 int n = 0; 2562 2563 while (mask) 2564 { 2565 mask &= mask - 1; 2566 ++n; 2567 } 2568 return n; 2569} 2570 2571/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. 2572 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag 2573 containing FIRST_ADDR. */ 2574 2575unsigned long 2576slot_index (slot_addr, slot_frag, first_addr, first_frag) 2577 unsigned long slot_addr; 2578 fragS *slot_frag; 2579 unsigned long first_addr; 2580 fragS *first_frag; 2581{ 2582 unsigned long index = 0; 2583 2584 /* First time we are called, the initial address and frag are invalid. */ 2585 if (first_addr == 0) 2586 return 0; 2587 2588 /* If the two addresses are in different frags, then we need to add in 2589 the remaining size of this frag, and then the entire size of intermediate 2590 frags. */ 2591 while (slot_frag != first_frag) 2592 { 2593 unsigned long start_addr = (unsigned long) &first_frag->fr_literal; 2594 2595 /* Add in the full size of the frag converted to instruction slots. */ 2596 index += 3 * (first_frag->fr_fix >> 4); 2597 /* Subtract away the initial part before first_addr. */ 2598 index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) 2599 + ((first_addr & 0x3) - (start_addr & 0x3))); 2600 2601 /* Move to the beginning of the next frag. */ 2602 first_frag = first_frag->fr_next; 2603 first_addr = (unsigned long) &first_frag->fr_literal; 2604 } 2605 2606 /* Add in the used part of the last frag. */ 2607 index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) 2608 + ((slot_addr & 0x3) - (first_addr & 0x3))); 2609 return index; 2610} 2611 2612/* Optimize unwind record directives. */ 2613 2614static unw_rec_list * 2615optimize_unw_records (list) 2616 unw_rec_list *list; 2617{ 2618 if (!list) 2619 return NULL; 2620 2621 /* If the only unwind record is ".prologue" or ".prologue" followed 2622 by ".body", then we can optimize the unwind directives away. */ 2623 if (list->r.type == prologue 2624 && (list->next == NULL 2625 || (list->next->r.type == body && list->next->next == NULL))) 2626 return NULL; 2627 2628 return list; 2629} 2630 2631/* Given a complete record list, process any records which have 2632 unresolved fields, (ie length counts for a prologue). After 2633 this has been run, all neccessary information should be available 2634 within each record to generate an image. */ 2635 2636static void 2637fixup_unw_records (list) 2638 unw_rec_list *list; 2639{ 2640 unw_rec_list *ptr, *region = 0; 2641 unsigned long first_addr = 0, rlen = 0, t; 2642 fragS *first_frag = 0; 2643 2644 for (ptr = list; ptr; ptr = ptr->next) 2645 { 2646 if (ptr->slot_number == SLOT_NUM_NOT_SET) 2647 as_bad (" Insn slot not set in unwind record."); 2648 t = slot_index (ptr->slot_number, ptr->slot_frag, 2649 first_addr, first_frag); 2650 switch (ptr->r.type) 2651 { 2652 case prologue: 2653 case prologue_gr: 2654 case body: 2655 { 2656 unw_rec_list *last; 2657 int size, dir_len = 0; 2658 unsigned long last_addr; 2659 fragS *last_frag; 2660 2661 first_addr = ptr->slot_number; 2662 first_frag = ptr->slot_frag; 2663 ptr->slot_number = 0; 2664 /* Find either the next body/prologue start, or the end of 2665 the list, and determine the size of the region. */ 2666 last_addr = unwind.next_slot_number; 2667 last_frag = unwind.next_slot_frag; 2668 for (last = ptr->next; last != NULL; last = last->next) 2669 if (last->r.type == prologue || last->r.type == prologue_gr 2670 || last->r.type == body) 2671 { 2672 last_addr = last->slot_number; 2673 last_frag = last->slot_frag; 2674 break; 2675 } 2676 else if (!last->next) 2677 { 2678 /* In the absence of an explicit .body directive, 2679 the prologue ends after the last instruction 2680 covered by an unwind directive. */ 2681 if (ptr->r.type != body) 2682 { 2683 last_addr = last->slot_number; 2684 last_frag = last->slot_frag; 2685 switch (last->r.type) 2686 { 2687 case frgr_mem: 2688 dir_len = (count_bits (last->r.record.p.frmask) 2689 + count_bits (last->r.record.p.grmask)); 2690 break; 2691 case fr_mem: 2692 case gr_mem: 2693 dir_len += count_bits (last->r.record.p.rmask); 2694 break; 2695 case br_mem: 2696 case br_gr: 2697 dir_len += count_bits (last->r.record.p.brmask); 2698 break; 2699 case gr_gr: 2700 dir_len += count_bits (last->r.record.p.grmask); 2701 break; 2702 default: 2703 dir_len = 1; 2704 break; 2705 } 2706 } 2707 break; 2708 } 2709 size = (slot_index (last_addr, last_frag, first_addr, first_frag) 2710 + dir_len); 2711 rlen = ptr->r.record.r.rlen = size; 2712 region = ptr; 2713 break; 2714 } 2715 case epilogue: 2716 ptr->r.record.b.t = rlen - 1 - t; 2717 break; 2718 2719 case mem_stack_f: 2720 case mem_stack_v: 2721 case rp_when: 2722 case pfs_when: 2723 case preds_when: 2724 case unat_when: 2725 case lc_when: 2726 case fpsr_when: 2727 case priunat_when_gr: 2728 case priunat_when_mem: 2729 case bsp_when: 2730 case bspstore_when: 2731 case rnat_when: 2732 ptr->r.record.p.t = t; 2733 break; 2734 2735 case spill_reg: 2736 case spill_sprel: 2737 case spill_psprel: 2738 case spill_reg_p: 2739 case spill_sprel_p: 2740 case spill_psprel_p: 2741 ptr->r.record.x.t = t; 2742 break; 2743 2744 case frgr_mem: 2745 if (!region) 2746 { 2747 as_bad ("frgr_mem record before region record!\n"); 2748 return; 2749 } 2750 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; 2751 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; 2752 set_imask (region, ptr->r.record.p.frmask, t, 1); 2753 set_imask (region, ptr->r.record.p.grmask, t, 2); 2754 break; 2755 case fr_mem: 2756 if (!region) 2757 { 2758 as_bad ("fr_mem record before region record!\n"); 2759 return; 2760 } 2761 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; 2762 set_imask (region, ptr->r.record.p.rmask, t, 1); 2763 break; 2764 case gr_mem: 2765 if (!region) 2766 { 2767 as_bad ("gr_mem record before region record!\n"); 2768 return; 2769 } 2770 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; 2771 set_imask (region, ptr->r.record.p.rmask, t, 2); 2772 break; 2773 case br_mem: 2774 if (!region) 2775 { 2776 as_bad ("br_mem record before region record!\n"); 2777 return; 2778 } 2779 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; 2780 set_imask (region, ptr->r.record.p.brmask, t, 3); 2781 break; 2782 2783 case gr_gr: 2784 if (!region) 2785 { 2786 as_bad ("gr_gr record before region record!\n"); 2787 return; 2788 } 2789 set_imask (region, ptr->r.record.p.grmask, t, 2); 2790 break; 2791 case br_gr: 2792 if (!region) 2793 { 2794 as_bad ("br_gr record before region record!\n"); 2795 return; 2796 } 2797 set_imask (region, ptr->r.record.p.brmask, t, 3); 2798 break; 2799 2800 default: 2801 break; 2802 } 2803 } 2804} 2805 2806/* Helper routine for output_unw_records. Emits the header for the unwind 2807 info. */ 2808 2809static int 2810setup_unwind_header (int size, unsigned char **mem) 2811{ 2812 int x, extra = 0; 2813 valueT flag_value; 2814 2815 /* pad to pointer-size boundry. */ 2816 x = size % md.pointer_size; 2817 if (x != 0) 2818 extra = md.pointer_size - x; 2819 2820 /* Add 8 for the header + a pointer for the 2821 personality offset. */ 2822 *mem = xmalloc (size + extra + 8 + md.pointer_size); 2823 2824 /* Clear the padding area and personality. */ 2825 memset (*mem + 8 + size, 0 , extra + md.pointer_size); 2826 2827 /* Initialize the header area. */ 2828 if (unwind.personality_routine) 2829 { 2830 if (md.flags & EF_IA_64_ABI64) 2831 flag_value = (bfd_vma) 3 << 32; 2832 else 2833 /* 32-bit unwind info block. */ 2834 flag_value = (bfd_vma) 0x1003 << 32; 2835 } 2836 else 2837 flag_value = 0; 2838 2839 md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */ 2840 | flag_value /* U & E handler flags. */ 2841 | ((size + extra) / md.pointer_size)), /* Length. */ 2842 8); 2843 2844 return extra; 2845} 2846 2847/* Generate an unwind image from a record list. Returns the number of 2848 bytes in the resulting image. The memory image itselof is returned 2849 in the 'ptr' parameter. */ 2850static int 2851output_unw_records (list, ptr) 2852 unw_rec_list *list; 2853 void **ptr; 2854{ 2855 int size, extra; 2856 unsigned char *mem; 2857 2858 *ptr = NULL; 2859 2860 list = optimize_unw_records (list); 2861 fixup_unw_records (list); 2862 size = calc_record_size (list); 2863 2864 if (size > 0 || unwind.force_unwind_entry) 2865 { 2866 unwind.force_unwind_entry = 0; 2867 extra = setup_unwind_header (size, &mem); 2868 2869 vbyte_mem_ptr = mem + 8; 2870 process_unw_records (list, output_vbyte_mem); 2871 2872 *ptr = mem; 2873 2874 size += extra + 8 + md.pointer_size; 2875 } 2876 return size; 2877} 2878 2879static int 2880convert_expr_to_ab_reg (e, ab, regp) 2881 expressionS *e; 2882 unsigned int *ab; 2883 unsigned int *regp; 2884{ 2885 unsigned int reg; 2886 2887 if (e->X_op != O_register) 2888 return 0; 2889 2890 reg = e->X_add_number; 2891 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) 2892 { 2893 *ab = 0; 2894 *regp = reg - REG_GR; 2895 } 2896 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) 2897 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) 2898 { 2899 *ab = 1; 2900 *regp = reg - REG_FR; 2901 } 2902 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) 2903 { 2904 *ab = 2; 2905 *regp = reg - REG_BR; 2906 } 2907 else 2908 { 2909 *ab = 3; 2910 switch (reg) 2911 { 2912 case REG_PR: *regp = 0; break; 2913 case REG_PSP: *regp = 1; break; 2914 case REG_PRIUNAT: *regp = 2; break; 2915 case REG_BR + 0: *regp = 3; break; 2916 case REG_AR + AR_BSP: *regp = 4; break; 2917 case REG_AR + AR_BSPSTORE: *regp = 5; break; 2918 case REG_AR + AR_RNAT: *regp = 6; break; 2919 case REG_AR + AR_UNAT: *regp = 7; break; 2920 case REG_AR + AR_FPSR: *regp = 8; break; 2921 case REG_AR + AR_PFS: *regp = 9; break; 2922 case REG_AR + AR_LC: *regp = 10; break; 2923 2924 default: 2925 return 0; 2926 } 2927 } 2928 return 1; 2929} 2930 2931static int 2932convert_expr_to_xy_reg (e, xy, regp) 2933 expressionS *e; 2934 unsigned int *xy; 2935 unsigned int *regp; 2936{ 2937 unsigned int reg; 2938 2939 if (e->X_op != O_register) 2940 return 0; 2941 2942 reg = e->X_add_number; 2943 2944 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) 2945 { 2946 *xy = 0; 2947 *regp = reg - REG_GR; 2948 } 2949 else if (reg >= REG_FR && reg <= (REG_FR + 127)) 2950 { 2951 *xy = 1; 2952 *regp = reg - REG_FR; 2953 } 2954 else if (reg >= REG_BR && reg <= (REG_BR + 7)) 2955 { 2956 *xy = 2; 2957 *regp = reg - REG_BR; 2958 } 2959 else 2960 return -1; 2961 return 1; 2962} 2963 2964static void 2965dot_radix (dummy) 2966 int dummy ATTRIBUTE_UNUSED; 2967{ 2968 int radix; 2969 2970 SKIP_WHITESPACE (); 2971 radix = *input_line_pointer++; 2972 2973 if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) 2974 { 2975 as_bad ("Radix `%c' unsupported", *input_line_pointer); 2976 ignore_rest_of_line (); 2977 return; 2978 } 2979} 2980 2981/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ 2982static void 2983dot_special_section (which) 2984 int which; 2985{ 2986 set_section ((char *) special_section_name[which]); 2987} 2988 2989static void 2990add_unwind_entry (ptr) 2991 unw_rec_list *ptr; 2992{ 2993 if (unwind.tail) 2994 unwind.tail->next = ptr; 2995 else 2996 unwind.list = ptr; 2997 unwind.tail = ptr; 2998 2999 /* The current entry can in fact be a chain of unwind entries. */ 3000 if (unwind.current_entry == NULL) 3001 unwind.current_entry = ptr; 3002} 3003 3004static void 3005dot_fframe (dummy) 3006 int dummy ATTRIBUTE_UNUSED; 3007{ 3008 expressionS e; 3009 3010 parse_operand (&e); 3011 3012 if (e.X_op != O_constant) 3013 as_bad ("Operand to .fframe must be a constant"); 3014 else 3015 add_unwind_entry (output_mem_stack_f (e.X_add_number)); 3016} 3017 3018static void 3019dot_vframe (dummy) 3020 int dummy ATTRIBUTE_UNUSED; 3021{ 3022 expressionS e; 3023 unsigned reg; 3024 3025 parse_operand (&e); 3026 reg = e.X_add_number - REG_GR; 3027 if (e.X_op == O_register && reg < 128) 3028 { 3029 add_unwind_entry (output_mem_stack_v ()); 3030 if (! (unwind.prologue_mask & 2)) 3031 add_unwind_entry (output_psp_gr (reg)); 3032 } 3033 else 3034 as_bad ("First operand to .vframe must be a general register"); 3035} 3036 3037static void 3038dot_vframesp (dummy) 3039 int dummy ATTRIBUTE_UNUSED; 3040{ 3041 expressionS e; 3042 3043 parse_operand (&e); 3044 if (e.X_op == O_constant) 3045 { 3046 add_unwind_entry (output_mem_stack_v ()); 3047 add_unwind_entry (output_psp_sprel (e.X_add_number)); 3048 } 3049 else 3050 as_bad ("First operand to .vframesp must be a general register"); 3051} 3052 3053static void 3054dot_vframepsp (dummy) 3055 int dummy ATTRIBUTE_UNUSED; 3056{ 3057 expressionS e; 3058 3059 parse_operand (&e); 3060 if (e.X_op == O_constant) 3061 { 3062 add_unwind_entry (output_mem_stack_v ()); 3063 add_unwind_entry (output_psp_sprel (e.X_add_number)); 3064 } 3065 else 3066 as_bad ("First operand to .vframepsp must be a general register"); 3067} 3068 3069static void 3070dot_save (dummy) 3071 int dummy ATTRIBUTE_UNUSED; 3072{ 3073 expressionS e1, e2; 3074 int sep; 3075 int reg1, reg2; 3076 3077 sep = parse_operand (&e1); 3078 if (sep != ',') 3079 as_bad ("No second operand to .save"); 3080 sep = parse_operand (&e2); 3081 3082 reg1 = e1.X_add_number; 3083 reg2 = e2.X_add_number - REG_GR; 3084 3085 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3086 if (e1.X_op == O_register) 3087 { 3088 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) 3089 { 3090 switch (reg1) 3091 { 3092 case REG_AR + AR_BSP: 3093 add_unwind_entry (output_bsp_when ()); 3094 add_unwind_entry (output_bsp_gr (reg2)); 3095 break; 3096 case REG_AR + AR_BSPSTORE: 3097 add_unwind_entry (output_bspstore_when ()); 3098 add_unwind_entry (output_bspstore_gr (reg2)); 3099 break; 3100 case REG_AR + AR_RNAT: 3101 add_unwind_entry (output_rnat_when ()); 3102 add_unwind_entry (output_rnat_gr (reg2)); 3103 break; 3104 case REG_AR + AR_UNAT: 3105 add_unwind_entry (output_unat_when ()); 3106 add_unwind_entry (output_unat_gr (reg2)); 3107 break; 3108 case REG_AR + AR_FPSR: 3109 add_unwind_entry (output_fpsr_when ()); 3110 add_unwind_entry (output_fpsr_gr (reg2)); 3111 break; 3112 case REG_AR + AR_PFS: 3113 add_unwind_entry (output_pfs_when ()); 3114 if (! (unwind.prologue_mask & 4)) 3115 add_unwind_entry (output_pfs_gr (reg2)); 3116 break; 3117 case REG_AR + AR_LC: 3118 add_unwind_entry (output_lc_when ()); 3119 add_unwind_entry (output_lc_gr (reg2)); 3120 break; 3121 case REG_BR: 3122 add_unwind_entry (output_rp_when ()); 3123 if (! (unwind.prologue_mask & 8)) 3124 add_unwind_entry (output_rp_gr (reg2)); 3125 break; 3126 case REG_PR: 3127 add_unwind_entry (output_preds_when ()); 3128 if (! (unwind.prologue_mask & 1)) 3129 add_unwind_entry (output_preds_gr (reg2)); 3130 break; 3131 case REG_PRIUNAT: 3132 add_unwind_entry (output_priunat_when_gr ()); 3133 add_unwind_entry (output_priunat_gr (reg2)); 3134 break; 3135 default: 3136 as_bad ("First operand not a valid register"); 3137 } 3138 } 3139 else 3140 as_bad (" Second operand not a valid register"); 3141 } 3142 else 3143 as_bad ("First operand not a register"); 3144} 3145 3146static void 3147dot_restore (dummy) 3148 int dummy ATTRIBUTE_UNUSED; 3149{ 3150 expressionS e1, e2; 3151 unsigned long ecount; /* # of _additional_ regions to pop */ 3152 int sep; 3153 3154 sep = parse_operand (&e1); 3155 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) 3156 { 3157 as_bad ("First operand to .restore must be stack pointer (sp)"); 3158 return; 3159 } 3160 3161 if (sep == ',') 3162 { 3163 parse_operand (&e2); 3164 if (e2.X_op != O_constant || e2.X_add_number < 0) 3165 { 3166 as_bad ("Second operand to .restore must be a constant >= 0"); 3167 return; 3168 } 3169 ecount = e2.X_add_number; 3170 } 3171 else 3172 ecount = unwind.prologue_count - 1; 3173 3174 if (ecount >= unwind.prologue_count) 3175 { 3176 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)", 3177 ecount + 1, unwind.prologue_count); 3178 return; 3179 } 3180 3181 add_unwind_entry (output_epilogue (ecount)); 3182 3183 if (ecount < unwind.prologue_count) 3184 unwind.prologue_count -= ecount + 1; 3185 else 3186 unwind.prologue_count = 0; 3187} 3188 3189static void 3190dot_restorereg (dummy) 3191 int dummy ATTRIBUTE_UNUSED; 3192{ 3193 unsigned int ab, reg; 3194 expressionS e; 3195 3196 parse_operand (&e); 3197 3198 if (!convert_expr_to_ab_reg (&e, &ab, ®)) 3199 { 3200 as_bad ("First operand to .restorereg must be a preserved register"); 3201 return; 3202 } 3203 add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); 3204} 3205 3206static void 3207dot_restorereg_p (dummy) 3208 int dummy ATTRIBUTE_UNUSED; 3209{ 3210 unsigned int qp, ab, reg; 3211 expressionS e1, e2; 3212 int sep; 3213 3214 sep = parse_operand (&e1); 3215 if (sep != ',') 3216 { 3217 as_bad ("No second operand to .restorereg.p"); 3218 return; 3219 } 3220 3221 parse_operand (&e2); 3222 3223 qp = e1.X_add_number - REG_P; 3224 if (e1.X_op != O_register || qp > 63) 3225 { 3226 as_bad ("First operand to .restorereg.p must be a predicate"); 3227 return; 3228 } 3229 3230 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3231 { 3232 as_bad ("Second operand to .restorereg.p must be a preserved register"); 3233 return; 3234 } 3235 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); 3236} 3237 3238static int 3239generate_unwind_image (text_name) 3240 const char *text_name; 3241{ 3242 int size; 3243 unsigned char *unw_rec; 3244 3245 /* Force out pending instructions, to make sure all unwind records have 3246 a valid slot_number field. */ 3247 ia64_flush_insns (); 3248 3249 /* Generate the unwind record. */ 3250 size = output_unw_records (unwind.list, (void **) &unw_rec); 3251 if (size % md.pointer_size != 0) 3252 as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size); 3253 3254 /* If there are unwind records, switch sections, and output the info. */ 3255 if (size != 0) 3256 { 3257 unsigned char *where; 3258 char *sec_name; 3259 expressionS exp; 3260 bfd_reloc_code_real_type reloc; 3261 3262 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); 3263 set_section (sec_name); 3264 bfd_set_section_flags (stdoutput, now_seg, 3265 SEC_LOAD | SEC_ALLOC | SEC_READONLY); 3266 3267 /* Make sure the section has 4 byte alignment for ILP32 and 3268 8 byte alignment for LP64. */ 3269 frag_align (md.pointer_size_shift, 0, 0); 3270 record_alignment (now_seg, md.pointer_size_shift); 3271 3272 /* Set expression which points to start of unwind descriptor area. */ 3273 unwind.info = expr_build_dot (); 3274 3275 where = (unsigned char *) frag_more (size); 3276 3277 /* Issue a label for this address, and keep track of it to put it 3278 in the unwind section. */ 3279 3280 /* Copy the information from the unwind record into this section. The 3281 data is already in the correct byte order. */ 3282 memcpy (where, unw_rec, size); 3283 3284 /* Add the personality address to the image. */ 3285 if (unwind.personality_routine != 0) 3286 { 3287 exp.X_op = O_symbol; 3288 exp.X_add_symbol = unwind.personality_routine; 3289 exp.X_add_number = 0; 3290 3291 if (md.flags & EF_IA_64_BE) 3292 { 3293 if (md.flags & EF_IA_64_ABI64) 3294 reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB; 3295 else 3296 reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB; 3297 } 3298 else 3299 { 3300 if (md.flags & EF_IA_64_ABI64) 3301 reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB; 3302 else 3303 reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB; 3304 } 3305 3306 fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, 3307 md.pointer_size, & exp, 0, reloc); 3308 unwind.personality_routine = 0; 3309 } 3310 } 3311 3312 free_list_records (unwind.list); 3313 free_saved_prologue_counts (); 3314 unwind.list = unwind.tail = unwind.current_entry = NULL; 3315 3316 return size; 3317} 3318 3319static void 3320dot_handlerdata (dummy) 3321 int dummy ATTRIBUTE_UNUSED; 3322{ 3323 const char *text_name = segment_name (now_seg); 3324 3325 /* If text section name starts with ".text" (which it should), 3326 strip this prefix off. */ 3327 if (strcmp (text_name, ".text") == 0) 3328 text_name = ""; 3329 3330 unwind.force_unwind_entry = 1; 3331 3332 /* Remember which segment we're in so we can switch back after .endp */ 3333 unwind.saved_text_seg = now_seg; 3334 unwind.saved_text_subseg = now_subseg; 3335 3336 /* Generate unwind info into unwind-info section and then leave that 3337 section as the currently active one so dataXX directives go into 3338 the language specific data area of the unwind info block. */ 3339 generate_unwind_image (text_name); 3340 demand_empty_rest_of_line (); 3341} 3342 3343static void 3344dot_unwentry (dummy) 3345 int dummy ATTRIBUTE_UNUSED; 3346{ 3347 unwind.force_unwind_entry = 1; 3348 demand_empty_rest_of_line (); 3349} 3350 3351static void 3352dot_altrp (dummy) 3353 int dummy ATTRIBUTE_UNUSED; 3354{ 3355 expressionS e; 3356 unsigned reg; 3357 3358 parse_operand (&e); 3359 reg = e.X_add_number - REG_BR; 3360 if (e.X_op == O_register && reg < 8) 3361 add_unwind_entry (output_rp_br (reg)); 3362 else 3363 as_bad ("First operand not a valid branch register"); 3364} 3365 3366static void 3367dot_savemem (psprel) 3368 int psprel; 3369{ 3370 expressionS e1, e2; 3371 int sep; 3372 int reg1, val; 3373 3374 sep = parse_operand (&e1); 3375 if (sep != ',') 3376 as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); 3377 sep = parse_operand (&e2); 3378 3379 reg1 = e1.X_add_number; 3380 val = e2.X_add_number; 3381 3382 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3383 if (e1.X_op == O_register) 3384 { 3385 if (e2.X_op == O_constant) 3386 { 3387 switch (reg1) 3388 { 3389 case REG_AR + AR_BSP: 3390 add_unwind_entry (output_bsp_when ()); 3391 add_unwind_entry ((psprel 3392 ? output_bsp_psprel 3393 : output_bsp_sprel) (val)); 3394 break; 3395 case REG_AR + AR_BSPSTORE: 3396 add_unwind_entry (output_bspstore_when ()); 3397 add_unwind_entry ((psprel 3398 ? output_bspstore_psprel 3399 : output_bspstore_sprel) (val)); 3400 break; 3401 case REG_AR + AR_RNAT: 3402 add_unwind_entry (output_rnat_when ()); 3403 add_unwind_entry ((psprel 3404 ? output_rnat_psprel 3405 : output_rnat_sprel) (val)); 3406 break; 3407 case REG_AR + AR_UNAT: 3408 add_unwind_entry (output_unat_when ()); 3409 add_unwind_entry ((psprel 3410 ? output_unat_psprel 3411 : output_unat_sprel) (val)); 3412 break; 3413 case REG_AR + AR_FPSR: 3414 add_unwind_entry (output_fpsr_when ()); 3415 add_unwind_entry ((psprel 3416 ? output_fpsr_psprel 3417 : output_fpsr_sprel) (val)); 3418 break; 3419 case REG_AR + AR_PFS: 3420 add_unwind_entry (output_pfs_when ()); 3421 add_unwind_entry ((psprel 3422 ? output_pfs_psprel 3423 : output_pfs_sprel) (val)); 3424 break; 3425 case REG_AR + AR_LC: 3426 add_unwind_entry (output_lc_when ()); 3427 add_unwind_entry ((psprel 3428 ? output_lc_psprel 3429 : output_lc_sprel) (val)); 3430 break; 3431 case REG_BR: 3432 add_unwind_entry (output_rp_when ()); 3433 add_unwind_entry ((psprel 3434 ? output_rp_psprel 3435 : output_rp_sprel) (val)); 3436 break; 3437 case REG_PR: 3438 add_unwind_entry (output_preds_when ()); 3439 add_unwind_entry ((psprel 3440 ? output_preds_psprel 3441 : output_preds_sprel) (val)); 3442 break; 3443 case REG_PRIUNAT: 3444 add_unwind_entry (output_priunat_when_mem ()); 3445 add_unwind_entry ((psprel 3446 ? output_priunat_psprel 3447 : output_priunat_sprel) (val)); 3448 break; 3449 default: 3450 as_bad ("First operand not a valid register"); 3451 } 3452 } 3453 else 3454 as_bad (" Second operand not a valid constant"); 3455 } 3456 else 3457 as_bad ("First operand not a register"); 3458} 3459 3460static void 3461dot_saveg (dummy) 3462 int dummy ATTRIBUTE_UNUSED; 3463{ 3464 expressionS e1, e2; 3465 int sep; 3466 sep = parse_operand (&e1); 3467 if (sep == ',') 3468 parse_operand (&e2); 3469 3470 if (e1.X_op != O_constant) 3471 as_bad ("First operand to .save.g must be a constant."); 3472 else 3473 { 3474 int grmask = e1.X_add_number; 3475 if (sep != ',') 3476 add_unwind_entry (output_gr_mem (grmask)); 3477 else 3478 { 3479 int reg = e2.X_add_number - REG_GR; 3480 if (e2.X_op == O_register && reg >= 0 && reg < 128) 3481 add_unwind_entry (output_gr_gr (grmask, reg)); 3482 else 3483 as_bad ("Second operand is an invalid register."); 3484 } 3485 } 3486} 3487 3488static void 3489dot_savef (dummy) 3490 int dummy ATTRIBUTE_UNUSED; 3491{ 3492 expressionS e1; 3493 int sep; 3494 sep = parse_operand (&e1); 3495 3496 if (e1.X_op != O_constant) 3497 as_bad ("Operand to .save.f must be a constant."); 3498 else 3499 add_unwind_entry (output_fr_mem (e1.X_add_number)); 3500} 3501 3502static void 3503dot_saveb (dummy) 3504 int dummy ATTRIBUTE_UNUSED; 3505{ 3506 expressionS e1, e2; 3507 unsigned int reg; 3508 unsigned char sep; 3509 int brmask; 3510 3511 sep = parse_operand (&e1); 3512 if (e1.X_op != O_constant) 3513 { 3514 as_bad ("First operand to .save.b must be a constant."); 3515 return; 3516 } 3517 brmask = e1.X_add_number; 3518 3519 if (sep == ',') 3520 { 3521 sep = parse_operand (&e2); 3522 reg = e2.X_add_number - REG_GR; 3523 if (e2.X_op != O_register || reg > 127) 3524 { 3525 as_bad ("Second operand to .save.b must be a general register."); 3526 return; 3527 } 3528 add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); 3529 } 3530 else 3531 add_unwind_entry (output_br_mem (brmask)); 3532 3533 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3534 ignore_rest_of_line (); 3535} 3536 3537static void 3538dot_savegf (dummy) 3539 int dummy ATTRIBUTE_UNUSED; 3540{ 3541 expressionS e1, e2; 3542 int sep; 3543 sep = parse_operand (&e1); 3544 if (sep == ',') 3545 parse_operand (&e2); 3546 3547 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) 3548 as_bad ("Both operands of .save.gf must be constants."); 3549 else 3550 { 3551 int grmask = e1.X_add_number; 3552 int frmask = e2.X_add_number; 3553 add_unwind_entry (output_frgr_mem (grmask, frmask)); 3554 } 3555} 3556 3557static void 3558dot_spill (dummy) 3559 int dummy ATTRIBUTE_UNUSED; 3560{ 3561 expressionS e; 3562 unsigned char sep; 3563 3564 sep = parse_operand (&e); 3565 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3566 ignore_rest_of_line (); 3567 3568 if (e.X_op != O_constant) 3569 as_bad ("Operand to .spill must be a constant"); 3570 else 3571 add_unwind_entry (output_spill_base (e.X_add_number)); 3572} 3573 3574static void 3575dot_spillreg (dummy) 3576 int dummy ATTRIBUTE_UNUSED; 3577{ 3578 int sep, ab, xy, reg, treg; 3579 expressionS e1, e2; 3580 3581 sep = parse_operand (&e1); 3582 if (sep != ',') 3583 { 3584 as_bad ("No second operand to .spillreg"); 3585 return; 3586 } 3587 3588 parse_operand (&e2); 3589 3590 if (!convert_expr_to_ab_reg (&e1, &ab, ®)) 3591 { 3592 as_bad ("First operand to .spillreg must be a preserved register"); 3593 return; 3594 } 3595 3596 if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) 3597 { 3598 as_bad ("Second operand to .spillreg must be a register"); 3599 return; 3600 } 3601 3602 add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); 3603} 3604 3605static void 3606dot_spillmem (psprel) 3607 int psprel; 3608{ 3609 expressionS e1, e2; 3610 int sep, ab, reg; 3611 3612 sep = parse_operand (&e1); 3613 if (sep != ',') 3614 { 3615 as_bad ("Second operand missing"); 3616 return; 3617 } 3618 3619 parse_operand (&e2); 3620 3621 if (!convert_expr_to_ab_reg (&e1, &ab, ®)) 3622 { 3623 as_bad ("First operand to .spill%s must be a preserved register", 3624 psprel ? "psp" : "sp"); 3625 return; 3626 } 3627 3628 if (e2.X_op != O_constant) 3629 { 3630 as_bad ("Second operand to .spill%s must be a constant", 3631 psprel ? "psp" : "sp"); 3632 return; 3633 } 3634 3635 if (psprel) 3636 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); 3637 else 3638 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); 3639} 3640 3641static void 3642dot_spillreg_p (dummy) 3643 int dummy ATTRIBUTE_UNUSED; 3644{ 3645 int sep, ab, xy, reg, treg; 3646 expressionS e1, e2, e3; 3647 unsigned int qp; 3648 3649 sep = parse_operand (&e1); 3650 if (sep != ',') 3651 { 3652 as_bad ("No second and third operand to .spillreg.p"); 3653 return; 3654 } 3655 3656 sep = parse_operand (&e2); 3657 if (sep != ',') 3658 { 3659 as_bad ("No third operand to .spillreg.p"); 3660 return; 3661 } 3662 3663 parse_operand (&e3); 3664 3665 qp = e1.X_add_number - REG_P; 3666 3667 if (e1.X_op != O_register || qp > 63) 3668 { 3669 as_bad ("First operand to .spillreg.p must be a predicate"); 3670 return; 3671 } 3672 3673 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3674 { 3675 as_bad ("Second operand to .spillreg.p must be a preserved register"); 3676 return; 3677 } 3678 3679 if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) 3680 { 3681 as_bad ("Third operand to .spillreg.p must be a register"); 3682 return; 3683 } 3684 3685 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); 3686} 3687 3688static void 3689dot_spillmem_p (psprel) 3690 int psprel; 3691{ 3692 expressionS e1, e2, e3; 3693 int sep, ab, reg; 3694 unsigned int qp; 3695 3696 sep = parse_operand (&e1); 3697 if (sep != ',') 3698 { 3699 as_bad ("Second operand missing"); 3700 return; 3701 } 3702 3703 parse_operand (&e2); 3704 if (sep != ',') 3705 { 3706 as_bad ("Second operand missing"); 3707 return; 3708 } 3709 3710 parse_operand (&e3); 3711 3712 qp = e1.X_add_number - REG_P; 3713 if (e1.X_op != O_register || qp > 63) 3714 { 3715 as_bad ("First operand to .spill%s_p must be a predicate", 3716 psprel ? "psp" : "sp"); 3717 return; 3718 } 3719 3720 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3721 { 3722 as_bad ("Second operand to .spill%s_p must be a preserved register", 3723 psprel ? "psp" : "sp"); 3724 return; 3725 } 3726 3727 if (e3.X_op != O_constant) 3728 { 3729 as_bad ("Third operand to .spill%s_p must be a constant", 3730 psprel ? "psp" : "sp"); 3731 return; 3732 } 3733 3734 if (psprel) 3735 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp)); 3736 else 3737 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp)); 3738} 3739 3740static unsigned int 3741get_saved_prologue_count (lbl) 3742 unsigned long lbl; 3743{ 3744 label_prologue_count *lpc = unwind.saved_prologue_counts; 3745 3746 while (lpc != NULL && lpc->label_number != lbl) 3747 lpc = lpc->next; 3748 3749 if (lpc != NULL) 3750 return lpc->prologue_count; 3751 3752 as_bad ("Missing .label_state %ld", lbl); 3753 return 1; 3754} 3755 3756static void 3757save_prologue_count (lbl, count) 3758 unsigned long lbl; 3759 unsigned int count; 3760{ 3761 label_prologue_count *lpc = unwind.saved_prologue_counts; 3762 3763 while (lpc != NULL && lpc->label_number != lbl) 3764 lpc = lpc->next; 3765 3766 if (lpc != NULL) 3767 lpc->prologue_count = count; 3768 else 3769 { 3770 label_prologue_count * new_lpc = xmalloc (sizeof (* new_lpc)); 3771 3772 new_lpc->next = unwind.saved_prologue_counts; 3773 new_lpc->label_number = lbl; 3774 new_lpc->prologue_count = count; 3775 unwind.saved_prologue_counts = new_lpc; 3776 } 3777} 3778 3779static void 3780free_saved_prologue_counts () 3781{ 3782 label_prologue_count * lpc = unwind.saved_prologue_counts; 3783 label_prologue_count * next; 3784 3785 while (lpc != NULL) 3786 { 3787 next = lpc->next; 3788 free (lpc); 3789 lpc = next; 3790 } 3791 3792 unwind.saved_prologue_counts = NULL; 3793} 3794 3795static void 3796dot_label_state (dummy) 3797 int dummy ATTRIBUTE_UNUSED; 3798{ 3799 expressionS e; 3800 3801 parse_operand (&e); 3802 if (e.X_op != O_constant) 3803 { 3804 as_bad ("Operand to .label_state must be a constant"); 3805 return; 3806 } 3807 add_unwind_entry (output_label_state (e.X_add_number)); 3808 save_prologue_count (e.X_add_number, unwind.prologue_count); 3809} 3810 3811static void 3812dot_copy_state (dummy) 3813 int dummy ATTRIBUTE_UNUSED; 3814{ 3815 expressionS e; 3816 3817 parse_operand (&e); 3818 if (e.X_op != O_constant) 3819 { 3820 as_bad ("Operand to .copy_state must be a constant"); 3821 return; 3822 } 3823 add_unwind_entry (output_copy_state (e.X_add_number)); 3824 unwind.prologue_count = get_saved_prologue_count (e.X_add_number); 3825} 3826 3827static void 3828dot_unwabi (dummy) 3829 int dummy ATTRIBUTE_UNUSED; 3830{ 3831 expressionS e1, e2; 3832 unsigned char sep; 3833 3834 sep = parse_operand (&e1); 3835 if (sep != ',') 3836 { 3837 as_bad ("Second operand to .unwabi missing"); 3838 return; 3839 } 3840 sep = parse_operand (&e2); 3841 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3842 ignore_rest_of_line (); 3843 3844 if (e1.X_op != O_constant) 3845 { 3846 as_bad ("First operand to .unwabi must be a constant"); 3847 return; 3848 } 3849 3850 if (e2.X_op != O_constant) 3851 { 3852 as_bad ("Second operand to .unwabi must be a constant"); 3853 return; 3854 } 3855 3856 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); 3857} 3858 3859static void 3860dot_personality (dummy) 3861 int dummy ATTRIBUTE_UNUSED; 3862{ 3863 char *name, *p, c; 3864 SKIP_WHITESPACE (); 3865 name = input_line_pointer; 3866 c = get_symbol_end (); 3867 p = input_line_pointer; 3868 unwind.personality_routine = symbol_find_or_make (name); 3869 unwind.force_unwind_entry = 1; 3870 *p = c; 3871 SKIP_WHITESPACE (); 3872 demand_empty_rest_of_line (); 3873} 3874 3875static void 3876dot_proc (dummy) 3877 int dummy ATTRIBUTE_UNUSED; 3878{ 3879 char *name, *p, c; 3880 symbolS *sym; 3881 3882 unwind.proc_start = expr_build_dot (); 3883 /* Parse names of main and alternate entry points and mark them as 3884 function symbols: */ 3885 while (1) 3886 { 3887 SKIP_WHITESPACE (); 3888 name = input_line_pointer; 3889 c = get_symbol_end (); 3890 p = input_line_pointer; 3891 sym = symbol_find_or_make (name); 3892 if (unwind.proc_start == 0) 3893 { 3894 unwind.proc_start = sym; 3895 } 3896 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; 3897 *p = c; 3898 SKIP_WHITESPACE (); 3899 if (*input_line_pointer != ',') 3900 break; 3901 ++input_line_pointer; 3902 } 3903 demand_empty_rest_of_line (); 3904 ia64_do_align (16); 3905 3906 unwind.prologue_count = 0; 3907 unwind.list = unwind.tail = unwind.current_entry = NULL; 3908 unwind.personality_routine = 0; 3909} 3910 3911static void 3912dot_body (dummy) 3913 int dummy ATTRIBUTE_UNUSED; 3914{ 3915 unwind.prologue = 0; 3916 unwind.prologue_mask = 0; 3917 3918 add_unwind_entry (output_body ()); 3919 demand_empty_rest_of_line (); 3920} 3921 3922static void 3923dot_prologue (dummy) 3924 int dummy ATTRIBUTE_UNUSED; 3925{ 3926 unsigned char sep; 3927 int mask = 0, grsave = 0; 3928 3929 if (!is_it_end_of_statement ()) 3930 { 3931 expressionS e1, e2; 3932 sep = parse_operand (&e1); 3933 if (sep != ',') 3934 as_bad ("No second operand to .prologue"); 3935 sep = parse_operand (&e2); 3936 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3937 ignore_rest_of_line (); 3938 3939 if (e1.X_op == O_constant) 3940 { 3941 mask = e1.X_add_number; 3942 3943 if (e2.X_op == O_constant) 3944 grsave = e2.X_add_number; 3945 else if (e2.X_op == O_register 3946 && (grsave = e2.X_add_number - REG_GR) < 128) 3947 ; 3948 else 3949 as_bad ("Second operand not a constant or general register"); 3950 3951 add_unwind_entry (output_prologue_gr (mask, grsave)); 3952 } 3953 else 3954 as_bad ("First operand not a constant"); 3955 } 3956 else 3957 add_unwind_entry (output_prologue ()); 3958 3959 unwind.prologue = 1; 3960 unwind.prologue_mask = mask; 3961 ++unwind.prologue_count; 3962} 3963 3964static void 3965dot_endp (dummy) 3966 int dummy ATTRIBUTE_UNUSED; 3967{ 3968 expressionS e; 3969 unsigned char *ptr; 3970 int bytes_per_address; 3971 long where; 3972 segT saved_seg; 3973 subsegT saved_subseg; 3974 const char *sec_name, *text_name; 3975 char *name, *p, c; 3976 symbolS *sym; 3977 3978 if (unwind.saved_text_seg) 3979 { 3980 saved_seg = unwind.saved_text_seg; 3981 saved_subseg = unwind.saved_text_subseg; 3982 unwind.saved_text_seg = NULL; 3983 } 3984 else 3985 { 3986 saved_seg = now_seg; 3987 saved_subseg = now_subseg; 3988 } 3989 3990 /* 3991 Use a slightly ugly scheme to derive the unwind section names from 3992 the text section name: 3993 3994 text sect. unwind table sect. 3995 name: name: comments: 3996 ---------- ----------------- -------------------------------- 3997 .text .IA_64.unwind 3998 .text.foo .IA_64.unwind.text.foo 3999 .foo .IA_64.unwind.foo 4000 .gnu.linkonce.t.foo 4001 .gnu.linkonce.ia64unw.foo 4002 _info .IA_64.unwind_info gas issues error message (ditto) 4003 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) 4004 4005 This mapping is done so that: 4006 4007 (a) An object file with unwind info only in .text will use 4008 unwind section names .IA_64.unwind and .IA_64.unwind_info. 4009 This follows the letter of the ABI and also ensures backwards 4010 compatibility with older toolchains. 4011 4012 (b) An object file with unwind info in multiple text sections 4013 will use separate unwind sections for each text section. 4014 This allows us to properly set the "sh_info" and "sh_link" 4015 fields in SHT_IA_64_UNWIND as required by the ABI and also 4016 lets GNU ld support programs with multiple segments 4017 containing unwind info (as might be the case for certain 4018 embedded applications). 4019 4020 (c) An error is issued if there would be a name clash. 4021 */ 4022 text_name = segment_name (saved_seg); 4023 if (strncmp (text_name, "_info", 5) == 0) 4024 { 4025 as_bad ("Illegal section name `%s' (causes unwind section name clash)", 4026 text_name); 4027 ignore_rest_of_line (); 4028 return; 4029 } 4030 if (strcmp (text_name, ".text") == 0) 4031 text_name = ""; 4032 4033 insn_group_break (1, 0, 0); 4034 4035 /* If there wasn't a .handlerdata, we haven't generated an image yet. */ 4036 if (!unwind.info) 4037 generate_unwind_image (text_name); 4038 4039 if (unwind.info || unwind.force_unwind_entry) 4040 { 4041 subseg_set (md.last_text_seg, 0); 4042 unwind.proc_end = expr_build_dot (); 4043 4044 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); 4045 set_section ((char *) sec_name); 4046 bfd_set_section_flags (stdoutput, now_seg, 4047 SEC_LOAD | SEC_ALLOC | SEC_READONLY); 4048 4049 /* Make sure that section has 4 byte alignment for ILP32 and 4050 8 byte alignment for LP64. */ 4051 record_alignment (now_seg, md.pointer_size_shift); 4052 4053 /* Need space for 3 pointers for procedure start, procedure end, 4054 and unwind info. */ 4055 ptr = frag_more (3 * md.pointer_size); 4056 where = frag_now_fix () - (3 * md.pointer_size); 4057 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; 4058 4059 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ 4060 e.X_op = O_pseudo_fixup; 4061 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4062 e.X_add_number = 0; 4063 e.X_add_symbol = unwind.proc_start; 4064 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); 4065 4066 e.X_op = O_pseudo_fixup; 4067 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4068 e.X_add_number = 0; 4069 e.X_add_symbol = unwind.proc_end; 4070 ia64_cons_fix_new (frag_now, where + bytes_per_address, 4071 bytes_per_address, &e); 4072 4073 if (unwind.info) 4074 { 4075 e.X_op = O_pseudo_fixup; 4076 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4077 e.X_add_number = 0; 4078 e.X_add_symbol = unwind.info; 4079 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), 4080 bytes_per_address, &e); 4081 } 4082 else 4083 md_number_to_chars (ptr + (bytes_per_address * 2), 0, 4084 bytes_per_address); 4085 4086 } 4087 subseg_set (saved_seg, saved_subseg); 4088 4089 /* Parse names of main and alternate entry points and set symbol sizes. */ 4090 while (1) 4091 { 4092 SKIP_WHITESPACE (); 4093 name = input_line_pointer; 4094 c = get_symbol_end (); 4095 p = input_line_pointer; 4096 sym = symbol_find (name); 4097 if (sym && unwind.proc_start 4098 && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION) 4099 && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL) 4100 { 4101 fragS *fr = symbol_get_frag (unwind.proc_start); 4102 fragS *frag = symbol_get_frag (sym); 4103 4104 /* Check whether the function label is at or beyond last 4105 .proc directive. */ 4106 while (fr && fr != frag) 4107 fr = fr->fr_next; 4108 if (fr) 4109 { 4110 if (frag == frag_now && SEG_NORMAL (now_seg)) 4111 S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); 4112 else 4113 { 4114 symbol_get_obj (sym)->size = 4115 (expressionS *) xmalloc (sizeof (expressionS)); 4116 symbol_get_obj (sym)->size->X_op = O_subtract; 4117 symbol_get_obj (sym)->size->X_add_symbol 4118 = symbol_new (FAKE_LABEL_NAME, now_seg, 4119 frag_now_fix (), frag_now); 4120 symbol_get_obj (sym)->size->X_op_symbol = sym; 4121 symbol_get_obj (sym)->size->X_add_number = 0; 4122 } 4123 } 4124 } 4125 *p = c; 4126 SKIP_WHITESPACE (); 4127 if (*input_line_pointer != ',') 4128 break; 4129 ++input_line_pointer; 4130 } 4131 demand_empty_rest_of_line (); 4132 unwind.proc_start = unwind.proc_end = unwind.info = 0; 4133} 4134 4135static void 4136dot_template (template) 4137 int template; 4138{ 4139 CURR_SLOT.user_template = template; 4140} 4141 4142static void 4143dot_regstk (dummy) 4144 int dummy ATTRIBUTE_UNUSED; 4145{ 4146 int ins, locs, outs, rots; 4147 4148 if (is_it_end_of_statement ()) 4149 ins = locs = outs = rots = 0; 4150 else 4151 { 4152 ins = get_absolute_expression (); 4153 if (*input_line_pointer++ != ',') 4154 goto err; 4155 locs = get_absolute_expression (); 4156 if (*input_line_pointer++ != ',') 4157 goto err; 4158 outs = get_absolute_expression (); 4159 if (*input_line_pointer++ != ',') 4160 goto err; 4161 rots = get_absolute_expression (); 4162 } 4163 set_regstack (ins, locs, outs, rots); 4164 return; 4165 4166 err: 4167 as_bad ("Comma expected"); 4168 ignore_rest_of_line (); 4169} 4170 4171static void 4172dot_rot (type) 4173 int type; 4174{ 4175 unsigned num_regs, num_alloced = 0; 4176 struct dynreg **drpp, *dr; 4177 int ch, base_reg = 0; 4178 char *name, *start; 4179 size_t len; 4180 4181 switch (type) 4182 { 4183 case DYNREG_GR: base_reg = REG_GR + 32; break; 4184 case DYNREG_FR: base_reg = REG_FR + 32; break; 4185 case DYNREG_PR: base_reg = REG_P + 16; break; 4186 default: break; 4187 } 4188 4189 /* First, remove existing names from hash table. */ 4190 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) 4191 { 4192 hash_delete (md.dynreg_hash, dr->name); 4193 dr->num_regs = 0; 4194 } 4195 4196 drpp = &md.dynreg[type]; 4197 while (1) 4198 { 4199 start = input_line_pointer; 4200 ch = get_symbol_end (); 4201 *input_line_pointer = ch; 4202 len = (input_line_pointer - start); 4203 4204 SKIP_WHITESPACE (); 4205 if (*input_line_pointer != '[') 4206 { 4207 as_bad ("Expected '['"); 4208 goto err; 4209 } 4210 ++input_line_pointer; /* skip '[' */ 4211 4212 num_regs = get_absolute_expression (); 4213 4214 if (*input_line_pointer++ != ']') 4215 { 4216 as_bad ("Expected ']'"); 4217 goto err; 4218 } 4219 SKIP_WHITESPACE (); 4220 4221 num_alloced += num_regs; 4222 switch (type) 4223 { 4224 case DYNREG_GR: 4225 if (num_alloced > md.rot.num_regs) 4226 { 4227 as_bad ("Used more than the declared %d rotating registers", 4228 md.rot.num_regs); 4229 goto err; 4230 } 4231 break; 4232 case DYNREG_FR: 4233 if (num_alloced > 96) 4234 { 4235 as_bad ("Used more than the available 96 rotating registers"); 4236 goto err; 4237 } 4238 break; 4239 case DYNREG_PR: 4240 if (num_alloced > 48) 4241 { 4242 as_bad ("Used more than the available 48 rotating registers"); 4243 goto err; 4244 } 4245 break; 4246 4247 default: 4248 break; 4249 } 4250 4251 name = obstack_alloc (¬es, len + 1); 4252 memcpy (name, start, len); 4253 name[len] = '\0'; 4254 4255 if (!*drpp) 4256 { 4257 *drpp = obstack_alloc (¬es, sizeof (*dr)); 4258 memset (*drpp, 0, sizeof (*dr)); 4259 } 4260 4261 dr = *drpp; 4262 dr->name = name; 4263 dr->num_regs = num_regs; 4264 dr->base = base_reg; 4265 drpp = &dr->next; 4266 base_reg += num_regs; 4267 4268 if (hash_insert (md.dynreg_hash, name, dr)) 4269 { 4270 as_bad ("Attempt to redefine register set `%s'", name); 4271 goto err; 4272 } 4273 4274 if (*input_line_pointer != ',') 4275 break; 4276 ++input_line_pointer; /* skip comma */ 4277 SKIP_WHITESPACE (); 4278 } 4279 demand_empty_rest_of_line (); 4280 return; 4281 4282 err: 4283 ignore_rest_of_line (); 4284} 4285 4286static void 4287dot_byteorder (byteorder) 4288 int byteorder; 4289{ 4290 target_big_endian = byteorder; 4291} 4292 4293static void 4294dot_psr (dummy) 4295 int dummy ATTRIBUTE_UNUSED; 4296{ 4297 char *option; 4298 int ch; 4299 4300 while (1) 4301 { 4302 option = input_line_pointer; 4303 ch = get_symbol_end (); 4304 if (strcmp (option, "lsb") == 0) 4305 md.flags &= ~EF_IA_64_BE; 4306 else if (strcmp (option, "msb") == 0) 4307 md.flags |= EF_IA_64_BE; 4308 else if (strcmp (option, "abi32") == 0) 4309 md.flags &= ~EF_IA_64_ABI64; 4310 else if (strcmp (option, "abi64") == 0) 4311 md.flags |= EF_IA_64_ABI64; 4312 else 4313 as_bad ("Unknown psr option `%s'", option); 4314 *input_line_pointer = ch; 4315 4316 SKIP_WHITESPACE (); 4317 if (*input_line_pointer != ',') 4318 break; 4319 4320 ++input_line_pointer; 4321 SKIP_WHITESPACE (); 4322 } 4323 demand_empty_rest_of_line (); 4324} 4325 4326static void 4327dot_alias (dummy) 4328 int dummy ATTRIBUTE_UNUSED; 4329{ 4330 as_bad (".alias not implemented yet"); 4331} 4332 4333static void 4334dot_ln (dummy) 4335 int dummy ATTRIBUTE_UNUSED; 4336{ 4337 new_logical_line (0, get_absolute_expression ()); 4338 demand_empty_rest_of_line (); 4339} 4340 4341static char * 4342parse_section_name () 4343{ 4344 char *name; 4345 int len; 4346 4347 SKIP_WHITESPACE (); 4348 if (*input_line_pointer != '"') 4349 { 4350 as_bad ("Missing section name"); 4351 ignore_rest_of_line (); 4352 return 0; 4353 } 4354 name = demand_copy_C_string (&len); 4355 if (!name) 4356 { 4357 ignore_rest_of_line (); 4358 return 0; 4359 } 4360 SKIP_WHITESPACE (); 4361 if (*input_line_pointer != ',') 4362 { 4363 as_bad ("Comma expected after section name"); 4364 ignore_rest_of_line (); 4365 return 0; 4366 } 4367 ++input_line_pointer; /* skip comma */ 4368 return name; 4369} 4370 4371static void 4372dot_xdata (size) 4373 int size; 4374{ 4375 char *name = parse_section_name (); 4376 if (!name) 4377 return; 4378 4379 md.keep_pending_output = 1; 4380 set_section (name); 4381 cons (size); 4382 obj_elf_previous (0); 4383 md.keep_pending_output = 0; 4384} 4385 4386/* Why doesn't float_cons() call md_cons_align() the way cons() does? */ 4387 4388static void 4389stmt_float_cons (kind) 4390 int kind; 4391{ 4392 size_t size; 4393 4394 switch (kind) 4395 { 4396 case 'd': size = 8; break; 4397 case 'x': size = 10; break; 4398 4399 case 'f': 4400 default: 4401 size = 4; 4402 break; 4403 } 4404 ia64_do_align (size); 4405 float_cons (kind); 4406} 4407 4408static void 4409stmt_cons_ua (size) 4410 int size; 4411{ 4412 int saved_auto_align = md.auto_align; 4413 4414 md.auto_align = 0; 4415 cons (size); 4416 md.auto_align = saved_auto_align; 4417} 4418 4419static void 4420dot_xfloat_cons (kind) 4421 int kind; 4422{ 4423 char *name = parse_section_name (); 4424 if (!name) 4425 return; 4426 4427 md.keep_pending_output = 1; 4428 set_section (name); 4429 stmt_float_cons (kind); 4430 obj_elf_previous (0); 4431 md.keep_pending_output = 0; 4432} 4433 4434static void 4435dot_xstringer (zero) 4436 int zero; 4437{ 4438 char *name = parse_section_name (); 4439 if (!name) 4440 return; 4441 4442 md.keep_pending_output = 1; 4443 set_section (name); 4444 stringer (zero); 4445 obj_elf_previous (0); 4446 md.keep_pending_output = 0; 4447} 4448 4449static void 4450dot_xdata_ua (size) 4451 int size; 4452{ 4453 int saved_auto_align = md.auto_align; 4454 char *name = parse_section_name (); 4455 if (!name) 4456 return; 4457 4458 md.keep_pending_output = 1; 4459 set_section (name); 4460 md.auto_align = 0; 4461 cons (size); 4462 md.auto_align = saved_auto_align; 4463 obj_elf_previous (0); 4464 md.keep_pending_output = 0; 4465} 4466 4467static void 4468dot_xfloat_cons_ua (kind) 4469 int kind; 4470{ 4471 int saved_auto_align = md.auto_align; 4472 char *name = parse_section_name (); 4473 if (!name) 4474 return; 4475 4476 md.keep_pending_output = 1; 4477 set_section (name); 4478 md.auto_align = 0; 4479 stmt_float_cons (kind); 4480 md.auto_align = saved_auto_align; 4481 obj_elf_previous (0); 4482 md.keep_pending_output = 0; 4483} 4484 4485/* .reg.val <regname>,value */ 4486 4487static void 4488dot_reg_val (dummy) 4489 int dummy ATTRIBUTE_UNUSED; 4490{ 4491 expressionS reg; 4492 4493 expression (®); 4494 if (reg.X_op != O_register) 4495 { 4496 as_bad (_("Register name expected")); 4497 ignore_rest_of_line (); 4498 } 4499 else if (*input_line_pointer++ != ',') 4500 { 4501 as_bad (_("Comma expected")); 4502 ignore_rest_of_line (); 4503 } 4504 else 4505 { 4506 valueT value = get_absolute_expression (); 4507 int regno = reg.X_add_number; 4508 if (regno < REG_GR || regno > REG_GR + 128) 4509 as_warn (_("Register value annotation ignored")); 4510 else 4511 { 4512 gr_values[regno - REG_GR].known = 1; 4513 gr_values[regno - REG_GR].value = value; 4514 gr_values[regno - REG_GR].path = md.path; 4515 } 4516 } 4517 demand_empty_rest_of_line (); 4518} 4519 4520/* select dv checking mode 4521 .auto 4522 .explicit 4523 .default 4524 4525 A stop is inserted when changing modes 4526 */ 4527 4528static void 4529dot_dv_mode (type) 4530 int type; 4531{ 4532 if (md.manual_bundling) 4533 as_warn (_("Directive invalid within a bundle")); 4534 4535 if (type == 'E' || type == 'A') 4536 md.mode_explicitly_set = 0; 4537 else 4538 md.mode_explicitly_set = 1; 4539 4540 md.detect_dv = 1; 4541 switch (type) 4542 { 4543 case 'A': 4544 case 'a': 4545 if (md.explicit_mode) 4546 insn_group_break (1, 0, 0); 4547 md.explicit_mode = 0; 4548 break; 4549 case 'E': 4550 case 'e': 4551 if (!md.explicit_mode) 4552 insn_group_break (1, 0, 0); 4553 md.explicit_mode = 1; 4554 break; 4555 default: 4556 case 'd': 4557 if (md.explicit_mode != md.default_explicit_mode) 4558 insn_group_break (1, 0, 0); 4559 md.explicit_mode = md.default_explicit_mode; 4560 md.mode_explicitly_set = 0; 4561 break; 4562 } 4563} 4564 4565static void 4566print_prmask (mask) 4567 valueT mask; 4568{ 4569 int regno; 4570 char *comma = ""; 4571 for (regno = 0; regno < 64; regno++) 4572 { 4573 if (mask & ((valueT) 1 << regno)) 4574 { 4575 fprintf (stderr, "%s p%d", comma, regno); 4576 comma = ","; 4577 } 4578 } 4579} 4580 4581/* 4582 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") 4583 .pred.rel.imply p1, p2 (also .pred.rel "imply") 4584 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") 4585 .pred.safe_across_calls p1 [, p2 [,...]] 4586 */ 4587 4588static void 4589dot_pred_rel (type) 4590 int type; 4591{ 4592 valueT mask = 0; 4593 int count = 0; 4594 int p1 = -1, p2 = -1; 4595 4596 if (type == 0) 4597 { 4598 if (*input_line_pointer != '"') 4599 { 4600 as_bad (_("Missing predicate relation type")); 4601 ignore_rest_of_line (); 4602 return; 4603 } 4604 else 4605 { 4606 int len; 4607 char *form = demand_copy_C_string (&len); 4608 if (strcmp (form, "mutex") == 0) 4609 type = 'm'; 4610 else if (strcmp (form, "clear") == 0) 4611 type = 'c'; 4612 else if (strcmp (form, "imply") == 0) 4613 type = 'i'; 4614 else 4615 { 4616 as_bad (_("Unrecognized predicate relation type")); 4617 ignore_rest_of_line (); 4618 return; 4619 } 4620 } 4621 if (*input_line_pointer == ',') 4622 ++input_line_pointer; 4623 SKIP_WHITESPACE (); 4624 } 4625 4626 SKIP_WHITESPACE (); 4627 while (1) 4628 { 4629 valueT bit = 1; 4630 int regno; 4631 4632 if (TOUPPER (*input_line_pointer) != 'P' 4633 || (regno = atoi (++input_line_pointer)) < 0 4634 || regno > 63) 4635 { 4636 as_bad (_("Predicate register expected")); 4637 ignore_rest_of_line (); 4638 return; 4639 } 4640 while (ISDIGIT (*input_line_pointer)) 4641 ++input_line_pointer; 4642 if (p1 == -1) 4643 p1 = regno; 4644 else if (p2 == -1) 4645 p2 = regno; 4646 bit <<= regno; 4647 if (mask & bit) 4648 as_warn (_("Duplicate predicate register ignored")); 4649 mask |= bit; 4650 count++; 4651 /* See if it's a range. */ 4652 if (*input_line_pointer == '-') 4653 { 4654 valueT stop = 1; 4655 ++input_line_pointer; 4656 4657 if (TOUPPER (*input_line_pointer) != 'P' 4658 || (regno = atoi (++input_line_pointer)) < 0 4659 || regno > 63) 4660 { 4661 as_bad (_("Predicate register expected")); 4662 ignore_rest_of_line (); 4663 return; 4664 } 4665 while (ISDIGIT (*input_line_pointer)) 4666 ++input_line_pointer; 4667 stop <<= regno; 4668 if (bit >= stop) 4669 { 4670 as_bad (_("Bad register range")); 4671 ignore_rest_of_line (); 4672 return; 4673 } 4674 while (bit < stop) 4675 { 4676 bit <<= 1; 4677 mask |= bit; 4678 count++; 4679 } 4680 SKIP_WHITESPACE (); 4681 } 4682 if (*input_line_pointer != ',') 4683 break; 4684 ++input_line_pointer; 4685 SKIP_WHITESPACE (); 4686 } 4687 4688 switch (type) 4689 { 4690 case 'c': 4691 if (count == 0) 4692 mask = ~(valueT) 0; 4693 clear_qp_mutex (mask); 4694 clear_qp_implies (mask, (valueT) 0); 4695 break; 4696 case 'i': 4697 if (count != 2 || p1 == -1 || p2 == -1) 4698 as_bad (_("Predicate source and target required")); 4699 else if (p1 == 0 || p2 == 0) 4700 as_bad (_("Use of p0 is not valid in this context")); 4701 else 4702 add_qp_imply (p1, p2); 4703 break; 4704 case 'm': 4705 if (count < 2) 4706 { 4707 as_bad (_("At least two PR arguments expected")); 4708 break; 4709 } 4710 else if (mask & 1) 4711 { 4712 as_bad (_("Use of p0 is not valid in this context")); 4713 break; 4714 } 4715 add_qp_mutex (mask); 4716 break; 4717 case 's': 4718 /* note that we don't override any existing relations */ 4719 if (count == 0) 4720 { 4721 as_bad (_("At least one PR argument expected")); 4722 break; 4723 } 4724 if (md.debug_dv) 4725 { 4726 fprintf (stderr, "Safe across calls: "); 4727 print_prmask (mask); 4728 fprintf (stderr, "\n"); 4729 } 4730 qp_safe_across_calls = mask; 4731 break; 4732 } 4733 demand_empty_rest_of_line (); 4734} 4735 4736/* .entry label [, label [, ...]] 4737 Hint to DV code that the given labels are to be considered entry points. 4738 Otherwise, only global labels are considered entry points. */ 4739 4740static void 4741dot_entry (dummy) 4742 int dummy ATTRIBUTE_UNUSED; 4743{ 4744 const char *err; 4745 char *name; 4746 int c; 4747 symbolS *symbolP; 4748 4749 do 4750 { 4751 name = input_line_pointer; 4752 c = get_symbol_end (); 4753 symbolP = symbol_find_or_make (name); 4754 4755 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); 4756 if (err) 4757 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), 4758 name, err); 4759 4760 *input_line_pointer = c; 4761 SKIP_WHITESPACE (); 4762 c = *input_line_pointer; 4763 if (c == ',') 4764 { 4765 input_line_pointer++; 4766 SKIP_WHITESPACE (); 4767 if (*input_line_pointer == '\n') 4768 c = '\n'; 4769 } 4770 } 4771 while (c == ','); 4772 4773 demand_empty_rest_of_line (); 4774} 4775 4776/* .mem.offset offset, base 4777 "base" is used to distinguish between offsets from a different base. */ 4778 4779static void 4780dot_mem_offset (dummy) 4781 int dummy ATTRIBUTE_UNUSED; 4782{ 4783 md.mem_offset.hint = 1; 4784 md.mem_offset.offset = get_absolute_expression (); 4785 if (*input_line_pointer != ',') 4786 { 4787 as_bad (_("Comma expected")); 4788 ignore_rest_of_line (); 4789 return; 4790 } 4791 ++input_line_pointer; 4792 md.mem_offset.base = get_absolute_expression (); 4793 demand_empty_rest_of_line (); 4794} 4795 4796/* ia64-specific pseudo-ops: */ 4797const pseudo_typeS md_pseudo_table[] = 4798 { 4799 { "radix", dot_radix, 0 }, 4800 { "lcomm", s_lcomm_bytes, 1 }, 4801 { "bss", dot_special_section, SPECIAL_SECTION_BSS }, 4802 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, 4803 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, 4804 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, 4805 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, 4806 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, 4807 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, 4808 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, 4809 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, 4810 { "proc", dot_proc, 0 }, 4811 { "body", dot_body, 0 }, 4812 { "prologue", dot_prologue, 0 }, 4813 { "endp", dot_endp, 0 }, 4814 { "file", dwarf2_directive_file, 0 }, 4815 { "loc", dwarf2_directive_loc, 0 }, 4816 4817 { "fframe", dot_fframe, 0 }, 4818 { "vframe", dot_vframe, 0 }, 4819 { "vframesp", dot_vframesp, 0 }, 4820 { "vframepsp", dot_vframepsp, 0 }, 4821 { "save", dot_save, 0 }, 4822 { "restore", dot_restore, 0 }, 4823 { "restorereg", dot_restorereg, 0 }, 4824 { "restorereg.p", dot_restorereg_p, 0 }, 4825 { "handlerdata", dot_handlerdata, 0 }, 4826 { "unwentry", dot_unwentry, 0 }, 4827 { "altrp", dot_altrp, 0 }, 4828 { "savesp", dot_savemem, 0 }, 4829 { "savepsp", dot_savemem, 1 }, 4830 { "save.g", dot_saveg, 0 }, 4831 { "save.f", dot_savef, 0 }, 4832 { "save.b", dot_saveb, 0 }, 4833 { "save.gf", dot_savegf, 0 }, 4834 { "spill", dot_spill, 0 }, 4835 { "spillreg", dot_spillreg, 0 }, 4836 { "spillsp", dot_spillmem, 0 }, 4837 { "spillpsp", dot_spillmem, 1 }, 4838 { "spillreg.p", dot_spillreg_p, 0 }, 4839 { "spillsp.p", dot_spillmem_p, 0 }, 4840 { "spillpsp.p", dot_spillmem_p, 1 }, 4841 { "label_state", dot_label_state, 0 }, 4842 { "copy_state", dot_copy_state, 0 }, 4843 { "unwabi", dot_unwabi, 0 }, 4844 { "personality", dot_personality, 0 }, 4845#if 0 4846 { "estate", dot_estate, 0 }, 4847#endif 4848 { "mii", dot_template, 0x0 }, 4849 { "mli", dot_template, 0x2 }, /* old format, for compatibility */ 4850 { "mlx", dot_template, 0x2 }, 4851 { "mmi", dot_template, 0x4 }, 4852 { "mfi", dot_template, 0x6 }, 4853 { "mmf", dot_template, 0x7 }, 4854 { "mib", dot_template, 0x8 }, 4855 { "mbb", dot_template, 0x9 }, 4856 { "bbb", dot_template, 0xb }, 4857 { "mmb", dot_template, 0xc }, 4858 { "mfb", dot_template, 0xe }, 4859#if 0 4860 { "lb", dot_scope, 0 }, 4861 { "le", dot_scope, 1 }, 4862#endif 4863 { "align", s_align_bytes, 0 }, 4864 { "regstk", dot_regstk, 0 }, 4865 { "rotr", dot_rot, DYNREG_GR }, 4866 { "rotf", dot_rot, DYNREG_FR }, 4867 { "rotp", dot_rot, DYNREG_PR }, 4868 { "lsb", dot_byteorder, 0 }, 4869 { "msb", dot_byteorder, 1 }, 4870 { "psr", dot_psr, 0 }, 4871 { "alias", dot_alias, 0 }, 4872 { "ln", dot_ln, 0 }, /* source line info (for debugging) */ 4873 4874 { "xdata1", dot_xdata, 1 }, 4875 { "xdata2", dot_xdata, 2 }, 4876 { "xdata4", dot_xdata, 4 }, 4877 { "xdata8", dot_xdata, 8 }, 4878 { "xreal4", dot_xfloat_cons, 'f' }, 4879 { "xreal8", dot_xfloat_cons, 'd' }, 4880 { "xreal10", dot_xfloat_cons, 'x' }, 4881 { "xstring", dot_xstringer, 0 }, 4882 { "xstringz", dot_xstringer, 1 }, 4883 4884 /* unaligned versions: */ 4885 { "xdata2.ua", dot_xdata_ua, 2 }, 4886 { "xdata4.ua", dot_xdata_ua, 4 }, 4887 { "xdata8.ua", dot_xdata_ua, 8 }, 4888 { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, 4889 { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, 4890 { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, 4891 4892 /* annotations/DV checking support */ 4893 { "entry", dot_entry, 0 }, 4894 { "mem.offset", dot_mem_offset, 0 }, 4895 { "pred.rel", dot_pred_rel, 0 }, 4896 { "pred.rel.clear", dot_pred_rel, 'c' }, 4897 { "pred.rel.imply", dot_pred_rel, 'i' }, 4898 { "pred.rel.mutex", dot_pred_rel, 'm' }, 4899 { "pred.safe_across_calls", dot_pred_rel, 's' }, 4900 { "reg.val", dot_reg_val, 0 }, 4901 { "auto", dot_dv_mode, 'a' }, 4902 { "explicit", dot_dv_mode, 'e' }, 4903 { "default", dot_dv_mode, 'd' }, 4904 4905 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. 4906 IA-64 aligns data allocation pseudo-ops by default, so we have to 4907 tell it that these ones are supposed to be unaligned. Long term, 4908 should rewrite so that only IA-64 specific data allocation pseudo-ops 4909 are aligned by default. */ 4910 {"2byte", stmt_cons_ua, 2}, 4911 {"4byte", stmt_cons_ua, 4}, 4912 {"8byte", stmt_cons_ua, 8}, 4913 4914 { NULL, 0, 0 } 4915 }; 4916 4917static const struct pseudo_opcode 4918 { 4919 const char *name; 4920 void (*handler) (int); 4921 int arg; 4922 } 4923pseudo_opcode[] = 4924 { 4925 /* these are more like pseudo-ops, but don't start with a dot */ 4926 { "data1", cons, 1 }, 4927 { "data2", cons, 2 }, 4928 { "data4", cons, 4 }, 4929 { "data8", cons, 8 }, 4930 { "data16", cons, 16 }, 4931 { "real4", stmt_float_cons, 'f' }, 4932 { "real8", stmt_float_cons, 'd' }, 4933 { "real10", stmt_float_cons, 'x' }, 4934 { "string", stringer, 0 }, 4935 { "stringz", stringer, 1 }, 4936 4937 /* unaligned versions: */ 4938 { "data2.ua", stmt_cons_ua, 2 }, 4939 { "data4.ua", stmt_cons_ua, 4 }, 4940 { "data8.ua", stmt_cons_ua, 8 }, 4941 { "data16.ua", stmt_cons_ua, 16 }, 4942 { "real4.ua", float_cons, 'f' }, 4943 { "real8.ua", float_cons, 'd' }, 4944 { "real10.ua", float_cons, 'x' }, 4945 }; 4946 4947/* Declare a register by creating a symbol for it and entering it in 4948 the symbol table. */ 4949 4950static symbolS * 4951declare_register (name, regnum) 4952 const char *name; 4953 int regnum; 4954{ 4955 const char *err; 4956 symbolS *sym; 4957 4958 sym = symbol_new (name, reg_section, regnum, &zero_address_frag); 4959 4960 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); 4961 if (err) 4962 as_fatal ("Inserting \"%s\" into register table failed: %s", 4963 name, err); 4964 4965 return sym; 4966} 4967 4968static void 4969declare_register_set (prefix, num_regs, base_regnum) 4970 const char *prefix; 4971 int num_regs; 4972 int base_regnum; 4973{ 4974 char name[8]; 4975 int i; 4976 4977 for (i = 0; i < num_regs; ++i) 4978 { 4979 sprintf (name, "%s%u", prefix, i); 4980 declare_register (name, base_regnum + i); 4981 } 4982} 4983 4984static unsigned int 4985operand_width (opnd) 4986 enum ia64_opnd opnd; 4987{ 4988 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; 4989 unsigned int bits = 0; 4990 int i; 4991 4992 bits = 0; 4993 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) 4994 bits += odesc->field[i].bits; 4995 4996 return bits; 4997} 4998 4999static enum operand_match_result 5000operand_match (idesc, index, e) 5001 const struct ia64_opcode *idesc; 5002 int index; 5003 expressionS *e; 5004{ 5005 enum ia64_opnd opnd = idesc->operands[index]; 5006 int bits, relocatable = 0; 5007 struct insn_fix *fix; 5008 bfd_signed_vma val; 5009 5010 switch (opnd) 5011 { 5012 /* constants: */ 5013 5014 case IA64_OPND_AR_CCV: 5015 if (e->X_op == O_register && e->X_add_number == REG_AR + 32) 5016 return OPERAND_MATCH; 5017 break; 5018 5019 case IA64_OPND_AR_PFS: 5020 if (e->X_op == O_register && e->X_add_number == REG_AR + 64) 5021 return OPERAND_MATCH; 5022 break; 5023 5024 case IA64_OPND_GR0: 5025 if (e->X_op == O_register && e->X_add_number == REG_GR + 0) 5026 return OPERAND_MATCH; 5027 break; 5028 5029 case IA64_OPND_IP: 5030 if (e->X_op == O_register && e->X_add_number == REG_IP) 5031 return OPERAND_MATCH; 5032 break; 5033 5034 case IA64_OPND_PR: 5035 if (e->X_op == O_register && e->X_add_number == REG_PR) 5036 return OPERAND_MATCH; 5037 break; 5038 5039 case IA64_OPND_PR_ROT: 5040 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) 5041 return OPERAND_MATCH; 5042 break; 5043 5044 case IA64_OPND_PSR: 5045 if (e->X_op == O_register && e->X_add_number == REG_PSR) 5046 return OPERAND_MATCH; 5047 break; 5048 5049 case IA64_OPND_PSR_L: 5050 if (e->X_op == O_register && e->X_add_number == REG_PSR_L) 5051 return OPERAND_MATCH; 5052 break; 5053 5054 case IA64_OPND_PSR_UM: 5055 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) 5056 return OPERAND_MATCH; 5057 break; 5058 5059 case IA64_OPND_C1: 5060 if (e->X_op == O_constant) 5061 { 5062 if (e->X_add_number == 1) 5063 return OPERAND_MATCH; 5064 else 5065 return OPERAND_OUT_OF_RANGE; 5066 } 5067 break; 5068 5069 case IA64_OPND_C8: 5070 if (e->X_op == O_constant) 5071 { 5072 if (e->X_add_number == 8) 5073 return OPERAND_MATCH; 5074 else 5075 return OPERAND_OUT_OF_RANGE; 5076 } 5077 break; 5078 5079 case IA64_OPND_C16: 5080 if (e->X_op == O_constant) 5081 { 5082 if (e->X_add_number == 16) 5083 return OPERAND_MATCH; 5084 else 5085 return OPERAND_OUT_OF_RANGE; 5086 } 5087 break; 5088 5089 /* register operands: */ 5090 5091 case IA64_OPND_AR3: 5092 if (e->X_op == O_register && e->X_add_number >= REG_AR 5093 && e->X_add_number < REG_AR + 128) 5094 return OPERAND_MATCH; 5095 break; 5096 5097 case IA64_OPND_B1: 5098 case IA64_OPND_B2: 5099 if (e->X_op == O_register && e->X_add_number >= REG_BR 5100 && e->X_add_number < REG_BR + 8) 5101 return OPERAND_MATCH; 5102 break; 5103 5104 case IA64_OPND_CR3: 5105 if (e->X_op == O_register && e->X_add_number >= REG_CR 5106 && e->X_add_number < REG_CR + 128) 5107 return OPERAND_MATCH; 5108 break; 5109 5110 case IA64_OPND_F1: 5111 case IA64_OPND_F2: 5112 case IA64_OPND_F3: 5113 case IA64_OPND_F4: 5114 if (e->X_op == O_register && e->X_add_number >= REG_FR 5115 && e->X_add_number < REG_FR + 128) 5116 return OPERAND_MATCH; 5117 break; 5118 5119 case IA64_OPND_P1: 5120 case IA64_OPND_P2: 5121 if (e->X_op == O_register && e->X_add_number >= REG_P 5122 && e->X_add_number < REG_P + 64) 5123 return OPERAND_MATCH; 5124 break; 5125 5126 case IA64_OPND_R1: 5127 case IA64_OPND_R2: 5128 case IA64_OPND_R3: 5129 if (e->X_op == O_register && e->X_add_number >= REG_GR 5130 && e->X_add_number < REG_GR + 128) 5131 return OPERAND_MATCH; 5132 break; 5133 5134 case IA64_OPND_R3_2: 5135 if (e->X_op == O_register && e->X_add_number >= REG_GR) 5136 { 5137 if (e->X_add_number < REG_GR + 4) 5138 return OPERAND_MATCH; 5139 else if (e->X_add_number < REG_GR + 128) 5140 return OPERAND_OUT_OF_RANGE; 5141 } 5142 break; 5143 5144 /* indirect operands: */ 5145 case IA64_OPND_CPUID_R3: 5146 case IA64_OPND_DBR_R3: 5147 case IA64_OPND_DTR_R3: 5148 case IA64_OPND_ITR_R3: 5149 case IA64_OPND_IBR_R3: 5150 case IA64_OPND_MSR_R3: 5151 case IA64_OPND_PKR_R3: 5152 case IA64_OPND_PMC_R3: 5153 case IA64_OPND_PMD_R3: 5154 case IA64_OPND_RR_R3: 5155 if (e->X_op == O_index && e->X_op_symbol 5156 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID 5157 == opnd - IA64_OPND_CPUID_R3)) 5158 return OPERAND_MATCH; 5159 break; 5160 5161 case IA64_OPND_MR3: 5162 if (e->X_op == O_index && !e->X_op_symbol) 5163 return OPERAND_MATCH; 5164 break; 5165 5166 /* immediate operands: */ 5167 case IA64_OPND_CNT2a: 5168 case IA64_OPND_LEN4: 5169 case IA64_OPND_LEN6: 5170 bits = operand_width (idesc->operands[index]); 5171 if (e->X_op == O_constant) 5172 { 5173 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) 5174 return OPERAND_MATCH; 5175 else 5176 return OPERAND_OUT_OF_RANGE; 5177 } 5178 break; 5179 5180 case IA64_OPND_CNT2b: 5181 if (e->X_op == O_constant) 5182 { 5183 if ((bfd_vma) (e->X_add_number - 1) < 3) 5184 return OPERAND_MATCH; 5185 else 5186 return OPERAND_OUT_OF_RANGE; 5187 } 5188 break; 5189 5190 case IA64_OPND_CNT2c: 5191 val = e->X_add_number; 5192 if (e->X_op == O_constant) 5193 { 5194 if ((val == 0 || val == 7 || val == 15 || val == 16)) 5195 return OPERAND_MATCH; 5196 else 5197 return OPERAND_OUT_OF_RANGE; 5198 } 5199 break; 5200 5201 case IA64_OPND_SOR: 5202 /* SOR must be an integer multiple of 8 */ 5203 if (e->X_op == O_constant && e->X_add_number & 0x7) 5204 return OPERAND_OUT_OF_RANGE; 5205 case IA64_OPND_SOF: 5206 case IA64_OPND_SOL: 5207 if (e->X_op == O_constant) 5208 { 5209 if ((bfd_vma) e->X_add_number <= 96) 5210 return OPERAND_MATCH; 5211 else 5212 return OPERAND_OUT_OF_RANGE; 5213 } 5214 break; 5215 5216 case IA64_OPND_IMMU62: 5217 if (e->X_op == O_constant) 5218 { 5219 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) 5220 return OPERAND_MATCH; 5221 else 5222 return OPERAND_OUT_OF_RANGE; 5223 } 5224 else 5225 { 5226 /* FIXME -- need 62-bit relocation type */ 5227 as_bad (_("62-bit relocation not yet implemented")); 5228 } 5229 break; 5230 5231 case IA64_OPND_IMMU64: 5232 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup 5233 || e->X_op == O_subtract) 5234 { 5235 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5236 fix->code = BFD_RELOC_IA64_IMM64; 5237 if (e->X_op != O_subtract) 5238 { 5239 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5240 if (e->X_op == O_pseudo_fixup) 5241 e->X_op = O_symbol; 5242 } 5243 5244 fix->opnd = idesc->operands[index]; 5245 fix->expr = *e; 5246 fix->is_pcrel = 0; 5247 ++CURR_SLOT.num_fixups; 5248 return OPERAND_MATCH; 5249 } 5250 else if (e->X_op == O_constant) 5251 return OPERAND_MATCH; 5252 break; 5253 5254 case IA64_OPND_CCNT5: 5255 case IA64_OPND_CNT5: 5256 case IA64_OPND_CNT6: 5257 case IA64_OPND_CPOS6a: 5258 case IA64_OPND_CPOS6b: 5259 case IA64_OPND_CPOS6c: 5260 case IA64_OPND_IMMU2: 5261 case IA64_OPND_IMMU7a: 5262 case IA64_OPND_IMMU7b: 5263 case IA64_OPND_IMMU21: 5264 case IA64_OPND_IMMU24: 5265 case IA64_OPND_MBTYPE4: 5266 case IA64_OPND_MHTYPE8: 5267 case IA64_OPND_POS6: 5268 bits = operand_width (idesc->operands[index]); 5269 if (e->X_op == O_constant) 5270 { 5271 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5272 return OPERAND_MATCH; 5273 else 5274 return OPERAND_OUT_OF_RANGE; 5275 } 5276 break; 5277 5278 case IA64_OPND_IMMU9: 5279 bits = operand_width (idesc->operands[index]); 5280 if (e->X_op == O_constant) 5281 { 5282 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5283 { 5284 int lobits = e->X_add_number & 0x3; 5285 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) 5286 e->X_add_number |= (bfd_vma) 0x3; 5287 return OPERAND_MATCH; 5288 } 5289 else 5290 return OPERAND_OUT_OF_RANGE; 5291 } 5292 break; 5293 5294 case IA64_OPND_IMM44: 5295 /* least 16 bits must be zero */ 5296 if ((e->X_add_number & 0xffff) != 0) 5297 /* XXX technically, this is wrong: we should not be issuing warning 5298 messages until we're sure this instruction pattern is going to 5299 be used! */ 5300 as_warn (_("lower 16 bits of mask ignored")); 5301 5302 if (e->X_op == O_constant) 5303 { 5304 if (((e->X_add_number >= 0 5305 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) 5306 || (e->X_add_number < 0 5307 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) 5308 { 5309 /* sign-extend */ 5310 if (e->X_add_number >= 0 5311 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) 5312 { 5313 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); 5314 } 5315 return OPERAND_MATCH; 5316 } 5317 else 5318 return OPERAND_OUT_OF_RANGE; 5319 } 5320 break; 5321 5322 case IA64_OPND_IMM17: 5323 /* bit 0 is a don't care (pr0 is hardwired to 1) */ 5324 if (e->X_op == O_constant) 5325 { 5326 if (((e->X_add_number >= 0 5327 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) 5328 || (e->X_add_number < 0 5329 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) 5330 { 5331 /* sign-extend */ 5332 if (e->X_add_number >= 0 5333 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) 5334 { 5335 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); 5336 } 5337 return OPERAND_MATCH; 5338 } 5339 else 5340 return OPERAND_OUT_OF_RANGE; 5341 } 5342 break; 5343 5344 case IA64_OPND_IMM14: 5345 case IA64_OPND_IMM22: 5346 relocatable = 1; 5347 case IA64_OPND_IMM1: 5348 case IA64_OPND_IMM8: 5349 case IA64_OPND_IMM8U4: 5350 case IA64_OPND_IMM8M1: 5351 case IA64_OPND_IMM8M1U4: 5352 case IA64_OPND_IMM8M1U8: 5353 case IA64_OPND_IMM9a: 5354 case IA64_OPND_IMM9b: 5355 bits = operand_width (idesc->operands[index]); 5356 if (relocatable && (e->X_op == O_symbol 5357 || e->X_op == O_subtract 5358 || e->X_op == O_pseudo_fixup)) 5359 { 5360 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5361 5362 if (idesc->operands[index] == IA64_OPND_IMM14) 5363 fix->code = BFD_RELOC_IA64_IMM14; 5364 else 5365 fix->code = BFD_RELOC_IA64_IMM22; 5366 5367 if (e->X_op != O_subtract) 5368 { 5369 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5370 if (e->X_op == O_pseudo_fixup) 5371 e->X_op = O_symbol; 5372 } 5373 5374 fix->opnd = idesc->operands[index]; 5375 fix->expr = *e; 5376 fix->is_pcrel = 0; 5377 ++CURR_SLOT.num_fixups; 5378 return OPERAND_MATCH; 5379 } 5380 else if (e->X_op != O_constant 5381 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) 5382 return OPERAND_MISMATCH; 5383 5384 if (opnd == IA64_OPND_IMM8M1U4) 5385 { 5386 /* Zero is not valid for unsigned compares that take an adjusted 5387 constant immediate range. */ 5388 if (e->X_add_number == 0) 5389 return OPERAND_OUT_OF_RANGE; 5390 5391 /* Sign-extend 32-bit unsigned numbers, so that the following range 5392 checks will work. */ 5393 val = e->X_add_number; 5394 if (((val & (~(bfd_vma) 0 << 32)) == 0) 5395 && ((val & ((bfd_vma) 1 << 31)) != 0)) 5396 val = ((val << 32) >> 32); 5397 5398 /* Check for 0x100000000. This is valid because 5399 0x100000000-1 is the same as ((uint32_t) -1). */ 5400 if (val == ((bfd_signed_vma) 1 << 32)) 5401 return OPERAND_MATCH; 5402 5403 val = val - 1; 5404 } 5405 else if (opnd == IA64_OPND_IMM8M1U8) 5406 { 5407 /* Zero is not valid for unsigned compares that take an adjusted 5408 constant immediate range. */ 5409 if (e->X_add_number == 0) 5410 return OPERAND_OUT_OF_RANGE; 5411 5412 /* Check for 0x10000000000000000. */ 5413 if (e->X_op == O_big) 5414 { 5415 if (generic_bignum[0] == 0 5416 && generic_bignum[1] == 0 5417 && generic_bignum[2] == 0 5418 && generic_bignum[3] == 0 5419 && generic_bignum[4] == 1) 5420 return OPERAND_MATCH; 5421 else 5422 return OPERAND_OUT_OF_RANGE; 5423 } 5424 else 5425 val = e->X_add_number - 1; 5426 } 5427 else if (opnd == IA64_OPND_IMM8M1) 5428 val = e->X_add_number - 1; 5429 else if (opnd == IA64_OPND_IMM8U4) 5430 { 5431 /* Sign-extend 32-bit unsigned numbers, so that the following range 5432 checks will work. */ 5433 val = e->X_add_number; 5434 if (((val & (~(bfd_vma) 0 << 32)) == 0) 5435 && ((val & ((bfd_vma) 1 << 31)) != 0)) 5436 val = ((val << 32) >> 32); 5437 } 5438 else 5439 val = e->X_add_number; 5440 5441 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) 5442 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) 5443 return OPERAND_MATCH; 5444 else 5445 return OPERAND_OUT_OF_RANGE; 5446 5447 case IA64_OPND_INC3: 5448 /* +/- 1, 4, 8, 16 */ 5449 val = e->X_add_number; 5450 if (val < 0) 5451 val = -val; 5452 if (e->X_op == O_constant) 5453 { 5454 if ((val == 1 || val == 4 || val == 8 || val == 16)) 5455 return OPERAND_MATCH; 5456 else 5457 return OPERAND_OUT_OF_RANGE; 5458 } 5459 break; 5460 5461 case IA64_OPND_TGT25: 5462 case IA64_OPND_TGT25b: 5463 case IA64_OPND_TGT25c: 5464 case IA64_OPND_TGT64: 5465 if (e->X_op == O_symbol) 5466 { 5467 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5468 if (opnd == IA64_OPND_TGT25) 5469 fix->code = BFD_RELOC_IA64_PCREL21F; 5470 else if (opnd == IA64_OPND_TGT25b) 5471 fix->code = BFD_RELOC_IA64_PCREL21M; 5472 else if (opnd == IA64_OPND_TGT25c) 5473 fix->code = BFD_RELOC_IA64_PCREL21B; 5474 else if (opnd == IA64_OPND_TGT64) 5475 fix->code = BFD_RELOC_IA64_PCREL60B; 5476 else 5477 abort (); 5478 5479 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5480 fix->opnd = idesc->operands[index]; 5481 fix->expr = *e; 5482 fix->is_pcrel = 1; 5483 ++CURR_SLOT.num_fixups; 5484 return OPERAND_MATCH; 5485 } 5486 case IA64_OPND_TAG13: 5487 case IA64_OPND_TAG13b: 5488 switch (e->X_op) 5489 { 5490 case O_constant: 5491 return OPERAND_MATCH; 5492 5493 case O_symbol: 5494 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5495 /* There are no external relocs for TAG13/TAG13b fields, so we 5496 create a dummy reloc. This will not live past md_apply_fix3. */ 5497 fix->code = BFD_RELOC_UNUSED; 5498 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5499 fix->opnd = idesc->operands[index]; 5500 fix->expr = *e; 5501 fix->is_pcrel = 1; 5502 ++CURR_SLOT.num_fixups; 5503 return OPERAND_MATCH; 5504 5505 default: 5506 break; 5507 } 5508 break; 5509 5510 default: 5511 break; 5512 } 5513 return OPERAND_MISMATCH; 5514} 5515 5516static int 5517parse_operand (e) 5518 expressionS *e; 5519{ 5520 int sep = '\0'; 5521 5522 memset (e, 0, sizeof (*e)); 5523 e->X_op = O_absent; 5524 SKIP_WHITESPACE (); 5525 if (*input_line_pointer != '}') 5526 expression (e); 5527 sep = *input_line_pointer++; 5528 5529 if (sep == '}') 5530 { 5531 if (!md.manual_bundling) 5532 as_warn ("Found '}' when manual bundling is off"); 5533 else 5534 CURR_SLOT.manual_bundling_off = 1; 5535 md.manual_bundling = 0; 5536 sep = '\0'; 5537 } 5538 return sep; 5539} 5540 5541/* Returns the next entry in the opcode table that matches the one in 5542 IDESC, and frees the entry in IDESC. If no matching entry is 5543 found, NULL is returned instead. */ 5544 5545static struct ia64_opcode * 5546get_next_opcode (struct ia64_opcode *idesc) 5547{ 5548 struct ia64_opcode *next = ia64_find_next_opcode (idesc); 5549 ia64_free_opcode (idesc); 5550 return next; 5551} 5552 5553/* Parse the operands for the opcode and find the opcode variant that 5554 matches the specified operands, or NULL if no match is possible. */ 5555 5556static struct ia64_opcode * 5557parse_operands (idesc) 5558 struct ia64_opcode *idesc; 5559{ 5560 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; 5561 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; 5562 enum ia64_opnd expected_operand = IA64_OPND_NIL; 5563 enum operand_match_result result; 5564 char mnemonic[129]; 5565 char *first_arg = 0, *end, *saved_input_pointer; 5566 unsigned int sof; 5567 5568 assert (strlen (idesc->name) <= 128); 5569 5570 strcpy (mnemonic, idesc->name); 5571 if (idesc->operands[2] == IA64_OPND_SOF) 5572 { 5573 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we 5574 can't parse the first operand until we have parsed the 5575 remaining operands of the "alloc" instruction. */ 5576 SKIP_WHITESPACE (); 5577 first_arg = input_line_pointer; 5578 end = strchr (input_line_pointer, '='); 5579 if (!end) 5580 { 5581 as_bad ("Expected separator `='"); 5582 return 0; 5583 } 5584 input_line_pointer = end + 1; 5585 ++i; 5586 ++num_outputs; 5587 } 5588 5589 for (; i < NELEMS (CURR_SLOT.opnd); ++i) 5590 { 5591 sep = parse_operand (CURR_SLOT.opnd + i); 5592 if (CURR_SLOT.opnd[i].X_op == O_absent) 5593 break; 5594 5595 ++num_operands; 5596 5597 if (sep != '=' && sep != ',') 5598 break; 5599 5600 if (sep == '=') 5601 { 5602 if (num_outputs > 0) 5603 as_bad ("Duplicate equal sign (=) in instruction"); 5604 else 5605 num_outputs = i + 1; 5606 } 5607 } 5608 if (sep != '\0') 5609 { 5610 as_bad ("Illegal operand separator `%c'", sep); 5611 return 0; 5612 } 5613 5614 if (idesc->operands[2] == IA64_OPND_SOF) 5615 { 5616 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ 5617 know (strcmp (idesc->name, "alloc") == 0); 5618 if (num_operands == 5 /* first_arg not included in this count! */ 5619 && CURR_SLOT.opnd[2].X_op == O_constant 5620 && CURR_SLOT.opnd[3].X_op == O_constant 5621 && CURR_SLOT.opnd[4].X_op == O_constant 5622 && CURR_SLOT.opnd[5].X_op == O_constant) 5623 { 5624 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, 5625 CURR_SLOT.opnd[3].X_add_number, 5626 CURR_SLOT.opnd[4].X_add_number, 5627 CURR_SLOT.opnd[5].X_add_number); 5628 5629 /* now we can parse the first arg: */ 5630 saved_input_pointer = input_line_pointer; 5631 input_line_pointer = first_arg; 5632 sep = parse_operand (CURR_SLOT.opnd + 0); 5633 if (sep != '=') 5634 --num_outputs; /* force error */ 5635 input_line_pointer = saved_input_pointer; 5636 5637 CURR_SLOT.opnd[2].X_add_number = sof; 5638 CURR_SLOT.opnd[3].X_add_number 5639 = sof - CURR_SLOT.opnd[4].X_add_number; 5640 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; 5641 } 5642 } 5643 5644 highest_unmatched_operand = 0; 5645 curr_out_of_range_pos = -1; 5646 error_pos = 0; 5647 expected_operand = idesc->operands[0]; 5648 for (; idesc; idesc = get_next_opcode (idesc)) 5649 { 5650 if (num_outputs != idesc->num_outputs) 5651 continue; /* mismatch in # of outputs */ 5652 5653 CURR_SLOT.num_fixups = 0; 5654 5655 /* Try to match all operands. If we see an out-of-range operand, 5656 then continue trying to match the rest of the operands, since if 5657 the rest match, then this idesc will give the best error message. */ 5658 5659 out_of_range_pos = -1; 5660 for (i = 0; i < num_operands && idesc->operands[i]; ++i) 5661 { 5662 result = operand_match (idesc, i, CURR_SLOT.opnd + i); 5663 if (result != OPERAND_MATCH) 5664 { 5665 if (result != OPERAND_OUT_OF_RANGE) 5666 break; 5667 if (out_of_range_pos < 0) 5668 /* remember position of the first out-of-range operand: */ 5669 out_of_range_pos = i; 5670 } 5671 } 5672 5673 /* If we did not match all operands, or if at least one operand was 5674 out-of-range, then this idesc does not match. Keep track of which 5675 idesc matched the most operands before failing. If we have two 5676 idescs that failed at the same position, and one had an out-of-range 5677 operand, then prefer the out-of-range operand. Thus if we have 5678 "add r0=0x1000000,r1" we get an error saying the constant is out 5679 of range instead of an error saying that the constant should have been 5680 a register. */ 5681 5682 if (i != num_operands || out_of_range_pos >= 0) 5683 { 5684 if (i > highest_unmatched_operand 5685 || (i == highest_unmatched_operand 5686 && out_of_range_pos > curr_out_of_range_pos)) 5687 { 5688 highest_unmatched_operand = i; 5689 if (out_of_range_pos >= 0) 5690 { 5691 expected_operand = idesc->operands[out_of_range_pos]; 5692 error_pos = out_of_range_pos; 5693 } 5694 else 5695 { 5696 expected_operand = idesc->operands[i]; 5697 error_pos = i; 5698 } 5699 curr_out_of_range_pos = out_of_range_pos; 5700 } 5701 continue; 5702 } 5703 5704 if (num_operands < NELEMS (idesc->operands) 5705 && idesc->operands[num_operands]) 5706 continue; /* mismatch in number of arguments */ 5707 5708 break; 5709 } 5710 if (!idesc) 5711 { 5712 if (expected_operand) 5713 as_bad ("Operand %u of `%s' should be %s", 5714 error_pos + 1, mnemonic, 5715 elf64_ia64_operands[expected_operand].desc); 5716 else 5717 as_bad ("Operand mismatch"); 5718 return 0; 5719 } 5720 return idesc; 5721} 5722 5723/* Keep track of state necessary to determine whether a NOP is necessary 5724 to avoid an erratum in A and B step Itanium chips, and return 1 if we 5725 detect a case where additional NOPs may be necessary. */ 5726static int 5727errata_nop_necessary_p (slot, insn_unit) 5728 struct slot *slot; 5729 enum ia64_unit insn_unit; 5730{ 5731 int i; 5732 struct group *this_group = md.last_groups + md.group_idx; 5733 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; 5734 struct ia64_opcode *idesc = slot->idesc; 5735 5736 /* Test whether this could be the first insn in a problematic sequence. */ 5737 if (insn_unit == IA64_UNIT_F) 5738 { 5739 for (i = 0; i < idesc->num_outputs; i++) 5740 if (idesc->operands[i] == IA64_OPND_P1 5741 || idesc->operands[i] == IA64_OPND_P2) 5742 { 5743 int regno = slot->opnd[i].X_add_number - REG_P; 5744 /* Ignore invalid operands; they generate errors elsewhere. */ 5745 if (regno >= 64) 5746 return 0; 5747 this_group->p_reg_set[regno] = 1; 5748 } 5749 } 5750 5751 /* Test whether this could be the second insn in a problematic sequence. */ 5752 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 5753 && prev_group->p_reg_set[slot->qp_regno]) 5754 { 5755 for (i = 0; i < idesc->num_outputs; i++) 5756 if (idesc->operands[i] == IA64_OPND_R1 5757 || idesc->operands[i] == IA64_OPND_R2 5758 || idesc->operands[i] == IA64_OPND_R3) 5759 { 5760 int regno = slot->opnd[i].X_add_number - REG_GR; 5761 /* Ignore invalid operands; they generate errors elsewhere. */ 5762 if (regno >= 128) 5763 return 0; 5764 if (strncmp (idesc->name, "add", 3) != 0 5765 && strncmp (idesc->name, "sub", 3) != 0 5766 && strncmp (idesc->name, "shladd", 6) != 0 5767 && (idesc->flags & IA64_OPCODE_POSTINC) == 0) 5768 this_group->g_reg_set_conditionally[regno] = 1; 5769 } 5770 } 5771 5772 /* Test whether this could be the third insn in a problematic sequence. */ 5773 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) 5774 { 5775 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ 5776 idesc->operands[i] == IA64_OPND_R3 5777 /* For mov indirect. */ 5778 || idesc->operands[i] == IA64_OPND_RR_R3 5779 || idesc->operands[i] == IA64_OPND_DBR_R3 5780 || idesc->operands[i] == IA64_OPND_IBR_R3 5781 || idesc->operands[i] == IA64_OPND_PKR_R3 5782 || idesc->operands[i] == IA64_OPND_PMC_R3 5783 || idesc->operands[i] == IA64_OPND_PMD_R3 5784 || idesc->operands[i] == IA64_OPND_MSR_R3 5785 || idesc->operands[i] == IA64_OPND_CPUID_R3 5786 /* For itr. */ 5787 || idesc->operands[i] == IA64_OPND_ITR_R3 5788 || idesc->operands[i] == IA64_OPND_DTR_R3 5789 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ 5790 || idesc->operands[i] == IA64_OPND_MR3) 5791 { 5792 int regno = slot->opnd[i].X_add_number - REG_GR; 5793 /* Ignore invalid operands; they generate errors elsewhere. */ 5794 if (regno >= 128) 5795 return 0; 5796 if (idesc->operands[i] == IA64_OPND_R3) 5797 { 5798 if (strcmp (idesc->name, "fc") != 0 5799 && strcmp (idesc->name, "tak") != 0 5800 && strcmp (idesc->name, "thash") != 0 5801 && strcmp (idesc->name, "tpa") != 0 5802 && strcmp (idesc->name, "ttag") != 0 5803 && strncmp (idesc->name, "ptr", 3) != 0 5804 && strncmp (idesc->name, "ptc", 3) != 0 5805 && strncmp (idesc->name, "probe", 5) != 0) 5806 return 0; 5807 } 5808 if (prev_group->g_reg_set_conditionally[regno]) 5809 return 1; 5810 } 5811 } 5812 return 0; 5813} 5814 5815static void 5816build_insn (slot, insnp) 5817 struct slot *slot; 5818 bfd_vma *insnp; 5819{ 5820 const struct ia64_operand *odesc, *o2desc; 5821 struct ia64_opcode *idesc = slot->idesc; 5822 bfd_signed_vma insn, val; 5823 const char *err; 5824 int i; 5825 5826 insn = idesc->opcode | slot->qp_regno; 5827 5828 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) 5829 { 5830 if (slot->opnd[i].X_op == O_register 5831 || slot->opnd[i].X_op == O_constant 5832 || slot->opnd[i].X_op == O_index) 5833 val = slot->opnd[i].X_add_number; 5834 else if (slot->opnd[i].X_op == O_big) 5835 { 5836 /* This must be the value 0x10000000000000000. */ 5837 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); 5838 val = 0; 5839 } 5840 else 5841 val = 0; 5842 5843 switch (idesc->operands[i]) 5844 { 5845 case IA64_OPND_IMMU64: 5846 *insnp++ = (val >> 22) & 0x1ffffffffffLL; 5847 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) 5848 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) 5849 | (((val >> 63) & 0x1) << 36)); 5850 continue; 5851 5852 case IA64_OPND_IMMU62: 5853 val &= 0x3fffffffffffffffULL; 5854 if (val != slot->opnd[i].X_add_number) 5855 as_warn (_("Value truncated to 62 bits")); 5856 *insnp++ = (val >> 21) & 0x1ffffffffffLL; 5857 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); 5858 continue; 5859 5860 case IA64_OPND_TGT64: 5861 val >>= 4; 5862 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; 5863 insn |= ((((val >> 59) & 0x1) << 36) 5864 | (((val >> 0) & 0xfffff) << 13)); 5865 continue; 5866 5867 case IA64_OPND_AR3: 5868 val -= REG_AR; 5869 break; 5870 5871 case IA64_OPND_B1: 5872 case IA64_OPND_B2: 5873 val -= REG_BR; 5874 break; 5875 5876 case IA64_OPND_CR3: 5877 val -= REG_CR; 5878 break; 5879 5880 case IA64_OPND_F1: 5881 case IA64_OPND_F2: 5882 case IA64_OPND_F3: 5883 case IA64_OPND_F4: 5884 val -= REG_FR; 5885 break; 5886 5887 case IA64_OPND_P1: 5888 case IA64_OPND_P2: 5889 val -= REG_P; 5890 break; 5891 5892 case IA64_OPND_R1: 5893 case IA64_OPND_R2: 5894 case IA64_OPND_R3: 5895 case IA64_OPND_R3_2: 5896 case IA64_OPND_CPUID_R3: 5897 case IA64_OPND_DBR_R3: 5898 case IA64_OPND_DTR_R3: 5899 case IA64_OPND_ITR_R3: 5900 case IA64_OPND_IBR_R3: 5901 case IA64_OPND_MR3: 5902 case IA64_OPND_MSR_R3: 5903 case IA64_OPND_PKR_R3: 5904 case IA64_OPND_PMC_R3: 5905 case IA64_OPND_PMD_R3: 5906 case IA64_OPND_RR_R3: 5907 val -= REG_GR; 5908 break; 5909 5910 default: 5911 break; 5912 } 5913 5914 odesc = elf64_ia64_operands + idesc->operands[i]; 5915 err = (*odesc->insert) (odesc, val, &insn); 5916 if (err) 5917 as_bad_where (slot->src_file, slot->src_line, 5918 "Bad operand value: %s", err); 5919 if (idesc->flags & IA64_OPCODE_PSEUDO) 5920 { 5921 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) 5922 && odesc == elf64_ia64_operands + IA64_OPND_F3) 5923 { 5924 o2desc = elf64_ia64_operands + IA64_OPND_F2; 5925 (*o2desc->insert) (o2desc, val, &insn); 5926 } 5927 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) 5928 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a 5929 || odesc == elf64_ia64_operands + IA64_OPND_POS6)) 5930 { 5931 o2desc = elf64_ia64_operands + IA64_OPND_LEN6; 5932 (*o2desc->insert) (o2desc, 64 - val, &insn); 5933 } 5934 } 5935 } 5936 *insnp = insn; 5937} 5938 5939static void 5940emit_one_bundle () 5941{ 5942 unsigned int manual_bundling_on = 0, manual_bundling_off = 0; 5943 unsigned int manual_bundling = 0; 5944 enum ia64_unit required_unit, insn_unit = 0; 5945 enum ia64_insn_type type[3], insn_type; 5946 unsigned int template, orig_template; 5947 bfd_vma insn[3] = { -1, -1, -1 }; 5948 struct ia64_opcode *idesc; 5949 int end_of_insn_group = 0, user_template = -1; 5950 int n, i, j, first, curr; 5951 unw_rec_list *ptr; 5952 bfd_vma t0 = 0, t1 = 0; 5953 struct label_fix *lfix; 5954 struct insn_fix *ifix; 5955 char mnemonic[16]; 5956 fixS *fix; 5957 char *f; 5958 5959 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; 5960 know (first >= 0 & first < NUM_SLOTS); 5961 n = MIN (3, md.num_slots_in_use); 5962 5963 /* Determine template: user user_template if specified, best match 5964 otherwise: */ 5965 5966 if (md.slot[first].user_template >= 0) 5967 user_template = template = md.slot[first].user_template; 5968 else 5969 { 5970 /* Auto select appropriate template. */ 5971 memset (type, 0, sizeof (type)); 5972 curr = first; 5973 for (i = 0; i < n; ++i) 5974 { 5975 if (md.slot[curr].label_fixups && i != 0) 5976 break; 5977 type[i] = md.slot[curr].idesc->type; 5978 curr = (curr + 1) % NUM_SLOTS; 5979 } 5980 template = best_template[type[0]][type[1]][type[2]]; 5981 } 5982 5983 /* initialize instructions with appropriate nops: */ 5984 for (i = 0; i < 3; ++i) 5985 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; 5986 5987 f = frag_more (16); 5988 5989 /* now fill in slots with as many insns as possible: */ 5990 curr = first; 5991 idesc = md.slot[curr].idesc; 5992 end_of_insn_group = 0; 5993 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) 5994 { 5995 /* Set the slot number for prologue/body records now as those 5996 refer to the current point, not the point after the 5997 instruction has been issued: */ 5998 /* Don't try to delete prologue/body records here, as that will cause 5999 them to also be deleted from the master list of unwind records. */ 6000 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) 6001 if (ptr->r.type == prologue || ptr->r.type == prologue_gr 6002 || ptr->r.type == body) 6003 { 6004 ptr->slot_number = (unsigned long) f + i; 6005 ptr->slot_frag = frag_now; 6006 } 6007 6008 if (idesc->flags & IA64_OPCODE_SLOT2) 6009 { 6010 if (manual_bundling && i != 2) 6011 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6012 "`%s' must be last in bundle", idesc->name); 6013 else 6014 i = 2; 6015 } 6016 if (idesc->flags & IA64_OPCODE_LAST) 6017 { 6018 int required_slot; 6019 unsigned int required_template; 6020 6021 /* If we need a stop bit after an M slot, our only choice is 6022 template 5 (M;;MI). If we need a stop bit after a B 6023 slot, our only choice is to place it at the end of the 6024 bundle, because the only available templates are MIB, 6025 MBB, BBB, MMB, and MFB. We don't handle anything other 6026 than M and B slots because these are the only kind of 6027 instructions that can have the IA64_OPCODE_LAST bit set. */ 6028 required_template = template; 6029 switch (idesc->type) 6030 { 6031 case IA64_TYPE_M: 6032 required_slot = 0; 6033 required_template = 5; 6034 break; 6035 6036 case IA64_TYPE_B: 6037 required_slot = 2; 6038 break; 6039 6040 default: 6041 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6042 "Internal error: don't know how to force %s to end" 6043 "of instruction group", idesc->name); 6044 required_slot = i; 6045 break; 6046 } 6047 if (manual_bundling && i != required_slot) 6048 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6049 "`%s' must be last in instruction group", 6050 idesc->name); 6051 if (required_slot < i) 6052 /* Can't fit this instruction. */ 6053 break; 6054 6055 i = required_slot; 6056 if (required_template != template) 6057 { 6058 /* If we switch the template, we need to reset the NOPs 6059 after slot i. The slot-types of the instructions ahead 6060 of i never change, so we don't need to worry about 6061 changing NOPs in front of this slot. */ 6062 for (j = i; j < 3; ++j) 6063 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; 6064 } 6065 template = required_template; 6066 } 6067 if (curr != first && md.slot[curr].label_fixups) 6068 { 6069 if (manual_bundling_on) 6070 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6071 "Label must be first in a bundle"); 6072 /* This insn must go into the first slot of a bundle. */ 6073 break; 6074 } 6075 6076 manual_bundling_on = md.slot[curr].manual_bundling_on; 6077 manual_bundling_off = md.slot[curr].manual_bundling_off; 6078 6079 if (manual_bundling_on) 6080 { 6081 if (curr == first) 6082 manual_bundling = 1; 6083 else 6084 break; /* need to start a new bundle */ 6085 } 6086 6087 if (end_of_insn_group && md.num_slots_in_use >= 1) 6088 { 6089 /* We need an instruction group boundary in the middle of a 6090 bundle. See if we can switch to an other template with 6091 an appropriate boundary. */ 6092 6093 orig_template = template; 6094 if (i == 1 && (user_template == 4 6095 || (user_template < 0 6096 && (ia64_templ_desc[template].exec_unit[0] 6097 == IA64_UNIT_M)))) 6098 { 6099 template = 5; 6100 end_of_insn_group = 0; 6101 } 6102 else if (i == 2 && (user_template == 0 6103 || (user_template < 0 6104 && (ia64_templ_desc[template].exec_unit[1] 6105 == IA64_UNIT_I))) 6106 /* This test makes sure we don't switch the template if 6107 the next instruction is one that needs to be first in 6108 an instruction group. Since all those instructions are 6109 in the M group, there is no way such an instruction can 6110 fit in this bundle even if we switch the template. The 6111 reason we have to check for this is that otherwise we 6112 may end up generating "MI;;I M.." which has the deadly 6113 effect that the second M instruction is no longer the 6114 first in the bundle! --davidm 99/12/16 */ 6115 && (idesc->flags & IA64_OPCODE_FIRST) == 0) 6116 { 6117 template = 1; 6118 end_of_insn_group = 0; 6119 } 6120 else if (curr != first) 6121 /* can't fit this insn */ 6122 break; 6123 6124 if (template != orig_template) 6125 /* if we switch the template, we need to reset the NOPs 6126 after slot i. The slot-types of the instructions ahead 6127 of i never change, so we don't need to worry about 6128 changing NOPs in front of this slot. */ 6129 for (j = i; j < 3; ++j) 6130 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; 6131 } 6132 required_unit = ia64_templ_desc[template].exec_unit[i]; 6133 6134 /* resolve dynamic opcodes such as "break" and "nop": */ 6135 if (idesc->type == IA64_TYPE_DYN) 6136 { 6137 if ((strcmp (idesc->name, "nop") == 0) 6138 || (strcmp (idesc->name, "break") == 0)) 6139 insn_unit = required_unit; 6140 else if (strcmp (idesc->name, "chk.s") == 0) 6141 { 6142 insn_unit = IA64_UNIT_M; 6143 if (required_unit == IA64_UNIT_I) 6144 insn_unit = IA64_UNIT_I; 6145 } 6146 else 6147 as_fatal ("emit_one_bundle: unexpected dynamic op"); 6148 6149 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); 6150 ia64_free_opcode (idesc); 6151 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); 6152#if 0 6153 know (!idesc->next); /* no resolved dynamic ops have collisions */ 6154#endif 6155 } 6156 else 6157 { 6158 insn_type = idesc->type; 6159 insn_unit = IA64_UNIT_NIL; 6160 switch (insn_type) 6161 { 6162 case IA64_TYPE_A: 6163 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) 6164 insn_unit = required_unit; 6165 break; 6166 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; 6167 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; 6168 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; 6169 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; 6170 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; 6171 default: break; 6172 } 6173 } 6174 6175 if (insn_unit != required_unit) 6176 { 6177 if (required_unit == IA64_UNIT_L 6178 && insn_unit == IA64_UNIT_I 6179 && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) 6180 { 6181 /* we got ourselves an MLX template but the current 6182 instruction isn't an X-unit, or an I-unit instruction 6183 that can go into the X slot of an MLX template. Duh. */ 6184 if (md.num_slots_in_use >= NUM_SLOTS) 6185 { 6186 as_bad_where (md.slot[curr].src_file, 6187 md.slot[curr].src_line, 6188 "`%s' can't go in X slot of " 6189 "MLX template", idesc->name); 6190 /* drop this insn so we don't livelock: */ 6191 --md.num_slots_in_use; 6192 } 6193 break; 6194 } 6195 continue; /* try next slot */ 6196 } 6197 6198 { 6199 bfd_vma addr; 6200 6201 addr = frag_now->fr_address + frag_now_fix () - 16 + i; 6202 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); 6203 } 6204 6205 if (errata_nop_necessary_p (md.slot + curr, insn_unit)) 6206 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); 6207 6208 build_insn (md.slot + curr, insn + i); 6209 6210 /* Set slot counts for non prologue/body unwind records. */ 6211 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) 6212 if (ptr->r.type != prologue && ptr->r.type != prologue_gr 6213 && ptr->r.type != body) 6214 { 6215 ptr->slot_number = (unsigned long) f + i; 6216 ptr->slot_frag = frag_now; 6217 } 6218 md.slot[curr].unwind_record = NULL; 6219 6220 if (required_unit == IA64_UNIT_L) 6221 { 6222 know (i == 1); 6223 /* skip one slot for long/X-unit instructions */ 6224 ++i; 6225 } 6226 --md.num_slots_in_use; 6227 6228 /* now is a good time to fix up the labels for this insn: */ 6229 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) 6230 { 6231 S_SET_VALUE (lfix->sym, frag_now_fix () - 16); 6232 symbol_set_frag (lfix->sym, frag_now); 6233 } 6234 /* and fix up the tags also. */ 6235 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) 6236 { 6237 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); 6238 symbol_set_frag (lfix->sym, frag_now); 6239 } 6240 6241 for (j = 0; j < md.slot[curr].num_fixups; ++j) 6242 { 6243 ifix = md.slot[curr].fixup + j; 6244 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, 6245 &ifix->expr, ifix->is_pcrel, ifix->code); 6246 fix->tc_fix_data.opnd = ifix->opnd; 6247 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); 6248 fix->fx_file = md.slot[curr].src_file; 6249 fix->fx_line = md.slot[curr].src_line; 6250 } 6251 6252 end_of_insn_group = md.slot[curr].end_of_insn_group; 6253 6254 if (end_of_insn_group) 6255 { 6256 md.group_idx = (md.group_idx + 1) % 3; 6257 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); 6258 } 6259 6260 /* clear slot: */ 6261 ia64_free_opcode (md.slot[curr].idesc); 6262 memset (md.slot + curr, 0, sizeof (md.slot[curr])); 6263 md.slot[curr].user_template = -1; 6264 6265 if (manual_bundling_off) 6266 { 6267 manual_bundling = 0; 6268 break; 6269 } 6270 curr = (curr + 1) % NUM_SLOTS; 6271 idesc = md.slot[curr].idesc; 6272 } 6273 if (manual_bundling) 6274 { 6275 if (md.num_slots_in_use > 0) 6276 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6277 "`%s' does not fit into %s template", 6278 idesc->name, ia64_templ_desc[template].name); 6279 else 6280 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6281 "Missing '}' at end of file"); 6282 } 6283 know (md.num_slots_in_use < NUM_SLOTS); 6284 6285 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); 6286 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 6287 6288 number_to_chars_littleendian (f + 0, t0, 8); 6289 number_to_chars_littleendian (f + 8, t1, 8); 6290 6291 unwind.next_slot_number = (unsigned long) f + 16; 6292 unwind.next_slot_frag = frag_now; 6293} 6294 6295int 6296md_parse_option (c, arg) 6297 int c; 6298 char *arg; 6299{ 6300 6301 switch (c) 6302 { 6303 /* Switches from the Intel assembler. */ 6304 case 'm': 6305 if (strcmp (arg, "ilp64") == 0 6306 || strcmp (arg, "lp64") == 0 6307 || strcmp (arg, "p64") == 0) 6308 { 6309 md.flags |= EF_IA_64_ABI64; 6310 } 6311 else if (strcmp (arg, "ilp32") == 0) 6312 { 6313 md.flags &= ~EF_IA_64_ABI64; 6314 } 6315 else if (strcmp (arg, "le") == 0) 6316 { 6317 md.flags &= ~EF_IA_64_BE; 6318 } 6319 else if (strcmp (arg, "be") == 0) 6320 { 6321 md.flags |= EF_IA_64_BE; 6322 } 6323 else 6324 return 0; 6325 break; 6326 6327 case 'N': 6328 if (strcmp (arg, "so") == 0) 6329 { 6330 /* Suppress signon message. */ 6331 } 6332 else if (strcmp (arg, "pi") == 0) 6333 { 6334 /* Reject privileged instructions. FIXME */ 6335 } 6336 else if (strcmp (arg, "us") == 0) 6337 { 6338 /* Allow union of signed and unsigned range. FIXME */ 6339 } 6340 else if (strcmp (arg, "close_fcalls") == 0) 6341 { 6342 /* Do not resolve global function calls. */ 6343 } 6344 else 6345 return 0; 6346 break; 6347 6348 case 'C': 6349 /* temp[="prefix"] Insert temporary labels into the object file 6350 symbol table prefixed by "prefix". 6351 Default prefix is ":temp:". 6352 */ 6353 break; 6354 6355 case 'a': 6356 /* indirect=<tgt> Assume unannotated indirect branches behavior 6357 according to <tgt> -- 6358 exit: branch out from the current context (default) 6359 labels: all labels in context may be branch targets 6360 */ 6361 if (strncmp (arg, "indirect=", 9) != 0) 6362 return 0; 6363 break; 6364 6365 case 'x': 6366 /* -X conflicts with an ignored option, use -x instead */ 6367 md.detect_dv = 1; 6368 if (!arg || strcmp (arg, "explicit") == 0) 6369 { 6370 /* set default mode to explicit */ 6371 md.default_explicit_mode = 1; 6372 break; 6373 } 6374 else if (strcmp (arg, "auto") == 0) 6375 { 6376 md.default_explicit_mode = 0; 6377 } 6378 else if (strcmp (arg, "debug") == 0) 6379 { 6380 md.debug_dv = 1; 6381 } 6382 else if (strcmp (arg, "debugx") == 0) 6383 { 6384 md.default_explicit_mode = 1; 6385 md.debug_dv = 1; 6386 } 6387 else 6388 { 6389 as_bad (_("Unrecognized option '-x%s'"), arg); 6390 } 6391 break; 6392 6393 case 'S': 6394 /* nops Print nops statistics. */ 6395 break; 6396 6397 /* GNU specific switches for gcc. */ 6398 case OPTION_MCONSTANT_GP: 6399 md.flags |= EF_IA_64_CONS_GP; 6400 break; 6401 6402 case OPTION_MAUTO_PIC: 6403 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; 6404 break; 6405 6406 default: 6407 return 0; 6408 } 6409 6410 return 1; 6411} 6412 6413void 6414md_show_usage (stream) 6415 FILE *stream; 6416{ 6417 fputs (_("\ 6418IA-64 options:\n\ 6419 --mconstant-gp mark output file as using the constant-GP model\n\ 6420 (sets ELF header flag EF_IA_64_CONS_GP)\n\ 6421 --mauto-pic mark output file as using the constant-GP model\n\ 6422 without function descriptors (sets ELF header flag\n\ 6423 EF_IA_64_NOFUNCDESC_CONS_GP)\n\ 6424 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ 6425 -mle | -mbe select little- or big-endian byte order (default -mle)\n\ 6426 -x | -xexplicit turn on dependency violation checking (default)\n\ 6427 -xauto automagically remove dependency violations\n\ 6428 -xdebug debug dependency violation checker\n"), 6429 stream); 6430} 6431 6432void 6433ia64_after_parse_args () 6434{ 6435 if (debug_type == DEBUG_STABS) 6436 as_fatal (_("--gstabs is not supported for ia64")); 6437} 6438 6439/* Return true if TYPE fits in TEMPL at SLOT. */ 6440 6441static int 6442match (int templ, int type, int slot) 6443{ 6444 enum ia64_unit unit; 6445 int result; 6446 6447 unit = ia64_templ_desc[templ].exec_unit[slot]; 6448 switch (type) 6449 { 6450 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ 6451 case IA64_TYPE_A: 6452 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); 6453 break; 6454 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; 6455 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; 6456 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; 6457 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; 6458 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; 6459 default: result = 0; break; 6460 } 6461 return result; 6462} 6463 6464/* Add a bit of extra goodness if a nop of type F or B would fit 6465 in TEMPL at SLOT. */ 6466 6467static inline int 6468extra_goodness (int templ, int slot) 6469{ 6470 if (slot == 1 && match (templ, IA64_TYPE_F, slot)) 6471 return 2; 6472 if (slot == 2 && match (templ, IA64_TYPE_B, slot)) 6473 return 1; 6474 return 0; 6475} 6476 6477/* This function is called once, at assembler startup time. It sets 6478 up all the tables, etc. that the MD part of the assembler will need 6479 that can be determined before arguments are parsed. */ 6480void 6481md_begin () 6482{ 6483 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; 6484 const char *err; 6485 char name[8]; 6486 6487 md.auto_align = 1; 6488 md.explicit_mode = md.default_explicit_mode; 6489 6490 bfd_set_section_alignment (stdoutput, text_section, 4); 6491 6492 target_big_endian = TARGET_BYTES_BIG_ENDIAN; 6493 pseudo_func[FUNC_FPTR_RELATIVE].u.sym = 6494 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, 6495 &zero_address_frag); 6496 6497 pseudo_func[FUNC_GP_RELATIVE].u.sym = 6498 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, 6499 &zero_address_frag); 6500 6501 pseudo_func[FUNC_LT_RELATIVE].u.sym = 6502 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, 6503 &zero_address_frag); 6504 6505 pseudo_func[FUNC_PC_RELATIVE].u.sym = 6506 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, 6507 &zero_address_frag); 6508 6509 pseudo_func[FUNC_PLT_RELATIVE].u.sym = 6510 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, 6511 &zero_address_frag); 6512 6513 pseudo_func[FUNC_SEC_RELATIVE].u.sym = 6514 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, 6515 &zero_address_frag); 6516 6517 pseudo_func[FUNC_SEG_RELATIVE].u.sym = 6518 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, 6519 &zero_address_frag); 6520 6521 pseudo_func[FUNC_LTV_RELATIVE].u.sym = 6522 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, 6523 &zero_address_frag); 6524 6525 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = 6526 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, 6527 &zero_address_frag); 6528 6529 pseudo_func[FUNC_IPLT_RELOC].u.sym = 6530 symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC, 6531 &zero_address_frag); 6532 6533 /* Compute the table of best templates. We compute goodness as a 6534 base 4 value, in which each match counts for 3, each F counts 6535 for 2, each B counts for 1. This should maximize the number of 6536 F and B nops in the chosen bundles, which is good because these 6537 pipelines are least likely to be overcommitted. */ 6538 for (i = 0; i < IA64_NUM_TYPES; ++i) 6539 for (j = 0; j < IA64_NUM_TYPES; ++j) 6540 for (k = 0; k < IA64_NUM_TYPES; ++k) 6541 { 6542 best = 0; 6543 for (t = 0; t < NELEMS (ia64_templ_desc); ++t) 6544 { 6545 goodness = 0; 6546 if (match (t, i, 0)) 6547 { 6548 if (match (t, j, 1)) 6549 { 6550 if (match (t, k, 2)) 6551 goodness = 3 + 3 + 3; 6552 else 6553 goodness = 3 + 3 + extra_goodness (t, 2); 6554 } 6555 else if (match (t, j, 2)) 6556 goodness = 3 + 3 + extra_goodness (t, 1); 6557 else 6558 { 6559 goodness = 3; 6560 goodness += extra_goodness (t, 1); 6561 goodness += extra_goodness (t, 2); 6562 } 6563 } 6564 else if (match (t, i, 1)) 6565 { 6566 if (match (t, j, 2)) 6567 goodness = 3 + 3; 6568 else 6569 goodness = 3 + extra_goodness (t, 2); 6570 } 6571 else if (match (t, i, 2)) 6572 goodness = 3 + extra_goodness (t, 1); 6573 6574 if (goodness > best) 6575 { 6576 best = goodness; 6577 best_template[i][j][k] = t; 6578 } 6579 } 6580 } 6581 6582 for (i = 0; i < NUM_SLOTS; ++i) 6583 md.slot[i].user_template = -1; 6584 6585 md.pseudo_hash = hash_new (); 6586 for (i = 0; i < NELEMS (pseudo_opcode); ++i) 6587 { 6588 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, 6589 (void *) (pseudo_opcode + i)); 6590 if (err) 6591 as_fatal ("ia64.md_begin: can't hash `%s': %s", 6592 pseudo_opcode[i].name, err); 6593 } 6594 6595 md.reg_hash = hash_new (); 6596 md.dynreg_hash = hash_new (); 6597 md.const_hash = hash_new (); 6598 md.entry_hash = hash_new (); 6599 6600 /* general registers: */ 6601 6602 total = 128; 6603 for (i = 0; i < total; ++i) 6604 { 6605 sprintf (name, "r%d", i - REG_GR); 6606 md.regsym[i] = declare_register (name, i); 6607 } 6608 6609 /* floating point registers: */ 6610 total += 128; 6611 for (; i < total; ++i) 6612 { 6613 sprintf (name, "f%d", i - REG_FR); 6614 md.regsym[i] = declare_register (name, i); 6615 } 6616 6617 /* application registers: */ 6618 total += 128; 6619 ar_base = i; 6620 for (; i < total; ++i) 6621 { 6622 sprintf (name, "ar%d", i - REG_AR); 6623 md.regsym[i] = declare_register (name, i); 6624 } 6625 6626 /* control registers: */ 6627 total += 128; 6628 cr_base = i; 6629 for (; i < total; ++i) 6630 { 6631 sprintf (name, "cr%d", i - REG_CR); 6632 md.regsym[i] = declare_register (name, i); 6633 } 6634 6635 /* predicate registers: */ 6636 total += 64; 6637 for (; i < total; ++i) 6638 { 6639 sprintf (name, "p%d", i - REG_P); 6640 md.regsym[i] = declare_register (name, i); 6641 } 6642 6643 /* branch registers: */ 6644 total += 8; 6645 for (; i < total; ++i) 6646 { 6647 sprintf (name, "b%d", i - REG_BR); 6648 md.regsym[i] = declare_register (name, i); 6649 } 6650 6651 md.regsym[REG_IP] = declare_register ("ip", REG_IP); 6652 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); 6653 md.regsym[REG_PR] = declare_register ("pr", REG_PR); 6654 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); 6655 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); 6656 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); 6657 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); 6658 6659 for (i = 0; i < NELEMS (indirect_reg); ++i) 6660 { 6661 regnum = indirect_reg[i].regnum; 6662 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); 6663 } 6664 6665 /* define synonyms for application registers: */ 6666 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) 6667 md.regsym[i] = declare_register (ar[i - REG_AR].name, 6668 REG_AR + ar[i - REG_AR].regnum); 6669 6670 /* define synonyms for control registers: */ 6671 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) 6672 md.regsym[i] = declare_register (cr[i - REG_CR].name, 6673 REG_CR + cr[i - REG_CR].regnum); 6674 6675 declare_register ("gp", REG_GR + 1); 6676 declare_register ("sp", REG_GR + 12); 6677 declare_register ("rp", REG_BR + 0); 6678 6679 /* pseudo-registers used to specify unwind info: */ 6680 declare_register ("psp", REG_PSP); 6681 6682 declare_register_set ("ret", 4, REG_GR + 8); 6683 declare_register_set ("farg", 8, REG_FR + 8); 6684 declare_register_set ("fret", 8, REG_FR + 8); 6685 6686 for (i = 0; i < NELEMS (const_bits); ++i) 6687 { 6688 err = hash_insert (md.const_hash, const_bits[i].name, 6689 (PTR) (const_bits + i)); 6690 if (err) 6691 as_fatal ("Inserting \"%s\" into constant hash table failed: %s", 6692 name, err); 6693 } 6694 6695 /* Set the architecture and machine depending on defaults and command line 6696 options. */ 6697 if (md.flags & EF_IA_64_ABI64) 6698 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); 6699 else 6700 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); 6701 6702 if (! ok) 6703 as_warn (_("Could not set architecture and machine")); 6704 6705 /* Set the pointer size and pointer shift size depending on md.flags */ 6706 6707 if (md.flags & EF_IA_64_ABI64) 6708 { 6709 md.pointer_size = 8; /* pointers are 8 bytes */ 6710 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */ 6711 } 6712 else 6713 { 6714 md.pointer_size = 4; /* pointers are 4 bytes */ 6715 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */ 6716 } 6717 6718 md.mem_offset.hint = 0; 6719 md.path = 0; 6720 md.maxpaths = 0; 6721 md.entry_labels = NULL; 6722} 6723 6724/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin 6725 because that is called after md_parse_option which is where we do the 6726 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the 6727 default endianness. */ 6728 6729void 6730ia64_init (argc, argv) 6731 int argc ATTRIBUTE_UNUSED; 6732 char **argv ATTRIBUTE_UNUSED; 6733{ 6734 md.flags = MD_FLAGS_DEFAULT; 6735} 6736 6737/* Return a string for the target object file format. */ 6738 6739const char * 6740ia64_target_format () 6741{ 6742 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 6743 { 6744 if (md.flags & EF_IA_64_BE) 6745 { 6746 if (md.flags & EF_IA_64_ABI64) 6747#if defined(TE_AIX50) 6748 return "elf64-ia64-aix-big"; 6749#elif defined(TE_HPUX) 6750 return "elf64-ia64-hpux-big"; 6751#else 6752 return "elf64-ia64-big"; 6753#endif 6754 else 6755#if defined(TE_AIX50) 6756 return "elf32-ia64-aix-big"; 6757#elif defined(TE_HPUX) 6758 return "elf32-ia64-hpux-big"; 6759#else 6760 return "elf32-ia64-big"; 6761#endif 6762 } 6763 else 6764 { 6765 if (md.flags & EF_IA_64_ABI64) 6766#ifdef TE_AIX50 6767 return "elf64-ia64-aix-little"; 6768#else 6769 return "elf64-ia64-little"; 6770#endif 6771 else 6772#ifdef TE_AIX50 6773 return "elf32-ia64-aix-little"; 6774#else 6775 return "elf32-ia64-little"; 6776#endif 6777 } 6778 } 6779 else 6780 return "unknown-format"; 6781} 6782 6783void 6784ia64_end_of_source () 6785{ 6786 /* terminate insn group upon reaching end of file: */ 6787 insn_group_break (1, 0, 0); 6788 6789 /* emits slots we haven't written yet: */ 6790 ia64_flush_insns (); 6791 6792 bfd_set_private_flags (stdoutput, md.flags); 6793 6794 md.mem_offset.hint = 0; 6795} 6796 6797void 6798ia64_start_line () 6799{ 6800 if (md.qp.X_op == O_register) 6801 as_bad ("qualifying predicate not followed by instruction"); 6802 md.qp.X_op = O_absent; 6803 6804 if (ignore_input ()) 6805 return; 6806 6807 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') 6808 { 6809 if (md.detect_dv && !md.explicit_mode) 6810 as_warn (_("Explicit stops are ignored in auto mode")); 6811 else 6812 insn_group_break (1, 0, 0); 6813 } 6814} 6815 6816/* This is a hook for ia64_frob_label, so that it can distinguish tags from 6817 labels. */ 6818static int defining_tag = 0; 6819 6820int 6821ia64_unrecognized_line (ch) 6822 int ch; 6823{ 6824 switch (ch) 6825 { 6826 case '(': 6827 expression (&md.qp); 6828 if (*input_line_pointer++ != ')') 6829 { 6830 as_bad ("Expected ')'"); 6831 return 0; 6832 } 6833 if (md.qp.X_op != O_register) 6834 { 6835 as_bad ("Qualifying predicate expected"); 6836 return 0; 6837 } 6838 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) 6839 { 6840 as_bad ("Predicate register expected"); 6841 return 0; 6842 } 6843 return 1; 6844 6845 case '{': 6846 if (md.manual_bundling) 6847 as_warn ("Found '{' when manual bundling is already turned on"); 6848 else 6849 CURR_SLOT.manual_bundling_on = 1; 6850 md.manual_bundling = 1; 6851 6852 /* Bundling is only acceptable in explicit mode 6853 or when in default automatic mode. */ 6854 if (md.detect_dv && !md.explicit_mode) 6855 { 6856 if (!md.mode_explicitly_set 6857 && !md.default_explicit_mode) 6858 dot_dv_mode ('E'); 6859 else 6860 as_warn (_("Found '{' after explicit switch to automatic mode")); 6861 } 6862 return 1; 6863 6864 case '}': 6865 if (!md.manual_bundling) 6866 as_warn ("Found '}' when manual bundling is off"); 6867 else 6868 PREV_SLOT.manual_bundling_off = 1; 6869 md.manual_bundling = 0; 6870 6871 /* switch back to automatic mode, if applicable */ 6872 if (md.detect_dv 6873 && md.explicit_mode 6874 && !md.mode_explicitly_set 6875 && !md.default_explicit_mode) 6876 dot_dv_mode ('A'); 6877 6878 /* Allow '{' to follow on the same line. We also allow ";;", but that 6879 happens automatically because ';' is an end of line marker. */ 6880 SKIP_WHITESPACE (); 6881 if (input_line_pointer[0] == '{') 6882 { 6883 input_line_pointer++; 6884 return ia64_unrecognized_line ('{'); 6885 } 6886 6887 demand_empty_rest_of_line (); 6888 return 1; 6889 6890 case '[': 6891 { 6892 char *s; 6893 char c; 6894 symbolS *tag; 6895 int temp; 6896 6897 if (md.qp.X_op == O_register) 6898 { 6899 as_bad ("Tag must come before qualifying predicate."); 6900 return 0; 6901 } 6902 6903 /* This implements just enough of read_a_source_file in read.c to 6904 recognize labels. */ 6905 if (is_name_beginner (*input_line_pointer)) 6906 { 6907 s = input_line_pointer; 6908 c = get_symbol_end (); 6909 } 6910 else if (LOCAL_LABELS_FB 6911 && ISDIGIT (*input_line_pointer)) 6912 { 6913 temp = 0; 6914 while (ISDIGIT (*input_line_pointer)) 6915 temp = (temp * 10) + *input_line_pointer++ - '0'; 6916 fb_label_instance_inc (temp); 6917 s = fb_label_name (temp, 0); 6918 c = *input_line_pointer; 6919 } 6920 else 6921 { 6922 s = NULL; 6923 c = '\0'; 6924 } 6925 if (c != ':') 6926 { 6927 /* Put ':' back for error messages' sake. */ 6928 *input_line_pointer++ = ':'; 6929 as_bad ("Expected ':'"); 6930 return 0; 6931 } 6932 6933 defining_tag = 1; 6934 tag = colon (s); 6935 defining_tag = 0; 6936 /* Put ':' back for error messages' sake. */ 6937 *input_line_pointer++ = ':'; 6938 if (*input_line_pointer++ != ']') 6939 { 6940 as_bad ("Expected ']'"); 6941 return 0; 6942 } 6943 if (! tag) 6944 { 6945 as_bad ("Tag name expected"); 6946 return 0; 6947 } 6948 return 1; 6949 } 6950 6951 default: 6952 break; 6953 } 6954 6955 /* Not a valid line. */ 6956 return 0; 6957} 6958 6959void 6960ia64_frob_label (sym) 6961 struct symbol *sym; 6962{ 6963 struct label_fix *fix; 6964 6965 /* Tags need special handling since they are not bundle breaks like 6966 labels. */ 6967 if (defining_tag) 6968 { 6969 fix = obstack_alloc (¬es, sizeof (*fix)); 6970 fix->sym = sym; 6971 fix->next = CURR_SLOT.tag_fixups; 6972 CURR_SLOT.tag_fixups = fix; 6973 6974 return; 6975 } 6976 6977 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) 6978 { 6979 md.last_text_seg = now_seg; 6980 fix = obstack_alloc (¬es, sizeof (*fix)); 6981 fix->sym = sym; 6982 fix->next = CURR_SLOT.label_fixups; 6983 CURR_SLOT.label_fixups = fix; 6984 6985 /* Keep track of how many code entry points we've seen. */ 6986 if (md.path == md.maxpaths) 6987 { 6988 md.maxpaths += 20; 6989 md.entry_labels = (const char **) 6990 xrealloc ((void *) md.entry_labels, 6991 md.maxpaths * sizeof (char *)); 6992 } 6993 md.entry_labels[md.path++] = S_GET_NAME (sym); 6994 } 6995} 6996 6997void 6998ia64_flush_pending_output () 6999{ 7000 if (!md.keep_pending_output 7001 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) 7002 { 7003 /* ??? This causes many unnecessary stop bits to be emitted. 7004 Unfortunately, it isn't clear if it is safe to remove this. */ 7005 insn_group_break (1, 0, 0); 7006 ia64_flush_insns (); 7007 } 7008} 7009 7010/* Do ia64-specific expression optimization. All that's done here is 7011 to transform index expressions that are either due to the indexing 7012 of rotating registers or due to the indexing of indirect register 7013 sets. */ 7014int 7015ia64_optimize_expr (l, op, r) 7016 expressionS *l; 7017 operatorT op; 7018 expressionS *r; 7019{ 7020 unsigned num_regs; 7021 7022 if (op == O_index) 7023 { 7024 if (l->X_op == O_register && r->X_op == O_constant) 7025 { 7026 num_regs = (l->X_add_number >> 16); 7027 if ((unsigned) r->X_add_number >= num_regs) 7028 { 7029 if (!num_regs) 7030 as_bad ("No current frame"); 7031 else 7032 as_bad ("Index out of range 0..%u", num_regs - 1); 7033 r->X_add_number = 0; 7034 } 7035 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; 7036 return 1; 7037 } 7038 else if (l->X_op == O_register && r->X_op == O_register) 7039 { 7040 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR 7041 || l->X_add_number == IND_MEM) 7042 { 7043 as_bad ("Indirect register set name expected"); 7044 l->X_add_number = IND_CPUID; 7045 } 7046 l->X_op = O_index; 7047 l->X_op_symbol = md.regsym[l->X_add_number]; 7048 l->X_add_number = r->X_add_number; 7049 return 1; 7050 } 7051 } 7052 return 0; 7053} 7054 7055int 7056ia64_parse_name (name, e) 7057 char *name; 7058 expressionS *e; 7059{ 7060 struct const_desc *cdesc; 7061 struct dynreg *dr = 0; 7062 unsigned int regnum; 7063 struct symbol *sym; 7064 char *end; 7065 7066 /* first see if NAME is a known register name: */ 7067 sym = hash_find (md.reg_hash, name); 7068 if (sym) 7069 { 7070 e->X_op = O_register; 7071 e->X_add_number = S_GET_VALUE (sym); 7072 return 1; 7073 } 7074 7075 cdesc = hash_find (md.const_hash, name); 7076 if (cdesc) 7077 { 7078 e->X_op = O_constant; 7079 e->X_add_number = cdesc->value; 7080 return 1; 7081 } 7082 7083 /* check for inN, locN, or outN: */ 7084 switch (name[0]) 7085 { 7086 case 'i': 7087 if (name[1] == 'n' && ISDIGIT (name[2])) 7088 { 7089 dr = &md.in; 7090 name += 2; 7091 } 7092 break; 7093 7094 case 'l': 7095 if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3])) 7096 { 7097 dr = &md.loc; 7098 name += 3; 7099 } 7100 break; 7101 7102 case 'o': 7103 if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3])) 7104 { 7105 dr = &md.out; 7106 name += 3; 7107 } 7108 break; 7109 7110 default: 7111 break; 7112 } 7113 7114 if (dr) 7115 { 7116 /* The name is inN, locN, or outN; parse the register number. */ 7117 regnum = strtoul (name, &end, 10); 7118 if (end > name && *end == '\0') 7119 { 7120 if ((unsigned) regnum >= dr->num_regs) 7121 { 7122 if (!dr->num_regs) 7123 as_bad ("No current frame"); 7124 else 7125 as_bad ("Register number out of range 0..%u", 7126 dr->num_regs - 1); 7127 regnum = 0; 7128 } 7129 e->X_op = O_register; 7130 e->X_add_number = dr->base + regnum; 7131 return 1; 7132 } 7133 } 7134 7135 if ((dr = hash_find (md.dynreg_hash, name))) 7136 { 7137 /* We've got ourselves the name of a rotating register set. 7138 Store the base register number in the low 16 bits of 7139 X_add_number and the size of the register set in the top 16 7140 bits. */ 7141 e->X_op = O_register; 7142 e->X_add_number = dr->base | (dr->num_regs << 16); 7143 return 1; 7144 } 7145 return 0; 7146} 7147 7148/* Remove the '#' suffix that indicates a symbol as opposed to a register. */ 7149 7150char * 7151ia64_canonicalize_symbol_name (name) 7152 char *name; 7153{ 7154 size_t len = strlen (name); 7155 if (len > 1 && name[len - 1] == '#') 7156 name[len - 1] = '\0'; 7157 return name; 7158} 7159 7160/* Return true if idesc is a conditional branch instruction. This excludes 7161 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded 7162 because they always read/write resources regardless of the value of the 7163 qualifying predicate. br.ia must always use p0, and hence is always 7164 taken. Thus this function returns true for branches which can fall 7165 through, and which use no resources if they do fall through. */ 7166 7167static int 7168is_conditional_branch (idesc) 7169 struct ia64_opcode *idesc; 7170{ 7171 /* br is a conditional branch. Everything that starts with br. except 7172 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch. 7173 Everything that starts with brl is a conditional branch. */ 7174 return (idesc->name[0] == 'b' && idesc->name[1] == 'r' 7175 && (idesc->name[2] == '\0' 7176 || (idesc->name[2] == '.' && idesc->name[3] != 'i' 7177 && idesc->name[3] != 'c' && idesc->name[3] != 'w') 7178 || idesc->name[2] == 'l' 7179 /* br.cond, br.call, br.clr */ 7180 || (idesc->name[2] == '.' && idesc->name[3] == 'c' 7181 && (idesc->name[4] == 'a' || idesc->name[4] == 'o' 7182 || (idesc->name[4] == 'l' && idesc->name[5] == 'r'))))); 7183} 7184 7185/* Return whether the given opcode is a taken branch. If there's any doubt, 7186 returns zero. */ 7187 7188static int 7189is_taken_branch (idesc) 7190 struct ia64_opcode *idesc; 7191{ 7192 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) 7193 || strncmp (idesc->name, "br.ia", 5) == 0); 7194} 7195 7196/* Return whether the given opcode is an interruption or rfi. If there's any 7197 doubt, returns zero. */ 7198 7199static int 7200is_interruption_or_rfi (idesc) 7201 struct ia64_opcode *idesc; 7202{ 7203 if (strcmp (idesc->name, "rfi") == 0) 7204 return 1; 7205 return 0; 7206} 7207 7208/* Returns the index of the given dependency in the opcode's list of chks, or 7209 -1 if there is no dependency. */ 7210 7211static int 7212depends_on (depind, idesc) 7213 int depind; 7214 struct ia64_opcode *idesc; 7215{ 7216 int i; 7217 const struct ia64_opcode_dependency *dep = idesc->dependencies; 7218 for (i = 0; i < dep->nchks; i++) 7219 { 7220 if (depind == DEP (dep->chks[i])) 7221 return i; 7222 } 7223 return -1; 7224} 7225 7226/* Determine a set of specific resources used for a particular resource 7227 class. Returns the number of specific resources identified For those 7228 cases which are not determinable statically, the resource returned is 7229 marked nonspecific. 7230 7231 Meanings of value in 'NOTE': 7232 1) only read/write when the register number is explicitly encoded in the 7233 insn. 7234 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only 7235 accesses CFM when qualifying predicate is in the rotating region. 7236 3) general register value is used to specify an indirect register; not 7237 determinable statically. 7238 4) only read the given resource when bits 7:0 of the indirect index 7239 register value does not match the register number of the resource; not 7240 determinable statically. 7241 5) all rules are implementation specific. 7242 6) only when both the index specified by the reader and the index specified 7243 by the writer have the same value in bits 63:61; not determinable 7244 statically. 7245 7) only access the specified resource when the corresponding mask bit is 7246 set 7247 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is 7248 only read when these insns reference FR2-31 7249 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only 7250 written when these insns write FR32-127 7251 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the 7252 instruction 7253 11) The target predicates are written independently of PR[qp], but source 7254 registers are only read if PR[qp] is true. Since the state of PR[qp] 7255 cannot statically be determined, all source registers are marked used. 7256 12) This insn only reads the specified predicate register when that 7257 register is the PR[qp]. 7258 13) This reference to ld-c only applies to teh GR whose value is loaded 7259 with data returned from memory, not the post-incremented address register. 7260 14) The RSE resource includes the implementation-specific RSE internal 7261 state resources. At least one (and possibly more) of these resources are 7262 read by each instruction listed in IC:rse-readers. At least one (and 7263 possibly more) of these resources are written by each insn listed in 7264 IC:rse-writers. 7265 15+16) Represents reserved instructions, which the assembler does not 7266 generate. 7267 7268 Memory resources (i.e. locations in memory) are *not* marked or tracked by 7269 this code; there are no dependency violations based on memory access. 7270*/ 7271 7272#define MAX_SPECS 256 7273#define DV_CHK 1 7274#define DV_REG 0 7275 7276static int 7277specify_resource (dep, idesc, type, specs, note, path) 7278 const struct ia64_dependency *dep; 7279 struct ia64_opcode *idesc; 7280 int type; /* is this a DV chk or a DV reg? */ 7281 struct rsrc specs[MAX_SPECS]; /* returned specific resources */ 7282 int note; /* resource note for this insn's usage */ 7283 int path; /* which execution path to examine */ 7284{ 7285 int count = 0; 7286 int i; 7287 int rsrc_write = 0; 7288 struct rsrc tmpl; 7289 7290 if (dep->mode == IA64_DV_WAW 7291 || (dep->mode == IA64_DV_RAW && type == DV_REG) 7292 || (dep->mode == IA64_DV_WAR && type == DV_CHK)) 7293 rsrc_write = 1; 7294 7295 /* template for any resources we identify */ 7296 tmpl.dependency = dep; 7297 tmpl.note = note; 7298 tmpl.insn_srlz = tmpl.data_srlz = 0; 7299 tmpl.qp_regno = CURR_SLOT.qp_regno; 7300 tmpl.link_to_qp_branch = 1; 7301 tmpl.mem_offset.hint = 0; 7302 tmpl.specific = 1; 7303 tmpl.index = 0; 7304 tmpl.cmp_type = CMP_NONE; 7305 7306#define UNHANDLED \ 7307as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ 7308dep->name, idesc->name, (rsrc_write?"write":"read"), note) 7309#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) 7310 7311 /* we don't need to track these */ 7312 if (dep->semantics == IA64_DVS_NONE) 7313 return 0; 7314 7315 switch (dep->specifier) 7316 { 7317 case IA64_RS_AR_K: 7318 if (note == 1) 7319 { 7320 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7321 { 7322 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7323 if (regno >= 0 && regno <= 7) 7324 { 7325 specs[count] = tmpl; 7326 specs[count++].index = regno; 7327 } 7328 } 7329 } 7330 else if (note == 0) 7331 { 7332 for (i = 0; i < 8; i++) 7333 { 7334 specs[count] = tmpl; 7335 specs[count++].index = i; 7336 } 7337 } 7338 else 7339 { 7340 UNHANDLED; 7341 } 7342 break; 7343 7344 case IA64_RS_AR_UNAT: 7345 /* This is a mov =AR or mov AR= instruction. */ 7346 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7347 { 7348 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7349 if (regno == AR_UNAT) 7350 { 7351 specs[count++] = tmpl; 7352 } 7353 } 7354 else 7355 { 7356 /* This is a spill/fill, or other instruction that modifies the 7357 unat register. */ 7358 7359 /* Unless we can determine the specific bits used, mark the whole 7360 thing; bits 8:3 of the memory address indicate the bit used in 7361 UNAT. The .mem.offset hint may be used to eliminate a small 7362 subset of conflicts. */ 7363 specs[count] = tmpl; 7364 if (md.mem_offset.hint) 7365 { 7366 if (md.debug_dv) 7367 fprintf (stderr, " Using hint for spill/fill\n"); 7368 /* The index isn't actually used, just set it to something 7369 approximating the bit index. */ 7370 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; 7371 specs[count].mem_offset.hint = 1; 7372 specs[count].mem_offset.offset = md.mem_offset.offset; 7373 specs[count++].mem_offset.base = md.mem_offset.base; 7374 } 7375 else 7376 { 7377 specs[count++].specific = 0; 7378 } 7379 } 7380 break; 7381 7382 case IA64_RS_AR: 7383 if (note == 1) 7384 { 7385 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7386 { 7387 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7388 if ((regno >= 8 && regno <= 15) 7389 || (regno >= 20 && regno <= 23) 7390 || (regno >= 31 && regno <= 39) 7391 || (regno >= 41 && regno <= 47) 7392 || (regno >= 67 && regno <= 111)) 7393 { 7394 specs[count] = tmpl; 7395 specs[count++].index = regno; 7396 } 7397 } 7398 } 7399 else 7400 { 7401 UNHANDLED; 7402 } 7403 break; 7404 7405 case IA64_RS_ARb: 7406 if (note == 1) 7407 { 7408 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7409 { 7410 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7411 if ((regno >= 48 && regno <= 63) 7412 || (regno >= 112 && regno <= 127)) 7413 { 7414 specs[count] = tmpl; 7415 specs[count++].index = regno; 7416 } 7417 } 7418 } 7419 else if (note == 0) 7420 { 7421 for (i = 48; i < 64; i++) 7422 { 7423 specs[count] = tmpl; 7424 specs[count++].index = i; 7425 } 7426 for (i = 112; i < 128; i++) 7427 { 7428 specs[count] = tmpl; 7429 specs[count++].index = i; 7430 } 7431 } 7432 else 7433 { 7434 UNHANDLED; 7435 } 7436 break; 7437 7438 case IA64_RS_BR: 7439 if (note != 1) 7440 { 7441 UNHANDLED; 7442 } 7443 else 7444 { 7445 if (rsrc_write) 7446 { 7447 for (i = 0; i < idesc->num_outputs; i++) 7448 if (idesc->operands[i] == IA64_OPND_B1 7449 || idesc->operands[i] == IA64_OPND_B2) 7450 { 7451 specs[count] = tmpl; 7452 specs[count++].index = 7453 CURR_SLOT.opnd[i].X_add_number - REG_BR; 7454 } 7455 } 7456 else 7457 { 7458 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++) 7459 if (idesc->operands[i] == IA64_OPND_B1 7460 || idesc->operands[i] == IA64_OPND_B2) 7461 { 7462 specs[count] = tmpl; 7463 specs[count++].index = 7464 CURR_SLOT.opnd[i].X_add_number - REG_BR; 7465 } 7466 } 7467 } 7468 break; 7469 7470 case IA64_RS_CPUID: /* four or more registers */ 7471 if (note == 3) 7472 { 7473 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) 7474 { 7475 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7476 if (regno >= 0 && regno < NELEMS (gr_values) 7477 && KNOWN (regno)) 7478 { 7479 specs[count] = tmpl; 7480 specs[count++].index = gr_values[regno].value & 0xFF; 7481 } 7482 else 7483 { 7484 specs[count] = tmpl; 7485 specs[count++].specific = 0; 7486 } 7487 } 7488 } 7489 else 7490 { 7491 UNHANDLED; 7492 } 7493 break; 7494 7495 case IA64_RS_DBR: /* four or more registers */ 7496 if (note == 3) 7497 { 7498 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) 7499 { 7500 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7501 if (regno >= 0 && regno < NELEMS (gr_values) 7502 && KNOWN (regno)) 7503 { 7504 specs[count] = tmpl; 7505 specs[count++].index = gr_values[regno].value & 0xFF; 7506 } 7507 else 7508 { 7509 specs[count] = tmpl; 7510 specs[count++].specific = 0; 7511 } 7512 } 7513 } 7514 else if (note == 0 && !rsrc_write) 7515 { 7516 specs[count] = tmpl; 7517 specs[count++].specific = 0; 7518 } 7519 else 7520 { 7521 UNHANDLED; 7522 } 7523 break; 7524 7525 case IA64_RS_IBR: /* four or more registers */ 7526 if (note == 3) 7527 { 7528 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) 7529 { 7530 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7531 if (regno >= 0 && regno < NELEMS (gr_values) 7532 && KNOWN (regno)) 7533 { 7534 specs[count] = tmpl; 7535 specs[count++].index = gr_values[regno].value & 0xFF; 7536 } 7537 else 7538 { 7539 specs[count] = tmpl; 7540 specs[count++].specific = 0; 7541 } 7542 } 7543 } 7544 else 7545 { 7546 UNHANDLED; 7547 } 7548 break; 7549 7550 case IA64_RS_MSR: 7551 if (note == 5) 7552 { 7553 /* These are implementation specific. Force all references to 7554 conflict with all other references. */ 7555 specs[count] = tmpl; 7556 specs[count++].specific = 0; 7557 } 7558 else 7559 { 7560 UNHANDLED; 7561 } 7562 break; 7563 7564 case IA64_RS_PKR: /* 16 or more registers */ 7565 if (note == 3 || note == 4) 7566 { 7567 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) 7568 { 7569 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7570 if (regno >= 0 && regno < NELEMS (gr_values) 7571 && KNOWN (regno)) 7572 { 7573 if (note == 3) 7574 { 7575 specs[count] = tmpl; 7576 specs[count++].index = gr_values[regno].value & 0xFF; 7577 } 7578 else 7579 for (i = 0; i < NELEMS (gr_values); i++) 7580 { 7581 /* Uses all registers *except* the one in R3. */ 7582 if ((unsigned)i != (gr_values[regno].value & 0xFF)) 7583 { 7584 specs[count] = tmpl; 7585 specs[count++].index = i; 7586 } 7587 } 7588 } 7589 else 7590 { 7591 specs[count] = tmpl; 7592 specs[count++].specific = 0; 7593 } 7594 } 7595 } 7596 else if (note == 0) 7597 { 7598 /* probe et al. */ 7599 specs[count] = tmpl; 7600 specs[count++].specific = 0; 7601 } 7602 break; 7603 7604 case IA64_RS_PMC: /* four or more registers */ 7605 if (note == 3) 7606 { 7607 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 7608 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) 7609 7610 { 7611 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) 7612 ? 1 : !rsrc_write); 7613 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; 7614 if (regno >= 0 && regno < NELEMS (gr_values) 7615 && KNOWN (regno)) 7616 { 7617 specs[count] = tmpl; 7618 specs[count++].index = gr_values[regno].value & 0xFF; 7619 } 7620 else 7621 { 7622 specs[count] = tmpl; 7623 specs[count++].specific = 0; 7624 } 7625 } 7626 } 7627 else 7628 { 7629 UNHANDLED; 7630 } 7631 break; 7632 7633 case IA64_RS_PMD: /* four or more registers */ 7634 if (note == 3) 7635 { 7636 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) 7637 { 7638 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7639 if (regno >= 0 && regno < NELEMS (gr_values) 7640 && KNOWN (regno)) 7641 { 7642 specs[count] = tmpl; 7643 specs[count++].index = gr_values[regno].value & 0xFF; 7644 } 7645 else 7646 { 7647 specs[count] = tmpl; 7648 specs[count++].specific = 0; 7649 } 7650 } 7651 } 7652 else 7653 { 7654 UNHANDLED; 7655 } 7656 break; 7657 7658 case IA64_RS_RR: /* eight registers */ 7659 if (note == 6) 7660 { 7661 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) 7662 { 7663 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7664 if (regno >= 0 && regno < NELEMS (gr_values) 7665 && KNOWN (regno)) 7666 { 7667 specs[count] = tmpl; 7668 specs[count++].index = (gr_values[regno].value >> 61) & 0x7; 7669 } 7670 else 7671 { 7672 specs[count] = tmpl; 7673 specs[count++].specific = 0; 7674 } 7675 } 7676 } 7677 else if (note == 0 && !rsrc_write) 7678 { 7679 specs[count] = tmpl; 7680 specs[count++].specific = 0; 7681 } 7682 else 7683 { 7684 UNHANDLED; 7685 } 7686 break; 7687 7688 case IA64_RS_CR_IRR: 7689 if (note == 0) 7690 { 7691 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ 7692 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; 7693 if (rsrc_write 7694 && idesc->operands[1] == IA64_OPND_CR3 7695 && regno == CR_IVR) 7696 { 7697 for (i = 0; i < 4; i++) 7698 { 7699 specs[count] = tmpl; 7700 specs[count++].index = CR_IRR0 + i; 7701 } 7702 } 7703 } 7704 else if (note == 1) 7705 { 7706 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7707 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 7708 && regno >= CR_IRR0 7709 && regno <= CR_IRR3) 7710 { 7711 specs[count] = tmpl; 7712 specs[count++].index = regno; 7713 } 7714 } 7715 else 7716 { 7717 UNHANDLED; 7718 } 7719 break; 7720 7721 case IA64_RS_CR_LRR: 7722 if (note != 1) 7723 { 7724 UNHANDLED; 7725 } 7726 else 7727 { 7728 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7729 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 7730 && (regno == CR_LRR0 || regno == CR_LRR1)) 7731 { 7732 specs[count] = tmpl; 7733 specs[count++].index = regno; 7734 } 7735 } 7736 break; 7737 7738 case IA64_RS_CR: 7739 if (note == 1) 7740 { 7741 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 7742 { 7743 specs[count] = tmpl; 7744 specs[count++].index = 7745 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7746 } 7747 } 7748 else 7749 { 7750 UNHANDLED; 7751 } 7752 break; 7753 7754 case IA64_RS_FR: 7755 case IA64_RS_FRb: 7756 if (note != 1) 7757 { 7758 UNHANDLED; 7759 } 7760 else if (rsrc_write) 7761 { 7762 if (dep->specifier == IA64_RS_FRb 7763 && idesc->operands[0] == IA64_OPND_F1) 7764 { 7765 specs[count] = tmpl; 7766 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; 7767 } 7768 } 7769 else 7770 { 7771 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) 7772 { 7773 if (idesc->operands[i] == IA64_OPND_F2 7774 || idesc->operands[i] == IA64_OPND_F3 7775 || idesc->operands[i] == IA64_OPND_F4) 7776 { 7777 specs[count] = tmpl; 7778 specs[count++].index = 7779 CURR_SLOT.opnd[i].X_add_number - REG_FR; 7780 } 7781 } 7782 } 7783 break; 7784 7785 case IA64_RS_GR: 7786 if (note == 13) 7787 { 7788 /* This reference applies only to the GR whose value is loaded with 7789 data returned from memory. */ 7790 specs[count] = tmpl; 7791 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; 7792 } 7793 else if (note == 1) 7794 { 7795 if (rsrc_write) 7796 { 7797 for (i = 0; i < idesc->num_outputs; i++) 7798 if (idesc->operands[i] == IA64_OPND_R1 7799 || idesc->operands[i] == IA64_OPND_R2 7800 || idesc->operands[i] == IA64_OPND_R3) 7801 { 7802 specs[count] = tmpl; 7803 specs[count++].index = 7804 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7805 } 7806 if (idesc->flags & IA64_OPCODE_POSTINC) 7807 for (i = 0; i < NELEMS (idesc->operands); i++) 7808 if (idesc->operands[i] == IA64_OPND_MR3) 7809 { 7810 specs[count] = tmpl; 7811 specs[count++].index = 7812 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7813 } 7814 } 7815 else 7816 { 7817 /* Look for anything that reads a GR. */ 7818 for (i = 0; i < NELEMS (idesc->operands); i++) 7819 { 7820 if (idesc->operands[i] == IA64_OPND_MR3 7821 || idesc->operands[i] == IA64_OPND_CPUID_R3 7822 || idesc->operands[i] == IA64_OPND_DBR_R3 7823 || idesc->operands[i] == IA64_OPND_IBR_R3 7824 || idesc->operands[i] == IA64_OPND_MSR_R3 7825 || idesc->operands[i] == IA64_OPND_PKR_R3 7826 || idesc->operands[i] == IA64_OPND_PMC_R3 7827 || idesc->operands[i] == IA64_OPND_PMD_R3 7828 || idesc->operands[i] == IA64_OPND_RR_R3 7829 || ((i >= idesc->num_outputs) 7830 && (idesc->operands[i] == IA64_OPND_R1 7831 || idesc->operands[i] == IA64_OPND_R2 7832 || idesc->operands[i] == IA64_OPND_R3 7833 /* addl source register. */ 7834 || idesc->operands[i] == IA64_OPND_R3_2))) 7835 { 7836 specs[count] = tmpl; 7837 specs[count++].index = 7838 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7839 } 7840 } 7841 } 7842 } 7843 else 7844 { 7845 UNHANDLED; 7846 } 7847 break; 7848 7849 /* This is the same as IA64_RS_PRr, except that the register range is 7850 from 1 - 15, and there are no rotating register reads/writes here. */ 7851 case IA64_RS_PR: 7852 if (note == 0) 7853 { 7854 for (i = 1; i < 16; i++) 7855 { 7856 specs[count] = tmpl; 7857 specs[count++].index = i; 7858 } 7859 } 7860 else if (note == 7) 7861 { 7862 valueT mask = 0; 7863 /* Mark only those registers indicated by the mask. */ 7864 if (rsrc_write) 7865 { 7866 mask = CURR_SLOT.opnd[2].X_add_number; 7867 for (i = 1; i < 16; i++) 7868 if (mask & ((valueT) 1 << i)) 7869 { 7870 specs[count] = tmpl; 7871 specs[count++].index = i; 7872 } 7873 } 7874 else 7875 { 7876 UNHANDLED; 7877 } 7878 } 7879 else if (note == 11) /* note 11 implies note 1 as well */ 7880 { 7881 if (rsrc_write) 7882 { 7883 for (i = 0; i < idesc->num_outputs; i++) 7884 { 7885 if (idesc->operands[i] == IA64_OPND_P1 7886 || idesc->operands[i] == IA64_OPND_P2) 7887 { 7888 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 7889 if (regno >= 1 && regno < 16) 7890 { 7891 specs[count] = tmpl; 7892 specs[count++].index = regno; 7893 } 7894 } 7895 } 7896 } 7897 else 7898 { 7899 UNHANDLED; 7900 } 7901 } 7902 else if (note == 12) 7903 { 7904 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 7905 { 7906 specs[count] = tmpl; 7907 specs[count++].index = CURR_SLOT.qp_regno; 7908 } 7909 } 7910 else if (note == 1) 7911 { 7912 if (rsrc_write) 7913 { 7914 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 7915 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 7916 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 7917 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 7918 7919 if ((idesc->operands[0] == IA64_OPND_P1 7920 || idesc->operands[0] == IA64_OPND_P2) 7921 && p1 >= 1 && p1 < 16) 7922 { 7923 specs[count] = tmpl; 7924 specs[count].cmp_type = 7925 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 7926 specs[count++].index = p1; 7927 } 7928 if ((idesc->operands[1] == IA64_OPND_P1 7929 || idesc->operands[1] == IA64_OPND_P2) 7930 && p2 >= 1 && p2 < 16) 7931 { 7932 specs[count] = tmpl; 7933 specs[count].cmp_type = 7934 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 7935 specs[count++].index = p2; 7936 } 7937 } 7938 else 7939 { 7940 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 7941 { 7942 specs[count] = tmpl; 7943 specs[count++].index = CURR_SLOT.qp_regno; 7944 } 7945 if (idesc->operands[1] == IA64_OPND_PR) 7946 { 7947 for (i = 1; i < 16; i++) 7948 { 7949 specs[count] = tmpl; 7950 specs[count++].index = i; 7951 } 7952 } 7953 } 7954 } 7955 else 7956 { 7957 UNHANDLED; 7958 } 7959 break; 7960 7961 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are 7962 simplified cases of this. */ 7963 case IA64_RS_PRr: 7964 if (note == 0) 7965 { 7966 for (i = 16; i < 63; i++) 7967 { 7968 specs[count] = tmpl; 7969 specs[count++].index = i; 7970 } 7971 } 7972 else if (note == 7) 7973 { 7974 valueT mask = 0; 7975 /* Mark only those registers indicated by the mask. */ 7976 if (rsrc_write 7977 && idesc->operands[0] == IA64_OPND_PR) 7978 { 7979 mask = CURR_SLOT.opnd[2].X_add_number; 7980 if (mask & ((valueT) 1<<16)) 7981 for (i = 16; i < 63; i++) 7982 { 7983 specs[count] = tmpl; 7984 specs[count++].index = i; 7985 } 7986 } 7987 else if (rsrc_write 7988 && idesc->operands[0] == IA64_OPND_PR_ROT) 7989 { 7990 for (i = 16; i < 63; i++) 7991 { 7992 specs[count] = tmpl; 7993 specs[count++].index = i; 7994 } 7995 } 7996 else 7997 { 7998 UNHANDLED; 7999 } 8000 } 8001 else if (note == 11) /* note 11 implies note 1 as well */ 8002 { 8003 if (rsrc_write) 8004 { 8005 for (i = 0; i < idesc->num_outputs; i++) 8006 { 8007 if (idesc->operands[i] == IA64_OPND_P1 8008 || idesc->operands[i] == IA64_OPND_P2) 8009 { 8010 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 8011 if (regno >= 16 && regno < 63) 8012 { 8013 specs[count] = tmpl; 8014 specs[count++].index = regno; 8015 } 8016 } 8017 } 8018 } 8019 else 8020 { 8021 UNHANDLED; 8022 } 8023 } 8024 else if (note == 12) 8025 { 8026 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 8027 { 8028 specs[count] = tmpl; 8029 specs[count++].index = CURR_SLOT.qp_regno; 8030 } 8031 } 8032 else if (note == 1) 8033 { 8034 if (rsrc_write) 8035 { 8036 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8037 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8038 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 8039 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 8040 8041 if ((idesc->operands[0] == IA64_OPND_P1 8042 || idesc->operands[0] == IA64_OPND_P2) 8043 && p1 >= 16 && p1 < 63) 8044 { 8045 specs[count] = tmpl; 8046 specs[count].cmp_type = 8047 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 8048 specs[count++].index = p1; 8049 } 8050 if ((idesc->operands[1] == IA64_OPND_P1 8051 || idesc->operands[1] == IA64_OPND_P2) 8052 && p2 >= 16 && p2 < 63) 8053 { 8054 specs[count] = tmpl; 8055 specs[count].cmp_type = 8056 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 8057 specs[count++].index = p2; 8058 } 8059 } 8060 else 8061 { 8062 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 8063 { 8064 specs[count] = tmpl; 8065 specs[count++].index = CURR_SLOT.qp_regno; 8066 } 8067 if (idesc->operands[1] == IA64_OPND_PR) 8068 { 8069 for (i = 16; i < 63; i++) 8070 { 8071 specs[count] = tmpl; 8072 specs[count++].index = i; 8073 } 8074 } 8075 } 8076 } 8077 else 8078 { 8079 UNHANDLED; 8080 } 8081 break; 8082 8083 case IA64_RS_PSR: 8084 /* Verify that the instruction is using the PSR bit indicated in 8085 dep->regindex. */ 8086 if (note == 0) 8087 { 8088 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) 8089 { 8090 if (dep->regindex < 6) 8091 { 8092 specs[count++] = tmpl; 8093 } 8094 } 8095 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) 8096 { 8097 if (dep->regindex < 32 8098 || dep->regindex == 35 8099 || dep->regindex == 36 8100 || (!rsrc_write && dep->regindex == PSR_CPL)) 8101 { 8102 specs[count++] = tmpl; 8103 } 8104 } 8105 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) 8106 { 8107 if (dep->regindex < 32 8108 || dep->regindex == 35 8109 || dep->regindex == 36 8110 || (rsrc_write && dep->regindex == PSR_CPL)) 8111 { 8112 specs[count++] = tmpl; 8113 } 8114 } 8115 else 8116 { 8117 /* Several PSR bits have very specific dependencies. */ 8118 switch (dep->regindex) 8119 { 8120 default: 8121 specs[count++] = tmpl; 8122 break; 8123 case PSR_IC: 8124 if (rsrc_write) 8125 { 8126 specs[count++] = tmpl; 8127 } 8128 else 8129 { 8130 /* Only certain CR accesses use PSR.ic */ 8131 if (idesc->operands[0] == IA64_OPND_CR3 8132 || idesc->operands[1] == IA64_OPND_CR3) 8133 { 8134 int index = 8135 ((idesc->operands[0] == IA64_OPND_CR3) 8136 ? 0 : 1); 8137 int regno = 8138 CURR_SLOT.opnd[index].X_add_number - REG_CR; 8139 8140 switch (regno) 8141 { 8142 default: 8143 break; 8144 case CR_ITIR: 8145 case CR_IFS: 8146 case CR_IIM: 8147 case CR_IIP: 8148 case CR_IPSR: 8149 case CR_ISR: 8150 case CR_IFA: 8151 case CR_IHA: 8152 case CR_IIPA: 8153 specs[count++] = tmpl; 8154 break; 8155 } 8156 } 8157 } 8158 break; 8159 case PSR_CPL: 8160 if (rsrc_write) 8161 { 8162 specs[count++] = tmpl; 8163 } 8164 else 8165 { 8166 /* Only some AR accesses use cpl */ 8167 if (idesc->operands[0] == IA64_OPND_AR3 8168 || idesc->operands[1] == IA64_OPND_AR3) 8169 { 8170 int index = 8171 ((idesc->operands[0] == IA64_OPND_AR3) 8172 ? 0 : 1); 8173 int regno = 8174 CURR_SLOT.opnd[index].X_add_number - REG_AR; 8175 8176 if (regno == AR_ITC 8177 || (index == 0 8178 && (regno == AR_ITC 8179 || regno == AR_RSC 8180 || (regno >= AR_K0 8181 && regno <= AR_K7)))) 8182 { 8183 specs[count++] = tmpl; 8184 } 8185 } 8186 else 8187 { 8188 specs[count++] = tmpl; 8189 } 8190 break; 8191 } 8192 } 8193 } 8194 } 8195 else if (note == 7) 8196 { 8197 valueT mask = 0; 8198 if (idesc->operands[0] == IA64_OPND_IMMU24) 8199 { 8200 mask = CURR_SLOT.opnd[0].X_add_number; 8201 } 8202 else 8203 { 8204 UNHANDLED; 8205 } 8206 if (mask & ((valueT) 1 << dep->regindex)) 8207 { 8208 specs[count++] = tmpl; 8209 } 8210 } 8211 else if (note == 8) 8212 { 8213 int min = dep->regindex == PSR_DFL ? 2 : 32; 8214 int max = dep->regindex == PSR_DFL ? 31 : 127; 8215 /* dfh is read on FR32-127; dfl is read on FR2-31 */ 8216 for (i = 0; i < NELEMS (idesc->operands); i++) 8217 { 8218 if (idesc->operands[i] == IA64_OPND_F1 8219 || idesc->operands[i] == IA64_OPND_F2 8220 || idesc->operands[i] == IA64_OPND_F3 8221 || idesc->operands[i] == IA64_OPND_F4) 8222 { 8223 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8224 if (reg >= min && reg <= max) 8225 { 8226 specs[count++] = tmpl; 8227 } 8228 } 8229 } 8230 } 8231 else if (note == 9) 8232 { 8233 int min = dep->regindex == PSR_MFL ? 2 : 32; 8234 int max = dep->regindex == PSR_MFL ? 31 : 127; 8235 /* mfh is read on writes to FR32-127; mfl is read on writes to 8236 FR2-31 */ 8237 for (i = 0; i < idesc->num_outputs; i++) 8238 { 8239 if (idesc->operands[i] == IA64_OPND_F1) 8240 { 8241 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8242 if (reg >= min && reg <= max) 8243 { 8244 specs[count++] = tmpl; 8245 } 8246 } 8247 } 8248 } 8249 else if (note == 10) 8250 { 8251 for (i = 0; i < NELEMS (idesc->operands); i++) 8252 { 8253 if (idesc->operands[i] == IA64_OPND_R1 8254 || idesc->operands[i] == IA64_OPND_R2 8255 || idesc->operands[i] == IA64_OPND_R3) 8256 { 8257 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8258 if (regno >= 16 && regno <= 31) 8259 { 8260 specs[count++] = tmpl; 8261 } 8262 } 8263 } 8264 } 8265 else 8266 { 8267 UNHANDLED; 8268 } 8269 break; 8270 8271 case IA64_RS_AR_FPSR: 8272 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 8273 { 8274 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8275 if (regno == AR_FPSR) 8276 { 8277 specs[count++] = tmpl; 8278 } 8279 } 8280 else 8281 { 8282 specs[count++] = tmpl; 8283 } 8284 break; 8285 8286 case IA64_RS_ARX: 8287 /* Handle all AR[REG] resources */ 8288 if (note == 0 || note == 1) 8289 { 8290 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8291 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 8292 && regno == dep->regindex) 8293 { 8294 specs[count++] = tmpl; 8295 } 8296 /* other AR[REG] resources may be affected by AR accesses */ 8297 else if (idesc->operands[0] == IA64_OPND_AR3) 8298 { 8299 /* AR[] writes */ 8300 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; 8301 switch (dep->regindex) 8302 { 8303 default: 8304 break; 8305 case AR_BSP: 8306 case AR_RNAT: 8307 if (regno == AR_BSPSTORE) 8308 { 8309 specs[count++] = tmpl; 8310 } 8311 case AR_RSC: 8312 if (!rsrc_write && 8313 (regno == AR_BSPSTORE 8314 || regno == AR_RNAT)) 8315 { 8316 specs[count++] = tmpl; 8317 } 8318 break; 8319 } 8320 } 8321 else if (idesc->operands[1] == IA64_OPND_AR3) 8322 { 8323 /* AR[] reads */ 8324 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; 8325 switch (dep->regindex) 8326 { 8327 default: 8328 break; 8329 case AR_RSC: 8330 if (regno == AR_BSPSTORE || regno == AR_RNAT) 8331 { 8332 specs[count++] = tmpl; 8333 } 8334 break; 8335 } 8336 } 8337 else 8338 { 8339 specs[count++] = tmpl; 8340 } 8341 } 8342 else 8343 { 8344 UNHANDLED; 8345 } 8346 break; 8347 8348 case IA64_RS_CRX: 8349 /* Handle all CR[REG] resources */ 8350 if (note == 0 || note == 1) 8351 { 8352 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 8353 { 8354 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 8355 if (regno == dep->regindex) 8356 { 8357 specs[count++] = tmpl; 8358 } 8359 else if (!rsrc_write) 8360 { 8361 /* Reads from CR[IVR] affect other resources. */ 8362 if (regno == CR_IVR) 8363 { 8364 if ((dep->regindex >= CR_IRR0 8365 && dep->regindex <= CR_IRR3) 8366 || dep->regindex == CR_TPR) 8367 { 8368 specs[count++] = tmpl; 8369 } 8370 } 8371 } 8372 } 8373 else 8374 { 8375 specs[count++] = tmpl; 8376 } 8377 } 8378 else 8379 { 8380 UNHANDLED; 8381 } 8382 break; 8383 8384 case IA64_RS_INSERVICE: 8385 /* look for write of EOI (67) or read of IVR (65) */ 8386 if ((idesc->operands[0] == IA64_OPND_CR3 8387 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) 8388 || (idesc->operands[1] == IA64_OPND_CR3 8389 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) 8390 { 8391 specs[count++] = tmpl; 8392 } 8393 break; 8394 8395 case IA64_RS_GR0: 8396 if (note == 1) 8397 { 8398 specs[count++] = tmpl; 8399 } 8400 else 8401 { 8402 UNHANDLED; 8403 } 8404 break; 8405 8406 case IA64_RS_CFM: 8407 if (note != 2) 8408 { 8409 specs[count++] = tmpl; 8410 } 8411 else 8412 { 8413 /* Check if any of the registers accessed are in the rotating region. 8414 mov to/from pr accesses CFM only when qp_regno is in the rotating 8415 region */ 8416 for (i = 0; i < NELEMS (idesc->operands); i++) 8417 { 8418 if (idesc->operands[i] == IA64_OPND_R1 8419 || idesc->operands[i] == IA64_OPND_R2 8420 || idesc->operands[i] == IA64_OPND_R3) 8421 { 8422 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8423 /* Assumes that md.rot.num_regs is always valid */ 8424 if (md.rot.num_regs > 0 8425 && num > 31 8426 && num < 31 + md.rot.num_regs) 8427 { 8428 specs[count] = tmpl; 8429 specs[count++].specific = 0; 8430 } 8431 } 8432 else if (idesc->operands[i] == IA64_OPND_F1 8433 || idesc->operands[i] == IA64_OPND_F2 8434 || idesc->operands[i] == IA64_OPND_F3 8435 || idesc->operands[i] == IA64_OPND_F4) 8436 { 8437 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8438 if (num > 31) 8439 { 8440 specs[count] = tmpl; 8441 specs[count++].specific = 0; 8442 } 8443 } 8444 else if (idesc->operands[i] == IA64_OPND_P1 8445 || idesc->operands[i] == IA64_OPND_P2) 8446 { 8447 int num = CURR_SLOT.opnd[i].X_add_number - REG_P; 8448 if (num > 15) 8449 { 8450 specs[count] = tmpl; 8451 specs[count++].specific = 0; 8452 } 8453 } 8454 } 8455 if (CURR_SLOT.qp_regno > 15) 8456 { 8457 specs[count] = tmpl; 8458 specs[count++].specific = 0; 8459 } 8460 } 8461 break; 8462 8463 /* This is the same as IA64_RS_PRr, except simplified to account for 8464 the fact that there is only one register. */ 8465 case IA64_RS_PR63: 8466 if (note == 0) 8467 { 8468 specs[count++] = tmpl; 8469 } 8470 else if (note == 7) 8471 { 8472 valueT mask = 0; 8473 if (idesc->operands[2] == IA64_OPND_IMM17) 8474 mask = CURR_SLOT.opnd[2].X_add_number; 8475 if (mask & ((valueT) 1 << 63)) 8476 specs[count++] = tmpl; 8477 } 8478 else if (note == 11) 8479 { 8480 if ((idesc->operands[0] == IA64_OPND_P1 8481 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) 8482 || (idesc->operands[1] == IA64_OPND_P2 8483 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) 8484 { 8485 specs[count++] = tmpl; 8486 } 8487 } 8488 else if (note == 12) 8489 { 8490 if (CURR_SLOT.qp_regno == 63) 8491 { 8492 specs[count++] = tmpl; 8493 } 8494 } 8495 else if (note == 1) 8496 { 8497 if (rsrc_write) 8498 { 8499 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8500 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8501 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 8502 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 8503 8504 if (p1 == 63 8505 && (idesc->operands[0] == IA64_OPND_P1 8506 || idesc->operands[0] == IA64_OPND_P2)) 8507 { 8508 specs[count] = tmpl; 8509 specs[count++].cmp_type = 8510 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 8511 } 8512 if (p2 == 63 8513 && (idesc->operands[1] == IA64_OPND_P1 8514 || idesc->operands[1] == IA64_OPND_P2)) 8515 { 8516 specs[count] = tmpl; 8517 specs[count++].cmp_type = 8518 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 8519 } 8520 } 8521 else 8522 { 8523 if (CURR_SLOT.qp_regno == 63) 8524 { 8525 specs[count++] = tmpl; 8526 } 8527 } 8528 } 8529 else 8530 { 8531 UNHANDLED; 8532 } 8533 break; 8534 8535 case IA64_RS_RSE: 8536 /* FIXME we can identify some individual RSE written resources, but RSE 8537 read resources have not yet been completely identified, so for now 8538 treat RSE as a single resource */ 8539 if (strncmp (idesc->name, "mov", 3) == 0) 8540 { 8541 if (rsrc_write) 8542 { 8543 if (idesc->operands[0] == IA64_OPND_AR3 8544 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) 8545 { 8546 specs[count] = tmpl; 8547 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ 8548 } 8549 } 8550 else 8551 { 8552 if (idesc->operands[0] == IA64_OPND_AR3) 8553 { 8554 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE 8555 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) 8556 { 8557 specs[count++] = tmpl; 8558 } 8559 } 8560 else if (idesc->operands[1] == IA64_OPND_AR3) 8561 { 8562 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP 8563 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE 8564 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) 8565 { 8566 specs[count++] = tmpl; 8567 } 8568 } 8569 } 8570 } 8571 else 8572 { 8573 specs[count++] = tmpl; 8574 } 8575 break; 8576 8577 case IA64_RS_ANY: 8578 /* FIXME -- do any of these need to be non-specific? */ 8579 specs[count++] = tmpl; 8580 break; 8581 8582 default: 8583 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); 8584 break; 8585 } 8586 8587 return count; 8588} 8589 8590/* Clear branch flags on marked resources. This breaks the link between the 8591 QP of the marking instruction and a subsequent branch on the same QP. */ 8592 8593static void 8594clear_qp_branch_flag (mask) 8595 valueT mask; 8596{ 8597 int i; 8598 for (i = 0; i < regdepslen; i++) 8599 { 8600 valueT bit = ((valueT) 1 << regdeps[i].qp_regno); 8601 if ((bit & mask) != 0) 8602 { 8603 regdeps[i].link_to_qp_branch = 0; 8604 } 8605 } 8606} 8607 8608/* Remove any mutexes which contain any of the PRs indicated in the mask. 8609 8610 Any changes to a PR clears the mutex relations which include that PR. */ 8611 8612static void 8613clear_qp_mutex (mask) 8614 valueT mask; 8615{ 8616 int i; 8617 8618 i = 0; 8619 while (i < qp_mutexeslen) 8620 { 8621 if ((qp_mutexes[i].prmask & mask) != 0) 8622 { 8623 if (md.debug_dv) 8624 { 8625 fprintf (stderr, " Clearing mutex relation"); 8626 print_prmask (qp_mutexes[i].prmask); 8627 fprintf (stderr, "\n"); 8628 } 8629 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; 8630 } 8631 else 8632 ++i; 8633 } 8634} 8635 8636/* Clear implies relations which contain PRs in the given masks. 8637 P1_MASK indicates the source of the implies relation, while P2_MASK 8638 indicates the implied PR. */ 8639 8640static void 8641clear_qp_implies (p1_mask, p2_mask) 8642 valueT p1_mask; 8643 valueT p2_mask; 8644{ 8645 int i; 8646 8647 i = 0; 8648 while (i < qp_implieslen) 8649 { 8650 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 8651 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) 8652 { 8653 if (md.debug_dv) 8654 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", 8655 qp_implies[i].p1, qp_implies[i].p2); 8656 qp_implies[i] = qp_implies[--qp_implieslen]; 8657 } 8658 else 8659 ++i; 8660 } 8661} 8662 8663/* Add the PRs specified to the list of implied relations. */ 8664 8665static void 8666add_qp_imply (p1, p2) 8667 int p1, p2; 8668{ 8669 valueT mask; 8670 valueT bit; 8671 int i; 8672 8673 /* p0 is not meaningful here. */ 8674 if (p1 == 0 || p2 == 0) 8675 abort (); 8676 8677 if (p1 == p2) 8678 return; 8679 8680 /* If it exists already, ignore it. */ 8681 for (i = 0; i < qp_implieslen; i++) 8682 { 8683 if (qp_implies[i].p1 == p1 8684 && qp_implies[i].p2 == p2 8685 && qp_implies[i].path == md.path 8686 && !qp_implies[i].p2_branched) 8687 return; 8688 } 8689 8690 if (qp_implieslen == qp_impliestotlen) 8691 { 8692 qp_impliestotlen += 20; 8693 qp_implies = (struct qp_imply *) 8694 xrealloc ((void *) qp_implies, 8695 qp_impliestotlen * sizeof (struct qp_imply)); 8696 } 8697 if (md.debug_dv) 8698 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); 8699 qp_implies[qp_implieslen].p1 = p1; 8700 qp_implies[qp_implieslen].p2 = p2; 8701 qp_implies[qp_implieslen].path = md.path; 8702 qp_implies[qp_implieslen++].p2_branched = 0; 8703 8704 /* Add in the implied transitive relations; for everything that p2 implies, 8705 make p1 imply that, too; for everything that implies p1, make it imply p2 8706 as well. */ 8707 for (i = 0; i < qp_implieslen; i++) 8708 { 8709 if (qp_implies[i].p1 == p2) 8710 add_qp_imply (p1, qp_implies[i].p2); 8711 if (qp_implies[i].p2 == p1) 8712 add_qp_imply (qp_implies[i].p1, p2); 8713 } 8714 /* Add in mutex relations implied by this implies relation; for each mutex 8715 relation containing p2, duplicate it and replace p2 with p1. */ 8716 bit = (valueT) 1 << p1; 8717 mask = (valueT) 1 << p2; 8718 for (i = 0; i < qp_mutexeslen; i++) 8719 { 8720 if (qp_mutexes[i].prmask & mask) 8721 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); 8722 } 8723} 8724 8725/* Add the PRs specified in the mask to the mutex list; this means that only 8726 one of the PRs can be true at any time. PR0 should never be included in 8727 the mask. */ 8728 8729static void 8730add_qp_mutex (mask) 8731 valueT mask; 8732{ 8733 if (mask & 0x1) 8734 abort (); 8735 8736 if (qp_mutexeslen == qp_mutexestotlen) 8737 { 8738 qp_mutexestotlen += 20; 8739 qp_mutexes = (struct qpmutex *) 8740 xrealloc ((void *) qp_mutexes, 8741 qp_mutexestotlen * sizeof (struct qpmutex)); 8742 } 8743 if (md.debug_dv) 8744 { 8745 fprintf (stderr, " Registering mutex on"); 8746 print_prmask (mask); 8747 fprintf (stderr, "\n"); 8748 } 8749 qp_mutexes[qp_mutexeslen].path = md.path; 8750 qp_mutexes[qp_mutexeslen++].prmask = mask; 8751} 8752 8753static int 8754has_suffix_p (name, suffix) 8755 const char *name; 8756 const char *suffix; 8757{ 8758 size_t namelen = strlen (name); 8759 size_t sufflen = strlen (suffix); 8760 8761 if (namelen <= sufflen) 8762 return 0; 8763 return strcmp (name + namelen - sufflen, suffix) == 0; 8764} 8765 8766static void 8767clear_register_values () 8768{ 8769 int i; 8770 if (md.debug_dv) 8771 fprintf (stderr, " Clearing register values\n"); 8772 for (i = 1; i < NELEMS (gr_values); i++) 8773 gr_values[i].known = 0; 8774} 8775 8776/* Keep track of register values/changes which affect DV tracking. 8777 8778 optimization note: should add a flag to classes of insns where otherwise we 8779 have to examine a group of strings to identify them. */ 8780 8781static void 8782note_register_values (idesc) 8783 struct ia64_opcode *idesc; 8784{ 8785 valueT qp_changemask = 0; 8786 int i; 8787 8788 /* Invalidate values for registers being written to. */ 8789 for (i = 0; i < idesc->num_outputs; i++) 8790 { 8791 if (idesc->operands[i] == IA64_OPND_R1 8792 || idesc->operands[i] == IA64_OPND_R2 8793 || idesc->operands[i] == IA64_OPND_R3) 8794 { 8795 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8796 if (regno > 0 && regno < NELEMS (gr_values)) 8797 gr_values[regno].known = 0; 8798 } 8799 else if (idesc->operands[i] == IA64_OPND_R3_2) 8800 { 8801 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8802 if (regno > 0 && regno < 4) 8803 gr_values[regno].known = 0; 8804 } 8805 else if (idesc->operands[i] == IA64_OPND_P1 8806 || idesc->operands[i] == IA64_OPND_P2) 8807 { 8808 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 8809 qp_changemask |= (valueT) 1 << regno; 8810 } 8811 else if (idesc->operands[i] == IA64_OPND_PR) 8812 { 8813 if (idesc->operands[2] & (valueT) 0x10000) 8814 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; 8815 else 8816 qp_changemask = idesc->operands[2]; 8817 break; 8818 } 8819 else if (idesc->operands[i] == IA64_OPND_PR_ROT) 8820 { 8821 if (idesc->operands[1] & ((valueT) 1 << 43)) 8822 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; 8823 else 8824 qp_changemask = idesc->operands[1]; 8825 qp_changemask &= ~(valueT) 0xFFFF; 8826 break; 8827 } 8828 } 8829 8830 /* Always clear qp branch flags on any PR change. */ 8831 /* FIXME there may be exceptions for certain compares. */ 8832 clear_qp_branch_flag (qp_changemask); 8833 8834 /* Invalidate rotating registers on insns which affect RRBs in CFM. */ 8835 if (idesc->flags & IA64_OPCODE_MOD_RRBS) 8836 { 8837 qp_changemask |= ~(valueT) 0xFFFF; 8838 if (strcmp (idesc->name, "clrrrb.pr") != 0) 8839 { 8840 for (i = 32; i < 32 + md.rot.num_regs; i++) 8841 gr_values[i].known = 0; 8842 } 8843 clear_qp_mutex (qp_changemask); 8844 clear_qp_implies (qp_changemask, qp_changemask); 8845 } 8846 /* After a call, all register values are undefined, except those marked 8847 as "safe". */ 8848 else if (strncmp (idesc->name, "br.call", 6) == 0 8849 || strncmp (idesc->name, "brl.call", 7) == 0) 8850 { 8851 /* FIXME keep GR values which are marked as "safe_across_calls" */ 8852 clear_register_values (); 8853 clear_qp_mutex (~qp_safe_across_calls); 8854 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); 8855 clear_qp_branch_flag (~qp_safe_across_calls); 8856 } 8857 else if (is_interruption_or_rfi (idesc) 8858 || is_taken_branch (idesc)) 8859 { 8860 clear_register_values (); 8861 clear_qp_mutex (~(valueT) 0); 8862 clear_qp_implies (~(valueT) 0, ~(valueT) 0); 8863 } 8864 /* Look for mutex and implies relations. */ 8865 else if ((idesc->operands[0] == IA64_OPND_P1 8866 || idesc->operands[0] == IA64_OPND_P2) 8867 && (idesc->operands[1] == IA64_OPND_P1 8868 || idesc->operands[1] == IA64_OPND_P2)) 8869 { 8870 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8871 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8872 valueT p1mask = (valueT) 1 << p1; 8873 valueT p2mask = (valueT) 1 << p2; 8874 8875 /* If one of the PRs is PR0, we can't really do anything. */ 8876 if (p1 == 0 || p2 == 0) 8877 { 8878 if (md.debug_dv) 8879 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); 8880 } 8881 /* In general, clear mutexes and implies which include P1 or P2, 8882 with the following exceptions. */ 8883 else if (has_suffix_p (idesc->name, ".or.andcm") 8884 || has_suffix_p (idesc->name, ".and.orcm")) 8885 { 8886 add_qp_mutex (p1mask | p2mask); 8887 clear_qp_implies (p2mask, p1mask); 8888 } 8889 else if (has_suffix_p (idesc->name, ".andcm") 8890 || has_suffix_p (idesc->name, ".and")) 8891 { 8892 clear_qp_implies (0, p1mask | p2mask); 8893 } 8894 else if (has_suffix_p (idesc->name, ".orcm") 8895 || has_suffix_p (idesc->name, ".or")) 8896 { 8897 clear_qp_mutex (p1mask | p2mask); 8898 clear_qp_implies (p1mask | p2mask, 0); 8899 } 8900 else 8901 { 8902 clear_qp_implies (p1mask | p2mask, p1mask | p2mask); 8903 if (has_suffix_p (idesc->name, ".unc")) 8904 { 8905 add_qp_mutex (p1mask | p2mask); 8906 if (CURR_SLOT.qp_regno != 0) 8907 { 8908 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, 8909 CURR_SLOT.qp_regno); 8910 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, 8911 CURR_SLOT.qp_regno); 8912 } 8913 } 8914 else if (CURR_SLOT.qp_regno == 0) 8915 { 8916 add_qp_mutex (p1mask | p2mask); 8917 } 8918 else 8919 { 8920 clear_qp_mutex (p1mask | p2mask); 8921 } 8922 } 8923 } 8924 /* Look for mov imm insns into GRs. */ 8925 else if (idesc->operands[0] == IA64_OPND_R1 8926 && (idesc->operands[1] == IA64_OPND_IMM22 8927 || idesc->operands[1] == IA64_OPND_IMMU64) 8928 && (strcmp (idesc->name, "mov") == 0 8929 || strcmp (idesc->name, "movl") == 0)) 8930 { 8931 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; 8932 if (regno > 0 && regno < NELEMS (gr_values)) 8933 { 8934 gr_values[regno].known = 1; 8935 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; 8936 gr_values[regno].path = md.path; 8937 if (md.debug_dv) 8938 { 8939 fprintf (stderr, " Know gr%d = ", regno); 8940 fprintf_vma (stderr, gr_values[regno].value); 8941 fputs ("\n", stderr); 8942 } 8943 } 8944 } 8945 else 8946 { 8947 clear_qp_mutex (qp_changemask); 8948 clear_qp_implies (qp_changemask, qp_changemask); 8949 } 8950} 8951 8952/* Return whether the given predicate registers are currently mutex. */ 8953 8954static int 8955qp_mutex (p1, p2, path) 8956 int p1; 8957 int p2; 8958 int path; 8959{ 8960 int i; 8961 valueT mask; 8962 8963 if (p1 != p2) 8964 { 8965 mask = ((valueT) 1 << p1) | (valueT) 1 << p2; 8966 for (i = 0; i < qp_mutexeslen; i++) 8967 { 8968 if (qp_mutexes[i].path >= path 8969 && (qp_mutexes[i].prmask & mask) == mask) 8970 return 1; 8971 } 8972 } 8973 return 0; 8974} 8975 8976/* Return whether the given resource is in the given insn's list of chks 8977 Return 1 if the conflict is absolutely determined, 2 if it's a potential 8978 conflict. */ 8979 8980static int 8981resources_match (rs, idesc, note, qp_regno, path) 8982 struct rsrc *rs; 8983 struct ia64_opcode *idesc; 8984 int note; 8985 int qp_regno; 8986 int path; 8987{ 8988 struct rsrc specs[MAX_SPECS]; 8989 int count; 8990 8991 /* If the marked resource's qp_regno and the given qp_regno are mutex, 8992 we don't need to check. One exception is note 11, which indicates that 8993 target predicates are written regardless of PR[qp]. */ 8994 if (qp_mutex (rs->qp_regno, qp_regno, path) 8995 && note != 11) 8996 return 0; 8997 8998 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); 8999 while (count-- > 0) 9000 { 9001 /* UNAT checking is a bit more specific than other resources */ 9002 if (rs->dependency->specifier == IA64_RS_AR_UNAT 9003 && specs[count].mem_offset.hint 9004 && rs->mem_offset.hint) 9005 { 9006 if (rs->mem_offset.base == specs[count].mem_offset.base) 9007 { 9008 if (((rs->mem_offset.offset >> 3) & 0x3F) == 9009 ((specs[count].mem_offset.offset >> 3) & 0x3F)) 9010 return 1; 9011 else 9012 continue; 9013 } 9014 } 9015 9016 /* Skip apparent PR write conflicts where both writes are an AND or both 9017 writes are an OR. */ 9018 if (rs->dependency->specifier == IA64_RS_PR 9019 || rs->dependency->specifier == IA64_RS_PRr 9020 || rs->dependency->specifier == IA64_RS_PR63) 9021 { 9022 if (specs[count].cmp_type != CMP_NONE 9023 && specs[count].cmp_type == rs->cmp_type) 9024 { 9025 if (md.debug_dv) 9026 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", 9027 dv_mode[rs->dependency->mode], 9028 rs->dependency->specifier != IA64_RS_PR63 ? 9029 specs[count].index : 63); 9030 continue; 9031 } 9032 if (md.debug_dv) 9033 fprintf (stderr, 9034 " %s on parallel compare conflict %s vs %s on PR%d\n", 9035 dv_mode[rs->dependency->mode], 9036 dv_cmp_type[rs->cmp_type], 9037 dv_cmp_type[specs[count].cmp_type], 9038 rs->dependency->specifier != IA64_RS_PR63 ? 9039 specs[count].index : 63); 9040 9041 } 9042 9043 /* If either resource is not specific, conservatively assume a conflict 9044 */ 9045 if (!specs[count].specific || !rs->specific) 9046 return 2; 9047 else if (specs[count].index == rs->index) 9048 return 1; 9049 } 9050#if 0 9051 if (md.debug_dv) 9052 fprintf (stderr, " No %s conflicts\n", rs->dependency->name); 9053#endif 9054 9055 return 0; 9056} 9057 9058/* Indicate an instruction group break; if INSERT_STOP is non-zero, then 9059 insert a stop to create the break. Update all resource dependencies 9060 appropriately. If QP_REGNO is non-zero, only apply the break to resources 9061 which use the same QP_REGNO and have the link_to_qp_branch flag set. 9062 If SAVE_CURRENT is non-zero, don't affect resources marked by the current 9063 instruction. */ 9064 9065static void 9066insn_group_break (insert_stop, qp_regno, save_current) 9067 int insert_stop; 9068 int qp_regno; 9069 int save_current; 9070{ 9071 int i; 9072 9073 if (insert_stop && md.num_slots_in_use > 0) 9074 PREV_SLOT.end_of_insn_group = 1; 9075 9076 if (md.debug_dv) 9077 { 9078 fprintf (stderr, " Insn group break%s", 9079 (insert_stop ? " (w/stop)" : "")); 9080 if (qp_regno != 0) 9081 fprintf (stderr, " effective for QP=%d", qp_regno); 9082 fprintf (stderr, "\n"); 9083 } 9084 9085 i = 0; 9086 while (i < regdepslen) 9087 { 9088 const struct ia64_dependency *dep = regdeps[i].dependency; 9089 9090 if (qp_regno != 0 9091 && regdeps[i].qp_regno != qp_regno) 9092 { 9093 ++i; 9094 continue; 9095 } 9096 9097 if (save_current 9098 && CURR_SLOT.src_file == regdeps[i].file 9099 && CURR_SLOT.src_line == regdeps[i].line) 9100 { 9101 ++i; 9102 continue; 9103 } 9104 9105 /* clear dependencies which are automatically cleared by a stop, or 9106 those that have reached the appropriate state of insn serialization */ 9107 if (dep->semantics == IA64_DVS_IMPLIED 9108 || dep->semantics == IA64_DVS_IMPLIEDF 9109 || regdeps[i].insn_srlz == STATE_SRLZ) 9110 { 9111 print_dependency ("Removing", i); 9112 regdeps[i] = regdeps[--regdepslen]; 9113 } 9114 else 9115 { 9116 if (dep->semantics == IA64_DVS_DATA 9117 || dep->semantics == IA64_DVS_INSTR 9118 || dep->semantics == IA64_DVS_SPECIFIC) 9119 { 9120 if (regdeps[i].insn_srlz == STATE_NONE) 9121 regdeps[i].insn_srlz = STATE_STOP; 9122 if (regdeps[i].data_srlz == STATE_NONE) 9123 regdeps[i].data_srlz = STATE_STOP; 9124 } 9125 ++i; 9126 } 9127 } 9128} 9129 9130/* Add the given resource usage spec to the list of active dependencies. */ 9131 9132static void 9133mark_resource (idesc, dep, spec, depind, path) 9134 struct ia64_opcode *idesc ATTRIBUTE_UNUSED; 9135 const struct ia64_dependency *dep ATTRIBUTE_UNUSED; 9136 struct rsrc *spec; 9137 int depind; 9138 int path; 9139{ 9140 if (regdepslen == regdepstotlen) 9141 { 9142 regdepstotlen += 20; 9143 regdeps = (struct rsrc *) 9144 xrealloc ((void *) regdeps, 9145 regdepstotlen * sizeof (struct rsrc)); 9146 } 9147 9148 regdeps[regdepslen] = *spec; 9149 regdeps[regdepslen].depind = depind; 9150 regdeps[regdepslen].path = path; 9151 regdeps[regdepslen].file = CURR_SLOT.src_file; 9152 regdeps[regdepslen].line = CURR_SLOT.src_line; 9153 9154 print_dependency ("Adding", regdepslen); 9155 9156 ++regdepslen; 9157} 9158 9159static void 9160print_dependency (action, depind) 9161 const char *action; 9162 int depind; 9163{ 9164 if (md.debug_dv) 9165 { 9166 fprintf (stderr, " %s %s '%s'", 9167 action, dv_mode[(regdeps[depind].dependency)->mode], 9168 (regdeps[depind].dependency)->name); 9169 if (regdeps[depind].specific && regdeps[depind].index != 0) 9170 fprintf (stderr, " (%d)", regdeps[depind].index); 9171 if (regdeps[depind].mem_offset.hint) 9172 { 9173 fputs (" ", stderr); 9174 fprintf_vma (stderr, regdeps[depind].mem_offset.base); 9175 fputs ("+", stderr); 9176 fprintf_vma (stderr, regdeps[depind].mem_offset.offset); 9177 } 9178 fprintf (stderr, "\n"); 9179 } 9180} 9181 9182static void 9183instruction_serialization () 9184{ 9185 int i; 9186 if (md.debug_dv) 9187 fprintf (stderr, " Instruction serialization\n"); 9188 for (i = 0; i < regdepslen; i++) 9189 if (regdeps[i].insn_srlz == STATE_STOP) 9190 regdeps[i].insn_srlz = STATE_SRLZ; 9191} 9192 9193static void 9194data_serialization () 9195{ 9196 int i = 0; 9197 if (md.debug_dv) 9198 fprintf (stderr, " Data serialization\n"); 9199 while (i < regdepslen) 9200 { 9201 if (regdeps[i].data_srlz == STATE_STOP 9202 /* Note: as of 991210, all "other" dependencies are cleared by a 9203 data serialization. This might change with new tables */ 9204 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) 9205 { 9206 print_dependency ("Removing", i); 9207 regdeps[i] = regdeps[--regdepslen]; 9208 } 9209 else 9210 ++i; 9211 } 9212} 9213 9214/* Insert stops and serializations as needed to avoid DVs. */ 9215 9216static void 9217remove_marked_resource (rs) 9218 struct rsrc *rs; 9219{ 9220 switch (rs->dependency->semantics) 9221 { 9222 case IA64_DVS_SPECIFIC: 9223 if (md.debug_dv) 9224 fprintf (stderr, "Implementation-specific, assume worst case...\n"); 9225 /* ...fall through... */ 9226 case IA64_DVS_INSTR: 9227 if (md.debug_dv) 9228 fprintf (stderr, "Inserting instr serialization\n"); 9229 if (rs->insn_srlz < STATE_STOP) 9230 insn_group_break (1, 0, 0); 9231 if (rs->insn_srlz < STATE_SRLZ) 9232 { 9233 int oldqp = CURR_SLOT.qp_regno; 9234 struct ia64_opcode *oldidesc = CURR_SLOT.idesc; 9235 /* Manually jam a srlz.i insn into the stream */ 9236 CURR_SLOT.qp_regno = 0; 9237 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); 9238 instruction_serialization (); 9239 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9240 if (++md.num_slots_in_use >= NUM_SLOTS) 9241 emit_one_bundle (); 9242 CURR_SLOT.qp_regno = oldqp; 9243 CURR_SLOT.idesc = oldidesc; 9244 } 9245 insn_group_break (1, 0, 0); 9246 break; 9247 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all 9248 "other" types of DV are eliminated 9249 by a data serialization */ 9250 case IA64_DVS_DATA: 9251 if (md.debug_dv) 9252 fprintf (stderr, "Inserting data serialization\n"); 9253 if (rs->data_srlz < STATE_STOP) 9254 insn_group_break (1, 0, 0); 9255 { 9256 int oldqp = CURR_SLOT.qp_regno; 9257 struct ia64_opcode *oldidesc = CURR_SLOT.idesc; 9258 /* Manually jam a srlz.d insn into the stream */ 9259 CURR_SLOT.qp_regno = 0; 9260 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); 9261 data_serialization (); 9262 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9263 if (++md.num_slots_in_use >= NUM_SLOTS) 9264 emit_one_bundle (); 9265 CURR_SLOT.qp_regno = oldqp; 9266 CURR_SLOT.idesc = oldidesc; 9267 } 9268 break; 9269 case IA64_DVS_IMPLIED: 9270 case IA64_DVS_IMPLIEDF: 9271 if (md.debug_dv) 9272 fprintf (stderr, "Inserting stop\n"); 9273 insn_group_break (1, 0, 0); 9274 break; 9275 default: 9276 break; 9277 } 9278} 9279 9280/* Check the resources used by the given opcode against the current dependency 9281 list. 9282 9283 The check is run once for each execution path encountered. In this case, 9284 a unique execution path is the sequence of instructions following a code 9285 entry point, e.g. the following has three execution paths, one starting 9286 at L0, one at L1, and one at L2. 9287 9288 L0: nop 9289 L1: add 9290 L2: add 9291 br.ret 9292*/ 9293 9294static void 9295check_dependencies (idesc) 9296 struct ia64_opcode *idesc; 9297{ 9298 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 9299 int path; 9300 int i; 9301 9302 /* Note that the number of marked resources may change within the 9303 loop if in auto mode. */ 9304 i = 0; 9305 while (i < regdepslen) 9306 { 9307 struct rsrc *rs = ®deps[i]; 9308 const struct ia64_dependency *dep = rs->dependency; 9309 int chkind; 9310 int note; 9311 int start_over = 0; 9312 9313 if (dep->semantics == IA64_DVS_NONE 9314 || (chkind = depends_on (rs->depind, idesc)) == -1) 9315 { 9316 ++i; 9317 continue; 9318 } 9319 9320 note = NOTE (opdeps->chks[chkind]); 9321 9322 /* Check this resource against each execution path seen thus far. */ 9323 for (path = 0; path <= md.path; path++) 9324 { 9325 int matchtype; 9326 9327 /* If the dependency wasn't on the path being checked, ignore it. */ 9328 if (rs->path < path) 9329 continue; 9330 9331 /* If the QP for this insn implies a QP which has branched, don't 9332 bother checking. Ed. NOTE: I don't think this check is terribly 9333 useful; what's the point of generating code which will only be 9334 reached if its QP is zero? 9335 This code was specifically inserted to handle the following code, 9336 based on notes from Intel's DV checking code, where p1 implies p2. 9337 9338 mov r4 = 2 9339 (p2) br.cond L 9340 (p1) mov r4 = 7 9341 */ 9342 if (CURR_SLOT.qp_regno != 0) 9343 { 9344 int skip = 0; 9345 int implies; 9346 for (implies = 0; implies < qp_implieslen; implies++) 9347 { 9348 if (qp_implies[implies].path >= path 9349 && qp_implies[implies].p1 == CURR_SLOT.qp_regno 9350 && qp_implies[implies].p2_branched) 9351 { 9352 skip = 1; 9353 break; 9354 } 9355 } 9356 if (skip) 9357 continue; 9358 } 9359 9360 if ((matchtype = resources_match (rs, idesc, note, 9361 CURR_SLOT.qp_regno, path)) != 0) 9362 { 9363 char msg[1024]; 9364 char pathmsg[256] = ""; 9365 char indexmsg[256] = ""; 9366 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); 9367 9368 if (path != 0) 9369 sprintf (pathmsg, " when entry is at label '%s'", 9370 md.entry_labels[path - 1]); 9371 if (rs->specific && rs->index != 0) 9372 sprintf (indexmsg, ", specific resource number is %d", 9373 rs->index); 9374 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", 9375 idesc->name, 9376 (certain ? "violates" : "may violate"), 9377 dv_mode[dep->mode], dep->name, 9378 dv_sem[dep->semantics], 9379 pathmsg, indexmsg); 9380 9381 if (md.explicit_mode) 9382 { 9383 as_warn ("%s", msg); 9384 if (path < md.path) 9385 as_warn (_("Only the first path encountering the conflict " 9386 "is reported")); 9387 as_warn_where (rs->file, rs->line, 9388 _("This is the location of the " 9389 "conflicting usage")); 9390 /* Don't bother checking other paths, to avoid duplicating 9391 the same warning */ 9392 break; 9393 } 9394 else 9395 { 9396 if (md.debug_dv) 9397 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); 9398 9399 remove_marked_resource (rs); 9400 9401 /* since the set of dependencies has changed, start over */ 9402 /* FIXME -- since we're removing dvs as we go, we 9403 probably don't really need to start over... */ 9404 start_over = 1; 9405 break; 9406 } 9407 } 9408 } 9409 if (start_over) 9410 i = 0; 9411 else 9412 ++i; 9413 } 9414} 9415 9416/* Register new dependencies based on the given opcode. */ 9417 9418static void 9419mark_resources (idesc) 9420 struct ia64_opcode *idesc; 9421{ 9422 int i; 9423 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 9424 int add_only_qp_reads = 0; 9425 9426 /* A conditional branch only uses its resources if it is taken; if it is 9427 taken, we stop following that path. The other branch types effectively 9428 *always* write their resources. If it's not taken, register only QP 9429 reads. */ 9430 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) 9431 { 9432 add_only_qp_reads = 1; 9433 } 9434 9435 if (md.debug_dv) 9436 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); 9437 9438 for (i = 0; i < opdeps->nregs; i++) 9439 { 9440 const struct ia64_dependency *dep; 9441 struct rsrc specs[MAX_SPECS]; 9442 int note; 9443 int path; 9444 int count; 9445 9446 dep = ia64_find_dependency (opdeps->regs[i]); 9447 note = NOTE (opdeps->regs[i]); 9448 9449 if (add_only_qp_reads 9450 && !(dep->mode == IA64_DV_WAR 9451 && (dep->specifier == IA64_RS_PR 9452 || dep->specifier == IA64_RS_PRr 9453 || dep->specifier == IA64_RS_PR63))) 9454 continue; 9455 9456 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); 9457 9458#if 0 9459 if (md.debug_dv && !count) 9460 fprintf (stderr, " No %s %s usage found (path %d)\n", 9461 dv_mode[dep->mode], dep->name, md.path); 9462#endif 9463 9464 while (count-- > 0) 9465 { 9466 mark_resource (idesc, dep, &specs[count], 9467 DEP (opdeps->regs[i]), md.path); 9468 } 9469 9470 /* The execution path may affect register values, which may in turn 9471 affect which indirect-access resources are accessed. */ 9472 switch (dep->specifier) 9473 { 9474 default: 9475 break; 9476 case IA64_RS_CPUID: 9477 case IA64_RS_DBR: 9478 case IA64_RS_IBR: 9479 case IA64_RS_MSR: 9480 case IA64_RS_PKR: 9481 case IA64_RS_PMC: 9482 case IA64_RS_PMD: 9483 case IA64_RS_RR: 9484 for (path = 0; path < md.path; path++) 9485 { 9486 count = specify_resource (dep, idesc, DV_REG, specs, note, path); 9487 while (count-- > 0) 9488 mark_resource (idesc, dep, &specs[count], 9489 DEP (opdeps->regs[i]), path); 9490 } 9491 break; 9492 } 9493 } 9494} 9495 9496/* Remove dependencies when they no longer apply. */ 9497 9498static void 9499update_dependencies (idesc) 9500 struct ia64_opcode *idesc; 9501{ 9502 int i; 9503 9504 if (strcmp (idesc->name, "srlz.i") == 0) 9505 { 9506 instruction_serialization (); 9507 } 9508 else if (strcmp (idesc->name, "srlz.d") == 0) 9509 { 9510 data_serialization (); 9511 } 9512 else if (is_interruption_or_rfi (idesc) 9513 || is_taken_branch (idesc)) 9514 { 9515 /* Although technically the taken branch doesn't clear dependencies 9516 which require a srlz.[id], we don't follow the branch; the next 9517 instruction is assumed to start with a clean slate. */ 9518 regdepslen = 0; 9519 md.path = 0; 9520 } 9521 else if (is_conditional_branch (idesc) 9522 && CURR_SLOT.qp_regno != 0) 9523 { 9524 int is_call = strstr (idesc->name, ".call") != NULL; 9525 9526 for (i = 0; i < qp_implieslen; i++) 9527 { 9528 /* If the conditional branch's predicate is implied by the predicate 9529 in an existing dependency, remove that dependency. */ 9530 if (qp_implies[i].p2 == CURR_SLOT.qp_regno) 9531 { 9532 int depind = 0; 9533 /* Note that this implied predicate takes a branch so that if 9534 a later insn generates a DV but its predicate implies this 9535 one, we can avoid the false DV warning. */ 9536 qp_implies[i].p2_branched = 1; 9537 while (depind < regdepslen) 9538 { 9539 if (regdeps[depind].qp_regno == qp_implies[i].p1) 9540 { 9541 print_dependency ("Removing", depind); 9542 regdeps[depind] = regdeps[--regdepslen]; 9543 } 9544 else 9545 ++depind; 9546 } 9547 } 9548 } 9549 /* Any marked resources which have this same predicate should be 9550 cleared, provided that the QP hasn't been modified between the 9551 marking instruction and the branch. */ 9552 if (is_call) 9553 { 9554 insn_group_break (0, CURR_SLOT.qp_regno, 1); 9555 } 9556 else 9557 { 9558 i = 0; 9559 while (i < regdepslen) 9560 { 9561 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno 9562 && regdeps[i].link_to_qp_branch 9563 && (regdeps[i].file != CURR_SLOT.src_file 9564 || regdeps[i].line != CURR_SLOT.src_line)) 9565 { 9566 /* Treat like a taken branch */ 9567 print_dependency ("Removing", i); 9568 regdeps[i] = regdeps[--regdepslen]; 9569 } 9570 else 9571 ++i; 9572 } 9573 } 9574 } 9575} 9576 9577/* Examine the current instruction for dependency violations. */ 9578 9579static int 9580check_dv (idesc) 9581 struct ia64_opcode *idesc; 9582{ 9583 if (md.debug_dv) 9584 { 9585 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", 9586 idesc->name, CURR_SLOT.src_line, 9587 idesc->dependencies->nchks, 9588 idesc->dependencies->nregs); 9589 } 9590 9591 /* Look through the list of currently marked resources; if the current 9592 instruction has the dependency in its chks list which uses that resource, 9593 check against the specific resources used. */ 9594 check_dependencies (idesc); 9595 9596 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), 9597 then add them to the list of marked resources. */ 9598 mark_resources (idesc); 9599 9600 /* There are several types of dependency semantics, and each has its own 9601 requirements for being cleared 9602 9603 Instruction serialization (insns separated by interruption, rfi, or 9604 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. 9605 9606 Data serialization (instruction serialization, or writer + srlz.d + 9607 reader, where writer and srlz.d are in separate groups) clears 9608 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to 9609 always be the case). 9610 9611 Instruction group break (groups separated by stop, taken branch, 9612 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. 9613 */ 9614 update_dependencies (idesc); 9615 9616 /* Sometimes, knowing a register value allows us to avoid giving a false DV 9617 warning. Keep track of as many as possible that are useful. */ 9618 note_register_values (idesc); 9619 9620 /* We don't need or want this anymore. */ 9621 md.mem_offset.hint = 0; 9622 9623 return 0; 9624} 9625 9626/* Translate one line of assembly. Pseudo ops and labels do not show 9627 here. */ 9628void 9629md_assemble (str) 9630 char *str; 9631{ 9632 char *saved_input_line_pointer, *mnemonic; 9633 const struct pseudo_opcode *pdesc; 9634 struct ia64_opcode *idesc; 9635 unsigned char qp_regno; 9636 unsigned int flags; 9637 int ch; 9638 9639 saved_input_line_pointer = input_line_pointer; 9640 input_line_pointer = str; 9641 9642 /* extract the opcode (mnemonic): */ 9643 9644 mnemonic = input_line_pointer; 9645 ch = get_symbol_end (); 9646 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); 9647 if (pdesc) 9648 { 9649 *input_line_pointer = ch; 9650 (*pdesc->handler) (pdesc->arg); 9651 goto done; 9652 } 9653 9654 /* Find the instruction descriptor matching the arguments. */ 9655 9656 idesc = ia64_find_opcode (mnemonic); 9657 *input_line_pointer = ch; 9658 if (!idesc) 9659 { 9660 as_bad ("Unknown opcode `%s'", mnemonic); 9661 goto done; 9662 } 9663 9664 idesc = parse_operands (idesc); 9665 if (!idesc) 9666 goto done; 9667 9668 /* Handle the dynamic ops we can handle now: */ 9669 if (idesc->type == IA64_TYPE_DYN) 9670 { 9671 if (strcmp (idesc->name, "add") == 0) 9672 { 9673 if (CURR_SLOT.opnd[2].X_op == O_register 9674 && CURR_SLOT.opnd[2].X_add_number < 4) 9675 mnemonic = "addl"; 9676 else 9677 mnemonic = "adds"; 9678 ia64_free_opcode (idesc); 9679 idesc = ia64_find_opcode (mnemonic); 9680#if 0 9681 know (!idesc->next); 9682#endif 9683 } 9684 else if (strcmp (idesc->name, "mov") == 0) 9685 { 9686 enum ia64_opnd opnd1, opnd2; 9687 int rop; 9688 9689 opnd1 = idesc->operands[0]; 9690 opnd2 = idesc->operands[1]; 9691 if (opnd1 == IA64_OPND_AR3) 9692 rop = 0; 9693 else if (opnd2 == IA64_OPND_AR3) 9694 rop = 1; 9695 else 9696 abort (); 9697 if (CURR_SLOT.opnd[rop].X_op == O_register 9698 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) 9699 mnemonic = "mov.i"; 9700 else 9701 mnemonic = "mov.m"; 9702 ia64_free_opcode (idesc); 9703 idesc = ia64_find_opcode (mnemonic); 9704 while (idesc != NULL 9705 && (idesc->operands[0] != opnd1 9706 || idesc->operands[1] != opnd2)) 9707 idesc = get_next_opcode (idesc); 9708 } 9709 } 9710 9711 qp_regno = 0; 9712 if (md.qp.X_op == O_register) 9713 { 9714 qp_regno = md.qp.X_add_number - REG_P; 9715 md.qp.X_op = O_absent; 9716 } 9717 9718 flags = idesc->flags; 9719 9720 if ((flags & IA64_OPCODE_FIRST) != 0) 9721 insn_group_break (1, 0, 0); 9722 9723 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) 9724 { 9725 as_bad ("`%s' cannot be predicated", idesc->name); 9726 goto done; 9727 } 9728 9729 /* Build the instruction. */ 9730 CURR_SLOT.qp_regno = qp_regno; 9731 CURR_SLOT.idesc = idesc; 9732 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); 9733 dwarf2_where (&CURR_SLOT.debug_line); 9734 9735 /* Add unwind entry, if there is one. */ 9736 if (unwind.current_entry) 9737 { 9738 CURR_SLOT.unwind_record = unwind.current_entry; 9739 unwind.current_entry = NULL; 9740 } 9741 9742 /* Check for dependency violations. */ 9743 if (md.detect_dv) 9744 check_dv (idesc); 9745 9746 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9747 if (++md.num_slots_in_use >= NUM_SLOTS) 9748 emit_one_bundle (); 9749 9750 if ((flags & IA64_OPCODE_LAST) != 0) 9751 insn_group_break (1, 0, 0); 9752 9753 md.last_text_seg = now_seg; 9754 9755 done: 9756 input_line_pointer = saved_input_line_pointer; 9757} 9758 9759/* Called when symbol NAME cannot be found in the symbol table. 9760 Should be used for dynamic valued symbols only. */ 9761 9762symbolS * 9763md_undefined_symbol (name) 9764 char *name ATTRIBUTE_UNUSED; 9765{ 9766 return 0; 9767} 9768 9769/* Called for any expression that can not be recognized. When the 9770 function is called, `input_line_pointer' will point to the start of 9771 the expression. */ 9772 9773void 9774md_operand (e) 9775 expressionS *e; 9776{ 9777 enum pseudo_type pseudo_type; 9778 const char *name; 9779 size_t len; 9780 int ch, i; 9781 9782 switch (*input_line_pointer) 9783 { 9784 case '@': 9785 /* Find what relocation pseudo-function we're dealing with. */ 9786 pseudo_type = 0; 9787 ch = *++input_line_pointer; 9788 for (i = 0; i < NELEMS (pseudo_func); ++i) 9789 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) 9790 { 9791 len = strlen (pseudo_func[i].name); 9792 if (strncmp (pseudo_func[i].name + 1, 9793 input_line_pointer + 1, len - 1) == 0 9794 && !is_part_of_name (input_line_pointer[len])) 9795 { 9796 input_line_pointer += len; 9797 pseudo_type = pseudo_func[i].type; 9798 break; 9799 } 9800 } 9801 switch (pseudo_type) 9802 { 9803 case PSEUDO_FUNC_RELOC: 9804 SKIP_WHITESPACE (); 9805 if (*input_line_pointer != '(') 9806 { 9807 as_bad ("Expected '('"); 9808 goto err; 9809 } 9810 /* Skip '('. */ 9811 ++input_line_pointer; 9812 expression (e); 9813 if (*input_line_pointer++ != ')') 9814 { 9815 as_bad ("Missing ')'"); 9816 goto err; 9817 } 9818 if (e->X_op != O_symbol) 9819 { 9820 if (e->X_op != O_pseudo_fixup) 9821 { 9822 as_bad ("Not a symbolic expression"); 9823 goto err; 9824 } 9825 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE 9826 && i == FUNC_LT_RELATIVE) 9827 i = FUNC_LT_FPTR_RELATIVE; 9828 else 9829 { 9830 as_bad ("Illegal combination of relocation functions"); 9831 goto err; 9832 } 9833 } 9834 /* Make sure gas doesn't get rid of local symbols that are used 9835 in relocs. */ 9836 e->X_op = O_pseudo_fixup; 9837 e->X_op_symbol = pseudo_func[i].u.sym; 9838 break; 9839 9840 case PSEUDO_FUNC_CONST: 9841 e->X_op = O_constant; 9842 e->X_add_number = pseudo_func[i].u.ival; 9843 break; 9844 9845 case PSEUDO_FUNC_REG: 9846 e->X_op = O_register; 9847 e->X_add_number = pseudo_func[i].u.ival; 9848 break; 9849 9850 default: 9851 name = input_line_pointer - 1; 9852 get_symbol_end (); 9853 as_bad ("Unknown pseudo function `%s'", name); 9854 goto err; 9855 } 9856 break; 9857 9858 case '[': 9859 ++input_line_pointer; 9860 expression (e); 9861 if (*input_line_pointer != ']') 9862 { 9863 as_bad ("Closing bracket misssing"); 9864 goto err; 9865 } 9866 else 9867 { 9868 if (e->X_op != O_register) 9869 as_bad ("Register expected as index"); 9870 9871 ++input_line_pointer; 9872 e->X_op = O_index; 9873 } 9874 break; 9875 9876 default: 9877 break; 9878 } 9879 return; 9880 9881 err: 9882 ignore_rest_of_line (); 9883} 9884 9885/* Return 1 if it's OK to adjust a reloc by replacing the symbol with 9886 a section symbol plus some offset. For relocs involving @fptr(), 9887 directives we don't want such adjustments since we need to have the 9888 original symbol's name in the reloc. */ 9889int 9890ia64_fix_adjustable (fix) 9891 fixS *fix; 9892{ 9893 /* Prevent all adjustments to global symbols */ 9894 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) 9895 return 0; 9896 9897 switch (fix->fx_r_type) 9898 { 9899 case BFD_RELOC_IA64_FPTR64I: 9900 case BFD_RELOC_IA64_FPTR32MSB: 9901 case BFD_RELOC_IA64_FPTR32LSB: 9902 case BFD_RELOC_IA64_FPTR64MSB: 9903 case BFD_RELOC_IA64_FPTR64LSB: 9904 case BFD_RELOC_IA64_LTOFF_FPTR22: 9905 case BFD_RELOC_IA64_LTOFF_FPTR64I: 9906 return 0; 9907 default: 9908 break; 9909 } 9910 9911 return 1; 9912} 9913 9914int 9915ia64_force_relocation (fix) 9916 fixS *fix; 9917{ 9918 switch (fix->fx_r_type) 9919 { 9920 case BFD_RELOC_IA64_FPTR64I: 9921 case BFD_RELOC_IA64_FPTR32MSB: 9922 case BFD_RELOC_IA64_FPTR32LSB: 9923 case BFD_RELOC_IA64_FPTR64MSB: 9924 case BFD_RELOC_IA64_FPTR64LSB: 9925 9926 case BFD_RELOC_IA64_LTOFF22: 9927 case BFD_RELOC_IA64_LTOFF64I: 9928 case BFD_RELOC_IA64_LTOFF_FPTR22: 9929 case BFD_RELOC_IA64_LTOFF_FPTR64I: 9930 case BFD_RELOC_IA64_PLTOFF22: 9931 case BFD_RELOC_IA64_PLTOFF64I: 9932 case BFD_RELOC_IA64_PLTOFF64MSB: 9933 case BFD_RELOC_IA64_PLTOFF64LSB: 9934 return 1; 9935 9936 default: 9937 return 0; 9938 } 9939 return 0; 9940} 9941 9942/* Decide from what point a pc-relative relocation is relative to, 9943 relative to the pc-relative fixup. Er, relatively speaking. */ 9944long 9945ia64_pcrel_from_section (fix, sec) 9946 fixS *fix; 9947 segT sec; 9948{ 9949 unsigned long off = fix->fx_frag->fr_address + fix->fx_where; 9950 9951 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) 9952 off &= ~0xfUL; 9953 9954 return off; 9955} 9956 9957/* This is called whenever some data item (not an instruction) needs a 9958 fixup. We pick the right reloc code depending on the byteorder 9959 currently in effect. */ 9960void 9961ia64_cons_fix_new (f, where, nbytes, exp) 9962 fragS *f; 9963 int where; 9964 int nbytes; 9965 expressionS *exp; 9966{ 9967 bfd_reloc_code_real_type code; 9968 fixS *fix; 9969 9970 switch (nbytes) 9971 { 9972 /* There are no reloc for 8 and 16 bit quantities, but we allow 9973 them here since they will work fine as long as the expression 9974 is fully defined at the end of the pass over the source file. */ 9975 case 1: code = BFD_RELOC_8; break; 9976 case 2: code = BFD_RELOC_16; break; 9977 case 4: 9978 if (target_big_endian) 9979 code = BFD_RELOC_IA64_DIR32MSB; 9980 else 9981 code = BFD_RELOC_IA64_DIR32LSB; 9982 break; 9983 9984 case 8: 9985 if (target_big_endian) 9986 code = BFD_RELOC_IA64_DIR64MSB; 9987 else 9988 code = BFD_RELOC_IA64_DIR64LSB; 9989 break; 9990 9991 case 16: 9992 if (exp->X_op == O_pseudo_fixup 9993 && exp->X_op_symbol 9994 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC) 9995 { 9996 if (target_big_endian) 9997 code = BFD_RELOC_IA64_IPLTMSB; 9998 else 9999 code = BFD_RELOC_IA64_IPLTLSB; 10000 10001 exp->X_op = O_symbol; 10002 break; 10003 } 10004 /* FALLTHRU */ 10005 10006 default: 10007 as_bad ("Unsupported fixup size %d", nbytes); 10008 ignore_rest_of_line (); 10009 return; 10010 } 10011 if (exp->X_op == O_pseudo_fixup) 10012 { 10013 /* ??? */ 10014 exp->X_op = O_symbol; 10015 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); 10016 } 10017 10018 fix = fix_new_exp (f, where, nbytes, exp, 0, code); 10019 /* We need to store the byte order in effect in case we're going 10020 to fix an 8 or 16 bit relocation (for which there no real 10021 relocs available). See md_apply_fix3(). */ 10022 fix->tc_fix_data.bigendian = target_big_endian; 10023} 10024 10025/* Return the actual relocation we wish to associate with the pseudo 10026 reloc described by SYM and R_TYPE. SYM should be one of the 10027 symbols in the pseudo_func array, or NULL. */ 10028 10029static bfd_reloc_code_real_type 10030ia64_gen_real_reloc_type (sym, r_type) 10031 struct symbol *sym; 10032 bfd_reloc_code_real_type r_type; 10033{ 10034 bfd_reloc_code_real_type new = 0; 10035 10036 if (sym == NULL) 10037 { 10038 return r_type; 10039 } 10040 10041 switch (S_GET_VALUE (sym)) 10042 { 10043 case FUNC_FPTR_RELATIVE: 10044 switch (r_type) 10045 { 10046 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; 10047 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; 10048 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; 10049 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; 10050 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; 10051 default: break; 10052 } 10053 break; 10054 10055 case FUNC_GP_RELATIVE: 10056 switch (r_type) 10057 { 10058 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; 10059 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; 10060 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; 10061 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; 10062 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; 10063 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; 10064 default: break; 10065 } 10066 break; 10067 10068 case FUNC_LT_RELATIVE: 10069 switch (r_type) 10070 { 10071 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; 10072 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; 10073 default: break; 10074 } 10075 break; 10076 10077 case FUNC_PC_RELATIVE: 10078 switch (r_type) 10079 { 10080 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; 10081 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; 10082 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; 10083 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; 10084 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; 10085 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; 10086 default: break; 10087 } 10088 break; 10089 10090 case FUNC_PLT_RELATIVE: 10091 switch (r_type) 10092 { 10093 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; 10094 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; 10095 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; 10096 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; 10097 default: break; 10098 } 10099 break; 10100 10101 case FUNC_SEC_RELATIVE: 10102 switch (r_type) 10103 { 10104 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; 10105 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; 10106 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; 10107 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; 10108 default: break; 10109 } 10110 break; 10111 10112 case FUNC_SEG_RELATIVE: 10113 switch (r_type) 10114 { 10115 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; 10116 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; 10117 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; 10118 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; 10119 default: break; 10120 } 10121 break; 10122 10123 case FUNC_LTV_RELATIVE: 10124 switch (r_type) 10125 { 10126 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; 10127 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; 10128 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; 10129 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; 10130 default: break; 10131 } 10132 break; 10133 10134 case FUNC_LT_FPTR_RELATIVE: 10135 switch (r_type) 10136 { 10137 case BFD_RELOC_IA64_IMM22: 10138 new = BFD_RELOC_IA64_LTOFF_FPTR22; break; 10139 case BFD_RELOC_IA64_IMM64: 10140 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; 10141 default: 10142 break; 10143 } 10144 break; 10145 10146 case FUNC_IPLT_RELOC: 10147 break; 10148 10149 default: 10150 abort (); 10151 } 10152 /* Hmmmm. Should this ever occur? */ 10153 if (new) 10154 return new; 10155 else 10156 return r_type; 10157} 10158 10159/* Here is where generate the appropriate reloc for pseudo relocation 10160 functions. */ 10161void 10162ia64_validate_fix (fix) 10163 fixS *fix; 10164{ 10165 switch (fix->fx_r_type) 10166 { 10167 case BFD_RELOC_IA64_FPTR64I: 10168 case BFD_RELOC_IA64_FPTR32MSB: 10169 case BFD_RELOC_IA64_FPTR64LSB: 10170 case BFD_RELOC_IA64_LTOFF_FPTR22: 10171 case BFD_RELOC_IA64_LTOFF_FPTR64I: 10172 if (fix->fx_offset != 0) 10173 as_bad_where (fix->fx_file, fix->fx_line, 10174 "No addend allowed in @fptr() relocation"); 10175 break; 10176 default: 10177 break; 10178 } 10179 10180 return; 10181} 10182 10183static void 10184fix_insn (fix, odesc, value) 10185 fixS *fix; 10186 const struct ia64_operand *odesc; 10187 valueT value; 10188{ 10189 bfd_vma insn[3], t0, t1, control_bits; 10190 const char *err; 10191 char *fixpos; 10192 long slot; 10193 10194 slot = fix->fx_where & 0x3; 10195 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); 10196 10197 /* Bundles are always in little-endian byte order */ 10198 t0 = bfd_getl64 (fixpos); 10199 t1 = bfd_getl64 (fixpos + 8); 10200 control_bits = t0 & 0x1f; 10201 insn[0] = (t0 >> 5) & 0x1ffffffffffLL; 10202 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); 10203 insn[2] = (t1 >> 23) & 0x1ffffffffffLL; 10204 10205 err = NULL; 10206 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) 10207 { 10208 insn[1] = (value >> 22) & 0x1ffffffffffLL; 10209 insn[2] |= (((value & 0x7f) << 13) 10210 | (((value >> 7) & 0x1ff) << 27) 10211 | (((value >> 16) & 0x1f) << 22) 10212 | (((value >> 21) & 0x1) << 21) 10213 | (((value >> 63) & 0x1) << 36)); 10214 } 10215 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) 10216 { 10217 if (value & ~0x3fffffffffffffffULL) 10218 err = "integer operand out of range"; 10219 insn[1] = (value >> 21) & 0x1ffffffffffLL; 10220 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); 10221 } 10222 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) 10223 { 10224 value >>= 4; 10225 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; 10226 insn[2] |= ((((value >> 59) & 0x1) << 36) 10227 | (((value >> 0) & 0xfffff) << 13)); 10228 } 10229 else 10230 err = (*odesc->insert) (odesc, value, insn + slot); 10231 10232 if (err) 10233 as_bad_where (fix->fx_file, fix->fx_line, err); 10234 10235 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); 10236 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 10237 number_to_chars_littleendian (fixpos + 0, t0, 8); 10238 number_to_chars_littleendian (fixpos + 8, t1, 8); 10239} 10240 10241/* Attempt to simplify or even eliminate a fixup. The return value is 10242 ignored; perhaps it was once meaningful, but now it is historical. 10243 To indicate that a fixup has been eliminated, set FIXP->FX_DONE. 10244 10245 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry 10246 (if possible). */ 10247 10248void 10249md_apply_fix3 (fix, valP, seg) 10250 fixS *fix; 10251 valueT * valP; 10252 segT seg ATTRIBUTE_UNUSED; 10253{ 10254 char *fixpos; 10255 valueT value = * valP; 10256 int adjust = 0; 10257 10258 fixpos = fix->fx_frag->fr_literal + fix->fx_where; 10259 10260 if (fix->fx_pcrel) 10261 { 10262 switch (fix->fx_r_type) 10263 { 10264 case BFD_RELOC_IA64_DIR32MSB: 10265 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; 10266 adjust = 1; 10267 break; 10268 10269 case BFD_RELOC_IA64_DIR32LSB: 10270 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; 10271 adjust = 1; 10272 break; 10273 10274 case BFD_RELOC_IA64_DIR64MSB: 10275 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; 10276 adjust = 1; 10277 break; 10278 10279 case BFD_RELOC_IA64_DIR64LSB: 10280 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; 10281 adjust = 1; 10282 break; 10283 10284 default: 10285 break; 10286 } 10287 } 10288 if (fix->fx_addsy) 10289 { 10290 if (fix->fx_r_type == (int) BFD_RELOC_UNUSED) 10291 { 10292 /* This must be a TAG13 or TAG13b operand. There are no external 10293 relocs defined for them, so we must give an error. */ 10294 as_bad_where (fix->fx_file, fix->fx_line, 10295 "%s must have a constant value", 10296 elf64_ia64_operands[fix->tc_fix_data.opnd].desc); 10297 fix->fx_done = 1; 10298 return; 10299 } 10300 10301 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs 10302 work. There should be a better way to handle this. */ 10303 if (adjust) 10304 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; 10305 } 10306 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) 10307 { 10308 if (fix->tc_fix_data.bigendian) 10309 number_to_chars_bigendian (fixpos, value, fix->fx_size); 10310 else 10311 number_to_chars_littleendian (fixpos, value, fix->fx_size); 10312 fix->fx_done = 1; 10313 } 10314 else 10315 { 10316 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); 10317 fix->fx_done = 1; 10318 } 10319} 10320 10321/* Generate the BFD reloc to be stuck in the object file from the 10322 fixup used internally in the assembler. */ 10323 10324arelent * 10325tc_gen_reloc (sec, fixp) 10326 asection *sec ATTRIBUTE_UNUSED; 10327 fixS *fixp; 10328{ 10329 arelent *reloc; 10330 10331 reloc = xmalloc (sizeof (*reloc)); 10332 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 10333 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 10334 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 10335 reloc->addend = fixp->fx_offset; 10336 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 10337 10338 if (!reloc->howto) 10339 { 10340 as_bad_where (fixp->fx_file, fixp->fx_line, 10341 "Cannot represent %s relocation in object file", 10342 bfd_get_reloc_code_name (fixp->fx_r_type)); 10343 } 10344 return reloc; 10345} 10346 10347/* Turn a string in input_line_pointer into a floating point constant 10348 of type TYPE, and store the appropriate bytes in *LIT. The number 10349 of LITTLENUMS emitted is stored in *SIZE. An error message is 10350 returned, or NULL on OK. */ 10351 10352#define MAX_LITTLENUMS 5 10353 10354char * 10355md_atof (type, lit, size) 10356 int type; 10357 char *lit; 10358 int *size; 10359{ 10360 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 10361 LITTLENUM_TYPE *word; 10362 char *t; 10363 int prec; 10364 10365 switch (type) 10366 { 10367 /* IEEE floats */ 10368 case 'f': 10369 case 'F': 10370 case 's': 10371 case 'S': 10372 prec = 2; 10373 break; 10374 10375 case 'd': 10376 case 'D': 10377 case 'r': 10378 case 'R': 10379 prec = 4; 10380 break; 10381 10382 case 'x': 10383 case 'X': 10384 case 'p': 10385 case 'P': 10386 prec = 5; 10387 break; 10388 10389 default: 10390 *size = 0; 10391 return "Bad call to MD_ATOF()"; 10392 } 10393 t = atof_ieee (input_line_pointer, type, words); 10394 if (t) 10395 input_line_pointer = t; 10396 *size = prec * sizeof (LITTLENUM_TYPE); 10397 10398 for (word = words + prec - 1; prec--;) 10399 { 10400 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); 10401 lit += sizeof (LITTLENUM_TYPE); 10402 } 10403 return 0; 10404} 10405 10406/* Round up a section's size to the appropriate boundary. */ 10407valueT 10408md_section_align (seg, size) 10409 segT seg; 10410 valueT size; 10411{ 10412 int align = bfd_get_section_alignment (stdoutput, seg); 10413 valueT mask = ((valueT) 1 << align) - 1; 10414 10415 return (size + mask) & ~mask; 10416} 10417 10418/* Handle ia64 specific semantics of the align directive. */ 10419 10420void 10421ia64_md_do_align (n, fill, len, max) 10422 int n ATTRIBUTE_UNUSED; 10423 const char *fill ATTRIBUTE_UNUSED; 10424 int len ATTRIBUTE_UNUSED; 10425 int max ATTRIBUTE_UNUSED; 10426{ 10427 if (subseg_text_p (now_seg)) 10428 ia64_flush_insns (); 10429} 10430 10431/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 10432 of an rs_align_code fragment. */ 10433 10434void 10435ia64_handle_align (fragp) 10436 fragS *fragp; 10437{ 10438 /* Use mfi bundle of nops with no stop bits. */ 10439 static const unsigned char be_nop[] 10440 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 10441 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; 10442 static const unsigned char le_nop[] 10443 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 10444 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; 10445 10446 int bytes; 10447 char *p; 10448 10449 if (fragp->fr_type != rs_align_code) 10450 return; 10451 10452 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 10453 p = fragp->fr_literal + fragp->fr_fix; 10454 10455 /* Make sure we are on a 16-byte boundary, in case someone has been 10456 putting data into a text section. */ 10457 if (bytes & 15) 10458 { 10459 int fix = bytes & 15; 10460 memset (p, 0, fix); 10461 p += fix; 10462 bytes -= fix; 10463 fragp->fr_fix += fix; 10464 } 10465 10466 memcpy (p, (target_big_endian ? be_nop : le_nop), 16); 10467 fragp->fr_var = 16; 10468} 10469