tc-ia64.c revision 89857
1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. 2 Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22/* 23 TODO: 24 25 - optional operands 26 - directives: 27 .alias 28 .eb 29 .estate 30 .lb 31 .popsection 32 .previous 33 .psr 34 .pushsection 35 - labels are wrong if automatic alignment is introduced 36 (e.g., checkout the second real10 definition in test-data.s) 37 - DV-related stuff: 38 <reg>.safe_across_calls and any other DV-related directives I don't 39 have documentation for. 40 verify mod-sched-brs reads/writes are checked/marked (and other 41 notes) 42 43 */ 44 45#include "as.h" 46#include "safe-ctype.h" 47#include "dwarf2dbg.h" 48#include "subsegs.h" 49 50#include "opcode/ia64.h" 51 52#include "elf/ia64.h" 53 54#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) 55#define MIN(a,b) ((a) < (b) ? (a) : (b)) 56 57#define NUM_SLOTS 4 58#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] 59#define CURR_SLOT md.slot[md.curr_slot] 60 61#define O_pseudo_fixup (O_max + 1) 62 63enum special_section 64 { 65 /* IA-64 ABI section pseudo-ops. */ 66 SPECIAL_SECTION_BSS = 0, 67 SPECIAL_SECTION_SBSS, 68 SPECIAL_SECTION_SDATA, 69 SPECIAL_SECTION_RODATA, 70 SPECIAL_SECTION_COMMENT, 71 SPECIAL_SECTION_UNWIND, 72 SPECIAL_SECTION_UNWIND_INFO, 73 /* HPUX specific section pseudo-ops. */ 74 SPECIAL_SECTION_INIT_ARRAY, 75 SPECIAL_SECTION_FINI_ARRAY, 76 }; 77 78enum reloc_func 79 { 80 FUNC_FPTR_RELATIVE, 81 FUNC_GP_RELATIVE, 82 FUNC_LT_RELATIVE, 83 FUNC_PC_RELATIVE, 84 FUNC_PLT_RELATIVE, 85 FUNC_SEC_RELATIVE, 86 FUNC_SEG_RELATIVE, 87 FUNC_LTV_RELATIVE, 88 FUNC_LT_FPTR_RELATIVE, 89 FUNC_IPLT_RELOC, 90 }; 91 92enum reg_symbol 93 { 94 REG_GR = 0, 95 REG_FR = (REG_GR + 128), 96 REG_AR = (REG_FR + 128), 97 REG_CR = (REG_AR + 128), 98 REG_P = (REG_CR + 128), 99 REG_BR = (REG_P + 64), 100 REG_IP = (REG_BR + 8), 101 REG_CFM, 102 REG_PR, 103 REG_PR_ROT, 104 REG_PSR, 105 REG_PSR_L, 106 REG_PSR_UM, 107 /* The following are pseudo-registers for use by gas only. */ 108 IND_CPUID, 109 IND_DBR, 110 IND_DTR, 111 IND_ITR, 112 IND_IBR, 113 IND_MEM, 114 IND_MSR, 115 IND_PKR, 116 IND_PMC, 117 IND_PMD, 118 IND_RR, 119 /* The following pseudo-registers are used for unwind directives only: */ 120 REG_PSP, 121 REG_PRIUNAT, 122 REG_NUM 123 }; 124 125enum dynreg_type 126 { 127 DYNREG_GR = 0, /* dynamic general purpose register */ 128 DYNREG_FR, /* dynamic floating point register */ 129 DYNREG_PR, /* dynamic predicate register */ 130 DYNREG_NUM_TYPES 131 }; 132 133enum operand_match_result 134 { 135 OPERAND_MATCH, 136 OPERAND_OUT_OF_RANGE, 137 OPERAND_MISMATCH 138 }; 139 140/* On the ia64, we can't know the address of a text label until the 141 instructions are packed into a bundle. To handle this, we keep 142 track of the list of labels that appear in front of each 143 instruction. */ 144struct label_fix 145{ 146 struct label_fix *next; 147 struct symbol *sym; 148}; 149 150extern int target_big_endian; 151 152/* Characters which always start a comment. */ 153const char comment_chars[] = ""; 154 155/* Characters which start a comment at the beginning of a line. */ 156const char line_comment_chars[] = "#"; 157 158/* Characters which may be used to separate multiple commands on a 159 single line. */ 160const char line_separator_chars[] = ";"; 161 162/* Characters which are used to indicate an exponent in a floating 163 point number. */ 164const char EXP_CHARS[] = "eE"; 165 166/* Characters which mean that a number is a floating point constant, 167 as in 0d1.0. */ 168const char FLT_CHARS[] = "rRsSfFdDxXpP"; 169 170/* ia64-specific option processing: */ 171 172const char *md_shortopts = "m:N:x::"; 173 174struct option md_longopts[] = 175 { 176#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) 177 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, 178#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) 179 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} 180 }; 181 182size_t md_longopts_size = sizeof (md_longopts); 183 184static struct 185 { 186 struct hash_control *pseudo_hash; /* pseudo opcode hash table */ 187 struct hash_control *reg_hash; /* register name hash table */ 188 struct hash_control *dynreg_hash; /* dynamic register hash table */ 189 struct hash_control *const_hash; /* constant hash table */ 190 struct hash_control *entry_hash; /* code entry hint hash table */ 191 192 symbolS *regsym[REG_NUM]; 193 194 /* If X_op is != O_absent, the registername for the instruction's 195 qualifying predicate. If NULL, p0 is assumed for instructions 196 that are predicatable. */ 197 expressionS qp; 198 199 unsigned int 200 manual_bundling : 1, 201 debug_dv: 1, 202 detect_dv: 1, 203 explicit_mode : 1, /* which mode we're in */ 204 default_explicit_mode : 1, /* which mode is the default */ 205 mode_explicitly_set : 1, /* was the current mode explicitly set? */ 206 auto_align : 1, 207 keep_pending_output : 1; 208 209 /* Each bundle consists of up to three instructions. We keep 210 track of four most recent instructions so we can correctly set 211 the end_of_insn_group for the last instruction in a bundle. */ 212 int curr_slot; 213 int num_slots_in_use; 214 struct slot 215 { 216 unsigned int 217 end_of_insn_group : 1, 218 manual_bundling_on : 1, 219 manual_bundling_off : 1; 220 signed char user_template; /* user-selected template, if any */ 221 unsigned char qp_regno; /* qualifying predicate */ 222 /* This duplicates a good fraction of "struct fix" but we 223 can't use a "struct fix" instead since we can't call 224 fix_new_exp() until we know the address of the instruction. */ 225 int num_fixups; 226 struct insn_fix 227 { 228 bfd_reloc_code_real_type code; 229 enum ia64_opnd opnd; /* type of operand in need of fix */ 230 unsigned int is_pcrel : 1; /* is operand pc-relative? */ 231 expressionS expr; /* the value to be inserted */ 232 } 233 fixup[2]; /* at most two fixups per insn */ 234 struct ia64_opcode *idesc; 235 struct label_fix *label_fixups; 236 struct label_fix *tag_fixups; 237 struct unw_rec_list *unwind_record; /* Unwind directive. */ 238 expressionS opnd[6]; 239 char *src_file; 240 unsigned int src_line; 241 struct dwarf2_line_info debug_line; 242 } 243 slot[NUM_SLOTS]; 244 245 segT last_text_seg; 246 247 struct dynreg 248 { 249 struct dynreg *next; /* next dynamic register */ 250 const char *name; 251 unsigned short base; /* the base register number */ 252 unsigned short num_regs; /* # of registers in this set */ 253 } 254 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; 255 256 flagword flags; /* ELF-header flags */ 257 258 struct mem_offset { 259 unsigned hint:1; /* is this hint currently valid? */ 260 bfd_vma offset; /* mem.offset offset */ 261 bfd_vma base; /* mem.offset base */ 262 } mem_offset; 263 264 int path; /* number of alt. entry points seen */ 265 const char **entry_labels; /* labels of all alternate paths in 266 the current DV-checking block. */ 267 int maxpaths; /* size currently allocated for 268 entry_labels */ 269 /* Support for hardware errata workarounds. */ 270 271 /* Record data about the last three insn groups. */ 272 struct group 273 { 274 /* B-step workaround. 275 For each predicate register, this is set if the corresponding insn 276 group conditionally sets this register with one of the affected 277 instructions. */ 278 int p_reg_set[64]; 279 /* B-step workaround. 280 For each general register, this is set if the corresponding insn 281 a) is conditional one one of the predicate registers for which 282 P_REG_SET is 1 in the corresponding entry of the previous group, 283 b) sets this general register with one of the affected 284 instructions. */ 285 int g_reg_set_conditionally[128]; 286 } last_groups[3]; 287 int group_idx; 288 289 int pointer_size; /* size in bytes of a pointer */ 290 int pointer_size_shift; /* shift size of a pointer for alignment */ 291 } 292md; 293 294/* application registers: */ 295 296#define AR_K0 0 297#define AR_K7 7 298#define AR_RSC 16 299#define AR_BSP 17 300#define AR_BSPSTORE 18 301#define AR_RNAT 19 302#define AR_UNAT 36 303#define AR_FPSR 40 304#define AR_ITC 44 305#define AR_PFS 64 306#define AR_LC 65 307 308static const struct 309 { 310 const char *name; 311 int regnum; 312 } 313ar[] = 314 { 315 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, 316 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, 317 {"ar.rsc", 16}, {"ar.bsp", 17}, 318 {"ar.bspstore", 18}, {"ar.rnat", 19}, 319 {"ar.fcr", 21}, {"ar.eflag", 24}, 320 {"ar.csd", 25}, {"ar.ssd", 26}, 321 {"ar.cflg", 27}, {"ar.fsr", 28}, 322 {"ar.fir", 29}, {"ar.fdr", 30}, 323 {"ar.ccv", 32}, {"ar.unat", 36}, 324 {"ar.fpsr", 40}, {"ar.itc", 44}, 325 {"ar.pfs", 64}, {"ar.lc", 65}, 326 {"ar.ec", 66}, 327 }; 328 329#define CR_IPSR 16 330#define CR_ISR 17 331#define CR_IIP 19 332#define CR_IFA 20 333#define CR_ITIR 21 334#define CR_IIPA 22 335#define CR_IFS 23 336#define CR_IIM 24 337#define CR_IHA 25 338#define CR_IVR 65 339#define CR_TPR 66 340#define CR_EOI 67 341#define CR_IRR0 68 342#define CR_IRR3 71 343#define CR_LRR0 80 344#define CR_LRR1 81 345 346/* control registers: */ 347static const struct 348 { 349 const char *name; 350 int regnum; 351 } 352cr[] = 353 { 354 {"cr.dcr", 0}, 355 {"cr.itm", 1}, 356 {"cr.iva", 2}, 357 {"cr.pta", 8}, 358 {"cr.gpta", 9}, 359 {"cr.ipsr", 16}, 360 {"cr.isr", 17}, 361 {"cr.iip", 19}, 362 {"cr.ifa", 20}, 363 {"cr.itir", 21}, 364 {"cr.iipa", 22}, 365 {"cr.ifs", 23}, 366 {"cr.iim", 24}, 367 {"cr.iha", 25}, 368 {"cr.lid", 64}, 369 {"cr.ivr", 65}, 370 {"cr.tpr", 66}, 371 {"cr.eoi", 67}, 372 {"cr.irr0", 68}, 373 {"cr.irr1", 69}, 374 {"cr.irr2", 70}, 375 {"cr.irr3", 71}, 376 {"cr.itv", 72}, 377 {"cr.pmv", 73}, 378 {"cr.cmcv", 74}, 379 {"cr.lrr0", 80}, 380 {"cr.lrr1", 81} 381 }; 382 383#define PSR_MFL 4 384#define PSR_IC 13 385#define PSR_DFL 18 386#define PSR_CPL 32 387 388static const struct const_desc 389 { 390 const char *name; 391 valueT value; 392 } 393const_bits[] = 394 { 395 /* PSR constant masks: */ 396 397 /* 0: reserved */ 398 {"psr.be", ((valueT) 1) << 1}, 399 {"psr.up", ((valueT) 1) << 2}, 400 {"psr.ac", ((valueT) 1) << 3}, 401 {"psr.mfl", ((valueT) 1) << 4}, 402 {"psr.mfh", ((valueT) 1) << 5}, 403 /* 6-12: reserved */ 404 {"psr.ic", ((valueT) 1) << 13}, 405 {"psr.i", ((valueT) 1) << 14}, 406 {"psr.pk", ((valueT) 1) << 15}, 407 /* 16: reserved */ 408 {"psr.dt", ((valueT) 1) << 17}, 409 {"psr.dfl", ((valueT) 1) << 18}, 410 {"psr.dfh", ((valueT) 1) << 19}, 411 {"psr.sp", ((valueT) 1) << 20}, 412 {"psr.pp", ((valueT) 1) << 21}, 413 {"psr.di", ((valueT) 1) << 22}, 414 {"psr.si", ((valueT) 1) << 23}, 415 {"psr.db", ((valueT) 1) << 24}, 416 {"psr.lp", ((valueT) 1) << 25}, 417 {"psr.tb", ((valueT) 1) << 26}, 418 {"psr.rt", ((valueT) 1) << 27}, 419 /* 28-31: reserved */ 420 /* 32-33: cpl (current privilege level) */ 421 {"psr.is", ((valueT) 1) << 34}, 422 {"psr.mc", ((valueT) 1) << 35}, 423 {"psr.it", ((valueT) 1) << 36}, 424 {"psr.id", ((valueT) 1) << 37}, 425 {"psr.da", ((valueT) 1) << 38}, 426 {"psr.dd", ((valueT) 1) << 39}, 427 {"psr.ss", ((valueT) 1) << 40}, 428 /* 41-42: ri (restart instruction) */ 429 {"psr.ed", ((valueT) 1) << 43}, 430 {"psr.bn", ((valueT) 1) << 44}, 431 }; 432 433/* indirect register-sets/memory: */ 434 435static const struct 436 { 437 const char *name; 438 int regnum; 439 } 440indirect_reg[] = 441 { 442 { "CPUID", IND_CPUID }, 443 { "cpuid", IND_CPUID }, 444 { "dbr", IND_DBR }, 445 { "dtr", IND_DTR }, 446 { "itr", IND_ITR }, 447 { "ibr", IND_IBR }, 448 { "msr", IND_MSR }, 449 { "pkr", IND_PKR }, 450 { "pmc", IND_PMC }, 451 { "pmd", IND_PMD }, 452 { "rr", IND_RR }, 453 }; 454 455/* Pseudo functions used to indicate relocation types (these functions 456 start with an at sign (@). */ 457static struct 458 { 459 const char *name; 460 enum pseudo_type 461 { 462 PSEUDO_FUNC_NONE, 463 PSEUDO_FUNC_RELOC, 464 PSEUDO_FUNC_CONST, 465 PSEUDO_FUNC_REG, 466 PSEUDO_FUNC_FLOAT 467 } 468 type; 469 union 470 { 471 unsigned long ival; 472 symbolS *sym; 473 } 474 u; 475 } 476pseudo_func[] = 477 { 478 /* reloc pseudo functions (these must come first!): */ 479 { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, 480 { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, 481 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, 482 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, 483 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, 484 { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, 485 { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, 486 { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, 487 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ 488 { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, 489 490 /* mbtype4 constants: */ 491 { "alt", PSEUDO_FUNC_CONST, { 0xa } }, 492 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, 493 { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, 494 { "rev", PSEUDO_FUNC_CONST, { 0xb } }, 495 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, 496 497 /* fclass constants: */ 498 { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, 499 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, 500 { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, 501 { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, 502 { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, 503 { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, 504 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, 505 { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, 506 { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, 507 508 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ 509 510 /* unwind-related constants: */ 511 { "svr4", PSEUDO_FUNC_CONST, { 0 } }, 512 { "hpux", PSEUDO_FUNC_CONST, { 1 } }, 513 { "nt", PSEUDO_FUNC_CONST, { 2 } }, 514 515 /* unwind-related registers: */ 516 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } 517 }; 518 519/* 41-bit nop opcodes (one per unit): */ 520static const bfd_vma nop[IA64_NUM_UNITS] = 521 { 522 0x0000000000LL, /* NIL => break 0 */ 523 0x0008000000LL, /* I-unit nop */ 524 0x0008000000LL, /* M-unit nop */ 525 0x4000000000LL, /* B-unit nop */ 526 0x0008000000LL, /* F-unit nop */ 527 0x0008000000LL, /* L-"unit" nop */ 528 0x0008000000LL, /* X-unit nop */ 529 }; 530 531/* Can't be `const' as it's passed to input routines (which have the 532 habit of setting temporary sentinels. */ 533static char special_section_name[][20] = 534 { 535 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, 536 {".IA_64.unwind"}, {".IA_64.unwind_info"}, 537 {".init_array"}, {".fini_array"} 538 }; 539 540static char *special_linkonce_name[] = 541 { 542 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." 543 }; 544 545/* The best template for a particular sequence of up to three 546 instructions: */ 547#define N IA64_NUM_TYPES 548static unsigned char best_template[N][N][N]; 549#undef N 550 551/* Resource dependencies currently in effect */ 552static struct rsrc { 553 int depind; /* dependency index */ 554 const struct ia64_dependency *dependency; /* actual dependency */ 555 unsigned specific:1, /* is this a specific bit/regno? */ 556 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ 557 int index; /* specific regno/bit within dependency */ 558 int note; /* optional qualifying note (0 if none) */ 559#define STATE_NONE 0 560#define STATE_STOP 1 561#define STATE_SRLZ 2 562 int insn_srlz; /* current insn serialization state */ 563 int data_srlz; /* current data serialization state */ 564 int qp_regno; /* qualifying predicate for this usage */ 565 char *file; /* what file marked this dependency */ 566 unsigned int line; /* what line marked this dependency */ 567 struct mem_offset mem_offset; /* optional memory offset hint */ 568 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ 569 int path; /* corresponding code entry index */ 570} *regdeps = NULL; 571static int regdepslen = 0; 572static int regdepstotlen = 0; 573static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; 574static const char *dv_sem[] = { "none", "implied", "impliedf", 575 "data", "instr", "specific", "stop", "other" }; 576static const char *dv_cmp_type[] = { "none", "OR", "AND" }; 577 578/* Current state of PR mutexation */ 579static struct qpmutex { 580 valueT prmask; 581 int path; 582} *qp_mutexes = NULL; /* QP mutex bitmasks */ 583static int qp_mutexeslen = 0; 584static int qp_mutexestotlen = 0; 585static valueT qp_safe_across_calls = 0; 586 587/* Current state of PR implications */ 588static struct qp_imply { 589 unsigned p1:6; 590 unsigned p2:6; 591 unsigned p2_branched:1; 592 int path; 593} *qp_implies = NULL; 594static int qp_implieslen = 0; 595static int qp_impliestotlen = 0; 596 597/* Keep track of static GR values so that indirect register usage can 598 sometimes be tracked. */ 599static struct gr { 600 unsigned known:1; 601 int path; 602 valueT value; 603} gr_values[128] = {{ 1, 0, 0 }}; 604 605/* These are the routines required to output the various types of 606 unwind records. */ 607 608/* A slot_number is a frag address plus the slot index (0-2). We use the 609 frag address here so that if there is a section switch in the middle of 610 a function, then instructions emitted to a different section are not 611 counted. Since there may be more than one frag for a function, this 612 means we also need to keep track of which frag this address belongs to 613 so we can compute inter-frag distances. This also nicely solves the 614 problem with nops emitted for align directives, which can't easily be 615 counted, but can easily be derived from frag sizes. */ 616 617typedef struct unw_rec_list { 618 unwind_record r; 619 unsigned long slot_number; 620 fragS *slot_frag; 621 struct unw_rec_list *next; 622} unw_rec_list; 623 624#define SLOT_NUM_NOT_SET (unsigned)-1 625 626static struct 627{ 628 unsigned long next_slot_number; 629 fragS *next_slot_frag; 630 631 /* Maintain a list of unwind entries for the current function. */ 632 unw_rec_list *list; 633 unw_rec_list *tail; 634 635 /* Any unwind entires that should be attached to the current slot 636 that an insn is being constructed for. */ 637 unw_rec_list *current_entry; 638 639 /* These are used to create the unwind table entry for this function. */ 640 symbolS *proc_start; 641 symbolS *proc_end; 642 symbolS *info; /* pointer to unwind info */ 643 symbolS *personality_routine; 644 segT saved_text_seg; 645 subsegT saved_text_subseg; 646 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ 647 648 /* TRUE if processing unwind directives in a prologue region. */ 649 int prologue; 650 int prologue_mask; 651 unsigned int prologue_count; /* number of .prologues seen so far */ 652} unwind; 653 654typedef void (*vbyte_func) PARAMS ((int, char *, char *)); 655 656/* Forward delarations: */ 657static int ar_is_in_integer_unit PARAMS ((int regnum)); 658static void set_section PARAMS ((char *name)); 659static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, 660 unsigned int, unsigned int)); 661static void dot_radix PARAMS ((int)); 662static void dot_special_section PARAMS ((int)); 663static void dot_proc PARAMS ((int)); 664static void dot_fframe PARAMS ((int)); 665static void dot_vframe PARAMS ((int)); 666static void dot_vframesp PARAMS ((int)); 667static void dot_vframepsp PARAMS ((int)); 668static void dot_save PARAMS ((int)); 669static void dot_restore PARAMS ((int)); 670static void dot_restorereg PARAMS ((int)); 671static void dot_restorereg_p PARAMS ((int)); 672static void dot_handlerdata PARAMS ((int)); 673static void dot_unwentry PARAMS ((int)); 674static void dot_altrp PARAMS ((int)); 675static void dot_savemem PARAMS ((int)); 676static void dot_saveg PARAMS ((int)); 677static void dot_savef PARAMS ((int)); 678static void dot_saveb PARAMS ((int)); 679static void dot_savegf PARAMS ((int)); 680static void dot_spill PARAMS ((int)); 681static void dot_spillreg PARAMS ((int)); 682static void dot_spillmem PARAMS ((int)); 683static void dot_spillreg_p PARAMS ((int)); 684static void dot_spillmem_p PARAMS ((int)); 685static void dot_label_state PARAMS ((int)); 686static void dot_copy_state PARAMS ((int)); 687static void dot_unwabi PARAMS ((int)); 688static void dot_personality PARAMS ((int)); 689static void dot_body PARAMS ((int)); 690static void dot_prologue PARAMS ((int)); 691static void dot_endp PARAMS ((int)); 692static void dot_template PARAMS ((int)); 693static void dot_regstk PARAMS ((int)); 694static void dot_rot PARAMS ((int)); 695static void dot_byteorder PARAMS ((int)); 696static void dot_psr PARAMS ((int)); 697static void dot_alias PARAMS ((int)); 698static void dot_ln PARAMS ((int)); 699static char *parse_section_name PARAMS ((void)); 700static void dot_xdata PARAMS ((int)); 701static void stmt_float_cons PARAMS ((int)); 702static void stmt_cons_ua PARAMS ((int)); 703static void dot_xfloat_cons PARAMS ((int)); 704static void dot_xstringer PARAMS ((int)); 705static void dot_xdata_ua PARAMS ((int)); 706static void dot_xfloat_cons_ua PARAMS ((int)); 707static void print_prmask PARAMS ((valueT mask)); 708static void dot_pred_rel PARAMS ((int)); 709static void dot_reg_val PARAMS ((int)); 710static void dot_dv_mode PARAMS ((int)); 711static void dot_entry PARAMS ((int)); 712static void dot_mem_offset PARAMS ((int)); 713static void add_unwind_entry PARAMS((unw_rec_list *ptr)); 714static symbolS *declare_register PARAMS ((const char *name, int regnum)); 715static void declare_register_set PARAMS ((const char *, int, int)); 716static unsigned int operand_width PARAMS ((enum ia64_opnd)); 717static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, 718 int index, 719 expressionS *e)); 720static int parse_operand PARAMS ((expressionS *e)); 721static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); 722static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit)); 723static void build_insn PARAMS ((struct slot *, bfd_vma *)); 724static void emit_one_bundle PARAMS ((void)); 725static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); 726static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, 727 bfd_reloc_code_real_type r_type)); 728static void insn_group_break PARAMS ((int, int, int)); 729static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, 730 struct rsrc *, int depind, int path)); 731static void add_qp_mutex PARAMS((valueT mask)); 732static void add_qp_imply PARAMS((int p1, int p2)); 733static void clear_qp_branch_flag PARAMS((valueT mask)); 734static void clear_qp_mutex PARAMS((valueT mask)); 735static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); 736static int has_suffix_p PARAMS((const char *, const char *)); 737static void clear_register_values PARAMS ((void)); 738static void print_dependency PARAMS ((const char *action, int depind)); 739static void instruction_serialization PARAMS ((void)); 740static void data_serialization PARAMS ((void)); 741static void remove_marked_resource PARAMS ((struct rsrc *)); 742static int is_conditional_branch PARAMS ((struct ia64_opcode *)); 743static int is_taken_branch PARAMS ((struct ia64_opcode *)); 744static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); 745static int depends_on PARAMS ((int, struct ia64_opcode *)); 746static int specify_resource PARAMS ((const struct ia64_dependency *, 747 struct ia64_opcode *, int, struct rsrc [], int, int)); 748static int check_dv PARAMS((struct ia64_opcode *idesc)); 749static void check_dependencies PARAMS((struct ia64_opcode *)); 750static void mark_resources PARAMS((struct ia64_opcode *)); 751static void update_dependencies PARAMS((struct ia64_opcode *)); 752static void note_register_values PARAMS((struct ia64_opcode *)); 753static int qp_mutex PARAMS ((int, int, int)); 754static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); 755static void output_vbyte_mem PARAMS ((int, char *, char *)); 756static void count_output PARAMS ((int, char *, char *)); 757static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); 758static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); 759static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 760static void output_P1_format PARAMS ((vbyte_func, int)); 761static void output_P2_format PARAMS ((vbyte_func, int, int)); 762static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); 763static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); 764static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); 765static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); 766static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); 767static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 768static void output_P9_format PARAMS ((vbyte_func, int, int)); 769static void output_P10_format PARAMS ((vbyte_func, int, int)); 770static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 771static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); 772static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); 773static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); 774static char format_ab_reg PARAMS ((int, int)); 775static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, 776 unsigned long)); 777static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); 778static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, 779 unsigned long)); 780static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); 781static void free_list_records PARAMS ((unw_rec_list *)); 782static unw_rec_list *output_prologue PARAMS ((void)); 783static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); 784static unw_rec_list *output_body PARAMS ((void)); 785static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); 786static unw_rec_list *output_mem_stack_v PARAMS ((void)); 787static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); 788static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); 789static unw_rec_list *output_rp_when PARAMS ((void)); 790static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); 791static unw_rec_list *output_rp_br PARAMS ((unsigned int)); 792static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); 793static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); 794static unw_rec_list *output_pfs_when PARAMS ((void)); 795static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); 796static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); 797static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); 798static unw_rec_list *output_preds_when PARAMS ((void)); 799static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); 800static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); 801static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); 802static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); 803static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); 804static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); 805static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); 806static unw_rec_list *output_br_mem PARAMS ((unsigned int)); 807static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); 808static unw_rec_list *output_spill_base PARAMS ((unsigned int)); 809static unw_rec_list *output_unat_when PARAMS ((void)); 810static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); 811static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); 812static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); 813static unw_rec_list *output_lc_when PARAMS ((void)); 814static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); 815static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); 816static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); 817static unw_rec_list *output_fpsr_when PARAMS ((void)); 818static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); 819static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); 820static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); 821static unw_rec_list *output_priunat_when_gr PARAMS ((void)); 822static unw_rec_list *output_priunat_when_mem PARAMS ((void)); 823static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); 824static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); 825static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); 826static unw_rec_list *output_bsp_when PARAMS ((void)); 827static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); 828static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); 829static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); 830static unw_rec_list *output_bspstore_when PARAMS ((void)); 831static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); 832static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); 833static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); 834static unw_rec_list *output_rnat_when PARAMS ((void)); 835static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); 836static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); 837static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); 838static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); 839static unw_rec_list *output_epilogue PARAMS ((unsigned long)); 840static unw_rec_list *output_label_state PARAMS ((unsigned long)); 841static unw_rec_list *output_copy_state PARAMS ((unsigned long)); 842static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); 843static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); 844static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, 845 unsigned int)); 846static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, 847 unsigned int)); 848static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, 849 unsigned int)); 850static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, 851 unsigned int, unsigned int)); 852static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); 853static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); 854static int calc_record_size PARAMS ((unw_rec_list *)); 855static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); 856static int count_bits PARAMS ((unsigned long)); 857static unsigned long slot_index PARAMS ((unsigned long, fragS *, 858 unsigned long, fragS *)); 859static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); 860static void fixup_unw_records PARAMS ((unw_rec_list *)); 861static int output_unw_records PARAMS ((unw_rec_list *, void **)); 862static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); 863static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); 864static int generate_unwind_image PARAMS ((const char *)); 865 866/* Build the unwind section name by appending the (possibly stripped) 867 text section NAME to the unwind PREFIX. The resulting string 868 pointer is assigned to RESULT. The string is allocated on the 869 stack, so this must be a macro... */ 870#define make_unw_section_name(special, text_name, result) \ 871 { \ 872 const char *_prefix = special_section_name[special]; \ 873 const char *_suffix = text_name; \ 874 size_t _prefix_len, _suffix_len; \ 875 char *_result; \ 876 if (strncmp (text_name, ".gnu.linkonce.t.", \ 877 sizeof (".gnu.linkonce.t.") - 1) == 0) \ 878 { \ 879 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \ 880 _suffix += sizeof (".gnu.linkonce.t.") - 1; \ 881 } \ 882 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \ 883 _result = alloca (_prefix_len + _suffix_len + 1); \ 884 memcpy (_result, _prefix, _prefix_len); \ 885 memcpy (_result + _prefix_len, _suffix, _suffix_len); \ 886 _result[_prefix_len + _suffix_len] = '\0'; \ 887 result = _result; \ 888 } \ 889while (0) 890 891/* Determine if application register REGNUM resides in the integer 892 unit (as opposed to the memory unit). */ 893static int 894ar_is_in_integer_unit (reg) 895 int reg; 896{ 897 reg -= REG_AR; 898 899 return (reg == 64 /* pfs */ 900 || reg == 65 /* lc */ 901 || reg == 66 /* ec */ 902 /* ??? ias accepts and puts these in the integer unit. */ 903 || (reg >= 112 && reg <= 127)); 904} 905 906/* Switch to section NAME and create section if necessary. It's 907 rather ugly that we have to manipulate input_line_pointer but I 908 don't see any other way to accomplish the same thing without 909 changing obj-elf.c (which may be the Right Thing, in the end). */ 910static void 911set_section (name) 912 char *name; 913{ 914 char *saved_input_line_pointer; 915 916 saved_input_line_pointer = input_line_pointer; 917 input_line_pointer = name; 918 obj_elf_section (0); 919 input_line_pointer = saved_input_line_pointer; 920} 921 922/* Map 's' to SHF_IA_64_SHORT. */ 923 924int 925ia64_elf_section_letter (letter, ptr_msg) 926 int letter; 927 char **ptr_msg; 928{ 929 if (letter == 's') 930 return SHF_IA_64_SHORT; 931 932 *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S in string"); 933 return 0; 934} 935 936/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ 937 938flagword 939ia64_elf_section_flags (flags, attr, type) 940 flagword flags; 941 int attr, type ATTRIBUTE_UNUSED; 942{ 943 if (attr & SHF_IA_64_SHORT) 944 flags |= SEC_SMALL_DATA; 945 return flags; 946} 947 948int 949ia64_elf_section_type (str, len) 950 const char *str; 951 size_t len; 952{ 953#define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0)) 954 955 if (STREQ (ELF_STRING_ia64_unwind_info)) 956 return SHT_PROGBITS; 957 958 if (STREQ (ELF_STRING_ia64_unwind_info_once)) 959 return SHT_PROGBITS; 960 961 if (STREQ (ELF_STRING_ia64_unwind)) 962 return SHT_IA_64_UNWIND; 963 964 if (STREQ (ELF_STRING_ia64_unwind_once)) 965 return SHT_IA_64_UNWIND; 966 967 if (STREQ ("init_array")) 968 return SHT_INIT_ARRAY; 969 970 if (STREQ ("fini_array")) 971 return SHT_FINI_ARRAY; 972 973 return -1; 974#undef STREQ 975} 976 977static unsigned int 978set_regstack (ins, locs, outs, rots) 979 unsigned int ins, locs, outs, rots; 980{ 981 /* Size of frame. */ 982 unsigned int sof; 983 984 sof = ins + locs + outs; 985 if (sof > 96) 986 { 987 as_bad ("Size of frame exceeds maximum of 96 registers"); 988 return 0; 989 } 990 if (rots > sof) 991 { 992 as_warn ("Size of rotating registers exceeds frame size"); 993 return 0; 994 } 995 md.in.base = REG_GR + 32; 996 md.loc.base = md.in.base + ins; 997 md.out.base = md.loc.base + locs; 998 999 md.in.num_regs = ins; 1000 md.loc.num_regs = locs; 1001 md.out.num_regs = outs; 1002 md.rot.num_regs = rots; 1003 return sof; 1004} 1005 1006void 1007ia64_flush_insns () 1008{ 1009 struct label_fix *lfix; 1010 segT saved_seg; 1011 subsegT saved_subseg; 1012 unw_rec_list *ptr; 1013 1014 if (!md.last_text_seg) 1015 return; 1016 1017 saved_seg = now_seg; 1018 saved_subseg = now_subseg; 1019 1020 subseg_set (md.last_text_seg, 0); 1021 1022 while (md.num_slots_in_use > 0) 1023 emit_one_bundle (); /* force out queued instructions */ 1024 1025 /* In case there are labels following the last instruction, resolve 1026 those now: */ 1027 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) 1028 { 1029 S_SET_VALUE (lfix->sym, frag_now_fix ()); 1030 symbol_set_frag (lfix->sym, frag_now); 1031 } 1032 CURR_SLOT.label_fixups = 0; 1033 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) 1034 { 1035 S_SET_VALUE (lfix->sym, frag_now_fix ()); 1036 symbol_set_frag (lfix->sym, frag_now); 1037 } 1038 CURR_SLOT.tag_fixups = 0; 1039 1040 /* In case there are unwind directives following the last instruction, 1041 resolve those now. We only handle body and prologue directives here. 1042 Give an error for others. */ 1043 for (ptr = unwind.current_entry; ptr; ptr = ptr->next) 1044 { 1045 if (ptr->r.type == prologue || ptr->r.type == prologue_gr 1046 || ptr->r.type == body) 1047 { 1048 ptr->slot_number = (unsigned long) frag_more (0); 1049 ptr->slot_frag = frag_now; 1050 } 1051 else 1052 as_bad (_("Unwind directive not followed by an instruction.")); 1053 } 1054 unwind.current_entry = NULL; 1055 1056 subseg_set (saved_seg, saved_subseg); 1057 1058 if (md.qp.X_op == O_register) 1059 as_bad ("qualifying predicate not followed by instruction"); 1060} 1061 1062void 1063ia64_do_align (nbytes) 1064 int nbytes; 1065{ 1066 char *saved_input_line_pointer = input_line_pointer; 1067 1068 input_line_pointer = ""; 1069 s_align_bytes (nbytes); 1070 input_line_pointer = saved_input_line_pointer; 1071} 1072 1073void 1074ia64_cons_align (nbytes) 1075 int nbytes; 1076{ 1077 if (md.auto_align) 1078 { 1079 char *saved_input_line_pointer = input_line_pointer; 1080 input_line_pointer = ""; 1081 s_align_bytes (nbytes); 1082 input_line_pointer = saved_input_line_pointer; 1083 } 1084} 1085 1086/* Output COUNT bytes to a memory location. */ 1087static unsigned char *vbyte_mem_ptr = NULL; 1088 1089void 1090output_vbyte_mem (count, ptr, comment) 1091 int count; 1092 char *ptr; 1093 char *comment ATTRIBUTE_UNUSED; 1094{ 1095 int x; 1096 if (vbyte_mem_ptr == NULL) 1097 abort (); 1098 1099 if (count == 0) 1100 return; 1101 for (x = 0; x < count; x++) 1102 *(vbyte_mem_ptr++) = ptr[x]; 1103} 1104 1105/* Count the number of bytes required for records. */ 1106static int vbyte_count = 0; 1107void 1108count_output (count, ptr, comment) 1109 int count; 1110 char *ptr ATTRIBUTE_UNUSED; 1111 char *comment ATTRIBUTE_UNUSED; 1112{ 1113 vbyte_count += count; 1114} 1115 1116static void 1117output_R1_format (f, rtype, rlen) 1118 vbyte_func f; 1119 unw_record_type rtype; 1120 int rlen; 1121{ 1122 int r = 0; 1123 char byte; 1124 if (rlen > 0x1f) 1125 { 1126 output_R3_format (f, rtype, rlen); 1127 return; 1128 } 1129 1130 if (rtype == body) 1131 r = 1; 1132 else if (rtype != prologue) 1133 as_bad ("record type is not valid"); 1134 1135 byte = UNW_R1 | (r << 5) | (rlen & 0x1f); 1136 (*f) (1, &byte, NULL); 1137} 1138 1139static void 1140output_R2_format (f, mask, grsave, rlen) 1141 vbyte_func f; 1142 int mask, grsave; 1143 unsigned long rlen; 1144{ 1145 char bytes[20]; 1146 int count = 2; 1147 mask = (mask & 0x0f); 1148 grsave = (grsave & 0x7f); 1149 1150 bytes[0] = (UNW_R2 | (mask >> 1)); 1151 bytes[1] = (((mask & 0x01) << 7) | grsave); 1152 count += output_leb128 (bytes + 2, rlen, 0); 1153 (*f) (count, bytes, NULL); 1154} 1155 1156static void 1157output_R3_format (f, rtype, rlen) 1158 vbyte_func f; 1159 unw_record_type rtype; 1160 unsigned long rlen; 1161{ 1162 int r = 0, count; 1163 char bytes[20]; 1164 if (rlen <= 0x1f) 1165 { 1166 output_R1_format (f, rtype, rlen); 1167 return; 1168 } 1169 1170 if (rtype == body) 1171 r = 1; 1172 else if (rtype != prologue) 1173 as_bad ("record type is not valid"); 1174 bytes[0] = (UNW_R3 | r); 1175 count = output_leb128 (bytes + 1, rlen, 0); 1176 (*f) (count + 1, bytes, NULL); 1177} 1178 1179static void 1180output_P1_format (f, brmask) 1181 vbyte_func f; 1182 int brmask; 1183{ 1184 char byte; 1185 byte = UNW_P1 | (brmask & 0x1f); 1186 (*f) (1, &byte, NULL); 1187} 1188 1189static void 1190output_P2_format (f, brmask, gr) 1191 vbyte_func f; 1192 int brmask; 1193 int gr; 1194{ 1195 char bytes[2]; 1196 brmask = (brmask & 0x1f); 1197 bytes[0] = UNW_P2 | (brmask >> 1); 1198 bytes[1] = (((brmask & 1) << 7) | gr); 1199 (*f) (2, bytes, NULL); 1200} 1201 1202static void 1203output_P3_format (f, rtype, reg) 1204 vbyte_func f; 1205 unw_record_type rtype; 1206 int reg; 1207{ 1208 char bytes[2]; 1209 int r = 0; 1210 reg = (reg & 0x7f); 1211 switch (rtype) 1212 { 1213 case psp_gr: 1214 r = 0; 1215 break; 1216 case rp_gr: 1217 r = 1; 1218 break; 1219 case pfs_gr: 1220 r = 2; 1221 break; 1222 case preds_gr: 1223 r = 3; 1224 break; 1225 case unat_gr: 1226 r = 4; 1227 break; 1228 case lc_gr: 1229 r = 5; 1230 break; 1231 case rp_br: 1232 r = 6; 1233 break; 1234 case rnat_gr: 1235 r = 7; 1236 break; 1237 case bsp_gr: 1238 r = 8; 1239 break; 1240 case bspstore_gr: 1241 r = 9; 1242 break; 1243 case fpsr_gr: 1244 r = 10; 1245 break; 1246 case priunat_gr: 1247 r = 11; 1248 break; 1249 default: 1250 as_bad ("Invalid record type for P3 format."); 1251 } 1252 bytes[0] = (UNW_P3 | (r >> 1)); 1253 bytes[1] = (((r & 1) << 7) | reg); 1254 (*f) (2, bytes, NULL); 1255} 1256 1257static void 1258output_P4_format (f, imask, imask_size) 1259 vbyte_func f; 1260 unsigned char *imask; 1261 unsigned long imask_size; 1262{ 1263 imask[0] = UNW_P4; 1264 (*f) (imask_size, imask, NULL); 1265} 1266 1267static void 1268output_P5_format (f, grmask, frmask) 1269 vbyte_func f; 1270 int grmask; 1271 unsigned long frmask; 1272{ 1273 char bytes[4]; 1274 grmask = (grmask & 0x0f); 1275 1276 bytes[0] = UNW_P5; 1277 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); 1278 bytes[2] = ((frmask & 0x0000ff00) >> 8); 1279 bytes[3] = (frmask & 0x000000ff); 1280 (*f) (4, bytes, NULL); 1281} 1282 1283static void 1284output_P6_format (f, rtype, rmask) 1285 vbyte_func f; 1286 unw_record_type rtype; 1287 int rmask; 1288{ 1289 char byte; 1290 int r = 0; 1291 1292 if (rtype == gr_mem) 1293 r = 1; 1294 else if (rtype != fr_mem) 1295 as_bad ("Invalid record type for format P6"); 1296 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); 1297 (*f) (1, &byte, NULL); 1298} 1299 1300static void 1301output_P7_format (f, rtype, w1, w2) 1302 vbyte_func f; 1303 unw_record_type rtype; 1304 unsigned long w1; 1305 unsigned long w2; 1306{ 1307 char bytes[20]; 1308 int count = 1; 1309 int r = 0; 1310 count += output_leb128 (bytes + 1, w1, 0); 1311 switch (rtype) 1312 { 1313 case mem_stack_f: 1314 r = 0; 1315 count += output_leb128 (bytes + count, w2 >> 4, 0); 1316 break; 1317 case mem_stack_v: 1318 r = 1; 1319 break; 1320 case spill_base: 1321 r = 2; 1322 break; 1323 case psp_sprel: 1324 r = 3; 1325 break; 1326 case rp_when: 1327 r = 4; 1328 break; 1329 case rp_psprel: 1330 r = 5; 1331 break; 1332 case pfs_when: 1333 r = 6; 1334 break; 1335 case pfs_psprel: 1336 r = 7; 1337 break; 1338 case preds_when: 1339 r = 8; 1340 break; 1341 case preds_psprel: 1342 r = 9; 1343 break; 1344 case lc_when: 1345 r = 10; 1346 break; 1347 case lc_psprel: 1348 r = 11; 1349 break; 1350 case unat_when: 1351 r = 12; 1352 break; 1353 case unat_psprel: 1354 r = 13; 1355 break; 1356 case fpsr_when: 1357 r = 14; 1358 break; 1359 case fpsr_psprel: 1360 r = 15; 1361 break; 1362 default: 1363 break; 1364 } 1365 bytes[0] = (UNW_P7 | r); 1366 (*f) (count, bytes, NULL); 1367} 1368 1369static void 1370output_P8_format (f, rtype, t) 1371 vbyte_func f; 1372 unw_record_type rtype; 1373 unsigned long t; 1374{ 1375 char bytes[20]; 1376 int r = 0; 1377 int count = 2; 1378 bytes[0] = UNW_P8; 1379 switch (rtype) 1380 { 1381 case rp_sprel: 1382 r = 1; 1383 break; 1384 case pfs_sprel: 1385 r = 2; 1386 break; 1387 case preds_sprel: 1388 r = 3; 1389 break; 1390 case lc_sprel: 1391 r = 4; 1392 break; 1393 case unat_sprel: 1394 r = 5; 1395 break; 1396 case fpsr_sprel: 1397 r = 6; 1398 break; 1399 case bsp_when: 1400 r = 7; 1401 break; 1402 case bsp_psprel: 1403 r = 8; 1404 break; 1405 case bsp_sprel: 1406 r = 9; 1407 break; 1408 case bspstore_when: 1409 r = 10; 1410 break; 1411 case bspstore_psprel: 1412 r = 11; 1413 break; 1414 case bspstore_sprel: 1415 r = 12; 1416 break; 1417 case rnat_when: 1418 r = 13; 1419 break; 1420 case rnat_psprel: 1421 r = 14; 1422 break; 1423 case rnat_sprel: 1424 r = 15; 1425 break; 1426 case priunat_when_gr: 1427 r = 16; 1428 break; 1429 case priunat_psprel: 1430 r = 17; 1431 break; 1432 case priunat_sprel: 1433 r = 18; 1434 break; 1435 case priunat_when_mem: 1436 r = 19; 1437 break; 1438 default: 1439 break; 1440 } 1441 bytes[1] = r; 1442 count += output_leb128 (bytes + 2, t, 0); 1443 (*f) (count, bytes, NULL); 1444} 1445 1446static void 1447output_P9_format (f, grmask, gr) 1448 vbyte_func f; 1449 int grmask; 1450 int gr; 1451{ 1452 char bytes[3]; 1453 bytes[0] = UNW_P9; 1454 bytes[1] = (grmask & 0x0f); 1455 bytes[2] = (gr & 0x7f); 1456 (*f) (3, bytes, NULL); 1457} 1458 1459static void 1460output_P10_format (f, abi, context) 1461 vbyte_func f; 1462 int abi; 1463 int context; 1464{ 1465 char bytes[3]; 1466 bytes[0] = UNW_P10; 1467 bytes[1] = (abi & 0xff); 1468 bytes[2] = (context & 0xff); 1469 (*f) (3, bytes, NULL); 1470} 1471 1472static void 1473output_B1_format (f, rtype, label) 1474 vbyte_func f; 1475 unw_record_type rtype; 1476 unsigned long label; 1477{ 1478 char byte; 1479 int r = 0; 1480 if (label > 0x1f) 1481 { 1482 output_B4_format (f, rtype, label); 1483 return; 1484 } 1485 if (rtype == copy_state) 1486 r = 1; 1487 else if (rtype != label_state) 1488 as_bad ("Invalid record type for format B1"); 1489 1490 byte = (UNW_B1 | (r << 5) | (label & 0x1f)); 1491 (*f) (1, &byte, NULL); 1492} 1493 1494static void 1495output_B2_format (f, ecount, t) 1496 vbyte_func f; 1497 unsigned long ecount; 1498 unsigned long t; 1499{ 1500 char bytes[20]; 1501 int count = 1; 1502 if (ecount > 0x1f) 1503 { 1504 output_B3_format (f, ecount, t); 1505 return; 1506 } 1507 bytes[0] = (UNW_B2 | (ecount & 0x1f)); 1508 count += output_leb128 (bytes + 1, t, 0); 1509 (*f) (count, bytes, NULL); 1510} 1511 1512static void 1513output_B3_format (f, ecount, t) 1514 vbyte_func f; 1515 unsigned long ecount; 1516 unsigned long t; 1517{ 1518 char bytes[20]; 1519 int count = 1; 1520 if (ecount <= 0x1f) 1521 { 1522 output_B2_format (f, ecount, t); 1523 return; 1524 } 1525 bytes[0] = UNW_B3; 1526 count += output_leb128 (bytes + 1, t, 0); 1527 count += output_leb128 (bytes + count, ecount, 0); 1528 (*f) (count, bytes, NULL); 1529} 1530 1531static void 1532output_B4_format (f, rtype, label) 1533 vbyte_func f; 1534 unw_record_type rtype; 1535 unsigned long label; 1536{ 1537 char bytes[20]; 1538 int r = 0; 1539 int count = 1; 1540 if (label <= 0x1f) 1541 { 1542 output_B1_format (f, rtype, label); 1543 return; 1544 } 1545 1546 if (rtype == copy_state) 1547 r = 1; 1548 else if (rtype != label_state) 1549 as_bad ("Invalid record type for format B1"); 1550 1551 bytes[0] = (UNW_B4 | (r << 3)); 1552 count += output_leb128 (bytes + 1, label, 0); 1553 (*f) (count, bytes, NULL); 1554} 1555 1556static char 1557format_ab_reg (ab, reg) 1558 int ab; 1559 int reg; 1560{ 1561 int ret; 1562 ab = (ab & 3); 1563 reg = (reg & 0x1f); 1564 ret = (ab << 5) | reg; 1565 return ret; 1566} 1567 1568static void 1569output_X1_format (f, rtype, ab, reg, t, w1) 1570 vbyte_func f; 1571 unw_record_type rtype; 1572 int ab, reg; 1573 unsigned long t; 1574 unsigned long w1; 1575{ 1576 char bytes[20]; 1577 int r = 0; 1578 int count = 2; 1579 bytes[0] = UNW_X1; 1580 1581 if (rtype == spill_sprel) 1582 r = 1; 1583 else if (rtype != spill_psprel) 1584 as_bad ("Invalid record type for format X1"); 1585 bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); 1586 count += output_leb128 (bytes + 2, t, 0); 1587 count += output_leb128 (bytes + count, w1, 0); 1588 (*f) (count, bytes, NULL); 1589} 1590 1591static void 1592output_X2_format (f, ab, reg, x, y, treg, t) 1593 vbyte_func f; 1594 int ab, reg; 1595 int x, y, treg; 1596 unsigned long t; 1597{ 1598 char bytes[20]; 1599 int count = 3; 1600 bytes[0] = UNW_X2; 1601 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1602 bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); 1603 count += output_leb128 (bytes + 3, t, 0); 1604 (*f) (count, bytes, NULL); 1605} 1606 1607static void 1608output_X3_format (f, rtype, qp, ab, reg, t, w1) 1609 vbyte_func f; 1610 unw_record_type rtype; 1611 int qp; 1612 int ab, reg; 1613 unsigned long t; 1614 unsigned long w1; 1615{ 1616 char bytes[20]; 1617 int r = 0; 1618 int count = 3; 1619 bytes[0] = UNW_X3; 1620 1621 if (rtype == spill_sprel_p) 1622 r = 1; 1623 else if (rtype != spill_psprel_p) 1624 as_bad ("Invalid record type for format X3"); 1625 bytes[1] = ((r << 7) | (qp & 0x3f)); 1626 bytes[2] = format_ab_reg (ab, reg); 1627 count += output_leb128 (bytes + 3, t, 0); 1628 count += output_leb128 (bytes + count, w1, 0); 1629 (*f) (count, bytes, NULL); 1630} 1631 1632static void 1633output_X4_format (f, qp, ab, reg, x, y, treg, t) 1634 vbyte_func f; 1635 int qp; 1636 int ab, reg; 1637 int x, y, treg; 1638 unsigned long t; 1639{ 1640 char bytes[20]; 1641 int count = 4; 1642 bytes[0] = UNW_X4; 1643 bytes[1] = (qp & 0x3f); 1644 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1645 bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); 1646 count += output_leb128 (bytes + 4, t, 0); 1647 (*f) (count, bytes, NULL); 1648} 1649 1650/* This function allocates a record list structure, and initializes fields. */ 1651 1652static unw_rec_list * 1653alloc_record (unw_record_type t) 1654{ 1655 unw_rec_list *ptr; 1656 ptr = xmalloc (sizeof (*ptr)); 1657 ptr->next = NULL; 1658 ptr->slot_number = SLOT_NUM_NOT_SET; 1659 ptr->r.type = t; 1660 return ptr; 1661} 1662 1663/* This function frees an entire list of record structures. */ 1664 1665void 1666free_list_records (unw_rec_list *first) 1667{ 1668 unw_rec_list *ptr; 1669 for (ptr = first; ptr != NULL;) 1670 { 1671 unw_rec_list *tmp = ptr; 1672 1673 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) 1674 && tmp->r.record.r.mask.i) 1675 free (tmp->r.record.r.mask.i); 1676 1677 ptr = ptr->next; 1678 free (tmp); 1679 } 1680} 1681 1682static unw_rec_list * 1683output_prologue () 1684{ 1685 unw_rec_list *ptr = alloc_record (prologue); 1686 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1687 return ptr; 1688} 1689 1690static unw_rec_list * 1691output_prologue_gr (saved_mask, reg) 1692 unsigned int saved_mask; 1693 unsigned int reg; 1694{ 1695 unw_rec_list *ptr = alloc_record (prologue_gr); 1696 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1697 ptr->r.record.r.grmask = saved_mask; 1698 ptr->r.record.r.grsave = reg; 1699 return ptr; 1700} 1701 1702static unw_rec_list * 1703output_body () 1704{ 1705 unw_rec_list *ptr = alloc_record (body); 1706 return ptr; 1707} 1708 1709static unw_rec_list * 1710output_mem_stack_f (size) 1711 unsigned int size; 1712{ 1713 unw_rec_list *ptr = alloc_record (mem_stack_f); 1714 ptr->r.record.p.size = size; 1715 return ptr; 1716} 1717 1718static unw_rec_list * 1719output_mem_stack_v () 1720{ 1721 unw_rec_list *ptr = alloc_record (mem_stack_v); 1722 return ptr; 1723} 1724 1725static unw_rec_list * 1726output_psp_gr (gr) 1727 unsigned int gr; 1728{ 1729 unw_rec_list *ptr = alloc_record (psp_gr); 1730 ptr->r.record.p.gr = gr; 1731 return ptr; 1732} 1733 1734static unw_rec_list * 1735output_psp_sprel (offset) 1736 unsigned int offset; 1737{ 1738 unw_rec_list *ptr = alloc_record (psp_sprel); 1739 ptr->r.record.p.spoff = offset / 4; 1740 return ptr; 1741} 1742 1743static unw_rec_list * 1744output_rp_when () 1745{ 1746 unw_rec_list *ptr = alloc_record (rp_when); 1747 return ptr; 1748} 1749 1750static unw_rec_list * 1751output_rp_gr (gr) 1752 unsigned int gr; 1753{ 1754 unw_rec_list *ptr = alloc_record (rp_gr); 1755 ptr->r.record.p.gr = gr; 1756 return ptr; 1757} 1758 1759static unw_rec_list * 1760output_rp_br (br) 1761 unsigned int br; 1762{ 1763 unw_rec_list *ptr = alloc_record (rp_br); 1764 ptr->r.record.p.br = br; 1765 return ptr; 1766} 1767 1768static unw_rec_list * 1769output_rp_psprel (offset) 1770 unsigned int offset; 1771{ 1772 unw_rec_list *ptr = alloc_record (rp_psprel); 1773 ptr->r.record.p.pspoff = offset / 4; 1774 return ptr; 1775} 1776 1777static unw_rec_list * 1778output_rp_sprel (offset) 1779 unsigned int offset; 1780{ 1781 unw_rec_list *ptr = alloc_record (rp_sprel); 1782 ptr->r.record.p.spoff = offset / 4; 1783 return ptr; 1784} 1785 1786static unw_rec_list * 1787output_pfs_when () 1788{ 1789 unw_rec_list *ptr = alloc_record (pfs_when); 1790 return ptr; 1791} 1792 1793static unw_rec_list * 1794output_pfs_gr (gr) 1795 unsigned int gr; 1796{ 1797 unw_rec_list *ptr = alloc_record (pfs_gr); 1798 ptr->r.record.p.gr = gr; 1799 return ptr; 1800} 1801 1802static unw_rec_list * 1803output_pfs_psprel (offset) 1804 unsigned int offset; 1805{ 1806 unw_rec_list *ptr = alloc_record (pfs_psprel); 1807 ptr->r.record.p.pspoff = offset / 4; 1808 return ptr; 1809} 1810 1811static unw_rec_list * 1812output_pfs_sprel (offset) 1813 unsigned int offset; 1814{ 1815 unw_rec_list *ptr = alloc_record (pfs_sprel); 1816 ptr->r.record.p.spoff = offset / 4; 1817 return ptr; 1818} 1819 1820static unw_rec_list * 1821output_preds_when () 1822{ 1823 unw_rec_list *ptr = alloc_record (preds_when); 1824 return ptr; 1825} 1826 1827static unw_rec_list * 1828output_preds_gr (gr) 1829 unsigned int gr; 1830{ 1831 unw_rec_list *ptr = alloc_record (preds_gr); 1832 ptr->r.record.p.gr = gr; 1833 return ptr; 1834} 1835 1836static unw_rec_list * 1837output_preds_psprel (offset) 1838 unsigned int offset; 1839{ 1840 unw_rec_list *ptr = alloc_record (preds_psprel); 1841 ptr->r.record.p.pspoff = offset / 4; 1842 return ptr; 1843} 1844 1845static unw_rec_list * 1846output_preds_sprel (offset) 1847 unsigned int offset; 1848{ 1849 unw_rec_list *ptr = alloc_record (preds_sprel); 1850 ptr->r.record.p.spoff = offset / 4; 1851 return ptr; 1852} 1853 1854static unw_rec_list * 1855output_fr_mem (mask) 1856 unsigned int mask; 1857{ 1858 unw_rec_list *ptr = alloc_record (fr_mem); 1859 ptr->r.record.p.rmask = mask; 1860 return ptr; 1861} 1862 1863static unw_rec_list * 1864output_frgr_mem (gr_mask, fr_mask) 1865 unsigned int gr_mask; 1866 unsigned int fr_mask; 1867{ 1868 unw_rec_list *ptr = alloc_record (frgr_mem); 1869 ptr->r.record.p.grmask = gr_mask; 1870 ptr->r.record.p.frmask = fr_mask; 1871 return ptr; 1872} 1873 1874static unw_rec_list * 1875output_gr_gr (mask, reg) 1876 unsigned int mask; 1877 unsigned int reg; 1878{ 1879 unw_rec_list *ptr = alloc_record (gr_gr); 1880 ptr->r.record.p.grmask = mask; 1881 ptr->r.record.p.gr = reg; 1882 return ptr; 1883} 1884 1885static unw_rec_list * 1886output_gr_mem (mask) 1887 unsigned int mask; 1888{ 1889 unw_rec_list *ptr = alloc_record (gr_mem); 1890 ptr->r.record.p.rmask = mask; 1891 return ptr; 1892} 1893 1894static unw_rec_list * 1895output_br_mem (unsigned int mask) 1896{ 1897 unw_rec_list *ptr = alloc_record (br_mem); 1898 ptr->r.record.p.brmask = mask; 1899 return ptr; 1900} 1901 1902static unw_rec_list * 1903output_br_gr (save_mask, reg) 1904 unsigned int save_mask; 1905 unsigned int reg; 1906{ 1907 unw_rec_list *ptr = alloc_record (br_gr); 1908 ptr->r.record.p.brmask = save_mask; 1909 ptr->r.record.p.gr = reg; 1910 return ptr; 1911} 1912 1913static unw_rec_list * 1914output_spill_base (offset) 1915 unsigned int offset; 1916{ 1917 unw_rec_list *ptr = alloc_record (spill_base); 1918 ptr->r.record.p.pspoff = offset / 4; 1919 return ptr; 1920} 1921 1922static unw_rec_list * 1923output_unat_when () 1924{ 1925 unw_rec_list *ptr = alloc_record (unat_when); 1926 return ptr; 1927} 1928 1929static unw_rec_list * 1930output_unat_gr (gr) 1931 unsigned int gr; 1932{ 1933 unw_rec_list *ptr = alloc_record (unat_gr); 1934 ptr->r.record.p.gr = gr; 1935 return ptr; 1936} 1937 1938static unw_rec_list * 1939output_unat_psprel (offset) 1940 unsigned int offset; 1941{ 1942 unw_rec_list *ptr = alloc_record (unat_psprel); 1943 ptr->r.record.p.pspoff = offset / 4; 1944 return ptr; 1945} 1946 1947static unw_rec_list * 1948output_unat_sprel (offset) 1949 unsigned int offset; 1950{ 1951 unw_rec_list *ptr = alloc_record (unat_sprel); 1952 ptr->r.record.p.spoff = offset / 4; 1953 return ptr; 1954} 1955 1956static unw_rec_list * 1957output_lc_when () 1958{ 1959 unw_rec_list *ptr = alloc_record (lc_when); 1960 return ptr; 1961} 1962 1963static unw_rec_list * 1964output_lc_gr (gr) 1965 unsigned int gr; 1966{ 1967 unw_rec_list *ptr = alloc_record (lc_gr); 1968 ptr->r.record.p.gr = gr; 1969 return ptr; 1970} 1971 1972static unw_rec_list * 1973output_lc_psprel (offset) 1974 unsigned int offset; 1975{ 1976 unw_rec_list *ptr = alloc_record (lc_psprel); 1977 ptr->r.record.p.pspoff = offset / 4; 1978 return ptr; 1979} 1980 1981static unw_rec_list * 1982output_lc_sprel (offset) 1983 unsigned int offset; 1984{ 1985 unw_rec_list *ptr = alloc_record (lc_sprel); 1986 ptr->r.record.p.spoff = offset / 4; 1987 return ptr; 1988} 1989 1990static unw_rec_list * 1991output_fpsr_when () 1992{ 1993 unw_rec_list *ptr = alloc_record (fpsr_when); 1994 return ptr; 1995} 1996 1997static unw_rec_list * 1998output_fpsr_gr (gr) 1999 unsigned int gr; 2000{ 2001 unw_rec_list *ptr = alloc_record (fpsr_gr); 2002 ptr->r.record.p.gr = gr; 2003 return ptr; 2004} 2005 2006static unw_rec_list * 2007output_fpsr_psprel (offset) 2008 unsigned int offset; 2009{ 2010 unw_rec_list *ptr = alloc_record (fpsr_psprel); 2011 ptr->r.record.p.pspoff = offset / 4; 2012 return ptr; 2013} 2014 2015static unw_rec_list * 2016output_fpsr_sprel (offset) 2017 unsigned int offset; 2018{ 2019 unw_rec_list *ptr = alloc_record (fpsr_sprel); 2020 ptr->r.record.p.spoff = offset / 4; 2021 return ptr; 2022} 2023 2024static unw_rec_list * 2025output_priunat_when_gr () 2026{ 2027 unw_rec_list *ptr = alloc_record (priunat_when_gr); 2028 return ptr; 2029} 2030 2031static unw_rec_list * 2032output_priunat_when_mem () 2033{ 2034 unw_rec_list *ptr = alloc_record (priunat_when_mem); 2035 return ptr; 2036} 2037 2038static unw_rec_list * 2039output_priunat_gr (gr) 2040 unsigned int gr; 2041{ 2042 unw_rec_list *ptr = alloc_record (priunat_gr); 2043 ptr->r.record.p.gr = gr; 2044 return ptr; 2045} 2046 2047static unw_rec_list * 2048output_priunat_psprel (offset) 2049 unsigned int offset; 2050{ 2051 unw_rec_list *ptr = alloc_record (priunat_psprel); 2052 ptr->r.record.p.pspoff = offset / 4; 2053 return ptr; 2054} 2055 2056static unw_rec_list * 2057output_priunat_sprel (offset) 2058 unsigned int offset; 2059{ 2060 unw_rec_list *ptr = alloc_record (priunat_sprel); 2061 ptr->r.record.p.spoff = offset / 4; 2062 return ptr; 2063} 2064 2065static unw_rec_list * 2066output_bsp_when () 2067{ 2068 unw_rec_list *ptr = alloc_record (bsp_when); 2069 return ptr; 2070} 2071 2072static unw_rec_list * 2073output_bsp_gr (gr) 2074 unsigned int gr; 2075{ 2076 unw_rec_list *ptr = alloc_record (bsp_gr); 2077 ptr->r.record.p.gr = gr; 2078 return ptr; 2079} 2080 2081static unw_rec_list * 2082output_bsp_psprel (offset) 2083 unsigned int offset; 2084{ 2085 unw_rec_list *ptr = alloc_record (bsp_psprel); 2086 ptr->r.record.p.pspoff = offset / 4; 2087 return ptr; 2088} 2089 2090static unw_rec_list * 2091output_bsp_sprel (offset) 2092 unsigned int offset; 2093{ 2094 unw_rec_list *ptr = alloc_record (bsp_sprel); 2095 ptr->r.record.p.spoff = offset / 4; 2096 return ptr; 2097} 2098 2099static unw_rec_list * 2100output_bspstore_when () 2101{ 2102 unw_rec_list *ptr = alloc_record (bspstore_when); 2103 return ptr; 2104} 2105 2106static unw_rec_list * 2107output_bspstore_gr (gr) 2108 unsigned int gr; 2109{ 2110 unw_rec_list *ptr = alloc_record (bspstore_gr); 2111 ptr->r.record.p.gr = gr; 2112 return ptr; 2113} 2114 2115static unw_rec_list * 2116output_bspstore_psprel (offset) 2117 unsigned int offset; 2118{ 2119 unw_rec_list *ptr = alloc_record (bspstore_psprel); 2120 ptr->r.record.p.pspoff = offset / 4; 2121 return ptr; 2122} 2123 2124static unw_rec_list * 2125output_bspstore_sprel (offset) 2126 unsigned int offset; 2127{ 2128 unw_rec_list *ptr = alloc_record (bspstore_sprel); 2129 ptr->r.record.p.spoff = offset / 4; 2130 return ptr; 2131} 2132 2133static unw_rec_list * 2134output_rnat_when () 2135{ 2136 unw_rec_list *ptr = alloc_record (rnat_when); 2137 return ptr; 2138} 2139 2140static unw_rec_list * 2141output_rnat_gr (gr) 2142 unsigned int gr; 2143{ 2144 unw_rec_list *ptr = alloc_record (rnat_gr); 2145 ptr->r.record.p.gr = gr; 2146 return ptr; 2147} 2148 2149static unw_rec_list * 2150output_rnat_psprel (offset) 2151 unsigned int offset; 2152{ 2153 unw_rec_list *ptr = alloc_record (rnat_psprel); 2154 ptr->r.record.p.pspoff = offset / 4; 2155 return ptr; 2156} 2157 2158static unw_rec_list * 2159output_rnat_sprel (offset) 2160 unsigned int offset; 2161{ 2162 unw_rec_list *ptr = alloc_record (rnat_sprel); 2163 ptr->r.record.p.spoff = offset / 4; 2164 return ptr; 2165} 2166 2167static unw_rec_list * 2168output_unwabi (abi, context) 2169 unsigned long abi; 2170 unsigned long context; 2171{ 2172 unw_rec_list *ptr = alloc_record (unwabi); 2173 ptr->r.record.p.abi = abi; 2174 ptr->r.record.p.context = context; 2175 return ptr; 2176} 2177 2178static unw_rec_list * 2179output_epilogue (unsigned long ecount) 2180{ 2181 unw_rec_list *ptr = alloc_record (epilogue); 2182 ptr->r.record.b.ecount = ecount; 2183 return ptr; 2184} 2185 2186static unw_rec_list * 2187output_label_state (unsigned long label) 2188{ 2189 unw_rec_list *ptr = alloc_record (label_state); 2190 ptr->r.record.b.label = label; 2191 return ptr; 2192} 2193 2194static unw_rec_list * 2195output_copy_state (unsigned long label) 2196{ 2197 unw_rec_list *ptr = alloc_record (copy_state); 2198 ptr->r.record.b.label = label; 2199 return ptr; 2200} 2201 2202static unw_rec_list * 2203output_spill_psprel (ab, reg, offset) 2204 unsigned int ab; 2205 unsigned int reg; 2206 unsigned int offset; 2207{ 2208 unw_rec_list *ptr = alloc_record (spill_psprel); 2209 ptr->r.record.x.ab = ab; 2210 ptr->r.record.x.reg = reg; 2211 ptr->r.record.x.pspoff = offset / 4; 2212 return ptr; 2213} 2214 2215static unw_rec_list * 2216output_spill_sprel (ab, reg, offset) 2217 unsigned int ab; 2218 unsigned int reg; 2219 unsigned int offset; 2220{ 2221 unw_rec_list *ptr = alloc_record (spill_sprel); 2222 ptr->r.record.x.ab = ab; 2223 ptr->r.record.x.reg = reg; 2224 ptr->r.record.x.spoff = offset / 4; 2225 return ptr; 2226} 2227 2228static unw_rec_list * 2229output_spill_psprel_p (ab, reg, offset, predicate) 2230 unsigned int ab; 2231 unsigned int reg; 2232 unsigned int offset; 2233 unsigned int predicate; 2234{ 2235 unw_rec_list *ptr = alloc_record (spill_psprel_p); 2236 ptr->r.record.x.ab = ab; 2237 ptr->r.record.x.reg = reg; 2238 ptr->r.record.x.pspoff = offset / 4; 2239 ptr->r.record.x.qp = predicate; 2240 return ptr; 2241} 2242 2243static unw_rec_list * 2244output_spill_sprel_p (ab, reg, offset, predicate) 2245 unsigned int ab; 2246 unsigned int reg; 2247 unsigned int offset; 2248 unsigned int predicate; 2249{ 2250 unw_rec_list *ptr = alloc_record (spill_sprel_p); 2251 ptr->r.record.x.ab = ab; 2252 ptr->r.record.x.reg = reg; 2253 ptr->r.record.x.spoff = offset / 4; 2254 ptr->r.record.x.qp = predicate; 2255 return ptr; 2256} 2257 2258static unw_rec_list * 2259output_spill_reg (ab, reg, targ_reg, xy) 2260 unsigned int ab; 2261 unsigned int reg; 2262 unsigned int targ_reg; 2263 unsigned int xy; 2264{ 2265 unw_rec_list *ptr = alloc_record (spill_reg); 2266 ptr->r.record.x.ab = ab; 2267 ptr->r.record.x.reg = reg; 2268 ptr->r.record.x.treg = targ_reg; 2269 ptr->r.record.x.xy = xy; 2270 return ptr; 2271} 2272 2273static unw_rec_list * 2274output_spill_reg_p (ab, reg, targ_reg, xy, predicate) 2275 unsigned int ab; 2276 unsigned int reg; 2277 unsigned int targ_reg; 2278 unsigned int xy; 2279 unsigned int predicate; 2280{ 2281 unw_rec_list *ptr = alloc_record (spill_reg_p); 2282 ptr->r.record.x.ab = ab; 2283 ptr->r.record.x.reg = reg; 2284 ptr->r.record.x.treg = targ_reg; 2285 ptr->r.record.x.xy = xy; 2286 ptr->r.record.x.qp = predicate; 2287 return ptr; 2288} 2289 2290/* Given a unw_rec_list process the correct format with the 2291 specified function. */ 2292 2293static void 2294process_one_record (ptr, f) 2295 unw_rec_list *ptr; 2296 vbyte_func f; 2297{ 2298 unsigned long fr_mask, gr_mask; 2299 2300 switch (ptr->r.type) 2301 { 2302 case gr_mem: 2303 case fr_mem: 2304 case br_mem: 2305 case frgr_mem: 2306 /* These are taken care of by prologue/prologue_gr. */ 2307 break; 2308 2309 case prologue_gr: 2310 case prologue: 2311 if (ptr->r.type == prologue_gr) 2312 output_R2_format (f, ptr->r.record.r.grmask, 2313 ptr->r.record.r.grsave, ptr->r.record.r.rlen); 2314 else 2315 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2316 2317 /* Output descriptor(s) for union of register spills (if any). */ 2318 gr_mask = ptr->r.record.r.mask.gr_mem; 2319 fr_mask = ptr->r.record.r.mask.fr_mem; 2320 if (fr_mask) 2321 { 2322 if ((fr_mask & ~0xfUL) == 0) 2323 output_P6_format (f, fr_mem, fr_mask); 2324 else 2325 { 2326 output_P5_format (f, gr_mask, fr_mask); 2327 gr_mask = 0; 2328 } 2329 } 2330 if (gr_mask) 2331 output_P6_format (f, gr_mem, gr_mask); 2332 if (ptr->r.record.r.mask.br_mem) 2333 output_P1_format (f, ptr->r.record.r.mask.br_mem); 2334 2335 /* output imask descriptor if necessary: */ 2336 if (ptr->r.record.r.mask.i) 2337 output_P4_format (f, ptr->r.record.r.mask.i, 2338 ptr->r.record.r.imask_size); 2339 break; 2340 2341 case body: 2342 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2343 break; 2344 case mem_stack_f: 2345 case mem_stack_v: 2346 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 2347 ptr->r.record.p.size); 2348 break; 2349 case psp_gr: 2350 case rp_gr: 2351 case pfs_gr: 2352 case preds_gr: 2353 case unat_gr: 2354 case lc_gr: 2355 case fpsr_gr: 2356 case priunat_gr: 2357 case bsp_gr: 2358 case bspstore_gr: 2359 case rnat_gr: 2360 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); 2361 break; 2362 case rp_br: 2363 output_P3_format (f, rp_br, ptr->r.record.p.br); 2364 break; 2365 case psp_sprel: 2366 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); 2367 break; 2368 case rp_when: 2369 case pfs_when: 2370 case preds_when: 2371 case unat_when: 2372 case lc_when: 2373 case fpsr_when: 2374 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); 2375 break; 2376 case rp_psprel: 2377 case pfs_psprel: 2378 case preds_psprel: 2379 case unat_psprel: 2380 case lc_psprel: 2381 case fpsr_psprel: 2382 case spill_base: 2383 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); 2384 break; 2385 case rp_sprel: 2386 case pfs_sprel: 2387 case preds_sprel: 2388 case unat_sprel: 2389 case lc_sprel: 2390 case fpsr_sprel: 2391 case priunat_sprel: 2392 case bsp_sprel: 2393 case bspstore_sprel: 2394 case rnat_sprel: 2395 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); 2396 break; 2397 case gr_gr: 2398 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); 2399 break; 2400 case br_gr: 2401 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); 2402 break; 2403 case spill_mask: 2404 as_bad ("spill_mask record unimplemented."); 2405 break; 2406 case priunat_when_gr: 2407 case priunat_when_mem: 2408 case bsp_when: 2409 case bspstore_when: 2410 case rnat_when: 2411 output_P8_format (f, ptr->r.type, ptr->r.record.p.t); 2412 break; 2413 case priunat_psprel: 2414 case bsp_psprel: 2415 case bspstore_psprel: 2416 case rnat_psprel: 2417 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); 2418 break; 2419 case unwabi: 2420 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); 2421 break; 2422 case epilogue: 2423 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); 2424 break; 2425 case label_state: 2426 case copy_state: 2427 output_B4_format (f, ptr->r.type, ptr->r.record.b.label); 2428 break; 2429 case spill_psprel: 2430 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2431 ptr->r.record.x.reg, ptr->r.record.x.t, 2432 ptr->r.record.x.pspoff); 2433 break; 2434 case spill_sprel: 2435 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2436 ptr->r.record.x.reg, ptr->r.record.x.t, 2437 ptr->r.record.x.spoff); 2438 break; 2439 case spill_reg: 2440 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, 2441 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, 2442 ptr->r.record.x.treg, ptr->r.record.x.t); 2443 break; 2444 case spill_psprel_p: 2445 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2446 ptr->r.record.x.ab, ptr->r.record.x.reg, 2447 ptr->r.record.x.t, ptr->r.record.x.pspoff); 2448 break; 2449 case spill_sprel_p: 2450 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2451 ptr->r.record.x.ab, ptr->r.record.x.reg, 2452 ptr->r.record.x.t, ptr->r.record.x.spoff); 2453 break; 2454 case spill_reg_p: 2455 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, 2456 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, 2457 ptr->r.record.x.xy, ptr->r.record.x.treg, 2458 ptr->r.record.x.t); 2459 break; 2460 default: 2461 as_bad ("record_type_not_valid"); 2462 break; 2463 } 2464} 2465 2466/* Given a unw_rec_list list, process all the records with 2467 the specified function. */ 2468static void 2469process_unw_records (list, f) 2470 unw_rec_list *list; 2471 vbyte_func f; 2472{ 2473 unw_rec_list *ptr; 2474 for (ptr = list; ptr; ptr = ptr->next) 2475 process_one_record (ptr, f); 2476} 2477 2478/* Determine the size of a record list in bytes. */ 2479static int 2480calc_record_size (list) 2481 unw_rec_list *list; 2482{ 2483 vbyte_count = 0; 2484 process_unw_records (list, count_output); 2485 return vbyte_count; 2486} 2487 2488/* Update IMASK bitmask to reflect the fact that one or more registers 2489 of type TYPE are saved starting at instruction with index T. If N 2490 bits are set in REGMASK, it is assumed that instructions T through 2491 T+N-1 save these registers. 2492 2493 TYPE values: 2494 0: no save 2495 1: instruction saves next fp reg 2496 2: instruction saves next general reg 2497 3: instruction saves next branch reg */ 2498static void 2499set_imask (region, regmask, t, type) 2500 unw_rec_list *region; 2501 unsigned long regmask; 2502 unsigned long t; 2503 unsigned int type; 2504{ 2505 unsigned char *imask; 2506 unsigned long imask_size; 2507 unsigned int i; 2508 int pos; 2509 2510 imask = region->r.record.r.mask.i; 2511 imask_size = region->r.record.r.imask_size; 2512 if (!imask) 2513 { 2514 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; 2515 imask = xmalloc (imask_size); 2516 memset (imask, 0, imask_size); 2517 2518 region->r.record.r.imask_size = imask_size; 2519 region->r.record.r.mask.i = imask; 2520 } 2521 2522 i = (t / 4) + 1; 2523 pos = 2 * (3 - t % 4); 2524 while (regmask) 2525 { 2526 if (i >= imask_size) 2527 { 2528 as_bad ("Ignoring attempt to spill beyond end of region"); 2529 return; 2530 } 2531 2532 imask[i] |= (type & 0x3) << pos; 2533 2534 regmask &= (regmask - 1); 2535 pos -= 2; 2536 if (pos < 0) 2537 { 2538 pos = 0; 2539 ++i; 2540 } 2541 } 2542} 2543 2544static int 2545count_bits (unsigned long mask) 2546{ 2547 int n = 0; 2548 2549 while (mask) 2550 { 2551 mask &= mask - 1; 2552 ++n; 2553 } 2554 return n; 2555} 2556 2557/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. 2558 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag 2559 containing FIRST_ADDR. */ 2560 2561unsigned long 2562slot_index (slot_addr, slot_frag, first_addr, first_frag) 2563 unsigned long slot_addr; 2564 fragS *slot_frag; 2565 unsigned long first_addr; 2566 fragS *first_frag; 2567{ 2568 unsigned long index = 0; 2569 2570 /* First time we are called, the initial address and frag are invalid. */ 2571 if (first_addr == 0) 2572 return 0; 2573 2574 /* If the two addresses are in different frags, then we need to add in 2575 the remaining size of this frag, and then the entire size of intermediate 2576 frags. */ 2577 while (slot_frag != first_frag) 2578 { 2579 unsigned long start_addr = (unsigned long) &first_frag->fr_literal; 2580 2581 /* Add in the full size of the frag converted to instruction slots. */ 2582 index += 3 * (first_frag->fr_fix >> 4); 2583 /* Subtract away the initial part before first_addr. */ 2584 index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) 2585 + ((first_addr & 0x3) - (start_addr & 0x3))); 2586 2587 /* Move to the beginning of the next frag. */ 2588 first_frag = first_frag->fr_next; 2589 first_addr = (unsigned long) &first_frag->fr_literal; 2590 } 2591 2592 /* Add in the used part of the last frag. */ 2593 index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) 2594 + ((slot_addr & 0x3) - (first_addr & 0x3))); 2595 return index; 2596} 2597 2598/* Optimize unwind record directives. */ 2599 2600static unw_rec_list * 2601optimize_unw_records (list) 2602 unw_rec_list *list; 2603{ 2604 if (!list) 2605 return NULL; 2606 2607 /* If the only unwind record is ".prologue" or ".prologue" followed 2608 by ".body", then we can optimize the unwind directives away. */ 2609 if (list->r.type == prologue 2610 && (list->next == NULL 2611 || (list->next->r.type == body && list->next->next == NULL))) 2612 return NULL; 2613 2614 return list; 2615} 2616 2617/* Given a complete record list, process any records which have 2618 unresolved fields, (ie length counts for a prologue). After 2619 this has been run, all neccessary information should be available 2620 within each record to generate an image. */ 2621 2622static void 2623fixup_unw_records (list) 2624 unw_rec_list *list; 2625{ 2626 unw_rec_list *ptr, *region = 0; 2627 unsigned long first_addr = 0, rlen = 0, t; 2628 fragS *first_frag = 0; 2629 2630 for (ptr = list; ptr; ptr = ptr->next) 2631 { 2632 if (ptr->slot_number == SLOT_NUM_NOT_SET) 2633 as_bad (" Insn slot not set in unwind record."); 2634 t = slot_index (ptr->slot_number, ptr->slot_frag, 2635 first_addr, first_frag); 2636 switch (ptr->r.type) 2637 { 2638 case prologue: 2639 case prologue_gr: 2640 case body: 2641 { 2642 unw_rec_list *last; 2643 int size, dir_len = 0; 2644 unsigned long last_addr; 2645 fragS *last_frag; 2646 2647 first_addr = ptr->slot_number; 2648 first_frag = ptr->slot_frag; 2649 ptr->slot_number = 0; 2650 /* Find either the next body/prologue start, or the end of 2651 the list, and determine the size of the region. */ 2652 last_addr = unwind.next_slot_number; 2653 last_frag = unwind.next_slot_frag; 2654 for (last = ptr->next; last != NULL; last = last->next) 2655 if (last->r.type == prologue || last->r.type == prologue_gr 2656 || last->r.type == body) 2657 { 2658 last_addr = last->slot_number; 2659 last_frag = last->slot_frag; 2660 break; 2661 } 2662 else if (!last->next) 2663 { 2664 /* In the absence of an explicit .body directive, 2665 the prologue ends after the last instruction 2666 covered by an unwind directive. */ 2667 if (ptr->r.type != body) 2668 { 2669 last_addr = last->slot_number; 2670 last_frag = last->slot_frag; 2671 switch (last->r.type) 2672 { 2673 case frgr_mem: 2674 dir_len = (count_bits (last->r.record.p.frmask) 2675 + count_bits (last->r.record.p.grmask)); 2676 break; 2677 case fr_mem: 2678 case gr_mem: 2679 dir_len += count_bits (last->r.record.p.rmask); 2680 break; 2681 case br_mem: 2682 case br_gr: 2683 dir_len += count_bits (last->r.record.p.brmask); 2684 break; 2685 case gr_gr: 2686 dir_len += count_bits (last->r.record.p.grmask); 2687 break; 2688 default: 2689 dir_len = 1; 2690 break; 2691 } 2692 } 2693 break; 2694 } 2695 size = (slot_index (last_addr, last_frag, first_addr, first_frag) 2696 + dir_len); 2697 rlen = ptr->r.record.r.rlen = size; 2698 region = ptr; 2699 break; 2700 } 2701 case epilogue: 2702 ptr->r.record.b.t = rlen - 1 - t; 2703 break; 2704 2705 case mem_stack_f: 2706 case mem_stack_v: 2707 case rp_when: 2708 case pfs_when: 2709 case preds_when: 2710 case unat_when: 2711 case lc_when: 2712 case fpsr_when: 2713 case priunat_when_gr: 2714 case priunat_when_mem: 2715 case bsp_when: 2716 case bspstore_when: 2717 case rnat_when: 2718 ptr->r.record.p.t = t; 2719 break; 2720 2721 case spill_reg: 2722 case spill_sprel: 2723 case spill_psprel: 2724 case spill_reg_p: 2725 case spill_sprel_p: 2726 case spill_psprel_p: 2727 ptr->r.record.x.t = t; 2728 break; 2729 2730 case frgr_mem: 2731 if (!region) 2732 { 2733 as_bad ("frgr_mem record before region record!\n"); 2734 return; 2735 } 2736 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; 2737 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; 2738 set_imask (region, ptr->r.record.p.frmask, t, 1); 2739 set_imask (region, ptr->r.record.p.grmask, t, 2); 2740 break; 2741 case fr_mem: 2742 if (!region) 2743 { 2744 as_bad ("fr_mem record before region record!\n"); 2745 return; 2746 } 2747 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; 2748 set_imask (region, ptr->r.record.p.rmask, t, 1); 2749 break; 2750 case gr_mem: 2751 if (!region) 2752 { 2753 as_bad ("gr_mem record before region record!\n"); 2754 return; 2755 } 2756 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; 2757 set_imask (region, ptr->r.record.p.rmask, t, 2); 2758 break; 2759 case br_mem: 2760 if (!region) 2761 { 2762 as_bad ("br_mem record before region record!\n"); 2763 return; 2764 } 2765 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; 2766 set_imask (region, ptr->r.record.p.brmask, t, 3); 2767 break; 2768 2769 case gr_gr: 2770 if (!region) 2771 { 2772 as_bad ("gr_gr record before region record!\n"); 2773 return; 2774 } 2775 set_imask (region, ptr->r.record.p.grmask, t, 2); 2776 break; 2777 case br_gr: 2778 if (!region) 2779 { 2780 as_bad ("br_gr record before region record!\n"); 2781 return; 2782 } 2783 set_imask (region, ptr->r.record.p.brmask, t, 3); 2784 break; 2785 2786 default: 2787 break; 2788 } 2789 } 2790} 2791 2792/* Helper routine for output_unw_records. Emits the header for the unwind 2793 info. */ 2794 2795static int 2796setup_unwind_header (int size, unsigned char **mem) 2797{ 2798 int x, extra = 0; 2799 valueT flag_value; 2800 2801 /* pad to pointer-size boundry. */ 2802 x = size % md.pointer_size; 2803 if (x != 0) 2804 extra = md.pointer_size - x; 2805 2806 /* Add 8 for the header + a pointer for the 2807 personality offset. */ 2808 *mem = xmalloc (size + extra + 8 + md.pointer_size); 2809 2810 /* Clear the padding area and personality. */ 2811 memset (*mem + 8 + size, 0 , extra + md.pointer_size); 2812 2813 /* Initialize the header area. */ 2814 if (unwind.personality_routine) 2815 { 2816 if (md.flags & EF_IA_64_ABI64) 2817 flag_value = (bfd_vma) 3 << 32; 2818 else 2819 /* 32-bit unwind info block. */ 2820 flag_value = (bfd_vma) 0x1003 << 32; 2821 } 2822 else 2823 flag_value = 0; 2824 2825 md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */ 2826 | flag_value /* U & E handler flags. */ 2827 | ((size + extra) / md.pointer_size)), /* Length. */ 2828 8); 2829 2830 return extra; 2831} 2832 2833/* Generate an unwind image from a record list. Returns the number of 2834 bytes in the resulting image. The memory image itselof is returned 2835 in the 'ptr' parameter. */ 2836static int 2837output_unw_records (list, ptr) 2838 unw_rec_list *list; 2839 void **ptr; 2840{ 2841 int size, extra; 2842 unsigned char *mem; 2843 2844 *ptr = NULL; 2845 2846 list = optimize_unw_records (list); 2847 fixup_unw_records (list); 2848 size = calc_record_size (list); 2849 2850 if (size > 0 || unwind.force_unwind_entry) 2851 { 2852 unwind.force_unwind_entry = 0; 2853 extra = setup_unwind_header (size, &mem); 2854 2855 vbyte_mem_ptr = mem + 8; 2856 process_unw_records (list, output_vbyte_mem); 2857 2858 *ptr = mem; 2859 2860 size += extra + 8 + md.pointer_size; 2861 } 2862 return size; 2863} 2864 2865static int 2866convert_expr_to_ab_reg (e, ab, regp) 2867 expressionS *e; 2868 unsigned int *ab; 2869 unsigned int *regp; 2870{ 2871 unsigned int reg; 2872 2873 if (e->X_op != O_register) 2874 return 0; 2875 2876 reg = e->X_add_number; 2877 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) 2878 { 2879 *ab = 0; 2880 *regp = reg - REG_GR; 2881 } 2882 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) 2883 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) 2884 { 2885 *ab = 1; 2886 *regp = reg - REG_FR; 2887 } 2888 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) 2889 { 2890 *ab = 2; 2891 *regp = reg - REG_BR; 2892 } 2893 else 2894 { 2895 *ab = 3; 2896 switch (reg) 2897 { 2898 case REG_PR: *regp = 0; break; 2899 case REG_PSP: *regp = 1; break; 2900 case REG_PRIUNAT: *regp = 2; break; 2901 case REG_BR + 0: *regp = 3; break; 2902 case REG_AR + AR_BSP: *regp = 4; break; 2903 case REG_AR + AR_BSPSTORE: *regp = 5; break; 2904 case REG_AR + AR_RNAT: *regp = 6; break; 2905 case REG_AR + AR_UNAT: *regp = 7; break; 2906 case REG_AR + AR_FPSR: *regp = 8; break; 2907 case REG_AR + AR_PFS: *regp = 9; break; 2908 case REG_AR + AR_LC: *regp = 10; break; 2909 2910 default: 2911 return 0; 2912 } 2913 } 2914 return 1; 2915} 2916 2917static int 2918convert_expr_to_xy_reg (e, xy, regp) 2919 expressionS *e; 2920 unsigned int *xy; 2921 unsigned int *regp; 2922{ 2923 unsigned int reg; 2924 2925 if (e->X_op != O_register) 2926 return 0; 2927 2928 reg = e->X_add_number; 2929 2930 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) 2931 { 2932 *xy = 0; 2933 *regp = reg - REG_GR; 2934 } 2935 else if (reg >= REG_FR && reg <= (REG_FR + 127)) 2936 { 2937 *xy = 1; 2938 *regp = reg - REG_FR; 2939 } 2940 else if (reg >= REG_BR && reg <= (REG_BR + 7)) 2941 { 2942 *xy = 2; 2943 *regp = reg - REG_BR; 2944 } 2945 else 2946 return -1; 2947 return 1; 2948} 2949 2950static void 2951dot_radix (dummy) 2952 int dummy ATTRIBUTE_UNUSED; 2953{ 2954 int radix; 2955 2956 SKIP_WHITESPACE (); 2957 radix = *input_line_pointer++; 2958 2959 if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) 2960 { 2961 as_bad ("Radix `%c' unsupported", *input_line_pointer); 2962 ignore_rest_of_line (); 2963 return; 2964 } 2965} 2966 2967/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ 2968static void 2969dot_special_section (which) 2970 int which; 2971{ 2972 set_section ((char *) special_section_name[which]); 2973} 2974 2975static void 2976add_unwind_entry (ptr) 2977 unw_rec_list *ptr; 2978{ 2979 if (unwind.tail) 2980 unwind.tail->next = ptr; 2981 else 2982 unwind.list = ptr; 2983 unwind.tail = ptr; 2984 2985 /* The current entry can in fact be a chain of unwind entries. */ 2986 if (unwind.current_entry == NULL) 2987 unwind.current_entry = ptr; 2988} 2989 2990static void 2991dot_fframe (dummy) 2992 int dummy ATTRIBUTE_UNUSED; 2993{ 2994 expressionS e; 2995 2996 parse_operand (&e); 2997 2998 if (e.X_op != O_constant) 2999 as_bad ("Operand to .fframe must be a constant"); 3000 else 3001 add_unwind_entry (output_mem_stack_f (e.X_add_number)); 3002} 3003 3004static void 3005dot_vframe (dummy) 3006 int dummy ATTRIBUTE_UNUSED; 3007{ 3008 expressionS e; 3009 unsigned reg; 3010 3011 parse_operand (&e); 3012 reg = e.X_add_number - REG_GR; 3013 if (e.X_op == O_register && reg < 128) 3014 { 3015 add_unwind_entry (output_mem_stack_v ()); 3016 if (! (unwind.prologue_mask & 2)) 3017 add_unwind_entry (output_psp_gr (reg)); 3018 } 3019 else 3020 as_bad ("First operand to .vframe must be a general register"); 3021} 3022 3023static void 3024dot_vframesp (dummy) 3025 int dummy ATTRIBUTE_UNUSED; 3026{ 3027 expressionS e; 3028 3029 parse_operand (&e); 3030 if (e.X_op == O_constant) 3031 { 3032 add_unwind_entry (output_mem_stack_v ()); 3033 add_unwind_entry (output_psp_sprel (e.X_add_number)); 3034 } 3035 else 3036 as_bad ("First operand to .vframesp must be a general register"); 3037} 3038 3039static void 3040dot_vframepsp (dummy) 3041 int dummy ATTRIBUTE_UNUSED; 3042{ 3043 expressionS e; 3044 3045 parse_operand (&e); 3046 if (e.X_op == O_constant) 3047 { 3048 add_unwind_entry (output_mem_stack_v ()); 3049 add_unwind_entry (output_psp_sprel (e.X_add_number)); 3050 } 3051 else 3052 as_bad ("First operand to .vframepsp must be a general register"); 3053} 3054 3055static void 3056dot_save (dummy) 3057 int dummy ATTRIBUTE_UNUSED; 3058{ 3059 expressionS e1, e2; 3060 int sep; 3061 int reg1, reg2; 3062 3063 sep = parse_operand (&e1); 3064 if (sep != ',') 3065 as_bad ("No second operand to .save"); 3066 sep = parse_operand (&e2); 3067 3068 reg1 = e1.X_add_number; 3069 reg2 = e2.X_add_number - REG_GR; 3070 3071 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3072 if (e1.X_op == O_register) 3073 { 3074 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) 3075 { 3076 switch (reg1) 3077 { 3078 case REG_AR + AR_BSP: 3079 add_unwind_entry (output_bsp_when ()); 3080 add_unwind_entry (output_bsp_gr (reg2)); 3081 break; 3082 case REG_AR + AR_BSPSTORE: 3083 add_unwind_entry (output_bspstore_when ()); 3084 add_unwind_entry (output_bspstore_gr (reg2)); 3085 break; 3086 case REG_AR + AR_RNAT: 3087 add_unwind_entry (output_rnat_when ()); 3088 add_unwind_entry (output_rnat_gr (reg2)); 3089 break; 3090 case REG_AR + AR_UNAT: 3091 add_unwind_entry (output_unat_when ()); 3092 add_unwind_entry (output_unat_gr (reg2)); 3093 break; 3094 case REG_AR + AR_FPSR: 3095 add_unwind_entry (output_fpsr_when ()); 3096 add_unwind_entry (output_fpsr_gr (reg2)); 3097 break; 3098 case REG_AR + AR_PFS: 3099 add_unwind_entry (output_pfs_when ()); 3100 if (! (unwind.prologue_mask & 4)) 3101 add_unwind_entry (output_pfs_gr (reg2)); 3102 break; 3103 case REG_AR + AR_LC: 3104 add_unwind_entry (output_lc_when ()); 3105 add_unwind_entry (output_lc_gr (reg2)); 3106 break; 3107 case REG_BR: 3108 add_unwind_entry (output_rp_when ()); 3109 if (! (unwind.prologue_mask & 8)) 3110 add_unwind_entry (output_rp_gr (reg2)); 3111 break; 3112 case REG_PR: 3113 add_unwind_entry (output_preds_when ()); 3114 if (! (unwind.prologue_mask & 1)) 3115 add_unwind_entry (output_preds_gr (reg2)); 3116 break; 3117 case REG_PRIUNAT: 3118 add_unwind_entry (output_priunat_when_gr ()); 3119 add_unwind_entry (output_priunat_gr (reg2)); 3120 break; 3121 default: 3122 as_bad ("First operand not a valid register"); 3123 } 3124 } 3125 else 3126 as_bad (" Second operand not a valid register"); 3127 } 3128 else 3129 as_bad ("First operand not a register"); 3130} 3131 3132static void 3133dot_restore (dummy) 3134 int dummy ATTRIBUTE_UNUSED; 3135{ 3136 expressionS e1, e2; 3137 unsigned long ecount; /* # of _additional_ regions to pop */ 3138 int sep; 3139 3140 sep = parse_operand (&e1); 3141 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) 3142 { 3143 as_bad ("First operand to .restore must be stack pointer (sp)"); 3144 return; 3145 } 3146 3147 if (sep == ',') 3148 { 3149 parse_operand (&e2); 3150 if (e2.X_op != O_constant || e2.X_add_number < 0) 3151 { 3152 as_bad ("Second operand to .restore must be a constant >= 0"); 3153 return; 3154 } 3155 ecount = e2.X_add_number; 3156 } 3157 else 3158 ecount = unwind.prologue_count - 1; 3159 add_unwind_entry (output_epilogue (ecount)); 3160 3161 if (ecount < unwind.prologue_count) 3162 unwind.prologue_count -= ecount + 1; 3163 else 3164 unwind.prologue_count = 0; 3165} 3166 3167static void 3168dot_restorereg (dummy) 3169 int dummy ATTRIBUTE_UNUSED; 3170{ 3171 unsigned int ab, reg; 3172 expressionS e; 3173 3174 parse_operand (&e); 3175 3176 if (!convert_expr_to_ab_reg (&e, &ab, ®)) 3177 { 3178 as_bad ("First operand to .restorereg must be a preserved register"); 3179 return; 3180 } 3181 add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); 3182} 3183 3184static void 3185dot_restorereg_p (dummy) 3186 int dummy ATTRIBUTE_UNUSED; 3187{ 3188 unsigned int qp, ab, reg; 3189 expressionS e1, e2; 3190 int sep; 3191 3192 sep = parse_operand (&e1); 3193 if (sep != ',') 3194 { 3195 as_bad ("No second operand to .restorereg.p"); 3196 return; 3197 } 3198 3199 parse_operand (&e2); 3200 3201 qp = e1.X_add_number - REG_P; 3202 if (e1.X_op != O_register || qp > 63) 3203 { 3204 as_bad ("First operand to .restorereg.p must be a predicate"); 3205 return; 3206 } 3207 3208 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3209 { 3210 as_bad ("Second operand to .restorereg.p must be a preserved register"); 3211 return; 3212 } 3213 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); 3214} 3215 3216static int 3217generate_unwind_image (text_name) 3218 const char *text_name; 3219{ 3220 int size; 3221 unsigned char *unw_rec; 3222 3223 /* Force out pending instructions, to make sure all unwind records have 3224 a valid slot_number field. */ 3225 ia64_flush_insns (); 3226 3227 /* Generate the unwind record. */ 3228 size = output_unw_records (unwind.list, (void **) &unw_rec); 3229 if (size % md.pointer_size != 0) 3230 as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size); 3231 3232 /* If there are unwind records, switch sections, and output the info. */ 3233 if (size != 0) 3234 { 3235 unsigned char *where; 3236 char *sec_name; 3237 expressionS exp; 3238 bfd_reloc_code_real_type reloc; 3239 3240 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); 3241 set_section (sec_name); 3242 bfd_set_section_flags (stdoutput, now_seg, 3243 SEC_LOAD | SEC_ALLOC | SEC_READONLY); 3244 3245 /* Make sure the section has 4 byte alignment for ILP32 and 3246 8 byte alignment for LP64. */ 3247 frag_align (md.pointer_size_shift, 0, 0); 3248 record_alignment (now_seg, md.pointer_size_shift); 3249 3250 /* Set expression which points to start of unwind descriptor area. */ 3251 unwind.info = expr_build_dot (); 3252 3253 where = (unsigned char *) frag_more (size); 3254 3255 /* Issue a label for this address, and keep track of it to put it 3256 in the unwind section. */ 3257 3258 /* Copy the information from the unwind record into this section. The 3259 data is already in the correct byte order. */ 3260 memcpy (where, unw_rec, size); 3261 3262 /* Add the personality address to the image. */ 3263 if (unwind.personality_routine != 0) 3264 { 3265 exp.X_op = O_symbol; 3266 exp.X_add_symbol = unwind.personality_routine; 3267 exp.X_add_number = 0; 3268 3269 if (md.flags & EF_IA_64_BE) 3270 { 3271 if (md.flags & EF_IA_64_ABI64) 3272 reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB; 3273 else 3274 reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB; 3275 } 3276 else 3277 { 3278 if (md.flags & EF_IA_64_ABI64) 3279 reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB; 3280 else 3281 reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB; 3282 } 3283 3284 fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, 3285 md.pointer_size, & exp, 0, reloc); 3286 unwind.personality_routine = 0; 3287 } 3288 } 3289 3290 free_list_records (unwind.list); 3291 unwind.list = unwind.tail = unwind.current_entry = NULL; 3292 3293 return size; 3294} 3295 3296static void 3297dot_handlerdata (dummy) 3298 int dummy ATTRIBUTE_UNUSED; 3299{ 3300 const char *text_name = segment_name (now_seg); 3301 3302 /* If text section name starts with ".text" (which it should), 3303 strip this prefix off. */ 3304 if (strcmp (text_name, ".text") == 0) 3305 text_name = ""; 3306 3307 unwind.force_unwind_entry = 1; 3308 3309 /* Remember which segment we're in so we can switch back after .endp */ 3310 unwind.saved_text_seg = now_seg; 3311 unwind.saved_text_subseg = now_subseg; 3312 3313 /* Generate unwind info into unwind-info section and then leave that 3314 section as the currently active one so dataXX directives go into 3315 the language specific data area of the unwind info block. */ 3316 generate_unwind_image (text_name); 3317 demand_empty_rest_of_line (); 3318} 3319 3320static void 3321dot_unwentry (dummy) 3322 int dummy ATTRIBUTE_UNUSED; 3323{ 3324 unwind.force_unwind_entry = 1; 3325 demand_empty_rest_of_line (); 3326} 3327 3328static void 3329dot_altrp (dummy) 3330 int dummy ATTRIBUTE_UNUSED; 3331{ 3332 expressionS e; 3333 unsigned reg; 3334 3335 parse_operand (&e); 3336 reg = e.X_add_number - REG_BR; 3337 if (e.X_op == O_register && reg < 8) 3338 add_unwind_entry (output_rp_br (reg)); 3339 else 3340 as_bad ("First operand not a valid branch register"); 3341} 3342 3343static void 3344dot_savemem (psprel) 3345 int psprel; 3346{ 3347 expressionS e1, e2; 3348 int sep; 3349 int reg1, val; 3350 3351 sep = parse_operand (&e1); 3352 if (sep != ',') 3353 as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); 3354 sep = parse_operand (&e2); 3355 3356 reg1 = e1.X_add_number; 3357 val = e2.X_add_number; 3358 3359 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3360 if (e1.X_op == O_register) 3361 { 3362 if (e2.X_op == O_constant) 3363 { 3364 switch (reg1) 3365 { 3366 case REG_AR + AR_BSP: 3367 add_unwind_entry (output_bsp_when ()); 3368 add_unwind_entry ((psprel 3369 ? output_bsp_psprel 3370 : output_bsp_sprel) (val)); 3371 break; 3372 case REG_AR + AR_BSPSTORE: 3373 add_unwind_entry (output_bspstore_when ()); 3374 add_unwind_entry ((psprel 3375 ? output_bspstore_psprel 3376 : output_bspstore_sprel) (val)); 3377 break; 3378 case REG_AR + AR_RNAT: 3379 add_unwind_entry (output_rnat_when ()); 3380 add_unwind_entry ((psprel 3381 ? output_rnat_psprel 3382 : output_rnat_sprel) (val)); 3383 break; 3384 case REG_AR + AR_UNAT: 3385 add_unwind_entry (output_unat_when ()); 3386 add_unwind_entry ((psprel 3387 ? output_unat_psprel 3388 : output_unat_sprel) (val)); 3389 break; 3390 case REG_AR + AR_FPSR: 3391 add_unwind_entry (output_fpsr_when ()); 3392 add_unwind_entry ((psprel 3393 ? output_fpsr_psprel 3394 : output_fpsr_sprel) (val)); 3395 break; 3396 case REG_AR + AR_PFS: 3397 add_unwind_entry (output_pfs_when ()); 3398 add_unwind_entry ((psprel 3399 ? output_pfs_psprel 3400 : output_pfs_sprel) (val)); 3401 break; 3402 case REG_AR + AR_LC: 3403 add_unwind_entry (output_lc_when ()); 3404 add_unwind_entry ((psprel 3405 ? output_lc_psprel 3406 : output_lc_sprel) (val)); 3407 break; 3408 case REG_BR: 3409 add_unwind_entry (output_rp_when ()); 3410 add_unwind_entry ((psprel 3411 ? output_rp_psprel 3412 : output_rp_sprel) (val)); 3413 break; 3414 case REG_PR: 3415 add_unwind_entry (output_preds_when ()); 3416 add_unwind_entry ((psprel 3417 ? output_preds_psprel 3418 : output_preds_sprel) (val)); 3419 break; 3420 case REG_PRIUNAT: 3421 add_unwind_entry (output_priunat_when_mem ()); 3422 add_unwind_entry ((psprel 3423 ? output_priunat_psprel 3424 : output_priunat_sprel) (val)); 3425 break; 3426 default: 3427 as_bad ("First operand not a valid register"); 3428 } 3429 } 3430 else 3431 as_bad (" Second operand not a valid constant"); 3432 } 3433 else 3434 as_bad ("First operand not a register"); 3435} 3436 3437static void 3438dot_saveg (dummy) 3439 int dummy ATTRIBUTE_UNUSED; 3440{ 3441 expressionS e1, e2; 3442 int sep; 3443 sep = parse_operand (&e1); 3444 if (sep == ',') 3445 parse_operand (&e2); 3446 3447 if (e1.X_op != O_constant) 3448 as_bad ("First operand to .save.g must be a constant."); 3449 else 3450 { 3451 int grmask = e1.X_add_number; 3452 if (sep != ',') 3453 add_unwind_entry (output_gr_mem (grmask)); 3454 else 3455 { 3456 int reg = e2.X_add_number - REG_GR; 3457 if (e2.X_op == O_register && reg >= 0 && reg < 128) 3458 add_unwind_entry (output_gr_gr (grmask, reg)); 3459 else 3460 as_bad ("Second operand is an invalid register."); 3461 } 3462 } 3463} 3464 3465static void 3466dot_savef (dummy) 3467 int dummy ATTRIBUTE_UNUSED; 3468{ 3469 expressionS e1; 3470 int sep; 3471 sep = parse_operand (&e1); 3472 3473 if (e1.X_op != O_constant) 3474 as_bad ("Operand to .save.f must be a constant."); 3475 else 3476 add_unwind_entry (output_fr_mem (e1.X_add_number)); 3477} 3478 3479static void 3480dot_saveb (dummy) 3481 int dummy ATTRIBUTE_UNUSED; 3482{ 3483 expressionS e1, e2; 3484 unsigned int reg; 3485 unsigned char sep; 3486 int brmask; 3487 3488 sep = parse_operand (&e1); 3489 if (e1.X_op != O_constant) 3490 { 3491 as_bad ("First operand to .save.b must be a constant."); 3492 return; 3493 } 3494 brmask = e1.X_add_number; 3495 3496 if (sep == ',') 3497 { 3498 sep = parse_operand (&e2); 3499 reg = e2.X_add_number - REG_GR; 3500 if (e2.X_op != O_register || reg > 127) 3501 { 3502 as_bad ("Second operand to .save.b must be a general register."); 3503 return; 3504 } 3505 add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); 3506 } 3507 else 3508 add_unwind_entry (output_br_mem (brmask)); 3509 3510 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3511 ignore_rest_of_line (); 3512} 3513 3514static void 3515dot_savegf (dummy) 3516 int dummy ATTRIBUTE_UNUSED; 3517{ 3518 expressionS e1, e2; 3519 int sep; 3520 sep = parse_operand (&e1); 3521 if (sep == ',') 3522 parse_operand (&e2); 3523 3524 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) 3525 as_bad ("Both operands of .save.gf must be constants."); 3526 else 3527 { 3528 int grmask = e1.X_add_number; 3529 int frmask = e2.X_add_number; 3530 add_unwind_entry (output_frgr_mem (grmask, frmask)); 3531 } 3532} 3533 3534static void 3535dot_spill (dummy) 3536 int dummy ATTRIBUTE_UNUSED; 3537{ 3538 expressionS e; 3539 unsigned char sep; 3540 3541 sep = parse_operand (&e); 3542 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3543 ignore_rest_of_line (); 3544 3545 if (e.X_op != O_constant) 3546 as_bad ("Operand to .spill must be a constant"); 3547 else 3548 add_unwind_entry (output_spill_base (e.X_add_number)); 3549} 3550 3551static void 3552dot_spillreg (dummy) 3553 int dummy ATTRIBUTE_UNUSED; 3554{ 3555 int sep, ab, xy, reg, treg; 3556 expressionS e1, e2; 3557 3558 sep = parse_operand (&e1); 3559 if (sep != ',') 3560 { 3561 as_bad ("No second operand to .spillreg"); 3562 return; 3563 } 3564 3565 parse_operand (&e2); 3566 3567 if (!convert_expr_to_ab_reg (&e1, &ab, ®)) 3568 { 3569 as_bad ("First operand to .spillreg must be a preserved register"); 3570 return; 3571 } 3572 3573 if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) 3574 { 3575 as_bad ("Second operand to .spillreg must be a register"); 3576 return; 3577 } 3578 3579 add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); 3580} 3581 3582static void 3583dot_spillmem (psprel) 3584 int psprel; 3585{ 3586 expressionS e1, e2; 3587 int sep, ab, reg; 3588 3589 sep = parse_operand (&e1); 3590 if (sep != ',') 3591 { 3592 as_bad ("Second operand missing"); 3593 return; 3594 } 3595 3596 parse_operand (&e2); 3597 3598 if (!convert_expr_to_ab_reg (&e1, &ab, ®)) 3599 { 3600 as_bad ("First operand to .spill%s must be a preserved register", 3601 psprel ? "psp" : "sp"); 3602 return; 3603 } 3604 3605 if (e2.X_op != O_constant) 3606 { 3607 as_bad ("Second operand to .spill%s must be a constant", 3608 psprel ? "psp" : "sp"); 3609 return; 3610 } 3611 3612 if (psprel) 3613 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); 3614 else 3615 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); 3616} 3617 3618static void 3619dot_spillreg_p (dummy) 3620 int dummy ATTRIBUTE_UNUSED; 3621{ 3622 int sep, ab, xy, reg, treg; 3623 expressionS e1, e2, e3; 3624 unsigned int qp; 3625 3626 sep = parse_operand (&e1); 3627 if (sep != ',') 3628 { 3629 as_bad ("No second and third operand to .spillreg.p"); 3630 return; 3631 } 3632 3633 sep = parse_operand (&e2); 3634 if (sep != ',') 3635 { 3636 as_bad ("No third operand to .spillreg.p"); 3637 return; 3638 } 3639 3640 parse_operand (&e3); 3641 3642 qp = e1.X_add_number - REG_P; 3643 3644 if (e1.X_op != O_register || qp > 63) 3645 { 3646 as_bad ("First operand to .spillreg.p must be a predicate"); 3647 return; 3648 } 3649 3650 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3651 { 3652 as_bad ("Second operand to .spillreg.p must be a preserved register"); 3653 return; 3654 } 3655 3656 if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) 3657 { 3658 as_bad ("Third operand to .spillreg.p must be a register"); 3659 return; 3660 } 3661 3662 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); 3663} 3664 3665static void 3666dot_spillmem_p (psprel) 3667 int psprel; 3668{ 3669 expressionS e1, e2, e3; 3670 int sep, ab, reg; 3671 unsigned int qp; 3672 3673 sep = parse_operand (&e1); 3674 if (sep != ',') 3675 { 3676 as_bad ("Second operand missing"); 3677 return; 3678 } 3679 3680 parse_operand (&e2); 3681 if (sep != ',') 3682 { 3683 as_bad ("Second operand missing"); 3684 return; 3685 } 3686 3687 parse_operand (&e3); 3688 3689 qp = e1.X_add_number - REG_P; 3690 if (e1.X_op != O_register || qp > 63) 3691 { 3692 as_bad ("First operand to .spill%s_p must be a predicate", 3693 psprel ? "psp" : "sp"); 3694 return; 3695 } 3696 3697 if (!convert_expr_to_ab_reg (&e2, &ab, ®)) 3698 { 3699 as_bad ("Second operand to .spill%s_p must be a preserved register", 3700 psprel ? "psp" : "sp"); 3701 return; 3702 } 3703 3704 if (e3.X_op != O_constant) 3705 { 3706 as_bad ("Third operand to .spill%s_p must be a constant", 3707 psprel ? "psp" : "sp"); 3708 return; 3709 } 3710 3711 if (psprel) 3712 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp)); 3713 else 3714 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp)); 3715} 3716 3717static void 3718dot_label_state (dummy) 3719 int dummy ATTRIBUTE_UNUSED; 3720{ 3721 expressionS e; 3722 3723 parse_operand (&e); 3724 if (e.X_op != O_constant) 3725 { 3726 as_bad ("Operand to .label_state must be a constant"); 3727 return; 3728 } 3729 add_unwind_entry (output_label_state (e.X_add_number)); 3730} 3731 3732static void 3733dot_copy_state (dummy) 3734 int dummy ATTRIBUTE_UNUSED; 3735{ 3736 expressionS e; 3737 3738 parse_operand (&e); 3739 if (e.X_op != O_constant) 3740 { 3741 as_bad ("Operand to .copy_state must be a constant"); 3742 return; 3743 } 3744 add_unwind_entry (output_copy_state (e.X_add_number)); 3745} 3746 3747static void 3748dot_unwabi (dummy) 3749 int dummy ATTRIBUTE_UNUSED; 3750{ 3751 expressionS e1, e2; 3752 unsigned char sep; 3753 3754 sep = parse_operand (&e1); 3755 if (sep != ',') 3756 { 3757 as_bad ("Second operand to .unwabi missing"); 3758 return; 3759 } 3760 sep = parse_operand (&e2); 3761 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3762 ignore_rest_of_line (); 3763 3764 if (e1.X_op != O_constant) 3765 { 3766 as_bad ("First operand to .unwabi must be a constant"); 3767 return; 3768 } 3769 3770 if (e2.X_op != O_constant) 3771 { 3772 as_bad ("Second operand to .unwabi must be a constant"); 3773 return; 3774 } 3775 3776 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); 3777} 3778 3779static void 3780dot_personality (dummy) 3781 int dummy ATTRIBUTE_UNUSED; 3782{ 3783 char *name, *p, c; 3784 SKIP_WHITESPACE (); 3785 name = input_line_pointer; 3786 c = get_symbol_end (); 3787 p = input_line_pointer; 3788 unwind.personality_routine = symbol_find_or_make (name); 3789 unwind.force_unwind_entry = 1; 3790 *p = c; 3791 SKIP_WHITESPACE (); 3792 demand_empty_rest_of_line (); 3793} 3794 3795static void 3796dot_proc (dummy) 3797 int dummy ATTRIBUTE_UNUSED; 3798{ 3799 char *name, *p, c; 3800 symbolS *sym; 3801 3802 unwind.proc_start = expr_build_dot (); 3803 /* Parse names of main and alternate entry points and mark them as 3804 function symbols: */ 3805 while (1) 3806 { 3807 SKIP_WHITESPACE (); 3808 name = input_line_pointer; 3809 c = get_symbol_end (); 3810 p = input_line_pointer; 3811 sym = symbol_find_or_make (name); 3812 if (unwind.proc_start == 0) 3813 { 3814 unwind.proc_start = sym; 3815 } 3816 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; 3817 *p = c; 3818 SKIP_WHITESPACE (); 3819 if (*input_line_pointer != ',') 3820 break; 3821 ++input_line_pointer; 3822 } 3823 demand_empty_rest_of_line (); 3824 ia64_do_align (16); 3825 3826 unwind.prologue_count = 0; 3827 unwind.list = unwind.tail = unwind.current_entry = NULL; 3828 unwind.personality_routine = 0; 3829} 3830 3831static void 3832dot_body (dummy) 3833 int dummy ATTRIBUTE_UNUSED; 3834{ 3835 unwind.prologue = 0; 3836 unwind.prologue_mask = 0; 3837 3838 add_unwind_entry (output_body ()); 3839 demand_empty_rest_of_line (); 3840} 3841 3842static void 3843dot_prologue (dummy) 3844 int dummy ATTRIBUTE_UNUSED; 3845{ 3846 unsigned char sep; 3847 int mask = 0, grsave = 0; 3848 3849 if (!is_it_end_of_statement ()) 3850 { 3851 expressionS e1, e2; 3852 sep = parse_operand (&e1); 3853 if (sep != ',') 3854 as_bad ("No second operand to .prologue"); 3855 sep = parse_operand (&e2); 3856 if (!is_end_of_line[sep] && !is_it_end_of_statement ()) 3857 ignore_rest_of_line (); 3858 3859 if (e1.X_op == O_constant) 3860 { 3861 mask = e1.X_add_number; 3862 3863 if (e2.X_op == O_constant) 3864 grsave = e2.X_add_number; 3865 else if (e2.X_op == O_register 3866 && (grsave = e2.X_add_number - REG_GR) < 128) 3867 ; 3868 else 3869 as_bad ("Second operand not a constant or general register"); 3870 3871 add_unwind_entry (output_prologue_gr (mask, grsave)); 3872 } 3873 else 3874 as_bad ("First operand not a constant"); 3875 } 3876 else 3877 add_unwind_entry (output_prologue ()); 3878 3879 unwind.prologue = 1; 3880 unwind.prologue_mask = mask; 3881 ++unwind.prologue_count; 3882} 3883 3884static void 3885dot_endp (dummy) 3886 int dummy ATTRIBUTE_UNUSED; 3887{ 3888 expressionS e; 3889 unsigned char *ptr; 3890 int bytes_per_address; 3891 long where; 3892 segT saved_seg; 3893 subsegT saved_subseg; 3894 const char *sec_name, *text_name; 3895 char *name, *p, c; 3896 symbolS *sym; 3897 3898 if (unwind.saved_text_seg) 3899 { 3900 saved_seg = unwind.saved_text_seg; 3901 saved_subseg = unwind.saved_text_subseg; 3902 unwind.saved_text_seg = NULL; 3903 } 3904 else 3905 { 3906 saved_seg = now_seg; 3907 saved_subseg = now_subseg; 3908 } 3909 3910 /* 3911 Use a slightly ugly scheme to derive the unwind section names from 3912 the text section name: 3913 3914 text sect. unwind table sect. 3915 name: name: comments: 3916 ---------- ----------------- -------------------------------- 3917 .text .IA_64.unwind 3918 .text.foo .IA_64.unwind.text.foo 3919 .foo .IA_64.unwind.foo 3920 .gnu.linkonce.t.foo 3921 .gnu.linkonce.ia64unw.foo 3922 _info .IA_64.unwind_info gas issues error message (ditto) 3923 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) 3924 3925 This mapping is done so that: 3926 3927 (a) An object file with unwind info only in .text will use 3928 unwind section names .IA_64.unwind and .IA_64.unwind_info. 3929 This follows the letter of the ABI and also ensures backwards 3930 compatibility with older toolchains. 3931 3932 (b) An object file with unwind info in multiple text sections 3933 will use separate unwind sections for each text section. 3934 This allows us to properly set the "sh_info" and "sh_link" 3935 fields in SHT_IA_64_UNWIND as required by the ABI and also 3936 lets GNU ld support programs with multiple segments 3937 containing unwind info (as might be the case for certain 3938 embedded applications). 3939 3940 (c) An error is issued if there would be a name clash. 3941 */ 3942 text_name = segment_name (saved_seg); 3943 if (strncmp (text_name, "_info", 5) == 0) 3944 { 3945 as_bad ("Illegal section name `%s' (causes unwind section name clash)", 3946 text_name); 3947 ignore_rest_of_line (); 3948 return; 3949 } 3950 if (strcmp (text_name, ".text") == 0) 3951 text_name = ""; 3952 3953 insn_group_break (1, 0, 0); 3954 3955 /* If there wasn't a .handlerdata, we haven't generated an image yet. */ 3956 if (!unwind.info) 3957 generate_unwind_image (text_name); 3958 3959 if (unwind.info || unwind.force_unwind_entry) 3960 { 3961 subseg_set (md.last_text_seg, 0); 3962 unwind.proc_end = expr_build_dot (); 3963 3964 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); 3965 set_section ((char *) sec_name); 3966 bfd_set_section_flags (stdoutput, now_seg, 3967 SEC_LOAD | SEC_ALLOC | SEC_READONLY); 3968 3969 /* Make sure that section has 4 byte alignment for ILP32 and 3970 8 byte alignment for LP64. */ 3971 record_alignment (now_seg, md.pointer_size_shift); 3972 3973 /* Need space for 3 pointers for procedure start, procedure end, 3974 and unwind info. */ 3975 ptr = frag_more (3 * md.pointer_size); 3976 where = frag_now_fix () - (3 * md.pointer_size); 3977 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; 3978 3979 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ 3980 e.X_op = O_pseudo_fixup; 3981 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 3982 e.X_add_number = 0; 3983 e.X_add_symbol = unwind.proc_start; 3984 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); 3985 3986 e.X_op = O_pseudo_fixup; 3987 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 3988 e.X_add_number = 0; 3989 e.X_add_symbol = unwind.proc_end; 3990 ia64_cons_fix_new (frag_now, where + bytes_per_address, 3991 bytes_per_address, &e); 3992 3993 if (unwind.info) 3994 { 3995 e.X_op = O_pseudo_fixup; 3996 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 3997 e.X_add_number = 0; 3998 e.X_add_symbol = unwind.info; 3999 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), 4000 bytes_per_address, &e); 4001 } 4002 else 4003 md_number_to_chars (ptr + (bytes_per_address * 2), 0, 4004 bytes_per_address); 4005 4006 } 4007 subseg_set (saved_seg, saved_subseg); 4008 4009 /* Parse names of main and alternate entry points and set symbol sizes. */ 4010 while (1) 4011 { 4012 SKIP_WHITESPACE (); 4013 name = input_line_pointer; 4014 c = get_symbol_end (); 4015 p = input_line_pointer; 4016 sym = symbol_find (name); 4017 if (sym && unwind.proc_start 4018 && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION) 4019 && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL) 4020 { 4021 fragS *fr = symbol_get_frag (unwind.proc_start); 4022 fragS *frag = symbol_get_frag (sym); 4023 4024 /* Check whether the function label is at or beyond last 4025 .proc directive. */ 4026 while (fr && fr != frag) 4027 fr = fr->fr_next; 4028 if (fr) 4029 { 4030 if (frag == frag_now && SEG_NORMAL (now_seg)) 4031 S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); 4032 else 4033 { 4034 symbol_get_obj (sym)->size = 4035 (expressionS *) xmalloc (sizeof (expressionS)); 4036 symbol_get_obj (sym)->size->X_op = O_subtract; 4037 symbol_get_obj (sym)->size->X_add_symbol 4038 = symbol_new (FAKE_LABEL_NAME, now_seg, 4039 frag_now_fix (), frag_now); 4040 symbol_get_obj (sym)->size->X_op_symbol = sym; 4041 symbol_get_obj (sym)->size->X_add_number = 0; 4042 } 4043 } 4044 } 4045 *p = c; 4046 SKIP_WHITESPACE (); 4047 if (*input_line_pointer != ',') 4048 break; 4049 ++input_line_pointer; 4050 } 4051 demand_empty_rest_of_line (); 4052 unwind.proc_start = unwind.proc_end = unwind.info = 0; 4053} 4054 4055static void 4056dot_template (template) 4057 int template; 4058{ 4059 CURR_SLOT.user_template = template; 4060} 4061 4062static void 4063dot_regstk (dummy) 4064 int dummy ATTRIBUTE_UNUSED; 4065{ 4066 int ins, locs, outs, rots; 4067 4068 if (is_it_end_of_statement ()) 4069 ins = locs = outs = rots = 0; 4070 else 4071 { 4072 ins = get_absolute_expression (); 4073 if (*input_line_pointer++ != ',') 4074 goto err; 4075 locs = get_absolute_expression (); 4076 if (*input_line_pointer++ != ',') 4077 goto err; 4078 outs = get_absolute_expression (); 4079 if (*input_line_pointer++ != ',') 4080 goto err; 4081 rots = get_absolute_expression (); 4082 } 4083 set_regstack (ins, locs, outs, rots); 4084 return; 4085 4086 err: 4087 as_bad ("Comma expected"); 4088 ignore_rest_of_line (); 4089} 4090 4091static void 4092dot_rot (type) 4093 int type; 4094{ 4095 unsigned num_regs, num_alloced = 0; 4096 struct dynreg **drpp, *dr; 4097 int ch, base_reg = 0; 4098 char *name, *start; 4099 size_t len; 4100 4101 switch (type) 4102 { 4103 case DYNREG_GR: base_reg = REG_GR + 32; break; 4104 case DYNREG_FR: base_reg = REG_FR + 32; break; 4105 case DYNREG_PR: base_reg = REG_P + 16; break; 4106 default: break; 4107 } 4108 4109 /* First, remove existing names from hash table. */ 4110 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) 4111 { 4112 hash_delete (md.dynreg_hash, dr->name); 4113 dr->num_regs = 0; 4114 } 4115 4116 drpp = &md.dynreg[type]; 4117 while (1) 4118 { 4119 start = input_line_pointer; 4120 ch = get_symbol_end (); 4121 *input_line_pointer = ch; 4122 len = (input_line_pointer - start); 4123 4124 SKIP_WHITESPACE (); 4125 if (*input_line_pointer != '[') 4126 { 4127 as_bad ("Expected '['"); 4128 goto err; 4129 } 4130 ++input_line_pointer; /* skip '[' */ 4131 4132 num_regs = get_absolute_expression (); 4133 4134 if (*input_line_pointer++ != ']') 4135 { 4136 as_bad ("Expected ']'"); 4137 goto err; 4138 } 4139 SKIP_WHITESPACE (); 4140 4141 num_alloced += num_regs; 4142 switch (type) 4143 { 4144 case DYNREG_GR: 4145 if (num_alloced > md.rot.num_regs) 4146 { 4147 as_bad ("Used more than the declared %d rotating registers", 4148 md.rot.num_regs); 4149 goto err; 4150 } 4151 break; 4152 case DYNREG_FR: 4153 if (num_alloced > 96) 4154 { 4155 as_bad ("Used more than the available 96 rotating registers"); 4156 goto err; 4157 } 4158 break; 4159 case DYNREG_PR: 4160 if (num_alloced > 48) 4161 { 4162 as_bad ("Used more than the available 48 rotating registers"); 4163 goto err; 4164 } 4165 break; 4166 4167 default: 4168 break; 4169 } 4170 4171 name = obstack_alloc (¬es, len + 1); 4172 memcpy (name, start, len); 4173 name[len] = '\0'; 4174 4175 if (!*drpp) 4176 { 4177 *drpp = obstack_alloc (¬es, sizeof (*dr)); 4178 memset (*drpp, 0, sizeof (*dr)); 4179 } 4180 4181 dr = *drpp; 4182 dr->name = name; 4183 dr->num_regs = num_regs; 4184 dr->base = base_reg; 4185 drpp = &dr->next; 4186 base_reg += num_regs; 4187 4188 if (hash_insert (md.dynreg_hash, name, dr)) 4189 { 4190 as_bad ("Attempt to redefine register set `%s'", name); 4191 goto err; 4192 } 4193 4194 if (*input_line_pointer != ',') 4195 break; 4196 ++input_line_pointer; /* skip comma */ 4197 SKIP_WHITESPACE (); 4198 } 4199 demand_empty_rest_of_line (); 4200 return; 4201 4202 err: 4203 ignore_rest_of_line (); 4204} 4205 4206static void 4207dot_byteorder (byteorder) 4208 int byteorder; 4209{ 4210 target_big_endian = byteorder; 4211} 4212 4213static void 4214dot_psr (dummy) 4215 int dummy ATTRIBUTE_UNUSED; 4216{ 4217 char *option; 4218 int ch; 4219 4220 while (1) 4221 { 4222 option = input_line_pointer; 4223 ch = get_symbol_end (); 4224 if (strcmp (option, "lsb") == 0) 4225 md.flags &= ~EF_IA_64_BE; 4226 else if (strcmp (option, "msb") == 0) 4227 md.flags |= EF_IA_64_BE; 4228 else if (strcmp (option, "abi32") == 0) 4229 md.flags &= ~EF_IA_64_ABI64; 4230 else if (strcmp (option, "abi64") == 0) 4231 md.flags |= EF_IA_64_ABI64; 4232 else 4233 as_bad ("Unknown psr option `%s'", option); 4234 *input_line_pointer = ch; 4235 4236 SKIP_WHITESPACE (); 4237 if (*input_line_pointer != ',') 4238 break; 4239 4240 ++input_line_pointer; 4241 SKIP_WHITESPACE (); 4242 } 4243 demand_empty_rest_of_line (); 4244} 4245 4246static void 4247dot_alias (dummy) 4248 int dummy ATTRIBUTE_UNUSED; 4249{ 4250 as_bad (".alias not implemented yet"); 4251} 4252 4253static void 4254dot_ln (dummy) 4255 int dummy ATTRIBUTE_UNUSED; 4256{ 4257 new_logical_line (0, get_absolute_expression ()); 4258 demand_empty_rest_of_line (); 4259} 4260 4261static char * 4262parse_section_name () 4263{ 4264 char *name; 4265 int len; 4266 4267 SKIP_WHITESPACE (); 4268 if (*input_line_pointer != '"') 4269 { 4270 as_bad ("Missing section name"); 4271 ignore_rest_of_line (); 4272 return 0; 4273 } 4274 name = demand_copy_C_string (&len); 4275 if (!name) 4276 { 4277 ignore_rest_of_line (); 4278 return 0; 4279 } 4280 SKIP_WHITESPACE (); 4281 if (*input_line_pointer != ',') 4282 { 4283 as_bad ("Comma expected after section name"); 4284 ignore_rest_of_line (); 4285 return 0; 4286 } 4287 ++input_line_pointer; /* skip comma */ 4288 return name; 4289} 4290 4291static void 4292dot_xdata (size) 4293 int size; 4294{ 4295 char *name = parse_section_name (); 4296 if (!name) 4297 return; 4298 4299 md.keep_pending_output = 1; 4300 set_section (name); 4301 cons (size); 4302 obj_elf_previous (0); 4303 md.keep_pending_output = 0; 4304} 4305 4306/* Why doesn't float_cons() call md_cons_align() the way cons() does? */ 4307 4308static void 4309stmt_float_cons (kind) 4310 int kind; 4311{ 4312 size_t size; 4313 4314 switch (kind) 4315 { 4316 case 'd': size = 8; break; 4317 case 'x': size = 10; break; 4318 4319 case 'f': 4320 default: 4321 size = 4; 4322 break; 4323 } 4324 ia64_do_align (size); 4325 float_cons (kind); 4326} 4327 4328static void 4329stmt_cons_ua (size) 4330 int size; 4331{ 4332 int saved_auto_align = md.auto_align; 4333 4334 md.auto_align = 0; 4335 cons (size); 4336 md.auto_align = saved_auto_align; 4337} 4338 4339static void 4340dot_xfloat_cons (kind) 4341 int kind; 4342{ 4343 char *name = parse_section_name (); 4344 if (!name) 4345 return; 4346 4347 md.keep_pending_output = 1; 4348 set_section (name); 4349 stmt_float_cons (kind); 4350 obj_elf_previous (0); 4351 md.keep_pending_output = 0; 4352} 4353 4354static void 4355dot_xstringer (zero) 4356 int zero; 4357{ 4358 char *name = parse_section_name (); 4359 if (!name) 4360 return; 4361 4362 md.keep_pending_output = 1; 4363 set_section (name); 4364 stringer (zero); 4365 obj_elf_previous (0); 4366 md.keep_pending_output = 0; 4367} 4368 4369static void 4370dot_xdata_ua (size) 4371 int size; 4372{ 4373 int saved_auto_align = md.auto_align; 4374 char *name = parse_section_name (); 4375 if (!name) 4376 return; 4377 4378 md.keep_pending_output = 1; 4379 set_section (name); 4380 md.auto_align = 0; 4381 cons (size); 4382 md.auto_align = saved_auto_align; 4383 obj_elf_previous (0); 4384 md.keep_pending_output = 0; 4385} 4386 4387static void 4388dot_xfloat_cons_ua (kind) 4389 int kind; 4390{ 4391 int saved_auto_align = md.auto_align; 4392 char *name = parse_section_name (); 4393 if (!name) 4394 return; 4395 4396 md.keep_pending_output = 1; 4397 set_section (name); 4398 md.auto_align = 0; 4399 stmt_float_cons (kind); 4400 md.auto_align = saved_auto_align; 4401 obj_elf_previous (0); 4402 md.keep_pending_output = 0; 4403} 4404 4405/* .reg.val <regname>,value */ 4406 4407static void 4408dot_reg_val (dummy) 4409 int dummy ATTRIBUTE_UNUSED; 4410{ 4411 expressionS reg; 4412 4413 expression (®); 4414 if (reg.X_op != O_register) 4415 { 4416 as_bad (_("Register name expected")); 4417 ignore_rest_of_line (); 4418 } 4419 else if (*input_line_pointer++ != ',') 4420 { 4421 as_bad (_("Comma expected")); 4422 ignore_rest_of_line (); 4423 } 4424 else 4425 { 4426 valueT value = get_absolute_expression (); 4427 int regno = reg.X_add_number; 4428 if (regno < REG_GR || regno > REG_GR + 128) 4429 as_warn (_("Register value annotation ignored")); 4430 else 4431 { 4432 gr_values[regno - REG_GR].known = 1; 4433 gr_values[regno - REG_GR].value = value; 4434 gr_values[regno - REG_GR].path = md.path; 4435 } 4436 } 4437 demand_empty_rest_of_line (); 4438} 4439 4440/* select dv checking mode 4441 .auto 4442 .explicit 4443 .default 4444 4445 A stop is inserted when changing modes 4446 */ 4447 4448static void 4449dot_dv_mode (type) 4450 int type; 4451{ 4452 if (md.manual_bundling) 4453 as_warn (_("Directive invalid within a bundle")); 4454 4455 if (type == 'E' || type == 'A') 4456 md.mode_explicitly_set = 0; 4457 else 4458 md.mode_explicitly_set = 1; 4459 4460 md.detect_dv = 1; 4461 switch (type) 4462 { 4463 case 'A': 4464 case 'a': 4465 if (md.explicit_mode) 4466 insn_group_break (1, 0, 0); 4467 md.explicit_mode = 0; 4468 break; 4469 case 'E': 4470 case 'e': 4471 if (!md.explicit_mode) 4472 insn_group_break (1, 0, 0); 4473 md.explicit_mode = 1; 4474 break; 4475 default: 4476 case 'd': 4477 if (md.explicit_mode != md.default_explicit_mode) 4478 insn_group_break (1, 0, 0); 4479 md.explicit_mode = md.default_explicit_mode; 4480 md.mode_explicitly_set = 0; 4481 break; 4482 } 4483} 4484 4485static void 4486print_prmask (mask) 4487 valueT mask; 4488{ 4489 int regno; 4490 char *comma = ""; 4491 for (regno = 0; regno < 64; regno++) 4492 { 4493 if (mask & ((valueT) 1 << regno)) 4494 { 4495 fprintf (stderr, "%s p%d", comma, regno); 4496 comma = ","; 4497 } 4498 } 4499} 4500 4501/* 4502 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") 4503 .pred.rel.imply p1, p2 (also .pred.rel "imply") 4504 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") 4505 .pred.safe_across_calls p1 [, p2 [,...]] 4506 */ 4507 4508static void 4509dot_pred_rel (type) 4510 int type; 4511{ 4512 valueT mask = 0; 4513 int count = 0; 4514 int p1 = -1, p2 = -1; 4515 4516 if (type == 0) 4517 { 4518 if (*input_line_pointer != '"') 4519 { 4520 as_bad (_("Missing predicate relation type")); 4521 ignore_rest_of_line (); 4522 return; 4523 } 4524 else 4525 { 4526 int len; 4527 char *form = demand_copy_C_string (&len); 4528 if (strcmp (form, "mutex") == 0) 4529 type = 'm'; 4530 else if (strcmp (form, "clear") == 0) 4531 type = 'c'; 4532 else if (strcmp (form, "imply") == 0) 4533 type = 'i'; 4534 else 4535 { 4536 as_bad (_("Unrecognized predicate relation type")); 4537 ignore_rest_of_line (); 4538 return; 4539 } 4540 } 4541 if (*input_line_pointer == ',') 4542 ++input_line_pointer; 4543 SKIP_WHITESPACE (); 4544 } 4545 4546 SKIP_WHITESPACE (); 4547 while (1) 4548 { 4549 valueT bit = 1; 4550 int regno; 4551 4552 if (TOUPPER (*input_line_pointer) != 'P' 4553 || (regno = atoi (++input_line_pointer)) < 0 4554 || regno > 63) 4555 { 4556 as_bad (_("Predicate register expected")); 4557 ignore_rest_of_line (); 4558 return; 4559 } 4560 while (ISDIGIT (*input_line_pointer)) 4561 ++input_line_pointer; 4562 if (p1 == -1) 4563 p1 = regno; 4564 else if (p2 == -1) 4565 p2 = regno; 4566 bit <<= regno; 4567 if (mask & bit) 4568 as_warn (_("Duplicate predicate register ignored")); 4569 mask |= bit; 4570 count++; 4571 /* See if it's a range. */ 4572 if (*input_line_pointer == '-') 4573 { 4574 valueT stop = 1; 4575 ++input_line_pointer; 4576 4577 if (TOUPPER (*input_line_pointer) != 'P' 4578 || (regno = atoi (++input_line_pointer)) < 0 4579 || regno > 63) 4580 { 4581 as_bad (_("Predicate register expected")); 4582 ignore_rest_of_line (); 4583 return; 4584 } 4585 while (ISDIGIT (*input_line_pointer)) 4586 ++input_line_pointer; 4587 stop <<= regno; 4588 if (bit >= stop) 4589 { 4590 as_bad (_("Bad register range")); 4591 ignore_rest_of_line (); 4592 return; 4593 } 4594 while (bit < stop) 4595 { 4596 bit <<= 1; 4597 mask |= bit; 4598 count++; 4599 } 4600 SKIP_WHITESPACE (); 4601 } 4602 if (*input_line_pointer != ',') 4603 break; 4604 ++input_line_pointer; 4605 SKIP_WHITESPACE (); 4606 } 4607 4608 switch (type) 4609 { 4610 case 'c': 4611 if (count == 0) 4612 mask = ~(valueT) 0; 4613 clear_qp_mutex (mask); 4614 clear_qp_implies (mask, (valueT) 0); 4615 break; 4616 case 'i': 4617 if (count != 2 || p1 == -1 || p2 == -1) 4618 as_bad (_("Predicate source and target required")); 4619 else if (p1 == 0 || p2 == 0) 4620 as_bad (_("Use of p0 is not valid in this context")); 4621 else 4622 add_qp_imply (p1, p2); 4623 break; 4624 case 'm': 4625 if (count < 2) 4626 { 4627 as_bad (_("At least two PR arguments expected")); 4628 break; 4629 } 4630 else if (mask & 1) 4631 { 4632 as_bad (_("Use of p0 is not valid in this context")); 4633 break; 4634 } 4635 add_qp_mutex (mask); 4636 break; 4637 case 's': 4638 /* note that we don't override any existing relations */ 4639 if (count == 0) 4640 { 4641 as_bad (_("At least one PR argument expected")); 4642 break; 4643 } 4644 if (md.debug_dv) 4645 { 4646 fprintf (stderr, "Safe across calls: "); 4647 print_prmask (mask); 4648 fprintf (stderr, "\n"); 4649 } 4650 qp_safe_across_calls = mask; 4651 break; 4652 } 4653 demand_empty_rest_of_line (); 4654} 4655 4656/* .entry label [, label [, ...]] 4657 Hint to DV code that the given labels are to be considered entry points. 4658 Otherwise, only global labels are considered entry points. */ 4659 4660static void 4661dot_entry (dummy) 4662 int dummy ATTRIBUTE_UNUSED; 4663{ 4664 const char *err; 4665 char *name; 4666 int c; 4667 symbolS *symbolP; 4668 4669 do 4670 { 4671 name = input_line_pointer; 4672 c = get_symbol_end (); 4673 symbolP = symbol_find_or_make (name); 4674 4675 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); 4676 if (err) 4677 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), 4678 name, err); 4679 4680 *input_line_pointer = c; 4681 SKIP_WHITESPACE (); 4682 c = *input_line_pointer; 4683 if (c == ',') 4684 { 4685 input_line_pointer++; 4686 SKIP_WHITESPACE (); 4687 if (*input_line_pointer == '\n') 4688 c = '\n'; 4689 } 4690 } 4691 while (c == ','); 4692 4693 demand_empty_rest_of_line (); 4694} 4695 4696/* .mem.offset offset, base 4697 "base" is used to distinguish between offsets from a different base. */ 4698 4699static void 4700dot_mem_offset (dummy) 4701 int dummy ATTRIBUTE_UNUSED; 4702{ 4703 md.mem_offset.hint = 1; 4704 md.mem_offset.offset = get_absolute_expression (); 4705 if (*input_line_pointer != ',') 4706 { 4707 as_bad (_("Comma expected")); 4708 ignore_rest_of_line (); 4709 return; 4710 } 4711 ++input_line_pointer; 4712 md.mem_offset.base = get_absolute_expression (); 4713 demand_empty_rest_of_line (); 4714} 4715 4716/* ia64-specific pseudo-ops: */ 4717const pseudo_typeS md_pseudo_table[] = 4718 { 4719 { "radix", dot_radix, 0 }, 4720 { "lcomm", s_lcomm_bytes, 1 }, 4721 { "bss", dot_special_section, SPECIAL_SECTION_BSS }, 4722 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, 4723 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, 4724 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, 4725 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, 4726 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, 4727 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, 4728 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, 4729 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, 4730 { "proc", dot_proc, 0 }, 4731 { "body", dot_body, 0 }, 4732 { "prologue", dot_prologue, 0 }, 4733 { "endp", dot_endp, 0 }, 4734 { "file", dwarf2_directive_file, 0 }, 4735 { "loc", dwarf2_directive_loc, 0 }, 4736 4737 { "fframe", dot_fframe, 0 }, 4738 { "vframe", dot_vframe, 0 }, 4739 { "vframesp", dot_vframesp, 0 }, 4740 { "vframepsp", dot_vframepsp, 0 }, 4741 { "save", dot_save, 0 }, 4742 { "restore", dot_restore, 0 }, 4743 { "restorereg", dot_restorereg, 0 }, 4744 { "restorereg.p", dot_restorereg_p, 0 }, 4745 { "handlerdata", dot_handlerdata, 0 }, 4746 { "unwentry", dot_unwentry, 0 }, 4747 { "altrp", dot_altrp, 0 }, 4748 { "savesp", dot_savemem, 0 }, 4749 { "savepsp", dot_savemem, 1 }, 4750 { "save.g", dot_saveg, 0 }, 4751 { "save.f", dot_savef, 0 }, 4752 { "save.b", dot_saveb, 0 }, 4753 { "save.gf", dot_savegf, 0 }, 4754 { "spill", dot_spill, 0 }, 4755 { "spillreg", dot_spillreg, 0 }, 4756 { "spillsp", dot_spillmem, 0 }, 4757 { "spillpsp", dot_spillmem, 1 }, 4758 { "spillreg.p", dot_spillreg_p, 0 }, 4759 { "spillsp.p", dot_spillmem_p, 0 }, 4760 { "spillpsp.p", dot_spillmem_p, 1 }, 4761 { "label_state", dot_label_state, 0 }, 4762 { "copy_state", dot_copy_state, 0 }, 4763 { "unwabi", dot_unwabi, 0 }, 4764 { "personality", dot_personality, 0 }, 4765#if 0 4766 { "estate", dot_estate, 0 }, 4767#endif 4768 { "mii", dot_template, 0x0 }, 4769 { "mli", dot_template, 0x2 }, /* old format, for compatibility */ 4770 { "mlx", dot_template, 0x2 }, 4771 { "mmi", dot_template, 0x4 }, 4772 { "mfi", dot_template, 0x6 }, 4773 { "mmf", dot_template, 0x7 }, 4774 { "mib", dot_template, 0x8 }, 4775 { "mbb", dot_template, 0x9 }, 4776 { "bbb", dot_template, 0xb }, 4777 { "mmb", dot_template, 0xc }, 4778 { "mfb", dot_template, 0xe }, 4779#if 0 4780 { "lb", dot_scope, 0 }, 4781 { "le", dot_scope, 1 }, 4782#endif 4783 { "align", s_align_bytes, 0 }, 4784 { "regstk", dot_regstk, 0 }, 4785 { "rotr", dot_rot, DYNREG_GR }, 4786 { "rotf", dot_rot, DYNREG_FR }, 4787 { "rotp", dot_rot, DYNREG_PR }, 4788 { "lsb", dot_byteorder, 0 }, 4789 { "msb", dot_byteorder, 1 }, 4790 { "psr", dot_psr, 0 }, 4791 { "alias", dot_alias, 0 }, 4792 { "ln", dot_ln, 0 }, /* source line info (for debugging) */ 4793 4794 { "xdata1", dot_xdata, 1 }, 4795 { "xdata2", dot_xdata, 2 }, 4796 { "xdata4", dot_xdata, 4 }, 4797 { "xdata8", dot_xdata, 8 }, 4798 { "xreal4", dot_xfloat_cons, 'f' }, 4799 { "xreal8", dot_xfloat_cons, 'd' }, 4800 { "xreal10", dot_xfloat_cons, 'x' }, 4801 { "xstring", dot_xstringer, 0 }, 4802 { "xstringz", dot_xstringer, 1 }, 4803 4804 /* unaligned versions: */ 4805 { "xdata2.ua", dot_xdata_ua, 2 }, 4806 { "xdata4.ua", dot_xdata_ua, 4 }, 4807 { "xdata8.ua", dot_xdata_ua, 8 }, 4808 { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, 4809 { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, 4810 { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, 4811 4812 /* annotations/DV checking support */ 4813 { "entry", dot_entry, 0 }, 4814 { "mem.offset", dot_mem_offset, 0 }, 4815 { "pred.rel", dot_pred_rel, 0 }, 4816 { "pred.rel.clear", dot_pred_rel, 'c' }, 4817 { "pred.rel.imply", dot_pred_rel, 'i' }, 4818 { "pred.rel.mutex", dot_pred_rel, 'm' }, 4819 { "pred.safe_across_calls", dot_pred_rel, 's' }, 4820 { "reg.val", dot_reg_val, 0 }, 4821 { "auto", dot_dv_mode, 'a' }, 4822 { "explicit", dot_dv_mode, 'e' }, 4823 { "default", dot_dv_mode, 'd' }, 4824 4825 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. 4826 IA-64 aligns data allocation pseudo-ops by default, so we have to 4827 tell it that these ones are supposed to be unaligned. Long term, 4828 should rewrite so that only IA-64 specific data allocation pseudo-ops 4829 are aligned by default. */ 4830 {"2byte", stmt_cons_ua, 2}, 4831 {"4byte", stmt_cons_ua, 4}, 4832 {"8byte", stmt_cons_ua, 8}, 4833 4834 { NULL, 0, 0 } 4835 }; 4836 4837static const struct pseudo_opcode 4838 { 4839 const char *name; 4840 void (*handler) (int); 4841 int arg; 4842 } 4843pseudo_opcode[] = 4844 { 4845 /* these are more like pseudo-ops, but don't start with a dot */ 4846 { "data1", cons, 1 }, 4847 { "data2", cons, 2 }, 4848 { "data4", cons, 4 }, 4849 { "data8", cons, 8 }, 4850 { "data16", cons, 16 }, 4851 { "real4", stmt_float_cons, 'f' }, 4852 { "real8", stmt_float_cons, 'd' }, 4853 { "real10", stmt_float_cons, 'x' }, 4854 { "string", stringer, 0 }, 4855 { "stringz", stringer, 1 }, 4856 4857 /* unaligned versions: */ 4858 { "data2.ua", stmt_cons_ua, 2 }, 4859 { "data4.ua", stmt_cons_ua, 4 }, 4860 { "data8.ua", stmt_cons_ua, 8 }, 4861 { "data16.ua", stmt_cons_ua, 16 }, 4862 { "real4.ua", float_cons, 'f' }, 4863 { "real8.ua", float_cons, 'd' }, 4864 { "real10.ua", float_cons, 'x' }, 4865 }; 4866 4867/* Declare a register by creating a symbol for it and entering it in 4868 the symbol table. */ 4869 4870static symbolS * 4871declare_register (name, regnum) 4872 const char *name; 4873 int regnum; 4874{ 4875 const char *err; 4876 symbolS *sym; 4877 4878 sym = symbol_new (name, reg_section, regnum, &zero_address_frag); 4879 4880 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); 4881 if (err) 4882 as_fatal ("Inserting \"%s\" into register table failed: %s", 4883 name, err); 4884 4885 return sym; 4886} 4887 4888static void 4889declare_register_set (prefix, num_regs, base_regnum) 4890 const char *prefix; 4891 int num_regs; 4892 int base_regnum; 4893{ 4894 char name[8]; 4895 int i; 4896 4897 for (i = 0; i < num_regs; ++i) 4898 { 4899 sprintf (name, "%s%u", prefix, i); 4900 declare_register (name, base_regnum + i); 4901 } 4902} 4903 4904static unsigned int 4905operand_width (opnd) 4906 enum ia64_opnd opnd; 4907{ 4908 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; 4909 unsigned int bits = 0; 4910 int i; 4911 4912 bits = 0; 4913 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) 4914 bits += odesc->field[i].bits; 4915 4916 return bits; 4917} 4918 4919static enum operand_match_result 4920operand_match (idesc, index, e) 4921 const struct ia64_opcode *idesc; 4922 int index; 4923 expressionS *e; 4924{ 4925 enum ia64_opnd opnd = idesc->operands[index]; 4926 int bits, relocatable = 0; 4927 struct insn_fix *fix; 4928 bfd_signed_vma val; 4929 4930 switch (opnd) 4931 { 4932 /* constants: */ 4933 4934 case IA64_OPND_AR_CCV: 4935 if (e->X_op == O_register && e->X_add_number == REG_AR + 32) 4936 return OPERAND_MATCH; 4937 break; 4938 4939 case IA64_OPND_AR_PFS: 4940 if (e->X_op == O_register && e->X_add_number == REG_AR + 64) 4941 return OPERAND_MATCH; 4942 break; 4943 4944 case IA64_OPND_GR0: 4945 if (e->X_op == O_register && e->X_add_number == REG_GR + 0) 4946 return OPERAND_MATCH; 4947 break; 4948 4949 case IA64_OPND_IP: 4950 if (e->X_op == O_register && e->X_add_number == REG_IP) 4951 return OPERAND_MATCH; 4952 break; 4953 4954 case IA64_OPND_PR: 4955 if (e->X_op == O_register && e->X_add_number == REG_PR) 4956 return OPERAND_MATCH; 4957 break; 4958 4959 case IA64_OPND_PR_ROT: 4960 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) 4961 return OPERAND_MATCH; 4962 break; 4963 4964 case IA64_OPND_PSR: 4965 if (e->X_op == O_register && e->X_add_number == REG_PSR) 4966 return OPERAND_MATCH; 4967 break; 4968 4969 case IA64_OPND_PSR_L: 4970 if (e->X_op == O_register && e->X_add_number == REG_PSR_L) 4971 return OPERAND_MATCH; 4972 break; 4973 4974 case IA64_OPND_PSR_UM: 4975 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) 4976 return OPERAND_MATCH; 4977 break; 4978 4979 case IA64_OPND_C1: 4980 if (e->X_op == O_constant) 4981 { 4982 if (e->X_add_number == 1) 4983 return OPERAND_MATCH; 4984 else 4985 return OPERAND_OUT_OF_RANGE; 4986 } 4987 break; 4988 4989 case IA64_OPND_C8: 4990 if (e->X_op == O_constant) 4991 { 4992 if (e->X_add_number == 8) 4993 return OPERAND_MATCH; 4994 else 4995 return OPERAND_OUT_OF_RANGE; 4996 } 4997 break; 4998 4999 case IA64_OPND_C16: 5000 if (e->X_op == O_constant) 5001 { 5002 if (e->X_add_number == 16) 5003 return OPERAND_MATCH; 5004 else 5005 return OPERAND_OUT_OF_RANGE; 5006 } 5007 break; 5008 5009 /* register operands: */ 5010 5011 case IA64_OPND_AR3: 5012 if (e->X_op == O_register && e->X_add_number >= REG_AR 5013 && e->X_add_number < REG_AR + 128) 5014 return OPERAND_MATCH; 5015 break; 5016 5017 case IA64_OPND_B1: 5018 case IA64_OPND_B2: 5019 if (e->X_op == O_register && e->X_add_number >= REG_BR 5020 && e->X_add_number < REG_BR + 8) 5021 return OPERAND_MATCH; 5022 break; 5023 5024 case IA64_OPND_CR3: 5025 if (e->X_op == O_register && e->X_add_number >= REG_CR 5026 && e->X_add_number < REG_CR + 128) 5027 return OPERAND_MATCH; 5028 break; 5029 5030 case IA64_OPND_F1: 5031 case IA64_OPND_F2: 5032 case IA64_OPND_F3: 5033 case IA64_OPND_F4: 5034 if (e->X_op == O_register && e->X_add_number >= REG_FR 5035 && e->X_add_number < REG_FR + 128) 5036 return OPERAND_MATCH; 5037 break; 5038 5039 case IA64_OPND_P1: 5040 case IA64_OPND_P2: 5041 if (e->X_op == O_register && e->X_add_number >= REG_P 5042 && e->X_add_number < REG_P + 64) 5043 return OPERAND_MATCH; 5044 break; 5045 5046 case IA64_OPND_R1: 5047 case IA64_OPND_R2: 5048 case IA64_OPND_R3: 5049 if (e->X_op == O_register && e->X_add_number >= REG_GR 5050 && e->X_add_number < REG_GR + 128) 5051 return OPERAND_MATCH; 5052 break; 5053 5054 case IA64_OPND_R3_2: 5055 if (e->X_op == O_register && e->X_add_number >= REG_GR) 5056 { 5057 if (e->X_add_number < REG_GR + 4) 5058 return OPERAND_MATCH; 5059 else if (e->X_add_number < REG_GR + 128) 5060 return OPERAND_OUT_OF_RANGE; 5061 } 5062 break; 5063 5064 /* indirect operands: */ 5065 case IA64_OPND_CPUID_R3: 5066 case IA64_OPND_DBR_R3: 5067 case IA64_OPND_DTR_R3: 5068 case IA64_OPND_ITR_R3: 5069 case IA64_OPND_IBR_R3: 5070 case IA64_OPND_MSR_R3: 5071 case IA64_OPND_PKR_R3: 5072 case IA64_OPND_PMC_R3: 5073 case IA64_OPND_PMD_R3: 5074 case IA64_OPND_RR_R3: 5075 if (e->X_op == O_index && e->X_op_symbol 5076 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID 5077 == opnd - IA64_OPND_CPUID_R3)) 5078 return OPERAND_MATCH; 5079 break; 5080 5081 case IA64_OPND_MR3: 5082 if (e->X_op == O_index && !e->X_op_symbol) 5083 return OPERAND_MATCH; 5084 break; 5085 5086 /* immediate operands: */ 5087 case IA64_OPND_CNT2a: 5088 case IA64_OPND_LEN4: 5089 case IA64_OPND_LEN6: 5090 bits = operand_width (idesc->operands[index]); 5091 if (e->X_op == O_constant) 5092 { 5093 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) 5094 return OPERAND_MATCH; 5095 else 5096 return OPERAND_OUT_OF_RANGE; 5097 } 5098 break; 5099 5100 case IA64_OPND_CNT2b: 5101 if (e->X_op == O_constant) 5102 { 5103 if ((bfd_vma) (e->X_add_number - 1) < 3) 5104 return OPERAND_MATCH; 5105 else 5106 return OPERAND_OUT_OF_RANGE; 5107 } 5108 break; 5109 5110 case IA64_OPND_CNT2c: 5111 val = e->X_add_number; 5112 if (e->X_op == O_constant) 5113 { 5114 if ((val == 0 || val == 7 || val == 15 || val == 16)) 5115 return OPERAND_MATCH; 5116 else 5117 return OPERAND_OUT_OF_RANGE; 5118 } 5119 break; 5120 5121 case IA64_OPND_SOR: 5122 /* SOR must be an integer multiple of 8 */ 5123 if (e->X_op == O_constant && e->X_add_number & 0x7) 5124 return OPERAND_OUT_OF_RANGE; 5125 case IA64_OPND_SOF: 5126 case IA64_OPND_SOL: 5127 if (e->X_op == O_constant) 5128 { 5129 if ((bfd_vma) e->X_add_number <= 96) 5130 return OPERAND_MATCH; 5131 else 5132 return OPERAND_OUT_OF_RANGE; 5133 } 5134 break; 5135 5136 case IA64_OPND_IMMU62: 5137 if (e->X_op == O_constant) 5138 { 5139 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) 5140 return OPERAND_MATCH; 5141 else 5142 return OPERAND_OUT_OF_RANGE; 5143 } 5144 else 5145 { 5146 /* FIXME -- need 62-bit relocation type */ 5147 as_bad (_("62-bit relocation not yet implemented")); 5148 } 5149 break; 5150 5151 case IA64_OPND_IMMU64: 5152 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup 5153 || e->X_op == O_subtract) 5154 { 5155 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5156 fix->code = BFD_RELOC_IA64_IMM64; 5157 if (e->X_op != O_subtract) 5158 { 5159 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5160 if (e->X_op == O_pseudo_fixup) 5161 e->X_op = O_symbol; 5162 } 5163 5164 fix->opnd = idesc->operands[index]; 5165 fix->expr = *e; 5166 fix->is_pcrel = 0; 5167 ++CURR_SLOT.num_fixups; 5168 return OPERAND_MATCH; 5169 } 5170 else if (e->X_op == O_constant) 5171 return OPERAND_MATCH; 5172 break; 5173 5174 case IA64_OPND_CCNT5: 5175 case IA64_OPND_CNT5: 5176 case IA64_OPND_CNT6: 5177 case IA64_OPND_CPOS6a: 5178 case IA64_OPND_CPOS6b: 5179 case IA64_OPND_CPOS6c: 5180 case IA64_OPND_IMMU2: 5181 case IA64_OPND_IMMU7a: 5182 case IA64_OPND_IMMU7b: 5183 case IA64_OPND_IMMU21: 5184 case IA64_OPND_IMMU24: 5185 case IA64_OPND_MBTYPE4: 5186 case IA64_OPND_MHTYPE8: 5187 case IA64_OPND_POS6: 5188 bits = operand_width (idesc->operands[index]); 5189 if (e->X_op == O_constant) 5190 { 5191 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5192 return OPERAND_MATCH; 5193 else 5194 return OPERAND_OUT_OF_RANGE; 5195 } 5196 break; 5197 5198 case IA64_OPND_IMMU9: 5199 bits = operand_width (idesc->operands[index]); 5200 if (e->X_op == O_constant) 5201 { 5202 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5203 { 5204 int lobits = e->X_add_number & 0x3; 5205 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) 5206 e->X_add_number |= (bfd_vma) 0x3; 5207 return OPERAND_MATCH; 5208 } 5209 else 5210 return OPERAND_OUT_OF_RANGE; 5211 } 5212 break; 5213 5214 case IA64_OPND_IMM44: 5215 /* least 16 bits must be zero */ 5216 if ((e->X_add_number & 0xffff) != 0) 5217 /* XXX technically, this is wrong: we should not be issuing warning 5218 messages until we're sure this instruction pattern is going to 5219 be used! */ 5220 as_warn (_("lower 16 bits of mask ignored")); 5221 5222 if (e->X_op == O_constant) 5223 { 5224 if (((e->X_add_number >= 0 5225 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) 5226 || (e->X_add_number < 0 5227 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) 5228 { 5229 /* sign-extend */ 5230 if (e->X_add_number >= 0 5231 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) 5232 { 5233 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); 5234 } 5235 return OPERAND_MATCH; 5236 } 5237 else 5238 return OPERAND_OUT_OF_RANGE; 5239 } 5240 break; 5241 5242 case IA64_OPND_IMM17: 5243 /* bit 0 is a don't care (pr0 is hardwired to 1) */ 5244 if (e->X_op == O_constant) 5245 { 5246 if (((e->X_add_number >= 0 5247 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) 5248 || (e->X_add_number < 0 5249 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) 5250 { 5251 /* sign-extend */ 5252 if (e->X_add_number >= 0 5253 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) 5254 { 5255 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); 5256 } 5257 return OPERAND_MATCH; 5258 } 5259 else 5260 return OPERAND_OUT_OF_RANGE; 5261 } 5262 break; 5263 5264 case IA64_OPND_IMM14: 5265 case IA64_OPND_IMM22: 5266 relocatable = 1; 5267 case IA64_OPND_IMM1: 5268 case IA64_OPND_IMM8: 5269 case IA64_OPND_IMM8U4: 5270 case IA64_OPND_IMM8M1: 5271 case IA64_OPND_IMM8M1U4: 5272 case IA64_OPND_IMM8M1U8: 5273 case IA64_OPND_IMM9a: 5274 case IA64_OPND_IMM9b: 5275 bits = operand_width (idesc->operands[index]); 5276 if (relocatable && (e->X_op == O_symbol 5277 || e->X_op == O_subtract 5278 || e->X_op == O_pseudo_fixup)) 5279 { 5280 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5281 5282 if (idesc->operands[index] == IA64_OPND_IMM14) 5283 fix->code = BFD_RELOC_IA64_IMM14; 5284 else 5285 fix->code = BFD_RELOC_IA64_IMM22; 5286 5287 if (e->X_op != O_subtract) 5288 { 5289 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5290 if (e->X_op == O_pseudo_fixup) 5291 e->X_op = O_symbol; 5292 } 5293 5294 fix->opnd = idesc->operands[index]; 5295 fix->expr = *e; 5296 fix->is_pcrel = 0; 5297 ++CURR_SLOT.num_fixups; 5298 return OPERAND_MATCH; 5299 } 5300 else if (e->X_op != O_constant 5301 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) 5302 return OPERAND_MISMATCH; 5303 5304 if (opnd == IA64_OPND_IMM8M1U4) 5305 { 5306 /* Zero is not valid for unsigned compares that take an adjusted 5307 constant immediate range. */ 5308 if (e->X_add_number == 0) 5309 return OPERAND_OUT_OF_RANGE; 5310 5311 /* Sign-extend 32-bit unsigned numbers, so that the following range 5312 checks will work. */ 5313 val = e->X_add_number; 5314 if (((val & (~(bfd_vma) 0 << 32)) == 0) 5315 && ((val & ((bfd_vma) 1 << 31)) != 0)) 5316 val = ((val << 32) >> 32); 5317 5318 /* Check for 0x100000000. This is valid because 5319 0x100000000-1 is the same as ((uint32_t) -1). */ 5320 if (val == ((bfd_signed_vma) 1 << 32)) 5321 return OPERAND_MATCH; 5322 5323 val = val - 1; 5324 } 5325 else if (opnd == IA64_OPND_IMM8M1U8) 5326 { 5327 /* Zero is not valid for unsigned compares that take an adjusted 5328 constant immediate range. */ 5329 if (e->X_add_number == 0) 5330 return OPERAND_OUT_OF_RANGE; 5331 5332 /* Check for 0x10000000000000000. */ 5333 if (e->X_op == O_big) 5334 { 5335 if (generic_bignum[0] == 0 5336 && generic_bignum[1] == 0 5337 && generic_bignum[2] == 0 5338 && generic_bignum[3] == 0 5339 && generic_bignum[4] == 1) 5340 return OPERAND_MATCH; 5341 else 5342 return OPERAND_OUT_OF_RANGE; 5343 } 5344 else 5345 val = e->X_add_number - 1; 5346 } 5347 else if (opnd == IA64_OPND_IMM8M1) 5348 val = e->X_add_number - 1; 5349 else if (opnd == IA64_OPND_IMM8U4) 5350 { 5351 /* Sign-extend 32-bit unsigned numbers, so that the following range 5352 checks will work. */ 5353 val = e->X_add_number; 5354 if (((val & (~(bfd_vma) 0 << 32)) == 0) 5355 && ((val & ((bfd_vma) 1 << 31)) != 0)) 5356 val = ((val << 32) >> 32); 5357 } 5358 else 5359 val = e->X_add_number; 5360 5361 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) 5362 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) 5363 return OPERAND_MATCH; 5364 else 5365 return OPERAND_OUT_OF_RANGE; 5366 5367 case IA64_OPND_INC3: 5368 /* +/- 1, 4, 8, 16 */ 5369 val = e->X_add_number; 5370 if (val < 0) 5371 val = -val; 5372 if (e->X_op == O_constant) 5373 { 5374 if ((val == 1 || val == 4 || val == 8 || val == 16)) 5375 return OPERAND_MATCH; 5376 else 5377 return OPERAND_OUT_OF_RANGE; 5378 } 5379 break; 5380 5381 case IA64_OPND_TGT25: 5382 case IA64_OPND_TGT25b: 5383 case IA64_OPND_TGT25c: 5384 case IA64_OPND_TGT64: 5385 if (e->X_op == O_symbol) 5386 { 5387 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5388 if (opnd == IA64_OPND_TGT25) 5389 fix->code = BFD_RELOC_IA64_PCREL21F; 5390 else if (opnd == IA64_OPND_TGT25b) 5391 fix->code = BFD_RELOC_IA64_PCREL21M; 5392 else if (opnd == IA64_OPND_TGT25c) 5393 fix->code = BFD_RELOC_IA64_PCREL21B; 5394 else if (opnd == IA64_OPND_TGT64) 5395 fix->code = BFD_RELOC_IA64_PCREL60B; 5396 else 5397 abort (); 5398 5399 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5400 fix->opnd = idesc->operands[index]; 5401 fix->expr = *e; 5402 fix->is_pcrel = 1; 5403 ++CURR_SLOT.num_fixups; 5404 return OPERAND_MATCH; 5405 } 5406 case IA64_OPND_TAG13: 5407 case IA64_OPND_TAG13b: 5408 switch (e->X_op) 5409 { 5410 case O_constant: 5411 return OPERAND_MATCH; 5412 5413 case O_symbol: 5414 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5415 /* There are no external relocs for TAG13/TAG13b fields, so we 5416 create a dummy reloc. This will not live past md_apply_fix3. */ 5417 fix->code = BFD_RELOC_UNUSED; 5418 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5419 fix->opnd = idesc->operands[index]; 5420 fix->expr = *e; 5421 fix->is_pcrel = 1; 5422 ++CURR_SLOT.num_fixups; 5423 return OPERAND_MATCH; 5424 5425 default: 5426 break; 5427 } 5428 break; 5429 5430 default: 5431 break; 5432 } 5433 return OPERAND_MISMATCH; 5434} 5435 5436static int 5437parse_operand (e) 5438 expressionS *e; 5439{ 5440 int sep = '\0'; 5441 5442 memset (e, 0, sizeof (*e)); 5443 e->X_op = O_absent; 5444 SKIP_WHITESPACE (); 5445 if (*input_line_pointer != '}') 5446 expression (e); 5447 sep = *input_line_pointer++; 5448 5449 if (sep == '}') 5450 { 5451 if (!md.manual_bundling) 5452 as_warn ("Found '}' when manual bundling is off"); 5453 else 5454 CURR_SLOT.manual_bundling_off = 1; 5455 md.manual_bundling = 0; 5456 sep = '\0'; 5457 } 5458 return sep; 5459} 5460 5461/* Returns the next entry in the opcode table that matches the one in 5462 IDESC, and frees the entry in IDESC. If no matching entry is 5463 found, NULL is returned instead. */ 5464 5465static struct ia64_opcode * 5466get_next_opcode (struct ia64_opcode *idesc) 5467{ 5468 struct ia64_opcode *next = ia64_find_next_opcode (idesc); 5469 ia64_free_opcode (idesc); 5470 return next; 5471} 5472 5473/* Parse the operands for the opcode and find the opcode variant that 5474 matches the specified operands, or NULL if no match is possible. */ 5475 5476static struct ia64_opcode * 5477parse_operands (idesc) 5478 struct ia64_opcode *idesc; 5479{ 5480 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; 5481 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; 5482 enum ia64_opnd expected_operand = IA64_OPND_NIL; 5483 enum operand_match_result result; 5484 char mnemonic[129]; 5485 char *first_arg = 0, *end, *saved_input_pointer; 5486 unsigned int sof; 5487 5488 assert (strlen (idesc->name) <= 128); 5489 5490 strcpy (mnemonic, idesc->name); 5491 if (idesc->operands[2] == IA64_OPND_SOF) 5492 { 5493 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we 5494 can't parse the first operand until we have parsed the 5495 remaining operands of the "alloc" instruction. */ 5496 SKIP_WHITESPACE (); 5497 first_arg = input_line_pointer; 5498 end = strchr (input_line_pointer, '='); 5499 if (!end) 5500 { 5501 as_bad ("Expected separator `='"); 5502 return 0; 5503 } 5504 input_line_pointer = end + 1; 5505 ++i; 5506 ++num_outputs; 5507 } 5508 5509 for (; i < NELEMS (CURR_SLOT.opnd); ++i) 5510 { 5511 sep = parse_operand (CURR_SLOT.opnd + i); 5512 if (CURR_SLOT.opnd[i].X_op == O_absent) 5513 break; 5514 5515 ++num_operands; 5516 5517 if (sep != '=' && sep != ',') 5518 break; 5519 5520 if (sep == '=') 5521 { 5522 if (num_outputs > 0) 5523 as_bad ("Duplicate equal sign (=) in instruction"); 5524 else 5525 num_outputs = i + 1; 5526 } 5527 } 5528 if (sep != '\0') 5529 { 5530 as_bad ("Illegal operand separator `%c'", sep); 5531 return 0; 5532 } 5533 5534 if (idesc->operands[2] == IA64_OPND_SOF) 5535 { 5536 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ 5537 know (strcmp (idesc->name, "alloc") == 0); 5538 if (num_operands == 5 /* first_arg not included in this count! */ 5539 && CURR_SLOT.opnd[2].X_op == O_constant 5540 && CURR_SLOT.opnd[3].X_op == O_constant 5541 && CURR_SLOT.opnd[4].X_op == O_constant 5542 && CURR_SLOT.opnd[5].X_op == O_constant) 5543 { 5544 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, 5545 CURR_SLOT.opnd[3].X_add_number, 5546 CURR_SLOT.opnd[4].X_add_number, 5547 CURR_SLOT.opnd[5].X_add_number); 5548 5549 /* now we can parse the first arg: */ 5550 saved_input_pointer = input_line_pointer; 5551 input_line_pointer = first_arg; 5552 sep = parse_operand (CURR_SLOT.opnd + 0); 5553 if (sep != '=') 5554 --num_outputs; /* force error */ 5555 input_line_pointer = saved_input_pointer; 5556 5557 CURR_SLOT.opnd[2].X_add_number = sof; 5558 CURR_SLOT.opnd[3].X_add_number 5559 = sof - CURR_SLOT.opnd[4].X_add_number; 5560 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; 5561 } 5562 } 5563 5564 highest_unmatched_operand = 0; 5565 curr_out_of_range_pos = -1; 5566 error_pos = 0; 5567 expected_operand = idesc->operands[0]; 5568 for (; idesc; idesc = get_next_opcode (idesc)) 5569 { 5570 if (num_outputs != idesc->num_outputs) 5571 continue; /* mismatch in # of outputs */ 5572 5573 CURR_SLOT.num_fixups = 0; 5574 5575 /* Try to match all operands. If we see an out-of-range operand, 5576 then continue trying to match the rest of the operands, since if 5577 the rest match, then this idesc will give the best error message. */ 5578 5579 out_of_range_pos = -1; 5580 for (i = 0; i < num_operands && idesc->operands[i]; ++i) 5581 { 5582 result = operand_match (idesc, i, CURR_SLOT.opnd + i); 5583 if (result != OPERAND_MATCH) 5584 { 5585 if (result != OPERAND_OUT_OF_RANGE) 5586 break; 5587 if (out_of_range_pos < 0) 5588 /* remember position of the first out-of-range operand: */ 5589 out_of_range_pos = i; 5590 } 5591 } 5592 5593 /* If we did not match all operands, or if at least one operand was 5594 out-of-range, then this idesc does not match. Keep track of which 5595 idesc matched the most operands before failing. If we have two 5596 idescs that failed at the same position, and one had an out-of-range 5597 operand, then prefer the out-of-range operand. Thus if we have 5598 "add r0=0x1000000,r1" we get an error saying the constant is out 5599 of range instead of an error saying that the constant should have been 5600 a register. */ 5601 5602 if (i != num_operands || out_of_range_pos >= 0) 5603 { 5604 if (i > highest_unmatched_operand 5605 || (i == highest_unmatched_operand 5606 && out_of_range_pos > curr_out_of_range_pos)) 5607 { 5608 highest_unmatched_operand = i; 5609 if (out_of_range_pos >= 0) 5610 { 5611 expected_operand = idesc->operands[out_of_range_pos]; 5612 error_pos = out_of_range_pos; 5613 } 5614 else 5615 { 5616 expected_operand = idesc->operands[i]; 5617 error_pos = i; 5618 } 5619 curr_out_of_range_pos = out_of_range_pos; 5620 } 5621 continue; 5622 } 5623 5624 if (num_operands < NELEMS (idesc->operands) 5625 && idesc->operands[num_operands]) 5626 continue; /* mismatch in number of arguments */ 5627 5628 break; 5629 } 5630 if (!idesc) 5631 { 5632 if (expected_operand) 5633 as_bad ("Operand %u of `%s' should be %s", 5634 error_pos + 1, mnemonic, 5635 elf64_ia64_operands[expected_operand].desc); 5636 else 5637 as_bad ("Operand mismatch"); 5638 return 0; 5639 } 5640 return idesc; 5641} 5642 5643/* Keep track of state necessary to determine whether a NOP is necessary 5644 to avoid an erratum in A and B step Itanium chips, and return 1 if we 5645 detect a case where additional NOPs may be necessary. */ 5646static int 5647errata_nop_necessary_p (slot, insn_unit) 5648 struct slot *slot; 5649 enum ia64_unit insn_unit; 5650{ 5651 int i; 5652 struct group *this_group = md.last_groups + md.group_idx; 5653 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; 5654 struct ia64_opcode *idesc = slot->idesc; 5655 5656 /* Test whether this could be the first insn in a problematic sequence. */ 5657 if (insn_unit == IA64_UNIT_F) 5658 { 5659 for (i = 0; i < idesc->num_outputs; i++) 5660 if (idesc->operands[i] == IA64_OPND_P1 5661 || idesc->operands[i] == IA64_OPND_P2) 5662 { 5663 int regno = slot->opnd[i].X_add_number - REG_P; 5664 /* Ignore invalid operands; they generate errors elsewhere. */ 5665 if (regno >= 64) 5666 return 0; 5667 this_group->p_reg_set[regno] = 1; 5668 } 5669 } 5670 5671 /* Test whether this could be the second insn in a problematic sequence. */ 5672 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 5673 && prev_group->p_reg_set[slot->qp_regno]) 5674 { 5675 for (i = 0; i < idesc->num_outputs; i++) 5676 if (idesc->operands[i] == IA64_OPND_R1 5677 || idesc->operands[i] == IA64_OPND_R2 5678 || idesc->operands[i] == IA64_OPND_R3) 5679 { 5680 int regno = slot->opnd[i].X_add_number - REG_GR; 5681 /* Ignore invalid operands; they generate errors elsewhere. */ 5682 if (regno >= 128) 5683 return 0; 5684 if (strncmp (idesc->name, "add", 3) != 0 5685 && strncmp (idesc->name, "sub", 3) != 0 5686 && strncmp (idesc->name, "shladd", 6) != 0 5687 && (idesc->flags & IA64_OPCODE_POSTINC) == 0) 5688 this_group->g_reg_set_conditionally[regno] = 1; 5689 } 5690 } 5691 5692 /* Test whether this could be the third insn in a problematic sequence. */ 5693 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) 5694 { 5695 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ 5696 idesc->operands[i] == IA64_OPND_R3 5697 /* For mov indirect. */ 5698 || idesc->operands[i] == IA64_OPND_RR_R3 5699 || idesc->operands[i] == IA64_OPND_DBR_R3 5700 || idesc->operands[i] == IA64_OPND_IBR_R3 5701 || idesc->operands[i] == IA64_OPND_PKR_R3 5702 || idesc->operands[i] == IA64_OPND_PMC_R3 5703 || idesc->operands[i] == IA64_OPND_PMD_R3 5704 || idesc->operands[i] == IA64_OPND_MSR_R3 5705 || idesc->operands[i] == IA64_OPND_CPUID_R3 5706 /* For itr. */ 5707 || idesc->operands[i] == IA64_OPND_ITR_R3 5708 || idesc->operands[i] == IA64_OPND_DTR_R3 5709 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ 5710 || idesc->operands[i] == IA64_OPND_MR3) 5711 { 5712 int regno = slot->opnd[i].X_add_number - REG_GR; 5713 /* Ignore invalid operands; they generate errors elsewhere. */ 5714 if (regno >= 128) 5715 return 0; 5716 if (idesc->operands[i] == IA64_OPND_R3) 5717 { 5718 if (strcmp (idesc->name, "fc") != 0 5719 && strcmp (idesc->name, "tak") != 0 5720 && strcmp (idesc->name, "thash") != 0 5721 && strcmp (idesc->name, "tpa") != 0 5722 && strcmp (idesc->name, "ttag") != 0 5723 && strncmp (idesc->name, "ptr", 3) != 0 5724 && strncmp (idesc->name, "ptc", 3) != 0 5725 && strncmp (idesc->name, "probe", 5) != 0) 5726 return 0; 5727 } 5728 if (prev_group->g_reg_set_conditionally[regno]) 5729 return 1; 5730 } 5731 } 5732 return 0; 5733} 5734 5735static void 5736build_insn (slot, insnp) 5737 struct slot *slot; 5738 bfd_vma *insnp; 5739{ 5740 const struct ia64_operand *odesc, *o2desc; 5741 struct ia64_opcode *idesc = slot->idesc; 5742 bfd_signed_vma insn, val; 5743 const char *err; 5744 int i; 5745 5746 insn = idesc->opcode | slot->qp_regno; 5747 5748 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) 5749 { 5750 if (slot->opnd[i].X_op == O_register 5751 || slot->opnd[i].X_op == O_constant 5752 || slot->opnd[i].X_op == O_index) 5753 val = slot->opnd[i].X_add_number; 5754 else if (slot->opnd[i].X_op == O_big) 5755 { 5756 /* This must be the value 0x10000000000000000. */ 5757 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); 5758 val = 0; 5759 } 5760 else 5761 val = 0; 5762 5763 switch (idesc->operands[i]) 5764 { 5765 case IA64_OPND_IMMU64: 5766 *insnp++ = (val >> 22) & 0x1ffffffffffLL; 5767 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) 5768 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) 5769 | (((val >> 63) & 0x1) << 36)); 5770 continue; 5771 5772 case IA64_OPND_IMMU62: 5773 val &= 0x3fffffffffffffffULL; 5774 if (val != slot->opnd[i].X_add_number) 5775 as_warn (_("Value truncated to 62 bits")); 5776 *insnp++ = (val >> 21) & 0x1ffffffffffLL; 5777 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); 5778 continue; 5779 5780 case IA64_OPND_TGT64: 5781 val >>= 4; 5782 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; 5783 insn |= ((((val >> 59) & 0x1) << 36) 5784 | (((val >> 0) & 0xfffff) << 13)); 5785 continue; 5786 5787 case IA64_OPND_AR3: 5788 val -= REG_AR; 5789 break; 5790 5791 case IA64_OPND_B1: 5792 case IA64_OPND_B2: 5793 val -= REG_BR; 5794 break; 5795 5796 case IA64_OPND_CR3: 5797 val -= REG_CR; 5798 break; 5799 5800 case IA64_OPND_F1: 5801 case IA64_OPND_F2: 5802 case IA64_OPND_F3: 5803 case IA64_OPND_F4: 5804 val -= REG_FR; 5805 break; 5806 5807 case IA64_OPND_P1: 5808 case IA64_OPND_P2: 5809 val -= REG_P; 5810 break; 5811 5812 case IA64_OPND_R1: 5813 case IA64_OPND_R2: 5814 case IA64_OPND_R3: 5815 case IA64_OPND_R3_2: 5816 case IA64_OPND_CPUID_R3: 5817 case IA64_OPND_DBR_R3: 5818 case IA64_OPND_DTR_R3: 5819 case IA64_OPND_ITR_R3: 5820 case IA64_OPND_IBR_R3: 5821 case IA64_OPND_MR3: 5822 case IA64_OPND_MSR_R3: 5823 case IA64_OPND_PKR_R3: 5824 case IA64_OPND_PMC_R3: 5825 case IA64_OPND_PMD_R3: 5826 case IA64_OPND_RR_R3: 5827 val -= REG_GR; 5828 break; 5829 5830 default: 5831 break; 5832 } 5833 5834 odesc = elf64_ia64_operands + idesc->operands[i]; 5835 err = (*odesc->insert) (odesc, val, &insn); 5836 if (err) 5837 as_bad_where (slot->src_file, slot->src_line, 5838 "Bad operand value: %s", err); 5839 if (idesc->flags & IA64_OPCODE_PSEUDO) 5840 { 5841 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) 5842 && odesc == elf64_ia64_operands + IA64_OPND_F3) 5843 { 5844 o2desc = elf64_ia64_operands + IA64_OPND_F2; 5845 (*o2desc->insert) (o2desc, val, &insn); 5846 } 5847 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) 5848 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a 5849 || odesc == elf64_ia64_operands + IA64_OPND_POS6)) 5850 { 5851 o2desc = elf64_ia64_operands + IA64_OPND_LEN6; 5852 (*o2desc->insert) (o2desc, 64 - val, &insn); 5853 } 5854 } 5855 } 5856 *insnp = insn; 5857} 5858 5859static void 5860emit_one_bundle () 5861{ 5862 unsigned int manual_bundling_on = 0, manual_bundling_off = 0; 5863 unsigned int manual_bundling = 0; 5864 enum ia64_unit required_unit, insn_unit = 0; 5865 enum ia64_insn_type type[3], insn_type; 5866 unsigned int template, orig_template; 5867 bfd_vma insn[3] = { -1, -1, -1 }; 5868 struct ia64_opcode *idesc; 5869 int end_of_insn_group = 0, user_template = -1; 5870 int n, i, j, first, curr; 5871 unw_rec_list *ptr; 5872 bfd_vma t0 = 0, t1 = 0; 5873 struct label_fix *lfix; 5874 struct insn_fix *ifix; 5875 char mnemonic[16]; 5876 fixS *fix; 5877 char *f; 5878 5879 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; 5880 know (first >= 0 & first < NUM_SLOTS); 5881 n = MIN (3, md.num_slots_in_use); 5882 5883 /* Determine template: user user_template if specified, best match 5884 otherwise: */ 5885 5886 if (md.slot[first].user_template >= 0) 5887 user_template = template = md.slot[first].user_template; 5888 else 5889 { 5890 /* Auto select appropriate template. */ 5891 memset (type, 0, sizeof (type)); 5892 curr = first; 5893 for (i = 0; i < n; ++i) 5894 { 5895 if (md.slot[curr].label_fixups && i != 0) 5896 break; 5897 type[i] = md.slot[curr].idesc->type; 5898 curr = (curr + 1) % NUM_SLOTS; 5899 } 5900 template = best_template[type[0]][type[1]][type[2]]; 5901 } 5902 5903 /* initialize instructions with appropriate nops: */ 5904 for (i = 0; i < 3; ++i) 5905 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; 5906 5907 f = frag_more (16); 5908 5909 /* now fill in slots with as many insns as possible: */ 5910 curr = first; 5911 idesc = md.slot[curr].idesc; 5912 end_of_insn_group = 0; 5913 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) 5914 { 5915 /* Set the slot number for prologue/body records now as those 5916 refer to the current point, not the point after the 5917 instruction has been issued: */ 5918 /* Don't try to delete prologue/body records here, as that will cause 5919 them to also be deleted from the master list of unwind records. */ 5920 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) 5921 if (ptr->r.type == prologue || ptr->r.type == prologue_gr 5922 || ptr->r.type == body) 5923 { 5924 ptr->slot_number = (unsigned long) f + i; 5925 ptr->slot_frag = frag_now; 5926 } 5927 5928 if (idesc->flags & IA64_OPCODE_SLOT2) 5929 { 5930 if (manual_bundling && i != 2) 5931 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 5932 "`%s' must be last in bundle", idesc->name); 5933 else 5934 i = 2; 5935 } 5936 if (idesc->flags & IA64_OPCODE_LAST) 5937 { 5938 int required_slot; 5939 unsigned int required_template; 5940 5941 /* If we need a stop bit after an M slot, our only choice is 5942 template 5 (M;;MI). If we need a stop bit after a B 5943 slot, our only choice is to place it at the end of the 5944 bundle, because the only available templates are MIB, 5945 MBB, BBB, MMB, and MFB. We don't handle anything other 5946 than M and B slots because these are the only kind of 5947 instructions that can have the IA64_OPCODE_LAST bit set. */ 5948 required_template = template; 5949 switch (idesc->type) 5950 { 5951 case IA64_TYPE_M: 5952 required_slot = 0; 5953 required_template = 5; 5954 break; 5955 5956 case IA64_TYPE_B: 5957 required_slot = 2; 5958 break; 5959 5960 default: 5961 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 5962 "Internal error: don't know how to force %s to end" 5963 "of instruction group", idesc->name); 5964 required_slot = i; 5965 break; 5966 } 5967 if (manual_bundling && i != required_slot) 5968 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 5969 "`%s' must be last in instruction group", 5970 idesc->name); 5971 if (required_slot < i) 5972 /* Can't fit this instruction. */ 5973 break; 5974 5975 i = required_slot; 5976 if (required_template != template) 5977 { 5978 /* If we switch the template, we need to reset the NOPs 5979 after slot i. The slot-types of the instructions ahead 5980 of i never change, so we don't need to worry about 5981 changing NOPs in front of this slot. */ 5982 for (j = i; j < 3; ++j) 5983 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; 5984 } 5985 template = required_template; 5986 } 5987 if (curr != first && md.slot[curr].label_fixups) 5988 { 5989 if (manual_bundling_on) 5990 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 5991 "Label must be first in a bundle"); 5992 /* This insn must go into the first slot of a bundle. */ 5993 break; 5994 } 5995 5996 manual_bundling_on = md.slot[curr].manual_bundling_on; 5997 manual_bundling_off = md.slot[curr].manual_bundling_off; 5998 5999 if (manual_bundling_on) 6000 { 6001 if (curr == first) 6002 manual_bundling = 1; 6003 else 6004 break; /* need to start a new bundle */ 6005 } 6006 6007 if (end_of_insn_group && md.num_slots_in_use >= 1) 6008 { 6009 /* We need an instruction group boundary in the middle of a 6010 bundle. See if we can switch to an other template with 6011 an appropriate boundary. */ 6012 6013 orig_template = template; 6014 if (i == 1 && (user_template == 4 6015 || (user_template < 0 6016 && (ia64_templ_desc[template].exec_unit[0] 6017 == IA64_UNIT_M)))) 6018 { 6019 template = 5; 6020 end_of_insn_group = 0; 6021 } 6022 else if (i == 2 && (user_template == 0 6023 || (user_template < 0 6024 && (ia64_templ_desc[template].exec_unit[1] 6025 == IA64_UNIT_I))) 6026 /* This test makes sure we don't switch the template if 6027 the next instruction is one that needs to be first in 6028 an instruction group. Since all those instructions are 6029 in the M group, there is no way such an instruction can 6030 fit in this bundle even if we switch the template. The 6031 reason we have to check for this is that otherwise we 6032 may end up generating "MI;;I M.." which has the deadly 6033 effect that the second M instruction is no longer the 6034 first in the bundle! --davidm 99/12/16 */ 6035 && (idesc->flags & IA64_OPCODE_FIRST) == 0) 6036 { 6037 template = 1; 6038 end_of_insn_group = 0; 6039 } 6040 else if (curr != first) 6041 /* can't fit this insn */ 6042 break; 6043 6044 if (template != orig_template) 6045 /* if we switch the template, we need to reset the NOPs 6046 after slot i. The slot-types of the instructions ahead 6047 of i never change, so we don't need to worry about 6048 changing NOPs in front of this slot. */ 6049 for (j = i; j < 3; ++j) 6050 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; 6051 } 6052 required_unit = ia64_templ_desc[template].exec_unit[i]; 6053 6054 /* resolve dynamic opcodes such as "break" and "nop": */ 6055 if (idesc->type == IA64_TYPE_DYN) 6056 { 6057 if ((strcmp (idesc->name, "nop") == 0) 6058 || (strcmp (idesc->name, "break") == 0)) 6059 insn_unit = required_unit; 6060 else if (strcmp (idesc->name, "chk.s") == 0) 6061 { 6062 insn_unit = IA64_UNIT_M; 6063 if (required_unit == IA64_UNIT_I) 6064 insn_unit = IA64_UNIT_I; 6065 } 6066 else 6067 as_fatal ("emit_one_bundle: unexpected dynamic op"); 6068 6069 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); 6070 ia64_free_opcode (idesc); 6071 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); 6072#if 0 6073 know (!idesc->next); /* no resolved dynamic ops have collisions */ 6074#endif 6075 } 6076 else 6077 { 6078 insn_type = idesc->type; 6079 insn_unit = IA64_UNIT_NIL; 6080 switch (insn_type) 6081 { 6082 case IA64_TYPE_A: 6083 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) 6084 insn_unit = required_unit; 6085 break; 6086 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; 6087 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; 6088 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; 6089 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; 6090 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; 6091 default: break; 6092 } 6093 } 6094 6095 if (insn_unit != required_unit) 6096 { 6097 if (required_unit == IA64_UNIT_L 6098 && insn_unit == IA64_UNIT_I 6099 && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) 6100 { 6101 /* we got ourselves an MLX template but the current 6102 instruction isn't an X-unit, or an I-unit instruction 6103 that can go into the X slot of an MLX template. Duh. */ 6104 if (md.num_slots_in_use >= NUM_SLOTS) 6105 { 6106 as_bad_where (md.slot[curr].src_file, 6107 md.slot[curr].src_line, 6108 "`%s' can't go in X slot of " 6109 "MLX template", idesc->name); 6110 /* drop this insn so we don't livelock: */ 6111 --md.num_slots_in_use; 6112 } 6113 break; 6114 } 6115 continue; /* try next slot */ 6116 } 6117 6118 { 6119 bfd_vma addr; 6120 6121 addr = frag_now->fr_address + frag_now_fix () - 16 + i; 6122 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); 6123 } 6124 6125 if (errata_nop_necessary_p (md.slot + curr, insn_unit)) 6126 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); 6127 6128 build_insn (md.slot + curr, insn + i); 6129 6130 /* Set slot counts for non prologue/body unwind records. */ 6131 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) 6132 if (ptr->r.type != prologue && ptr->r.type != prologue_gr 6133 && ptr->r.type != body) 6134 { 6135 ptr->slot_number = (unsigned long) f + i; 6136 ptr->slot_frag = frag_now; 6137 } 6138 md.slot[curr].unwind_record = NULL; 6139 6140 if (required_unit == IA64_UNIT_L) 6141 { 6142 know (i == 1); 6143 /* skip one slot for long/X-unit instructions */ 6144 ++i; 6145 } 6146 --md.num_slots_in_use; 6147 6148 /* now is a good time to fix up the labels for this insn: */ 6149 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) 6150 { 6151 S_SET_VALUE (lfix->sym, frag_now_fix () - 16); 6152 symbol_set_frag (lfix->sym, frag_now); 6153 } 6154 /* and fix up the tags also. */ 6155 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) 6156 { 6157 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); 6158 symbol_set_frag (lfix->sym, frag_now); 6159 } 6160 6161 for (j = 0; j < md.slot[curr].num_fixups; ++j) 6162 { 6163 ifix = md.slot[curr].fixup + j; 6164 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, 6165 &ifix->expr, ifix->is_pcrel, ifix->code); 6166 fix->tc_fix_data.opnd = ifix->opnd; 6167 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); 6168 fix->fx_file = md.slot[curr].src_file; 6169 fix->fx_line = md.slot[curr].src_line; 6170 } 6171 6172 end_of_insn_group = md.slot[curr].end_of_insn_group; 6173 6174 if (end_of_insn_group) 6175 { 6176 md.group_idx = (md.group_idx + 1) % 3; 6177 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); 6178 } 6179 6180 /* clear slot: */ 6181 ia64_free_opcode (md.slot[curr].idesc); 6182 memset (md.slot + curr, 0, sizeof (md.slot[curr])); 6183 md.slot[curr].user_template = -1; 6184 6185 if (manual_bundling_off) 6186 { 6187 manual_bundling = 0; 6188 break; 6189 } 6190 curr = (curr + 1) % NUM_SLOTS; 6191 idesc = md.slot[curr].idesc; 6192 } 6193 if (manual_bundling) 6194 { 6195 if (md.num_slots_in_use > 0) 6196 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6197 "`%s' does not fit into %s template", 6198 idesc->name, ia64_templ_desc[template].name); 6199 else 6200 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6201 "Missing '}' at end of file"); 6202 } 6203 know (md.num_slots_in_use < NUM_SLOTS); 6204 6205 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); 6206 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 6207 6208 number_to_chars_littleendian (f + 0, t0, 8); 6209 number_to_chars_littleendian (f + 8, t1, 8); 6210 6211 unwind.next_slot_number = (unsigned long) f + 16; 6212 unwind.next_slot_frag = frag_now; 6213} 6214 6215int 6216md_parse_option (c, arg) 6217 int c; 6218 char *arg; 6219{ 6220 6221 switch (c) 6222 { 6223 /* Switches from the Intel assembler. */ 6224 case 'm': 6225 if (strcmp (arg, "ilp64") == 0 6226 || strcmp (arg, "lp64") == 0 6227 || strcmp (arg, "p64") == 0) 6228 { 6229 md.flags |= EF_IA_64_ABI64; 6230 } 6231 else if (strcmp (arg, "ilp32") == 0) 6232 { 6233 md.flags &= ~EF_IA_64_ABI64; 6234 } 6235 else if (strcmp (arg, "le") == 0) 6236 { 6237 md.flags &= ~EF_IA_64_BE; 6238 } 6239 else if (strcmp (arg, "be") == 0) 6240 { 6241 md.flags |= EF_IA_64_BE; 6242 } 6243 else 6244 return 0; 6245 break; 6246 6247 case 'N': 6248 if (strcmp (arg, "so") == 0) 6249 { 6250 /* Suppress signon message. */ 6251 } 6252 else if (strcmp (arg, "pi") == 0) 6253 { 6254 /* Reject privileged instructions. FIXME */ 6255 } 6256 else if (strcmp (arg, "us") == 0) 6257 { 6258 /* Allow union of signed and unsigned range. FIXME */ 6259 } 6260 else if (strcmp (arg, "close_fcalls") == 0) 6261 { 6262 /* Do not resolve global function calls. */ 6263 } 6264 else 6265 return 0; 6266 break; 6267 6268 case 'C': 6269 /* temp[="prefix"] Insert temporary labels into the object file 6270 symbol table prefixed by "prefix". 6271 Default prefix is ":temp:". 6272 */ 6273 break; 6274 6275 case 'a': 6276 /* indirect=<tgt> Assume unannotated indirect branches behavior 6277 according to <tgt> -- 6278 exit: branch out from the current context (default) 6279 labels: all labels in context may be branch targets 6280 */ 6281 if (strncmp (arg, "indirect=", 9) != 0) 6282 return 0; 6283 break; 6284 6285 case 'x': 6286 /* -X conflicts with an ignored option, use -x instead */ 6287 md.detect_dv = 1; 6288 if (!arg || strcmp (arg, "explicit") == 0) 6289 { 6290 /* set default mode to explicit */ 6291 md.default_explicit_mode = 1; 6292 break; 6293 } 6294 else if (strcmp (arg, "auto") == 0) 6295 { 6296 md.default_explicit_mode = 0; 6297 } 6298 else if (strcmp (arg, "debug") == 0) 6299 { 6300 md.debug_dv = 1; 6301 } 6302 else if (strcmp (arg, "debugx") == 0) 6303 { 6304 md.default_explicit_mode = 1; 6305 md.debug_dv = 1; 6306 } 6307 else 6308 { 6309 as_bad (_("Unrecognized option '-x%s'"), arg); 6310 } 6311 break; 6312 6313 case 'S': 6314 /* nops Print nops statistics. */ 6315 break; 6316 6317 /* GNU specific switches for gcc. */ 6318 case OPTION_MCONSTANT_GP: 6319 md.flags |= EF_IA_64_CONS_GP; 6320 break; 6321 6322 case OPTION_MAUTO_PIC: 6323 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; 6324 break; 6325 6326 default: 6327 return 0; 6328 } 6329 6330 return 1; 6331} 6332 6333void 6334md_show_usage (stream) 6335 FILE *stream; 6336{ 6337 fputs (_("\ 6338IA-64 options:\n\ 6339 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ 6340 -mle | -mbe select little- or big-endian byte order (default -mle)\n\ 6341 -x | -xexplicit turn on dependency violation checking (default)\n\ 6342 -xauto automagically remove dependency violations\n\ 6343 -xdebug debug dependency violation checker\n"), 6344 stream); 6345} 6346 6347void 6348ia64_after_parse_args () 6349{ 6350 if (debug_type == DEBUG_STABS) 6351 as_fatal (_("--gstabs is not supported for ia64")); 6352} 6353 6354/* Return true if TYPE fits in TEMPL at SLOT. */ 6355 6356static int 6357match (int templ, int type, int slot) 6358{ 6359 enum ia64_unit unit; 6360 int result; 6361 6362 unit = ia64_templ_desc[templ].exec_unit[slot]; 6363 switch (type) 6364 { 6365 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ 6366 case IA64_TYPE_A: 6367 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); 6368 break; 6369 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; 6370 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; 6371 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; 6372 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; 6373 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; 6374 default: result = 0; break; 6375 } 6376 return result; 6377} 6378 6379/* Add a bit of extra goodness if a nop of type F or B would fit 6380 in TEMPL at SLOT. */ 6381 6382static inline int 6383extra_goodness (int templ, int slot) 6384{ 6385 if (slot == 1 && match (templ, IA64_TYPE_F, slot)) 6386 return 2; 6387 if (slot == 2 && match (templ, IA64_TYPE_B, slot)) 6388 return 1; 6389 return 0; 6390} 6391 6392/* This function is called once, at assembler startup time. It sets 6393 up all the tables, etc. that the MD part of the assembler will need 6394 that can be determined before arguments are parsed. */ 6395void 6396md_begin () 6397{ 6398 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; 6399 const char *err; 6400 char name[8]; 6401 6402 md.auto_align = 1; 6403 md.explicit_mode = md.default_explicit_mode; 6404 6405 bfd_set_section_alignment (stdoutput, text_section, 4); 6406 6407 target_big_endian = TARGET_BYTES_BIG_ENDIAN; 6408 pseudo_func[FUNC_FPTR_RELATIVE].u.sym = 6409 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, 6410 &zero_address_frag); 6411 6412 pseudo_func[FUNC_GP_RELATIVE].u.sym = 6413 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, 6414 &zero_address_frag); 6415 6416 pseudo_func[FUNC_LT_RELATIVE].u.sym = 6417 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, 6418 &zero_address_frag); 6419 6420 pseudo_func[FUNC_PC_RELATIVE].u.sym = 6421 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, 6422 &zero_address_frag); 6423 6424 pseudo_func[FUNC_PLT_RELATIVE].u.sym = 6425 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, 6426 &zero_address_frag); 6427 6428 pseudo_func[FUNC_SEC_RELATIVE].u.sym = 6429 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, 6430 &zero_address_frag); 6431 6432 pseudo_func[FUNC_SEG_RELATIVE].u.sym = 6433 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, 6434 &zero_address_frag); 6435 6436 pseudo_func[FUNC_LTV_RELATIVE].u.sym = 6437 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, 6438 &zero_address_frag); 6439 6440 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = 6441 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, 6442 &zero_address_frag); 6443 6444 pseudo_func[FUNC_IPLT_RELOC].u.sym = 6445 symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC, 6446 &zero_address_frag); 6447 6448 /* Compute the table of best templates. We compute goodness as a 6449 base 4 value, in which each match counts for 3, each F counts 6450 for 2, each B counts for 1. This should maximize the number of 6451 F and B nops in the chosen bundles, which is good because these 6452 pipelines are least likely to be overcommitted. */ 6453 for (i = 0; i < IA64_NUM_TYPES; ++i) 6454 for (j = 0; j < IA64_NUM_TYPES; ++j) 6455 for (k = 0; k < IA64_NUM_TYPES; ++k) 6456 { 6457 best = 0; 6458 for (t = 0; t < NELEMS (ia64_templ_desc); ++t) 6459 { 6460 goodness = 0; 6461 if (match (t, i, 0)) 6462 { 6463 if (match (t, j, 1)) 6464 { 6465 if (match (t, k, 2)) 6466 goodness = 3 + 3 + 3; 6467 else 6468 goodness = 3 + 3 + extra_goodness (t, 2); 6469 } 6470 else if (match (t, j, 2)) 6471 goodness = 3 + 3 + extra_goodness (t, 1); 6472 else 6473 { 6474 goodness = 3; 6475 goodness += extra_goodness (t, 1); 6476 goodness += extra_goodness (t, 2); 6477 } 6478 } 6479 else if (match (t, i, 1)) 6480 { 6481 if (match (t, j, 2)) 6482 goodness = 3 + 3; 6483 else 6484 goodness = 3 + extra_goodness (t, 2); 6485 } 6486 else if (match (t, i, 2)) 6487 goodness = 3 + extra_goodness (t, 1); 6488 6489 if (goodness > best) 6490 { 6491 best = goodness; 6492 best_template[i][j][k] = t; 6493 } 6494 } 6495 } 6496 6497 for (i = 0; i < NUM_SLOTS; ++i) 6498 md.slot[i].user_template = -1; 6499 6500 md.pseudo_hash = hash_new (); 6501 for (i = 0; i < NELEMS (pseudo_opcode); ++i) 6502 { 6503 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, 6504 (void *) (pseudo_opcode + i)); 6505 if (err) 6506 as_fatal ("ia64.md_begin: can't hash `%s': %s", 6507 pseudo_opcode[i].name, err); 6508 } 6509 6510 md.reg_hash = hash_new (); 6511 md.dynreg_hash = hash_new (); 6512 md.const_hash = hash_new (); 6513 md.entry_hash = hash_new (); 6514 6515 /* general registers: */ 6516 6517 total = 128; 6518 for (i = 0; i < total; ++i) 6519 { 6520 sprintf (name, "r%d", i - REG_GR); 6521 md.regsym[i] = declare_register (name, i); 6522 } 6523 6524 /* floating point registers: */ 6525 total += 128; 6526 for (; i < total; ++i) 6527 { 6528 sprintf (name, "f%d", i - REG_FR); 6529 md.regsym[i] = declare_register (name, i); 6530 } 6531 6532 /* application registers: */ 6533 total += 128; 6534 ar_base = i; 6535 for (; i < total; ++i) 6536 { 6537 sprintf (name, "ar%d", i - REG_AR); 6538 md.regsym[i] = declare_register (name, i); 6539 } 6540 6541 /* control registers: */ 6542 total += 128; 6543 cr_base = i; 6544 for (; i < total; ++i) 6545 { 6546 sprintf (name, "cr%d", i - REG_CR); 6547 md.regsym[i] = declare_register (name, i); 6548 } 6549 6550 /* predicate registers: */ 6551 total += 64; 6552 for (; i < total; ++i) 6553 { 6554 sprintf (name, "p%d", i - REG_P); 6555 md.regsym[i] = declare_register (name, i); 6556 } 6557 6558 /* branch registers: */ 6559 total += 8; 6560 for (; i < total; ++i) 6561 { 6562 sprintf (name, "b%d", i - REG_BR); 6563 md.regsym[i] = declare_register (name, i); 6564 } 6565 6566 md.regsym[REG_IP] = declare_register ("ip", REG_IP); 6567 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); 6568 md.regsym[REG_PR] = declare_register ("pr", REG_PR); 6569 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); 6570 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); 6571 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); 6572 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); 6573 6574 for (i = 0; i < NELEMS (indirect_reg); ++i) 6575 { 6576 regnum = indirect_reg[i].regnum; 6577 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); 6578 } 6579 6580 /* define synonyms for application registers: */ 6581 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) 6582 md.regsym[i] = declare_register (ar[i - REG_AR].name, 6583 REG_AR + ar[i - REG_AR].regnum); 6584 6585 /* define synonyms for control registers: */ 6586 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) 6587 md.regsym[i] = declare_register (cr[i - REG_CR].name, 6588 REG_CR + cr[i - REG_CR].regnum); 6589 6590 declare_register ("gp", REG_GR + 1); 6591 declare_register ("sp", REG_GR + 12); 6592 declare_register ("rp", REG_BR + 0); 6593 6594 /* pseudo-registers used to specify unwind info: */ 6595 declare_register ("psp", REG_PSP); 6596 6597 declare_register_set ("ret", 4, REG_GR + 8); 6598 declare_register_set ("farg", 8, REG_FR + 8); 6599 declare_register_set ("fret", 8, REG_FR + 8); 6600 6601 for (i = 0; i < NELEMS (const_bits); ++i) 6602 { 6603 err = hash_insert (md.const_hash, const_bits[i].name, 6604 (PTR) (const_bits + i)); 6605 if (err) 6606 as_fatal ("Inserting \"%s\" into constant hash table failed: %s", 6607 name, err); 6608 } 6609 6610 /* Set the architecture and machine depending on defaults and command line 6611 options. */ 6612 if (md.flags & EF_IA_64_ABI64) 6613 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); 6614 else 6615 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); 6616 6617 if (! ok) 6618 as_warn (_("Could not set architecture and machine")); 6619 6620 /* Set the pointer size and pointer shift size depending on md.flags */ 6621 6622 if (md.flags & EF_IA_64_ABI64) 6623 { 6624 md.pointer_size = 8; /* pointers are 8 bytes */ 6625 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */ 6626 } 6627 else 6628 { 6629 md.pointer_size = 4; /* pointers are 4 bytes */ 6630 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */ 6631 } 6632 6633 md.mem_offset.hint = 0; 6634 md.path = 0; 6635 md.maxpaths = 0; 6636 md.entry_labels = NULL; 6637} 6638 6639/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin 6640 because that is called after md_parse_option which is where we do the 6641 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the 6642 default endianness. */ 6643 6644void 6645ia64_init (argc, argv) 6646 int argc ATTRIBUTE_UNUSED; 6647 char **argv ATTRIBUTE_UNUSED; 6648{ 6649 md.flags = MD_FLAGS_DEFAULT; 6650} 6651 6652/* Return a string for the target object file format. */ 6653 6654const char * 6655ia64_target_format () 6656{ 6657 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 6658 { 6659 if (md.flags & EF_IA_64_BE) 6660 { 6661 if (md.flags & EF_IA_64_ABI64) 6662#if defined(TE_AIX50) 6663 return "elf64-ia64-aix-big"; 6664#elif defined(TE_HPUX) 6665 return "elf64-ia64-hpux-big"; 6666#else 6667 return "elf64-ia64-big"; 6668#endif 6669 else 6670#if defined(TE_AIX50) 6671 return "elf32-ia64-aix-big"; 6672#elif defined(TE_HPUX) 6673 return "elf32-ia64-hpux-big"; 6674#else 6675 return "elf32-ia64-big"; 6676#endif 6677 } 6678 else 6679 { 6680 if (md.flags & EF_IA_64_ABI64) 6681#ifdef TE_AIX50 6682 return "elf64-ia64-aix-little"; 6683#else 6684 return "elf64-ia64-little"; 6685#endif 6686 else 6687#ifdef TE_AIX50 6688 return "elf32-ia64-aix-little"; 6689#else 6690 return "elf32-ia64-little"; 6691#endif 6692 } 6693 } 6694 else 6695 return "unknown-format"; 6696} 6697 6698void 6699ia64_end_of_source () 6700{ 6701 /* terminate insn group upon reaching end of file: */ 6702 insn_group_break (1, 0, 0); 6703 6704 /* emits slots we haven't written yet: */ 6705 ia64_flush_insns (); 6706 6707 bfd_set_private_flags (stdoutput, md.flags); 6708 6709 md.mem_offset.hint = 0; 6710} 6711 6712void 6713ia64_start_line () 6714{ 6715 if (md.qp.X_op == O_register) 6716 as_bad ("qualifying predicate not followed by instruction"); 6717 md.qp.X_op = O_absent; 6718 6719 if (ignore_input ()) 6720 return; 6721 6722 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') 6723 { 6724 if (md.detect_dv && !md.explicit_mode) 6725 as_warn (_("Explicit stops are ignored in auto mode")); 6726 else 6727 insn_group_break (1, 0, 0); 6728 } 6729} 6730 6731/* This is a hook for ia64_frob_label, so that it can distinguish tags from 6732 labels. */ 6733static int defining_tag = 0; 6734 6735int 6736ia64_unrecognized_line (ch) 6737 int ch; 6738{ 6739 switch (ch) 6740 { 6741 case '(': 6742 expression (&md.qp); 6743 if (*input_line_pointer++ != ')') 6744 { 6745 as_bad ("Expected ')'"); 6746 return 0; 6747 } 6748 if (md.qp.X_op != O_register) 6749 { 6750 as_bad ("Qualifying predicate expected"); 6751 return 0; 6752 } 6753 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) 6754 { 6755 as_bad ("Predicate register expected"); 6756 return 0; 6757 } 6758 return 1; 6759 6760 case '{': 6761 if (md.manual_bundling) 6762 as_warn ("Found '{' when manual bundling is already turned on"); 6763 else 6764 CURR_SLOT.manual_bundling_on = 1; 6765 md.manual_bundling = 1; 6766 6767 /* Bundling is only acceptable in explicit mode 6768 or when in default automatic mode. */ 6769 if (md.detect_dv && !md.explicit_mode) 6770 { 6771 if (!md.mode_explicitly_set 6772 && !md.default_explicit_mode) 6773 dot_dv_mode ('E'); 6774 else 6775 as_warn (_("Found '{' after explicit switch to automatic mode")); 6776 } 6777 return 1; 6778 6779 case '}': 6780 if (!md.manual_bundling) 6781 as_warn ("Found '}' when manual bundling is off"); 6782 else 6783 PREV_SLOT.manual_bundling_off = 1; 6784 md.manual_bundling = 0; 6785 6786 /* switch back to automatic mode, if applicable */ 6787 if (md.detect_dv 6788 && md.explicit_mode 6789 && !md.mode_explicitly_set 6790 && !md.default_explicit_mode) 6791 dot_dv_mode ('A'); 6792 6793 /* Allow '{' to follow on the same line. We also allow ";;", but that 6794 happens automatically because ';' is an end of line marker. */ 6795 SKIP_WHITESPACE (); 6796 if (input_line_pointer[0] == '{') 6797 { 6798 input_line_pointer++; 6799 return ia64_unrecognized_line ('{'); 6800 } 6801 6802 demand_empty_rest_of_line (); 6803 return 1; 6804 6805 case '[': 6806 { 6807 char *s; 6808 char c; 6809 symbolS *tag; 6810 int temp; 6811 6812 if (md.qp.X_op == O_register) 6813 { 6814 as_bad ("Tag must come before qualifying predicate."); 6815 return 0; 6816 } 6817 6818 /* This implements just enough of read_a_source_file in read.c to 6819 recognize labels. */ 6820 if (is_name_beginner (*input_line_pointer)) 6821 { 6822 s = input_line_pointer; 6823 c = get_symbol_end (); 6824 } 6825 else if (LOCAL_LABELS_FB 6826 && ISDIGIT (*input_line_pointer)) 6827 { 6828 temp = 0; 6829 while (ISDIGIT (*input_line_pointer)) 6830 temp = (temp * 10) + *input_line_pointer++ - '0'; 6831 fb_label_instance_inc (temp); 6832 s = fb_label_name (temp, 0); 6833 c = *input_line_pointer; 6834 } 6835 else 6836 { 6837 s = NULL; 6838 c = '\0'; 6839 } 6840 if (c != ':') 6841 { 6842 /* Put ':' back for error messages' sake. */ 6843 *input_line_pointer++ = ':'; 6844 as_bad ("Expected ':'"); 6845 return 0; 6846 } 6847 6848 defining_tag = 1; 6849 tag = colon (s); 6850 defining_tag = 0; 6851 /* Put ':' back for error messages' sake. */ 6852 *input_line_pointer++ = ':'; 6853 if (*input_line_pointer++ != ']') 6854 { 6855 as_bad ("Expected ']'"); 6856 return 0; 6857 } 6858 if (! tag) 6859 { 6860 as_bad ("Tag name expected"); 6861 return 0; 6862 } 6863 return 1; 6864 } 6865 6866 default: 6867 break; 6868 } 6869 6870 /* Not a valid line. */ 6871 return 0; 6872} 6873 6874void 6875ia64_frob_label (sym) 6876 struct symbol *sym; 6877{ 6878 struct label_fix *fix; 6879 6880 /* Tags need special handling since they are not bundle breaks like 6881 labels. */ 6882 if (defining_tag) 6883 { 6884 fix = obstack_alloc (¬es, sizeof (*fix)); 6885 fix->sym = sym; 6886 fix->next = CURR_SLOT.tag_fixups; 6887 CURR_SLOT.tag_fixups = fix; 6888 6889 return; 6890 } 6891 6892 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) 6893 { 6894 md.last_text_seg = now_seg; 6895 fix = obstack_alloc (¬es, sizeof (*fix)); 6896 fix->sym = sym; 6897 fix->next = CURR_SLOT.label_fixups; 6898 CURR_SLOT.label_fixups = fix; 6899 6900 /* Keep track of how many code entry points we've seen. */ 6901 if (md.path == md.maxpaths) 6902 { 6903 md.maxpaths += 20; 6904 md.entry_labels = (const char **) 6905 xrealloc ((void *) md.entry_labels, 6906 md.maxpaths * sizeof (char *)); 6907 } 6908 md.entry_labels[md.path++] = S_GET_NAME (sym); 6909 } 6910} 6911 6912void 6913ia64_flush_pending_output () 6914{ 6915 if (!md.keep_pending_output 6916 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) 6917 { 6918 /* ??? This causes many unnecessary stop bits to be emitted. 6919 Unfortunately, it isn't clear if it is safe to remove this. */ 6920 insn_group_break (1, 0, 0); 6921 ia64_flush_insns (); 6922 } 6923} 6924 6925/* Do ia64-specific expression optimization. All that's done here is 6926 to transform index expressions that are either due to the indexing 6927 of rotating registers or due to the indexing of indirect register 6928 sets. */ 6929int 6930ia64_optimize_expr (l, op, r) 6931 expressionS *l; 6932 operatorT op; 6933 expressionS *r; 6934{ 6935 unsigned num_regs; 6936 6937 if (op == O_index) 6938 { 6939 if (l->X_op == O_register && r->X_op == O_constant) 6940 { 6941 num_regs = (l->X_add_number >> 16); 6942 if ((unsigned) r->X_add_number >= num_regs) 6943 { 6944 if (!num_regs) 6945 as_bad ("No current frame"); 6946 else 6947 as_bad ("Index out of range 0..%u", num_regs - 1); 6948 r->X_add_number = 0; 6949 } 6950 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; 6951 return 1; 6952 } 6953 else if (l->X_op == O_register && r->X_op == O_register) 6954 { 6955 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR 6956 || l->X_add_number == IND_MEM) 6957 { 6958 as_bad ("Indirect register set name expected"); 6959 l->X_add_number = IND_CPUID; 6960 } 6961 l->X_op = O_index; 6962 l->X_op_symbol = md.regsym[l->X_add_number]; 6963 l->X_add_number = r->X_add_number; 6964 return 1; 6965 } 6966 } 6967 return 0; 6968} 6969 6970int 6971ia64_parse_name (name, e) 6972 char *name; 6973 expressionS *e; 6974{ 6975 struct const_desc *cdesc; 6976 struct dynreg *dr = 0; 6977 unsigned int regnum; 6978 struct symbol *sym; 6979 char *end; 6980 6981 /* first see if NAME is a known register name: */ 6982 sym = hash_find (md.reg_hash, name); 6983 if (sym) 6984 { 6985 e->X_op = O_register; 6986 e->X_add_number = S_GET_VALUE (sym); 6987 return 1; 6988 } 6989 6990 cdesc = hash_find (md.const_hash, name); 6991 if (cdesc) 6992 { 6993 e->X_op = O_constant; 6994 e->X_add_number = cdesc->value; 6995 return 1; 6996 } 6997 6998 /* check for inN, locN, or outN: */ 6999 switch (name[0]) 7000 { 7001 case 'i': 7002 if (name[1] == 'n' && ISDIGIT (name[2])) 7003 { 7004 dr = &md.in; 7005 name += 2; 7006 } 7007 break; 7008 7009 case 'l': 7010 if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3])) 7011 { 7012 dr = &md.loc; 7013 name += 3; 7014 } 7015 break; 7016 7017 case 'o': 7018 if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3])) 7019 { 7020 dr = &md.out; 7021 name += 3; 7022 } 7023 break; 7024 7025 default: 7026 break; 7027 } 7028 7029 if (dr) 7030 { 7031 /* The name is inN, locN, or outN; parse the register number. */ 7032 regnum = strtoul (name, &end, 10); 7033 if (end > name && *end == '\0') 7034 { 7035 if ((unsigned) regnum >= dr->num_regs) 7036 { 7037 if (!dr->num_regs) 7038 as_bad ("No current frame"); 7039 else 7040 as_bad ("Register number out of range 0..%u", 7041 dr->num_regs - 1); 7042 regnum = 0; 7043 } 7044 e->X_op = O_register; 7045 e->X_add_number = dr->base + regnum; 7046 return 1; 7047 } 7048 } 7049 7050 if ((dr = hash_find (md.dynreg_hash, name))) 7051 { 7052 /* We've got ourselves the name of a rotating register set. 7053 Store the base register number in the low 16 bits of 7054 X_add_number and the size of the register set in the top 16 7055 bits. */ 7056 e->X_op = O_register; 7057 e->X_add_number = dr->base | (dr->num_regs << 16); 7058 return 1; 7059 } 7060 return 0; 7061} 7062 7063/* Remove the '#' suffix that indicates a symbol as opposed to a register. */ 7064 7065char * 7066ia64_canonicalize_symbol_name (name) 7067 char *name; 7068{ 7069 size_t len = strlen (name); 7070 if (len > 1 && name[len - 1] == '#') 7071 name[len - 1] = '\0'; 7072 return name; 7073} 7074 7075/* Return true if idesc is a conditional branch instruction. This excludes 7076 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded 7077 because they always read/write resources regardless of the value of the 7078 qualifying predicate. br.ia must always use p0, and hence is always 7079 taken. Thus this function returns true for branches which can fall 7080 through, and which use no resources if they do fall through. */ 7081 7082static int 7083is_conditional_branch (idesc) 7084 struct ia64_opcode *idesc; 7085{ 7086 /* br is a conditional branch. Everything that starts with br. except 7087 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch. 7088 Everything that starts with brl is a conditional branch. */ 7089 return (idesc->name[0] == 'b' && idesc->name[1] == 'r' 7090 && (idesc->name[2] == '\0' 7091 || (idesc->name[2] == '.' && idesc->name[3] != 'i' 7092 && idesc->name[3] != 'c' && idesc->name[3] != 'w') 7093 || idesc->name[2] == 'l' 7094 /* br.cond, br.call, br.clr */ 7095 || (idesc->name[2] == '.' && idesc->name[3] == 'c' 7096 && (idesc->name[4] == 'a' || idesc->name[4] == 'o' 7097 || (idesc->name[4] == 'l' && idesc->name[5] == 'r'))))); 7098} 7099 7100/* Return whether the given opcode is a taken branch. If there's any doubt, 7101 returns zero. */ 7102 7103static int 7104is_taken_branch (idesc) 7105 struct ia64_opcode *idesc; 7106{ 7107 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) 7108 || strncmp (idesc->name, "br.ia", 5) == 0); 7109} 7110 7111/* Return whether the given opcode is an interruption or rfi. If there's any 7112 doubt, returns zero. */ 7113 7114static int 7115is_interruption_or_rfi (idesc) 7116 struct ia64_opcode *idesc; 7117{ 7118 if (strcmp (idesc->name, "rfi") == 0) 7119 return 1; 7120 return 0; 7121} 7122 7123/* Returns the index of the given dependency in the opcode's list of chks, or 7124 -1 if there is no dependency. */ 7125 7126static int 7127depends_on (depind, idesc) 7128 int depind; 7129 struct ia64_opcode *idesc; 7130{ 7131 int i; 7132 const struct ia64_opcode_dependency *dep = idesc->dependencies; 7133 for (i = 0; i < dep->nchks; i++) 7134 { 7135 if (depind == DEP (dep->chks[i])) 7136 return i; 7137 } 7138 return -1; 7139} 7140 7141/* Determine a set of specific resources used for a particular resource 7142 class. Returns the number of specific resources identified For those 7143 cases which are not determinable statically, the resource returned is 7144 marked nonspecific. 7145 7146 Meanings of value in 'NOTE': 7147 1) only read/write when the register number is explicitly encoded in the 7148 insn. 7149 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only 7150 accesses CFM when qualifying predicate is in the rotating region. 7151 3) general register value is used to specify an indirect register; not 7152 determinable statically. 7153 4) only read the given resource when bits 7:0 of the indirect index 7154 register value does not match the register number of the resource; not 7155 determinable statically. 7156 5) all rules are implementation specific. 7157 6) only when both the index specified by the reader and the index specified 7158 by the writer have the same value in bits 63:61; not determinable 7159 statically. 7160 7) only access the specified resource when the corresponding mask bit is 7161 set 7162 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is 7163 only read when these insns reference FR2-31 7164 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only 7165 written when these insns write FR32-127 7166 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the 7167 instruction 7168 11) The target predicates are written independently of PR[qp], but source 7169 registers are only read if PR[qp] is true. Since the state of PR[qp] 7170 cannot statically be determined, all source registers are marked used. 7171 12) This insn only reads the specified predicate register when that 7172 register is the PR[qp]. 7173 13) This reference to ld-c only applies to teh GR whose value is loaded 7174 with data returned from memory, not the post-incremented address register. 7175 14) The RSE resource includes the implementation-specific RSE internal 7176 state resources. At least one (and possibly more) of these resources are 7177 read by each instruction listed in IC:rse-readers. At least one (and 7178 possibly more) of these resources are written by each insn listed in 7179 IC:rse-writers. 7180 15+16) Represents reserved instructions, which the assembler does not 7181 generate. 7182 7183 Memory resources (i.e. locations in memory) are *not* marked or tracked by 7184 this code; there are no dependency violations based on memory access. 7185*/ 7186 7187#define MAX_SPECS 256 7188#define DV_CHK 1 7189#define DV_REG 0 7190 7191static int 7192specify_resource (dep, idesc, type, specs, note, path) 7193 const struct ia64_dependency *dep; 7194 struct ia64_opcode *idesc; 7195 int type; /* is this a DV chk or a DV reg? */ 7196 struct rsrc specs[MAX_SPECS]; /* returned specific resources */ 7197 int note; /* resource note for this insn's usage */ 7198 int path; /* which execution path to examine */ 7199{ 7200 int count = 0; 7201 int i; 7202 int rsrc_write = 0; 7203 struct rsrc tmpl; 7204 7205 if (dep->mode == IA64_DV_WAW 7206 || (dep->mode == IA64_DV_RAW && type == DV_REG) 7207 || (dep->mode == IA64_DV_WAR && type == DV_CHK)) 7208 rsrc_write = 1; 7209 7210 /* template for any resources we identify */ 7211 tmpl.dependency = dep; 7212 tmpl.note = note; 7213 tmpl.insn_srlz = tmpl.data_srlz = 0; 7214 tmpl.qp_regno = CURR_SLOT.qp_regno; 7215 tmpl.link_to_qp_branch = 1; 7216 tmpl.mem_offset.hint = 0; 7217 tmpl.specific = 1; 7218 tmpl.index = 0; 7219 tmpl.cmp_type = CMP_NONE; 7220 7221#define UNHANDLED \ 7222as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ 7223dep->name, idesc->name, (rsrc_write?"write":"read"), note) 7224#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) 7225 7226 /* we don't need to track these */ 7227 if (dep->semantics == IA64_DVS_NONE) 7228 return 0; 7229 7230 switch (dep->specifier) 7231 { 7232 case IA64_RS_AR_K: 7233 if (note == 1) 7234 { 7235 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7236 { 7237 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7238 if (regno >= 0 && regno <= 7) 7239 { 7240 specs[count] = tmpl; 7241 specs[count++].index = regno; 7242 } 7243 } 7244 } 7245 else if (note == 0) 7246 { 7247 for (i = 0; i < 8; i++) 7248 { 7249 specs[count] = tmpl; 7250 specs[count++].index = i; 7251 } 7252 } 7253 else 7254 { 7255 UNHANDLED; 7256 } 7257 break; 7258 7259 case IA64_RS_AR_UNAT: 7260 /* This is a mov =AR or mov AR= instruction. */ 7261 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7262 { 7263 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7264 if (regno == AR_UNAT) 7265 { 7266 specs[count++] = tmpl; 7267 } 7268 } 7269 else 7270 { 7271 /* This is a spill/fill, or other instruction that modifies the 7272 unat register. */ 7273 7274 /* Unless we can determine the specific bits used, mark the whole 7275 thing; bits 8:3 of the memory address indicate the bit used in 7276 UNAT. The .mem.offset hint may be used to eliminate a small 7277 subset of conflicts. */ 7278 specs[count] = tmpl; 7279 if (md.mem_offset.hint) 7280 { 7281 if (md.debug_dv) 7282 fprintf (stderr, " Using hint for spill/fill\n"); 7283 /* The index isn't actually used, just set it to something 7284 approximating the bit index. */ 7285 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; 7286 specs[count].mem_offset.hint = 1; 7287 specs[count].mem_offset.offset = md.mem_offset.offset; 7288 specs[count++].mem_offset.base = md.mem_offset.base; 7289 } 7290 else 7291 { 7292 specs[count++].specific = 0; 7293 } 7294 } 7295 break; 7296 7297 case IA64_RS_AR: 7298 if (note == 1) 7299 { 7300 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7301 { 7302 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7303 if ((regno >= 8 && regno <= 15) 7304 || (regno >= 20 && regno <= 23) 7305 || (regno >= 31 && regno <= 39) 7306 || (regno >= 41 && regno <= 47) 7307 || (regno >= 67 && regno <= 111)) 7308 { 7309 specs[count] = tmpl; 7310 specs[count++].index = regno; 7311 } 7312 } 7313 } 7314 else 7315 { 7316 UNHANDLED; 7317 } 7318 break; 7319 7320 case IA64_RS_ARb: 7321 if (note == 1) 7322 { 7323 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 7324 { 7325 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 7326 if ((regno >= 48 && regno <= 63) 7327 || (regno >= 112 && regno <= 127)) 7328 { 7329 specs[count] = tmpl; 7330 specs[count++].index = regno; 7331 } 7332 } 7333 } 7334 else if (note == 0) 7335 { 7336 for (i = 48; i < 64; i++) 7337 { 7338 specs[count] = tmpl; 7339 specs[count++].index = i; 7340 } 7341 for (i = 112; i < 128; i++) 7342 { 7343 specs[count] = tmpl; 7344 specs[count++].index = i; 7345 } 7346 } 7347 else 7348 { 7349 UNHANDLED; 7350 } 7351 break; 7352 7353 case IA64_RS_BR: 7354 if (note != 1) 7355 { 7356 UNHANDLED; 7357 } 7358 else 7359 { 7360 if (rsrc_write) 7361 { 7362 for (i = 0; i < idesc->num_outputs; i++) 7363 if (idesc->operands[i] == IA64_OPND_B1 7364 || idesc->operands[i] == IA64_OPND_B2) 7365 { 7366 specs[count] = tmpl; 7367 specs[count++].index = 7368 CURR_SLOT.opnd[i].X_add_number - REG_BR; 7369 } 7370 } 7371 else 7372 { 7373 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++) 7374 if (idesc->operands[i] == IA64_OPND_B1 7375 || idesc->operands[i] == IA64_OPND_B2) 7376 { 7377 specs[count] = tmpl; 7378 specs[count++].index = 7379 CURR_SLOT.opnd[i].X_add_number - REG_BR; 7380 } 7381 } 7382 } 7383 break; 7384 7385 case IA64_RS_CPUID: /* four or more registers */ 7386 if (note == 3) 7387 { 7388 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) 7389 { 7390 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7391 if (regno >= 0 && regno < NELEMS (gr_values) 7392 && KNOWN (regno)) 7393 { 7394 specs[count] = tmpl; 7395 specs[count++].index = gr_values[regno].value & 0xFF; 7396 } 7397 else 7398 { 7399 specs[count] = tmpl; 7400 specs[count++].specific = 0; 7401 } 7402 } 7403 } 7404 else 7405 { 7406 UNHANDLED; 7407 } 7408 break; 7409 7410 case IA64_RS_DBR: /* four or more registers */ 7411 if (note == 3) 7412 { 7413 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) 7414 { 7415 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7416 if (regno >= 0 && regno < NELEMS (gr_values) 7417 && KNOWN (regno)) 7418 { 7419 specs[count] = tmpl; 7420 specs[count++].index = gr_values[regno].value & 0xFF; 7421 } 7422 else 7423 { 7424 specs[count] = tmpl; 7425 specs[count++].specific = 0; 7426 } 7427 } 7428 } 7429 else if (note == 0 && !rsrc_write) 7430 { 7431 specs[count] = tmpl; 7432 specs[count++].specific = 0; 7433 } 7434 else 7435 { 7436 UNHANDLED; 7437 } 7438 break; 7439 7440 case IA64_RS_IBR: /* four or more registers */ 7441 if (note == 3) 7442 { 7443 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) 7444 { 7445 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7446 if (regno >= 0 && regno < NELEMS (gr_values) 7447 && KNOWN (regno)) 7448 { 7449 specs[count] = tmpl; 7450 specs[count++].index = gr_values[regno].value & 0xFF; 7451 } 7452 else 7453 { 7454 specs[count] = tmpl; 7455 specs[count++].specific = 0; 7456 } 7457 } 7458 } 7459 else 7460 { 7461 UNHANDLED; 7462 } 7463 break; 7464 7465 case IA64_RS_MSR: 7466 if (note == 5) 7467 { 7468 /* These are implementation specific. Force all references to 7469 conflict with all other references. */ 7470 specs[count] = tmpl; 7471 specs[count++].specific = 0; 7472 } 7473 else 7474 { 7475 UNHANDLED; 7476 } 7477 break; 7478 7479 case IA64_RS_PKR: /* 16 or more registers */ 7480 if (note == 3 || note == 4) 7481 { 7482 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) 7483 { 7484 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7485 if (regno >= 0 && regno < NELEMS (gr_values) 7486 && KNOWN (regno)) 7487 { 7488 if (note == 3) 7489 { 7490 specs[count] = tmpl; 7491 specs[count++].index = gr_values[regno].value & 0xFF; 7492 } 7493 else 7494 for (i = 0; i < NELEMS (gr_values); i++) 7495 { 7496 /* Uses all registers *except* the one in R3. */ 7497 if ((unsigned)i != (gr_values[regno].value & 0xFF)) 7498 { 7499 specs[count] = tmpl; 7500 specs[count++].index = i; 7501 } 7502 } 7503 } 7504 else 7505 { 7506 specs[count] = tmpl; 7507 specs[count++].specific = 0; 7508 } 7509 } 7510 } 7511 else if (note == 0) 7512 { 7513 /* probe et al. */ 7514 specs[count] = tmpl; 7515 specs[count++].specific = 0; 7516 } 7517 break; 7518 7519 case IA64_RS_PMC: /* four or more registers */ 7520 if (note == 3) 7521 { 7522 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 7523 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) 7524 7525 { 7526 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) 7527 ? 1 : !rsrc_write); 7528 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; 7529 if (regno >= 0 && regno < NELEMS (gr_values) 7530 && KNOWN (regno)) 7531 { 7532 specs[count] = tmpl; 7533 specs[count++].index = gr_values[regno].value & 0xFF; 7534 } 7535 else 7536 { 7537 specs[count] = tmpl; 7538 specs[count++].specific = 0; 7539 } 7540 } 7541 } 7542 else 7543 { 7544 UNHANDLED; 7545 } 7546 break; 7547 7548 case IA64_RS_PMD: /* four or more registers */ 7549 if (note == 3) 7550 { 7551 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) 7552 { 7553 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7554 if (regno >= 0 && regno < NELEMS (gr_values) 7555 && KNOWN (regno)) 7556 { 7557 specs[count] = tmpl; 7558 specs[count++].index = gr_values[regno].value & 0xFF; 7559 } 7560 else 7561 { 7562 specs[count] = tmpl; 7563 specs[count++].specific = 0; 7564 } 7565 } 7566 } 7567 else 7568 { 7569 UNHANDLED; 7570 } 7571 break; 7572 7573 case IA64_RS_RR: /* eight registers */ 7574 if (note == 6) 7575 { 7576 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) 7577 { 7578 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 7579 if (regno >= 0 && regno < NELEMS (gr_values) 7580 && KNOWN (regno)) 7581 { 7582 specs[count] = tmpl; 7583 specs[count++].index = (gr_values[regno].value >> 61) & 0x7; 7584 } 7585 else 7586 { 7587 specs[count] = tmpl; 7588 specs[count++].specific = 0; 7589 } 7590 } 7591 } 7592 else if (note == 0 && !rsrc_write) 7593 { 7594 specs[count] = tmpl; 7595 specs[count++].specific = 0; 7596 } 7597 else 7598 { 7599 UNHANDLED; 7600 } 7601 break; 7602 7603 case IA64_RS_CR_IRR: 7604 if (note == 0) 7605 { 7606 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ 7607 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; 7608 if (rsrc_write 7609 && idesc->operands[1] == IA64_OPND_CR3 7610 && regno == CR_IVR) 7611 { 7612 for (i = 0; i < 4; i++) 7613 { 7614 specs[count] = tmpl; 7615 specs[count++].index = CR_IRR0 + i; 7616 } 7617 } 7618 } 7619 else if (note == 1) 7620 { 7621 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7622 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 7623 && regno >= CR_IRR0 7624 && regno <= CR_IRR3) 7625 { 7626 specs[count] = tmpl; 7627 specs[count++].index = regno; 7628 } 7629 } 7630 else 7631 { 7632 UNHANDLED; 7633 } 7634 break; 7635 7636 case IA64_RS_CR_LRR: 7637 if (note != 1) 7638 { 7639 UNHANDLED; 7640 } 7641 else 7642 { 7643 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7644 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 7645 && (regno == CR_LRR0 || regno == CR_LRR1)) 7646 { 7647 specs[count] = tmpl; 7648 specs[count++].index = regno; 7649 } 7650 } 7651 break; 7652 7653 case IA64_RS_CR: 7654 if (note == 1) 7655 { 7656 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 7657 { 7658 specs[count] = tmpl; 7659 specs[count++].index = 7660 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 7661 } 7662 } 7663 else 7664 { 7665 UNHANDLED; 7666 } 7667 break; 7668 7669 case IA64_RS_FR: 7670 case IA64_RS_FRb: 7671 if (note != 1) 7672 { 7673 UNHANDLED; 7674 } 7675 else if (rsrc_write) 7676 { 7677 if (dep->specifier == IA64_RS_FRb 7678 && idesc->operands[0] == IA64_OPND_F1) 7679 { 7680 specs[count] = tmpl; 7681 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; 7682 } 7683 } 7684 else 7685 { 7686 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) 7687 { 7688 if (idesc->operands[i] == IA64_OPND_F2 7689 || idesc->operands[i] == IA64_OPND_F3 7690 || idesc->operands[i] == IA64_OPND_F4) 7691 { 7692 specs[count] = tmpl; 7693 specs[count++].index = 7694 CURR_SLOT.opnd[i].X_add_number - REG_FR; 7695 } 7696 } 7697 } 7698 break; 7699 7700 case IA64_RS_GR: 7701 if (note == 13) 7702 { 7703 /* This reference applies only to the GR whose value is loaded with 7704 data returned from memory. */ 7705 specs[count] = tmpl; 7706 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; 7707 } 7708 else if (note == 1) 7709 { 7710 if (rsrc_write) 7711 { 7712 for (i = 0; i < idesc->num_outputs; i++) 7713 if (idesc->operands[i] == IA64_OPND_R1 7714 || idesc->operands[i] == IA64_OPND_R2 7715 || idesc->operands[i] == IA64_OPND_R3) 7716 { 7717 specs[count] = tmpl; 7718 specs[count++].index = 7719 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7720 } 7721 if (idesc->flags & IA64_OPCODE_POSTINC) 7722 for (i = 0; i < NELEMS (idesc->operands); i++) 7723 if (idesc->operands[i] == IA64_OPND_MR3) 7724 { 7725 specs[count] = tmpl; 7726 specs[count++].index = 7727 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7728 } 7729 } 7730 else 7731 { 7732 /* Look for anything that reads a GR. */ 7733 for (i = 0; i < NELEMS (idesc->operands); i++) 7734 { 7735 if (idesc->operands[i] == IA64_OPND_MR3 7736 || idesc->operands[i] == IA64_OPND_CPUID_R3 7737 || idesc->operands[i] == IA64_OPND_DBR_R3 7738 || idesc->operands[i] == IA64_OPND_IBR_R3 7739 || idesc->operands[i] == IA64_OPND_MSR_R3 7740 || idesc->operands[i] == IA64_OPND_PKR_R3 7741 || idesc->operands[i] == IA64_OPND_PMC_R3 7742 || idesc->operands[i] == IA64_OPND_PMD_R3 7743 || idesc->operands[i] == IA64_OPND_RR_R3 7744 || ((i >= idesc->num_outputs) 7745 && (idesc->operands[i] == IA64_OPND_R1 7746 || idesc->operands[i] == IA64_OPND_R2 7747 || idesc->operands[i] == IA64_OPND_R3 7748 /* addl source register. */ 7749 || idesc->operands[i] == IA64_OPND_R3_2))) 7750 { 7751 specs[count] = tmpl; 7752 specs[count++].index = 7753 CURR_SLOT.opnd[i].X_add_number - REG_GR; 7754 } 7755 } 7756 } 7757 } 7758 else 7759 { 7760 UNHANDLED; 7761 } 7762 break; 7763 7764 /* This is the same as IA64_RS_PRr, except that the register range is 7765 from 1 - 15, and there are no rotating register reads/writes here. */ 7766 case IA64_RS_PR: 7767 if (note == 0) 7768 { 7769 for (i = 1; i < 16; i++) 7770 { 7771 specs[count] = tmpl; 7772 specs[count++].index = i; 7773 } 7774 } 7775 else if (note == 7) 7776 { 7777 valueT mask = 0; 7778 /* Mark only those registers indicated by the mask. */ 7779 if (rsrc_write) 7780 { 7781 mask = CURR_SLOT.opnd[2].X_add_number; 7782 for (i = 1; i < 16; i++) 7783 if (mask & ((valueT) 1 << i)) 7784 { 7785 specs[count] = tmpl; 7786 specs[count++].index = i; 7787 } 7788 } 7789 else 7790 { 7791 UNHANDLED; 7792 } 7793 } 7794 else if (note == 11) /* note 11 implies note 1 as well */ 7795 { 7796 if (rsrc_write) 7797 { 7798 for (i = 0; i < idesc->num_outputs; i++) 7799 { 7800 if (idesc->operands[i] == IA64_OPND_P1 7801 || idesc->operands[i] == IA64_OPND_P2) 7802 { 7803 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 7804 if (regno >= 1 && regno < 16) 7805 { 7806 specs[count] = tmpl; 7807 specs[count++].index = regno; 7808 } 7809 } 7810 } 7811 } 7812 else 7813 { 7814 UNHANDLED; 7815 } 7816 } 7817 else if (note == 12) 7818 { 7819 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 7820 { 7821 specs[count] = tmpl; 7822 specs[count++].index = CURR_SLOT.qp_regno; 7823 } 7824 } 7825 else if (note == 1) 7826 { 7827 if (rsrc_write) 7828 { 7829 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 7830 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 7831 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 7832 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 7833 7834 if ((idesc->operands[0] == IA64_OPND_P1 7835 || idesc->operands[0] == IA64_OPND_P2) 7836 && p1 >= 1 && p1 < 16) 7837 { 7838 specs[count] = tmpl; 7839 specs[count].cmp_type = 7840 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 7841 specs[count++].index = p1; 7842 } 7843 if ((idesc->operands[1] == IA64_OPND_P1 7844 || idesc->operands[1] == IA64_OPND_P2) 7845 && p2 >= 1 && p2 < 16) 7846 { 7847 specs[count] = tmpl; 7848 specs[count].cmp_type = 7849 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 7850 specs[count++].index = p2; 7851 } 7852 } 7853 else 7854 { 7855 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 7856 { 7857 specs[count] = tmpl; 7858 specs[count++].index = CURR_SLOT.qp_regno; 7859 } 7860 if (idesc->operands[1] == IA64_OPND_PR) 7861 { 7862 for (i = 1; i < 16; i++) 7863 { 7864 specs[count] = tmpl; 7865 specs[count++].index = i; 7866 } 7867 } 7868 } 7869 } 7870 else 7871 { 7872 UNHANDLED; 7873 } 7874 break; 7875 7876 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are 7877 simplified cases of this. */ 7878 case IA64_RS_PRr: 7879 if (note == 0) 7880 { 7881 for (i = 16; i < 63; i++) 7882 { 7883 specs[count] = tmpl; 7884 specs[count++].index = i; 7885 } 7886 } 7887 else if (note == 7) 7888 { 7889 valueT mask = 0; 7890 /* Mark only those registers indicated by the mask. */ 7891 if (rsrc_write 7892 && idesc->operands[0] == IA64_OPND_PR) 7893 { 7894 mask = CURR_SLOT.opnd[2].X_add_number; 7895 if (mask & ((valueT) 1<<16)) 7896 for (i = 16; i < 63; i++) 7897 { 7898 specs[count] = tmpl; 7899 specs[count++].index = i; 7900 } 7901 } 7902 else if (rsrc_write 7903 && idesc->operands[0] == IA64_OPND_PR_ROT) 7904 { 7905 for (i = 16; i < 63; i++) 7906 { 7907 specs[count] = tmpl; 7908 specs[count++].index = i; 7909 } 7910 } 7911 else 7912 { 7913 UNHANDLED; 7914 } 7915 } 7916 else if (note == 11) /* note 11 implies note 1 as well */ 7917 { 7918 if (rsrc_write) 7919 { 7920 for (i = 0; i < idesc->num_outputs; i++) 7921 { 7922 if (idesc->operands[i] == IA64_OPND_P1 7923 || idesc->operands[i] == IA64_OPND_P2) 7924 { 7925 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 7926 if (regno >= 16 && regno < 63) 7927 { 7928 specs[count] = tmpl; 7929 specs[count++].index = regno; 7930 } 7931 } 7932 } 7933 } 7934 else 7935 { 7936 UNHANDLED; 7937 } 7938 } 7939 else if (note == 12) 7940 { 7941 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 7942 { 7943 specs[count] = tmpl; 7944 specs[count++].index = CURR_SLOT.qp_regno; 7945 } 7946 } 7947 else if (note == 1) 7948 { 7949 if (rsrc_write) 7950 { 7951 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 7952 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 7953 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 7954 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 7955 7956 if ((idesc->operands[0] == IA64_OPND_P1 7957 || idesc->operands[0] == IA64_OPND_P2) 7958 && p1 >= 16 && p1 < 63) 7959 { 7960 specs[count] = tmpl; 7961 specs[count].cmp_type = 7962 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 7963 specs[count++].index = p1; 7964 } 7965 if ((idesc->operands[1] == IA64_OPND_P1 7966 || idesc->operands[1] == IA64_OPND_P2) 7967 && p2 >= 16 && p2 < 63) 7968 { 7969 specs[count] = tmpl; 7970 specs[count].cmp_type = 7971 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 7972 specs[count++].index = p2; 7973 } 7974 } 7975 else 7976 { 7977 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 7978 { 7979 specs[count] = tmpl; 7980 specs[count++].index = CURR_SLOT.qp_regno; 7981 } 7982 if (idesc->operands[1] == IA64_OPND_PR) 7983 { 7984 for (i = 16; i < 63; i++) 7985 { 7986 specs[count] = tmpl; 7987 specs[count++].index = i; 7988 } 7989 } 7990 } 7991 } 7992 else 7993 { 7994 UNHANDLED; 7995 } 7996 break; 7997 7998 case IA64_RS_PSR: 7999 /* Verify that the instruction is using the PSR bit indicated in 8000 dep->regindex. */ 8001 if (note == 0) 8002 { 8003 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) 8004 { 8005 if (dep->regindex < 6) 8006 { 8007 specs[count++] = tmpl; 8008 } 8009 } 8010 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) 8011 { 8012 if (dep->regindex < 32 8013 || dep->regindex == 35 8014 || dep->regindex == 36 8015 || (!rsrc_write && dep->regindex == PSR_CPL)) 8016 { 8017 specs[count++] = tmpl; 8018 } 8019 } 8020 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) 8021 { 8022 if (dep->regindex < 32 8023 || dep->regindex == 35 8024 || dep->regindex == 36 8025 || (rsrc_write && dep->regindex == PSR_CPL)) 8026 { 8027 specs[count++] = tmpl; 8028 } 8029 } 8030 else 8031 { 8032 /* Several PSR bits have very specific dependencies. */ 8033 switch (dep->regindex) 8034 { 8035 default: 8036 specs[count++] = tmpl; 8037 break; 8038 case PSR_IC: 8039 if (rsrc_write) 8040 { 8041 specs[count++] = tmpl; 8042 } 8043 else 8044 { 8045 /* Only certain CR accesses use PSR.ic */ 8046 if (idesc->operands[0] == IA64_OPND_CR3 8047 || idesc->operands[1] == IA64_OPND_CR3) 8048 { 8049 int index = 8050 ((idesc->operands[0] == IA64_OPND_CR3) 8051 ? 0 : 1); 8052 int regno = 8053 CURR_SLOT.opnd[index].X_add_number - REG_CR; 8054 8055 switch (regno) 8056 { 8057 default: 8058 break; 8059 case CR_ITIR: 8060 case CR_IFS: 8061 case CR_IIM: 8062 case CR_IIP: 8063 case CR_IPSR: 8064 case CR_ISR: 8065 case CR_IFA: 8066 case CR_IHA: 8067 case CR_IIPA: 8068 specs[count++] = tmpl; 8069 break; 8070 } 8071 } 8072 } 8073 break; 8074 case PSR_CPL: 8075 if (rsrc_write) 8076 { 8077 specs[count++] = tmpl; 8078 } 8079 else 8080 { 8081 /* Only some AR accesses use cpl */ 8082 if (idesc->operands[0] == IA64_OPND_AR3 8083 || idesc->operands[1] == IA64_OPND_AR3) 8084 { 8085 int index = 8086 ((idesc->operands[0] == IA64_OPND_AR3) 8087 ? 0 : 1); 8088 int regno = 8089 CURR_SLOT.opnd[index].X_add_number - REG_AR; 8090 8091 if (regno == AR_ITC 8092 || (index == 0 8093 && (regno == AR_ITC 8094 || regno == AR_RSC 8095 || (regno >= AR_K0 8096 && regno <= AR_K7)))) 8097 { 8098 specs[count++] = tmpl; 8099 } 8100 } 8101 else 8102 { 8103 specs[count++] = tmpl; 8104 } 8105 break; 8106 } 8107 } 8108 } 8109 } 8110 else if (note == 7) 8111 { 8112 valueT mask = 0; 8113 if (idesc->operands[0] == IA64_OPND_IMMU24) 8114 { 8115 mask = CURR_SLOT.opnd[0].X_add_number; 8116 } 8117 else 8118 { 8119 UNHANDLED; 8120 } 8121 if (mask & ((valueT) 1 << dep->regindex)) 8122 { 8123 specs[count++] = tmpl; 8124 } 8125 } 8126 else if (note == 8) 8127 { 8128 int min = dep->regindex == PSR_DFL ? 2 : 32; 8129 int max = dep->regindex == PSR_DFL ? 31 : 127; 8130 /* dfh is read on FR32-127; dfl is read on FR2-31 */ 8131 for (i = 0; i < NELEMS (idesc->operands); i++) 8132 { 8133 if (idesc->operands[i] == IA64_OPND_F1 8134 || idesc->operands[i] == IA64_OPND_F2 8135 || idesc->operands[i] == IA64_OPND_F3 8136 || idesc->operands[i] == IA64_OPND_F4) 8137 { 8138 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8139 if (reg >= min && reg <= max) 8140 { 8141 specs[count++] = tmpl; 8142 } 8143 } 8144 } 8145 } 8146 else if (note == 9) 8147 { 8148 int min = dep->regindex == PSR_MFL ? 2 : 32; 8149 int max = dep->regindex == PSR_MFL ? 31 : 127; 8150 /* mfh is read on writes to FR32-127; mfl is read on writes to 8151 FR2-31 */ 8152 for (i = 0; i < idesc->num_outputs; i++) 8153 { 8154 if (idesc->operands[i] == IA64_OPND_F1) 8155 { 8156 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8157 if (reg >= min && reg <= max) 8158 { 8159 specs[count++] = tmpl; 8160 } 8161 } 8162 } 8163 } 8164 else if (note == 10) 8165 { 8166 for (i = 0; i < NELEMS (idesc->operands); i++) 8167 { 8168 if (idesc->operands[i] == IA64_OPND_R1 8169 || idesc->operands[i] == IA64_OPND_R2 8170 || idesc->operands[i] == IA64_OPND_R3) 8171 { 8172 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8173 if (regno >= 16 && regno <= 31) 8174 { 8175 specs[count++] = tmpl; 8176 } 8177 } 8178 } 8179 } 8180 else 8181 { 8182 UNHANDLED; 8183 } 8184 break; 8185 8186 case IA64_RS_AR_FPSR: 8187 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 8188 { 8189 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8190 if (regno == AR_FPSR) 8191 { 8192 specs[count++] = tmpl; 8193 } 8194 } 8195 else 8196 { 8197 specs[count++] = tmpl; 8198 } 8199 break; 8200 8201 case IA64_RS_ARX: 8202 /* Handle all AR[REG] resources */ 8203 if (note == 0 || note == 1) 8204 { 8205 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8206 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 8207 && regno == dep->regindex) 8208 { 8209 specs[count++] = tmpl; 8210 } 8211 /* other AR[REG] resources may be affected by AR accesses */ 8212 else if (idesc->operands[0] == IA64_OPND_AR3) 8213 { 8214 /* AR[] writes */ 8215 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; 8216 switch (dep->regindex) 8217 { 8218 default: 8219 break; 8220 case AR_BSP: 8221 case AR_RNAT: 8222 if (regno == AR_BSPSTORE) 8223 { 8224 specs[count++] = tmpl; 8225 } 8226 case AR_RSC: 8227 if (!rsrc_write && 8228 (regno == AR_BSPSTORE 8229 || regno == AR_RNAT)) 8230 { 8231 specs[count++] = tmpl; 8232 } 8233 break; 8234 } 8235 } 8236 else if (idesc->operands[1] == IA64_OPND_AR3) 8237 { 8238 /* AR[] reads */ 8239 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; 8240 switch (dep->regindex) 8241 { 8242 default: 8243 break; 8244 case AR_RSC: 8245 if (regno == AR_BSPSTORE || regno == AR_RNAT) 8246 { 8247 specs[count++] = tmpl; 8248 } 8249 break; 8250 } 8251 } 8252 else 8253 { 8254 specs[count++] = tmpl; 8255 } 8256 } 8257 else 8258 { 8259 UNHANDLED; 8260 } 8261 break; 8262 8263 case IA64_RS_CRX: 8264 /* Handle all CR[REG] resources */ 8265 if (note == 0 || note == 1) 8266 { 8267 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 8268 { 8269 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 8270 if (regno == dep->regindex) 8271 { 8272 specs[count++] = tmpl; 8273 } 8274 else if (!rsrc_write) 8275 { 8276 /* Reads from CR[IVR] affect other resources. */ 8277 if (regno == CR_IVR) 8278 { 8279 if ((dep->regindex >= CR_IRR0 8280 && dep->regindex <= CR_IRR3) 8281 || dep->regindex == CR_TPR) 8282 { 8283 specs[count++] = tmpl; 8284 } 8285 } 8286 } 8287 } 8288 else 8289 { 8290 specs[count++] = tmpl; 8291 } 8292 } 8293 else 8294 { 8295 UNHANDLED; 8296 } 8297 break; 8298 8299 case IA64_RS_INSERVICE: 8300 /* look for write of EOI (67) or read of IVR (65) */ 8301 if ((idesc->operands[0] == IA64_OPND_CR3 8302 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) 8303 || (idesc->operands[1] == IA64_OPND_CR3 8304 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) 8305 { 8306 specs[count++] = tmpl; 8307 } 8308 break; 8309 8310 case IA64_RS_GR0: 8311 if (note == 1) 8312 { 8313 specs[count++] = tmpl; 8314 } 8315 else 8316 { 8317 UNHANDLED; 8318 } 8319 break; 8320 8321 case IA64_RS_CFM: 8322 if (note != 2) 8323 { 8324 specs[count++] = tmpl; 8325 } 8326 else 8327 { 8328 /* Check if any of the registers accessed are in the rotating region. 8329 mov to/from pr accesses CFM only when qp_regno is in the rotating 8330 region */ 8331 for (i = 0; i < NELEMS (idesc->operands); i++) 8332 { 8333 if (idesc->operands[i] == IA64_OPND_R1 8334 || idesc->operands[i] == IA64_OPND_R2 8335 || idesc->operands[i] == IA64_OPND_R3) 8336 { 8337 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8338 /* Assumes that md.rot.num_regs is always valid */ 8339 if (md.rot.num_regs > 0 8340 && num > 31 8341 && num < 31 + md.rot.num_regs) 8342 { 8343 specs[count] = tmpl; 8344 specs[count++].specific = 0; 8345 } 8346 } 8347 else if (idesc->operands[i] == IA64_OPND_F1 8348 || idesc->operands[i] == IA64_OPND_F2 8349 || idesc->operands[i] == IA64_OPND_F3 8350 || idesc->operands[i] == IA64_OPND_F4) 8351 { 8352 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; 8353 if (num > 31) 8354 { 8355 specs[count] = tmpl; 8356 specs[count++].specific = 0; 8357 } 8358 } 8359 else if (idesc->operands[i] == IA64_OPND_P1 8360 || idesc->operands[i] == IA64_OPND_P2) 8361 { 8362 int num = CURR_SLOT.opnd[i].X_add_number - REG_P; 8363 if (num > 15) 8364 { 8365 specs[count] = tmpl; 8366 specs[count++].specific = 0; 8367 } 8368 } 8369 } 8370 if (CURR_SLOT.qp_regno > 15) 8371 { 8372 specs[count] = tmpl; 8373 specs[count++].specific = 0; 8374 } 8375 } 8376 break; 8377 8378 /* This is the same as IA64_RS_PRr, except simplified to account for 8379 the fact that there is only one register. */ 8380 case IA64_RS_PR63: 8381 if (note == 0) 8382 { 8383 specs[count++] = tmpl; 8384 } 8385 else if (note == 7) 8386 { 8387 valueT mask = 0; 8388 if (idesc->operands[2] == IA64_OPND_IMM17) 8389 mask = CURR_SLOT.opnd[2].X_add_number; 8390 if (mask & ((valueT) 1 << 63)) 8391 specs[count++] = tmpl; 8392 } 8393 else if (note == 11) 8394 { 8395 if ((idesc->operands[0] == IA64_OPND_P1 8396 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) 8397 || (idesc->operands[1] == IA64_OPND_P2 8398 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) 8399 { 8400 specs[count++] = tmpl; 8401 } 8402 } 8403 else if (note == 12) 8404 { 8405 if (CURR_SLOT.qp_regno == 63) 8406 { 8407 specs[count++] = tmpl; 8408 } 8409 } 8410 else if (note == 1) 8411 { 8412 if (rsrc_write) 8413 { 8414 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8415 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8416 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 8417 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 8418 8419 if (p1 == 63 8420 && (idesc->operands[0] == IA64_OPND_P1 8421 || idesc->operands[0] == IA64_OPND_P2)) 8422 { 8423 specs[count] = tmpl; 8424 specs[count++].cmp_type = 8425 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 8426 } 8427 if (p2 == 63 8428 && (idesc->operands[1] == IA64_OPND_P1 8429 || idesc->operands[1] == IA64_OPND_P2)) 8430 { 8431 specs[count] = tmpl; 8432 specs[count++].cmp_type = 8433 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 8434 } 8435 } 8436 else 8437 { 8438 if (CURR_SLOT.qp_regno == 63) 8439 { 8440 specs[count++] = tmpl; 8441 } 8442 } 8443 } 8444 else 8445 { 8446 UNHANDLED; 8447 } 8448 break; 8449 8450 case IA64_RS_RSE: 8451 /* FIXME we can identify some individual RSE written resources, but RSE 8452 read resources have not yet been completely identified, so for now 8453 treat RSE as a single resource */ 8454 if (strncmp (idesc->name, "mov", 3) == 0) 8455 { 8456 if (rsrc_write) 8457 { 8458 if (idesc->operands[0] == IA64_OPND_AR3 8459 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) 8460 { 8461 specs[count] = tmpl; 8462 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ 8463 } 8464 } 8465 else 8466 { 8467 if (idesc->operands[0] == IA64_OPND_AR3) 8468 { 8469 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE 8470 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) 8471 { 8472 specs[count++] = tmpl; 8473 } 8474 } 8475 else if (idesc->operands[1] == IA64_OPND_AR3) 8476 { 8477 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP 8478 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE 8479 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) 8480 { 8481 specs[count++] = tmpl; 8482 } 8483 } 8484 } 8485 } 8486 else 8487 { 8488 specs[count++] = tmpl; 8489 } 8490 break; 8491 8492 case IA64_RS_ANY: 8493 /* FIXME -- do any of these need to be non-specific? */ 8494 specs[count++] = tmpl; 8495 break; 8496 8497 default: 8498 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); 8499 break; 8500 } 8501 8502 return count; 8503} 8504 8505/* Clear branch flags on marked resources. This breaks the link between the 8506 QP of the marking instruction and a subsequent branch on the same QP. */ 8507 8508static void 8509clear_qp_branch_flag (mask) 8510 valueT mask; 8511{ 8512 int i; 8513 for (i = 0; i < regdepslen; i++) 8514 { 8515 valueT bit = ((valueT) 1 << regdeps[i].qp_regno); 8516 if ((bit & mask) != 0) 8517 { 8518 regdeps[i].link_to_qp_branch = 0; 8519 } 8520 } 8521} 8522 8523/* Remove any mutexes which contain any of the PRs indicated in the mask. 8524 8525 Any changes to a PR clears the mutex relations which include that PR. */ 8526 8527static void 8528clear_qp_mutex (mask) 8529 valueT mask; 8530{ 8531 int i; 8532 8533 i = 0; 8534 while (i < qp_mutexeslen) 8535 { 8536 if ((qp_mutexes[i].prmask & mask) != 0) 8537 { 8538 if (md.debug_dv) 8539 { 8540 fprintf (stderr, " Clearing mutex relation"); 8541 print_prmask (qp_mutexes[i].prmask); 8542 fprintf (stderr, "\n"); 8543 } 8544 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; 8545 } 8546 else 8547 ++i; 8548 } 8549} 8550 8551/* Clear implies relations which contain PRs in the given masks. 8552 P1_MASK indicates the source of the implies relation, while P2_MASK 8553 indicates the implied PR. */ 8554 8555static void 8556clear_qp_implies (p1_mask, p2_mask) 8557 valueT p1_mask; 8558 valueT p2_mask; 8559{ 8560 int i; 8561 8562 i = 0; 8563 while (i < qp_implieslen) 8564 { 8565 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 8566 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) 8567 { 8568 if (md.debug_dv) 8569 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", 8570 qp_implies[i].p1, qp_implies[i].p2); 8571 qp_implies[i] = qp_implies[--qp_implieslen]; 8572 } 8573 else 8574 ++i; 8575 } 8576} 8577 8578/* Add the PRs specified to the list of implied relations. */ 8579 8580static void 8581add_qp_imply (p1, p2) 8582 int p1, p2; 8583{ 8584 valueT mask; 8585 valueT bit; 8586 int i; 8587 8588 /* p0 is not meaningful here. */ 8589 if (p1 == 0 || p2 == 0) 8590 abort (); 8591 8592 if (p1 == p2) 8593 return; 8594 8595 /* If it exists already, ignore it. */ 8596 for (i = 0; i < qp_implieslen; i++) 8597 { 8598 if (qp_implies[i].p1 == p1 8599 && qp_implies[i].p2 == p2 8600 && qp_implies[i].path == md.path 8601 && !qp_implies[i].p2_branched) 8602 return; 8603 } 8604 8605 if (qp_implieslen == qp_impliestotlen) 8606 { 8607 qp_impliestotlen += 20; 8608 qp_implies = (struct qp_imply *) 8609 xrealloc ((void *) qp_implies, 8610 qp_impliestotlen * sizeof (struct qp_imply)); 8611 } 8612 if (md.debug_dv) 8613 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); 8614 qp_implies[qp_implieslen].p1 = p1; 8615 qp_implies[qp_implieslen].p2 = p2; 8616 qp_implies[qp_implieslen].path = md.path; 8617 qp_implies[qp_implieslen++].p2_branched = 0; 8618 8619 /* Add in the implied transitive relations; for everything that p2 implies, 8620 make p1 imply that, too; for everything that implies p1, make it imply p2 8621 as well. */ 8622 for (i = 0; i < qp_implieslen; i++) 8623 { 8624 if (qp_implies[i].p1 == p2) 8625 add_qp_imply (p1, qp_implies[i].p2); 8626 if (qp_implies[i].p2 == p1) 8627 add_qp_imply (qp_implies[i].p1, p2); 8628 } 8629 /* Add in mutex relations implied by this implies relation; for each mutex 8630 relation containing p2, duplicate it and replace p2 with p1. */ 8631 bit = (valueT) 1 << p1; 8632 mask = (valueT) 1 << p2; 8633 for (i = 0; i < qp_mutexeslen; i++) 8634 { 8635 if (qp_mutexes[i].prmask & mask) 8636 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); 8637 } 8638} 8639 8640/* Add the PRs specified in the mask to the mutex list; this means that only 8641 one of the PRs can be true at any time. PR0 should never be included in 8642 the mask. */ 8643 8644static void 8645add_qp_mutex (mask) 8646 valueT mask; 8647{ 8648 if (mask & 0x1) 8649 abort (); 8650 8651 if (qp_mutexeslen == qp_mutexestotlen) 8652 { 8653 qp_mutexestotlen += 20; 8654 qp_mutexes = (struct qpmutex *) 8655 xrealloc ((void *) qp_mutexes, 8656 qp_mutexestotlen * sizeof (struct qpmutex)); 8657 } 8658 if (md.debug_dv) 8659 { 8660 fprintf (stderr, " Registering mutex on"); 8661 print_prmask (mask); 8662 fprintf (stderr, "\n"); 8663 } 8664 qp_mutexes[qp_mutexeslen].path = md.path; 8665 qp_mutexes[qp_mutexeslen++].prmask = mask; 8666} 8667 8668static int 8669has_suffix_p (name, suffix) 8670 const char *name; 8671 const char *suffix; 8672{ 8673 size_t namelen = strlen (name); 8674 size_t sufflen = strlen (suffix); 8675 8676 if (namelen <= sufflen) 8677 return 0; 8678 return strcmp (name + namelen - sufflen, suffix) == 0; 8679} 8680 8681static void 8682clear_register_values () 8683{ 8684 int i; 8685 if (md.debug_dv) 8686 fprintf (stderr, " Clearing register values\n"); 8687 for (i = 1; i < NELEMS (gr_values); i++) 8688 gr_values[i].known = 0; 8689} 8690 8691/* Keep track of register values/changes which affect DV tracking. 8692 8693 optimization note: should add a flag to classes of insns where otherwise we 8694 have to examine a group of strings to identify them. */ 8695 8696static void 8697note_register_values (idesc) 8698 struct ia64_opcode *idesc; 8699{ 8700 valueT qp_changemask = 0; 8701 int i; 8702 8703 /* Invalidate values for registers being written to. */ 8704 for (i = 0; i < idesc->num_outputs; i++) 8705 { 8706 if (idesc->operands[i] == IA64_OPND_R1 8707 || idesc->operands[i] == IA64_OPND_R2 8708 || idesc->operands[i] == IA64_OPND_R3) 8709 { 8710 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8711 if (regno > 0 && regno < NELEMS (gr_values)) 8712 gr_values[regno].known = 0; 8713 } 8714 else if (idesc->operands[i] == IA64_OPND_R3_2) 8715 { 8716 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 8717 if (regno > 0 && regno < 4) 8718 gr_values[regno].known = 0; 8719 } 8720 else if (idesc->operands[i] == IA64_OPND_P1 8721 || idesc->operands[i] == IA64_OPND_P2) 8722 { 8723 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 8724 qp_changemask |= (valueT) 1 << regno; 8725 } 8726 else if (idesc->operands[i] == IA64_OPND_PR) 8727 { 8728 if (idesc->operands[2] & (valueT) 0x10000) 8729 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; 8730 else 8731 qp_changemask = idesc->operands[2]; 8732 break; 8733 } 8734 else if (idesc->operands[i] == IA64_OPND_PR_ROT) 8735 { 8736 if (idesc->operands[1] & ((valueT) 1 << 43)) 8737 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; 8738 else 8739 qp_changemask = idesc->operands[1]; 8740 qp_changemask &= ~(valueT) 0xFFFF; 8741 break; 8742 } 8743 } 8744 8745 /* Always clear qp branch flags on any PR change. */ 8746 /* FIXME there may be exceptions for certain compares. */ 8747 clear_qp_branch_flag (qp_changemask); 8748 8749 /* Invalidate rotating registers on insns which affect RRBs in CFM. */ 8750 if (idesc->flags & IA64_OPCODE_MOD_RRBS) 8751 { 8752 qp_changemask |= ~(valueT) 0xFFFF; 8753 if (strcmp (idesc->name, "clrrrb.pr") != 0) 8754 { 8755 for (i = 32; i < 32 + md.rot.num_regs; i++) 8756 gr_values[i].known = 0; 8757 } 8758 clear_qp_mutex (qp_changemask); 8759 clear_qp_implies (qp_changemask, qp_changemask); 8760 } 8761 /* After a call, all register values are undefined, except those marked 8762 as "safe". */ 8763 else if (strncmp (idesc->name, "br.call", 6) == 0 8764 || strncmp (idesc->name, "brl.call", 7) == 0) 8765 { 8766 /* FIXME keep GR values which are marked as "safe_across_calls" */ 8767 clear_register_values (); 8768 clear_qp_mutex (~qp_safe_across_calls); 8769 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); 8770 clear_qp_branch_flag (~qp_safe_across_calls); 8771 } 8772 else if (is_interruption_or_rfi (idesc) 8773 || is_taken_branch (idesc)) 8774 { 8775 clear_register_values (); 8776 clear_qp_mutex (~(valueT) 0); 8777 clear_qp_implies (~(valueT) 0, ~(valueT) 0); 8778 } 8779 /* Look for mutex and implies relations. */ 8780 else if ((idesc->operands[0] == IA64_OPND_P1 8781 || idesc->operands[0] == IA64_OPND_P2) 8782 && (idesc->operands[1] == IA64_OPND_P1 8783 || idesc->operands[1] == IA64_OPND_P2)) 8784 { 8785 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8786 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8787 valueT p1mask = (valueT) 1 << p1; 8788 valueT p2mask = (valueT) 1 << p2; 8789 8790 /* If one of the PRs is PR0, we can't really do anything. */ 8791 if (p1 == 0 || p2 == 0) 8792 { 8793 if (md.debug_dv) 8794 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); 8795 } 8796 /* In general, clear mutexes and implies which include P1 or P2, 8797 with the following exceptions. */ 8798 else if (has_suffix_p (idesc->name, ".or.andcm") 8799 || has_suffix_p (idesc->name, ".and.orcm")) 8800 { 8801 add_qp_mutex (p1mask | p2mask); 8802 clear_qp_implies (p2mask, p1mask); 8803 } 8804 else if (has_suffix_p (idesc->name, ".andcm") 8805 || has_suffix_p (idesc->name, ".and")) 8806 { 8807 clear_qp_implies (0, p1mask | p2mask); 8808 } 8809 else if (has_suffix_p (idesc->name, ".orcm") 8810 || has_suffix_p (idesc->name, ".or")) 8811 { 8812 clear_qp_mutex (p1mask | p2mask); 8813 clear_qp_implies (p1mask | p2mask, 0); 8814 } 8815 else 8816 { 8817 clear_qp_implies (p1mask | p2mask, p1mask | p2mask); 8818 if (has_suffix_p (idesc->name, ".unc")) 8819 { 8820 add_qp_mutex (p1mask | p2mask); 8821 if (CURR_SLOT.qp_regno != 0) 8822 { 8823 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, 8824 CURR_SLOT.qp_regno); 8825 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, 8826 CURR_SLOT.qp_regno); 8827 } 8828 } 8829 else if (CURR_SLOT.qp_regno == 0) 8830 { 8831 add_qp_mutex (p1mask | p2mask); 8832 } 8833 else 8834 { 8835 clear_qp_mutex (p1mask | p2mask); 8836 } 8837 } 8838 } 8839 /* Look for mov imm insns into GRs. */ 8840 else if (idesc->operands[0] == IA64_OPND_R1 8841 && (idesc->operands[1] == IA64_OPND_IMM22 8842 || idesc->operands[1] == IA64_OPND_IMMU64) 8843 && (strcmp (idesc->name, "mov") == 0 8844 || strcmp (idesc->name, "movl") == 0)) 8845 { 8846 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; 8847 if (regno > 0 && regno < NELEMS (gr_values)) 8848 { 8849 gr_values[regno].known = 1; 8850 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; 8851 gr_values[regno].path = md.path; 8852 if (md.debug_dv) 8853 { 8854 fprintf (stderr, " Know gr%d = ", regno); 8855 fprintf_vma (stderr, gr_values[regno].value); 8856 fputs ("\n", stderr); 8857 } 8858 } 8859 } 8860 else 8861 { 8862 clear_qp_mutex (qp_changemask); 8863 clear_qp_implies (qp_changemask, qp_changemask); 8864 } 8865} 8866 8867/* Return whether the given predicate registers are currently mutex. */ 8868 8869static int 8870qp_mutex (p1, p2, path) 8871 int p1; 8872 int p2; 8873 int path; 8874{ 8875 int i; 8876 valueT mask; 8877 8878 if (p1 != p2) 8879 { 8880 mask = ((valueT) 1 << p1) | (valueT) 1 << p2; 8881 for (i = 0; i < qp_mutexeslen; i++) 8882 { 8883 if (qp_mutexes[i].path >= path 8884 && (qp_mutexes[i].prmask & mask) == mask) 8885 return 1; 8886 } 8887 } 8888 return 0; 8889} 8890 8891/* Return whether the given resource is in the given insn's list of chks 8892 Return 1 if the conflict is absolutely determined, 2 if it's a potential 8893 conflict. */ 8894 8895static int 8896resources_match (rs, idesc, note, qp_regno, path) 8897 struct rsrc *rs; 8898 struct ia64_opcode *idesc; 8899 int note; 8900 int qp_regno; 8901 int path; 8902{ 8903 struct rsrc specs[MAX_SPECS]; 8904 int count; 8905 8906 /* If the marked resource's qp_regno and the given qp_regno are mutex, 8907 we don't need to check. One exception is note 11, which indicates that 8908 target predicates are written regardless of PR[qp]. */ 8909 if (qp_mutex (rs->qp_regno, qp_regno, path) 8910 && note != 11) 8911 return 0; 8912 8913 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); 8914 while (count-- > 0) 8915 { 8916 /* UNAT checking is a bit more specific than other resources */ 8917 if (rs->dependency->specifier == IA64_RS_AR_UNAT 8918 && specs[count].mem_offset.hint 8919 && rs->mem_offset.hint) 8920 { 8921 if (rs->mem_offset.base == specs[count].mem_offset.base) 8922 { 8923 if (((rs->mem_offset.offset >> 3) & 0x3F) == 8924 ((specs[count].mem_offset.offset >> 3) & 0x3F)) 8925 return 1; 8926 else 8927 continue; 8928 } 8929 } 8930 8931 /* Skip apparent PR write conflicts where both writes are an AND or both 8932 writes are an OR. */ 8933 if (rs->dependency->specifier == IA64_RS_PR 8934 || rs->dependency->specifier == IA64_RS_PRr 8935 || rs->dependency->specifier == IA64_RS_PR63) 8936 { 8937 if (specs[count].cmp_type != CMP_NONE 8938 && specs[count].cmp_type == rs->cmp_type) 8939 { 8940 if (md.debug_dv) 8941 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", 8942 dv_mode[rs->dependency->mode], 8943 rs->dependency->specifier != IA64_RS_PR63 ? 8944 specs[count].index : 63); 8945 continue; 8946 } 8947 if (md.debug_dv) 8948 fprintf (stderr, 8949 " %s on parallel compare conflict %s vs %s on PR%d\n", 8950 dv_mode[rs->dependency->mode], 8951 dv_cmp_type[rs->cmp_type], 8952 dv_cmp_type[specs[count].cmp_type], 8953 rs->dependency->specifier != IA64_RS_PR63 ? 8954 specs[count].index : 63); 8955 8956 } 8957 8958 /* If either resource is not specific, conservatively assume a conflict 8959 */ 8960 if (!specs[count].specific || !rs->specific) 8961 return 2; 8962 else if (specs[count].index == rs->index) 8963 return 1; 8964 } 8965#if 0 8966 if (md.debug_dv) 8967 fprintf (stderr, " No %s conflicts\n", rs->dependency->name); 8968#endif 8969 8970 return 0; 8971} 8972 8973/* Indicate an instruction group break; if INSERT_STOP is non-zero, then 8974 insert a stop to create the break. Update all resource dependencies 8975 appropriately. If QP_REGNO is non-zero, only apply the break to resources 8976 which use the same QP_REGNO and have the link_to_qp_branch flag set. 8977 If SAVE_CURRENT is non-zero, don't affect resources marked by the current 8978 instruction. */ 8979 8980static void 8981insn_group_break (insert_stop, qp_regno, save_current) 8982 int insert_stop; 8983 int qp_regno; 8984 int save_current; 8985{ 8986 int i; 8987 8988 if (insert_stop && md.num_slots_in_use > 0) 8989 PREV_SLOT.end_of_insn_group = 1; 8990 8991 if (md.debug_dv) 8992 { 8993 fprintf (stderr, " Insn group break%s", 8994 (insert_stop ? " (w/stop)" : "")); 8995 if (qp_regno != 0) 8996 fprintf (stderr, " effective for QP=%d", qp_regno); 8997 fprintf (stderr, "\n"); 8998 } 8999 9000 i = 0; 9001 while (i < regdepslen) 9002 { 9003 const struct ia64_dependency *dep = regdeps[i].dependency; 9004 9005 if (qp_regno != 0 9006 && regdeps[i].qp_regno != qp_regno) 9007 { 9008 ++i; 9009 continue; 9010 } 9011 9012 if (save_current 9013 && CURR_SLOT.src_file == regdeps[i].file 9014 && CURR_SLOT.src_line == regdeps[i].line) 9015 { 9016 ++i; 9017 continue; 9018 } 9019 9020 /* clear dependencies which are automatically cleared by a stop, or 9021 those that have reached the appropriate state of insn serialization */ 9022 if (dep->semantics == IA64_DVS_IMPLIED 9023 || dep->semantics == IA64_DVS_IMPLIEDF 9024 || regdeps[i].insn_srlz == STATE_SRLZ) 9025 { 9026 print_dependency ("Removing", i); 9027 regdeps[i] = regdeps[--regdepslen]; 9028 } 9029 else 9030 { 9031 if (dep->semantics == IA64_DVS_DATA 9032 || dep->semantics == IA64_DVS_INSTR 9033 || dep->semantics == IA64_DVS_SPECIFIC) 9034 { 9035 if (regdeps[i].insn_srlz == STATE_NONE) 9036 regdeps[i].insn_srlz = STATE_STOP; 9037 if (regdeps[i].data_srlz == STATE_NONE) 9038 regdeps[i].data_srlz = STATE_STOP; 9039 } 9040 ++i; 9041 } 9042 } 9043} 9044 9045/* Add the given resource usage spec to the list of active dependencies. */ 9046 9047static void 9048mark_resource (idesc, dep, spec, depind, path) 9049 struct ia64_opcode *idesc ATTRIBUTE_UNUSED; 9050 const struct ia64_dependency *dep ATTRIBUTE_UNUSED; 9051 struct rsrc *spec; 9052 int depind; 9053 int path; 9054{ 9055 if (regdepslen == regdepstotlen) 9056 { 9057 regdepstotlen += 20; 9058 regdeps = (struct rsrc *) 9059 xrealloc ((void *) regdeps, 9060 regdepstotlen * sizeof (struct rsrc)); 9061 } 9062 9063 regdeps[regdepslen] = *spec; 9064 regdeps[regdepslen].depind = depind; 9065 regdeps[regdepslen].path = path; 9066 regdeps[regdepslen].file = CURR_SLOT.src_file; 9067 regdeps[regdepslen].line = CURR_SLOT.src_line; 9068 9069 print_dependency ("Adding", regdepslen); 9070 9071 ++regdepslen; 9072} 9073 9074static void 9075print_dependency (action, depind) 9076 const char *action; 9077 int depind; 9078{ 9079 if (md.debug_dv) 9080 { 9081 fprintf (stderr, " %s %s '%s'", 9082 action, dv_mode[(regdeps[depind].dependency)->mode], 9083 (regdeps[depind].dependency)->name); 9084 if (regdeps[depind].specific && regdeps[depind].index != 0) 9085 fprintf (stderr, " (%d)", regdeps[depind].index); 9086 if (regdeps[depind].mem_offset.hint) 9087 { 9088 fputs (" ", stderr); 9089 fprintf_vma (stderr, regdeps[depind].mem_offset.base); 9090 fputs ("+", stderr); 9091 fprintf_vma (stderr, regdeps[depind].mem_offset.offset); 9092 } 9093 fprintf (stderr, "\n"); 9094 } 9095} 9096 9097static void 9098instruction_serialization () 9099{ 9100 int i; 9101 if (md.debug_dv) 9102 fprintf (stderr, " Instruction serialization\n"); 9103 for (i = 0; i < regdepslen; i++) 9104 if (regdeps[i].insn_srlz == STATE_STOP) 9105 regdeps[i].insn_srlz = STATE_SRLZ; 9106} 9107 9108static void 9109data_serialization () 9110{ 9111 int i = 0; 9112 if (md.debug_dv) 9113 fprintf (stderr, " Data serialization\n"); 9114 while (i < regdepslen) 9115 { 9116 if (regdeps[i].data_srlz == STATE_STOP 9117 /* Note: as of 991210, all "other" dependencies are cleared by a 9118 data serialization. This might change with new tables */ 9119 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) 9120 { 9121 print_dependency ("Removing", i); 9122 regdeps[i] = regdeps[--regdepslen]; 9123 } 9124 else 9125 ++i; 9126 } 9127} 9128 9129/* Insert stops and serializations as needed to avoid DVs. */ 9130 9131static void 9132remove_marked_resource (rs) 9133 struct rsrc *rs; 9134{ 9135 switch (rs->dependency->semantics) 9136 { 9137 case IA64_DVS_SPECIFIC: 9138 if (md.debug_dv) 9139 fprintf (stderr, "Implementation-specific, assume worst case...\n"); 9140 /* ...fall through... */ 9141 case IA64_DVS_INSTR: 9142 if (md.debug_dv) 9143 fprintf (stderr, "Inserting instr serialization\n"); 9144 if (rs->insn_srlz < STATE_STOP) 9145 insn_group_break (1, 0, 0); 9146 if (rs->insn_srlz < STATE_SRLZ) 9147 { 9148 int oldqp = CURR_SLOT.qp_regno; 9149 struct ia64_opcode *oldidesc = CURR_SLOT.idesc; 9150 /* Manually jam a srlz.i insn into the stream */ 9151 CURR_SLOT.qp_regno = 0; 9152 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); 9153 instruction_serialization (); 9154 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9155 if (++md.num_slots_in_use >= NUM_SLOTS) 9156 emit_one_bundle (); 9157 CURR_SLOT.qp_regno = oldqp; 9158 CURR_SLOT.idesc = oldidesc; 9159 } 9160 insn_group_break (1, 0, 0); 9161 break; 9162 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all 9163 "other" types of DV are eliminated 9164 by a data serialization */ 9165 case IA64_DVS_DATA: 9166 if (md.debug_dv) 9167 fprintf (stderr, "Inserting data serialization\n"); 9168 if (rs->data_srlz < STATE_STOP) 9169 insn_group_break (1, 0, 0); 9170 { 9171 int oldqp = CURR_SLOT.qp_regno; 9172 struct ia64_opcode *oldidesc = CURR_SLOT.idesc; 9173 /* Manually jam a srlz.d insn into the stream */ 9174 CURR_SLOT.qp_regno = 0; 9175 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); 9176 data_serialization (); 9177 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9178 if (++md.num_slots_in_use >= NUM_SLOTS) 9179 emit_one_bundle (); 9180 CURR_SLOT.qp_regno = oldqp; 9181 CURR_SLOT.idesc = oldidesc; 9182 } 9183 break; 9184 case IA64_DVS_IMPLIED: 9185 case IA64_DVS_IMPLIEDF: 9186 if (md.debug_dv) 9187 fprintf (stderr, "Inserting stop\n"); 9188 insn_group_break (1, 0, 0); 9189 break; 9190 default: 9191 break; 9192 } 9193} 9194 9195/* Check the resources used by the given opcode against the current dependency 9196 list. 9197 9198 The check is run once for each execution path encountered. In this case, 9199 a unique execution path is the sequence of instructions following a code 9200 entry point, e.g. the following has three execution paths, one starting 9201 at L0, one at L1, and one at L2. 9202 9203 L0: nop 9204 L1: add 9205 L2: add 9206 br.ret 9207*/ 9208 9209static void 9210check_dependencies (idesc) 9211 struct ia64_opcode *idesc; 9212{ 9213 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 9214 int path; 9215 int i; 9216 9217 /* Note that the number of marked resources may change within the 9218 loop if in auto mode. */ 9219 i = 0; 9220 while (i < regdepslen) 9221 { 9222 struct rsrc *rs = ®deps[i]; 9223 const struct ia64_dependency *dep = rs->dependency; 9224 int chkind; 9225 int note; 9226 int start_over = 0; 9227 9228 if (dep->semantics == IA64_DVS_NONE 9229 || (chkind = depends_on (rs->depind, idesc)) == -1) 9230 { 9231 ++i; 9232 continue; 9233 } 9234 9235 note = NOTE (opdeps->chks[chkind]); 9236 9237 /* Check this resource against each execution path seen thus far. */ 9238 for (path = 0; path <= md.path; path++) 9239 { 9240 int matchtype; 9241 9242 /* If the dependency wasn't on the path being checked, ignore it. */ 9243 if (rs->path < path) 9244 continue; 9245 9246 /* If the QP for this insn implies a QP which has branched, don't 9247 bother checking. Ed. NOTE: I don't think this check is terribly 9248 useful; what's the point of generating code which will only be 9249 reached if its QP is zero? 9250 This code was specifically inserted to handle the following code, 9251 based on notes from Intel's DV checking code, where p1 implies p2. 9252 9253 mov r4 = 2 9254 (p2) br.cond L 9255 (p1) mov r4 = 7 9256 */ 9257 if (CURR_SLOT.qp_regno != 0) 9258 { 9259 int skip = 0; 9260 int implies; 9261 for (implies = 0; implies < qp_implieslen; implies++) 9262 { 9263 if (qp_implies[implies].path >= path 9264 && qp_implies[implies].p1 == CURR_SLOT.qp_regno 9265 && qp_implies[implies].p2_branched) 9266 { 9267 skip = 1; 9268 break; 9269 } 9270 } 9271 if (skip) 9272 continue; 9273 } 9274 9275 if ((matchtype = resources_match (rs, idesc, note, 9276 CURR_SLOT.qp_regno, path)) != 0) 9277 { 9278 char msg[1024]; 9279 char pathmsg[256] = ""; 9280 char indexmsg[256] = ""; 9281 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); 9282 9283 if (path != 0) 9284 sprintf (pathmsg, " when entry is at label '%s'", 9285 md.entry_labels[path - 1]); 9286 if (rs->specific && rs->index != 0) 9287 sprintf (indexmsg, ", specific resource number is %d", 9288 rs->index); 9289 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", 9290 idesc->name, 9291 (certain ? "violates" : "may violate"), 9292 dv_mode[dep->mode], dep->name, 9293 dv_sem[dep->semantics], 9294 pathmsg, indexmsg); 9295 9296 if (md.explicit_mode) 9297 { 9298 as_warn ("%s", msg); 9299 if (path < md.path) 9300 as_warn (_("Only the first path encountering the conflict " 9301 "is reported")); 9302 as_warn_where (rs->file, rs->line, 9303 _("This is the location of the " 9304 "conflicting usage")); 9305 /* Don't bother checking other paths, to avoid duplicating 9306 the same warning */ 9307 break; 9308 } 9309 else 9310 { 9311 if (md.debug_dv) 9312 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); 9313 9314 remove_marked_resource (rs); 9315 9316 /* since the set of dependencies has changed, start over */ 9317 /* FIXME -- since we're removing dvs as we go, we 9318 probably don't really need to start over... */ 9319 start_over = 1; 9320 break; 9321 } 9322 } 9323 } 9324 if (start_over) 9325 i = 0; 9326 else 9327 ++i; 9328 } 9329} 9330 9331/* Register new dependencies based on the given opcode. */ 9332 9333static void 9334mark_resources (idesc) 9335 struct ia64_opcode *idesc; 9336{ 9337 int i; 9338 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 9339 int add_only_qp_reads = 0; 9340 9341 /* A conditional branch only uses its resources if it is taken; if it is 9342 taken, we stop following that path. The other branch types effectively 9343 *always* write their resources. If it's not taken, register only QP 9344 reads. */ 9345 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) 9346 { 9347 add_only_qp_reads = 1; 9348 } 9349 9350 if (md.debug_dv) 9351 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); 9352 9353 for (i = 0; i < opdeps->nregs; i++) 9354 { 9355 const struct ia64_dependency *dep; 9356 struct rsrc specs[MAX_SPECS]; 9357 int note; 9358 int path; 9359 int count; 9360 9361 dep = ia64_find_dependency (opdeps->regs[i]); 9362 note = NOTE (opdeps->regs[i]); 9363 9364 if (add_only_qp_reads 9365 && !(dep->mode == IA64_DV_WAR 9366 && (dep->specifier == IA64_RS_PR 9367 || dep->specifier == IA64_RS_PRr 9368 || dep->specifier == IA64_RS_PR63))) 9369 continue; 9370 9371 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); 9372 9373#if 0 9374 if (md.debug_dv && !count) 9375 fprintf (stderr, " No %s %s usage found (path %d)\n", 9376 dv_mode[dep->mode], dep->name, md.path); 9377#endif 9378 9379 while (count-- > 0) 9380 { 9381 mark_resource (idesc, dep, &specs[count], 9382 DEP (opdeps->regs[i]), md.path); 9383 } 9384 9385 /* The execution path may affect register values, which may in turn 9386 affect which indirect-access resources are accessed. */ 9387 switch (dep->specifier) 9388 { 9389 default: 9390 break; 9391 case IA64_RS_CPUID: 9392 case IA64_RS_DBR: 9393 case IA64_RS_IBR: 9394 case IA64_RS_MSR: 9395 case IA64_RS_PKR: 9396 case IA64_RS_PMC: 9397 case IA64_RS_PMD: 9398 case IA64_RS_RR: 9399 for (path = 0; path < md.path; path++) 9400 { 9401 count = specify_resource (dep, idesc, DV_REG, specs, note, path); 9402 while (count-- > 0) 9403 mark_resource (idesc, dep, &specs[count], 9404 DEP (opdeps->regs[i]), path); 9405 } 9406 break; 9407 } 9408 } 9409} 9410 9411/* Remove dependencies when they no longer apply. */ 9412 9413static void 9414update_dependencies (idesc) 9415 struct ia64_opcode *idesc; 9416{ 9417 int i; 9418 9419 if (strcmp (idesc->name, "srlz.i") == 0) 9420 { 9421 instruction_serialization (); 9422 } 9423 else if (strcmp (idesc->name, "srlz.d") == 0) 9424 { 9425 data_serialization (); 9426 } 9427 else if (is_interruption_or_rfi (idesc) 9428 || is_taken_branch (idesc)) 9429 { 9430 /* Although technically the taken branch doesn't clear dependencies 9431 which require a srlz.[id], we don't follow the branch; the next 9432 instruction is assumed to start with a clean slate. */ 9433 regdepslen = 0; 9434 md.path = 0; 9435 } 9436 else if (is_conditional_branch (idesc) 9437 && CURR_SLOT.qp_regno != 0) 9438 { 9439 int is_call = strstr (idesc->name, ".call") != NULL; 9440 9441 for (i = 0; i < qp_implieslen; i++) 9442 { 9443 /* If the conditional branch's predicate is implied by the predicate 9444 in an existing dependency, remove that dependency. */ 9445 if (qp_implies[i].p2 == CURR_SLOT.qp_regno) 9446 { 9447 int depind = 0; 9448 /* Note that this implied predicate takes a branch so that if 9449 a later insn generates a DV but its predicate implies this 9450 one, we can avoid the false DV warning. */ 9451 qp_implies[i].p2_branched = 1; 9452 while (depind < regdepslen) 9453 { 9454 if (regdeps[depind].qp_regno == qp_implies[i].p1) 9455 { 9456 print_dependency ("Removing", depind); 9457 regdeps[depind] = regdeps[--regdepslen]; 9458 } 9459 else 9460 ++depind; 9461 } 9462 } 9463 } 9464 /* Any marked resources which have this same predicate should be 9465 cleared, provided that the QP hasn't been modified between the 9466 marking instruction and the branch. */ 9467 if (is_call) 9468 { 9469 insn_group_break (0, CURR_SLOT.qp_regno, 1); 9470 } 9471 else 9472 { 9473 i = 0; 9474 while (i < regdepslen) 9475 { 9476 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno 9477 && regdeps[i].link_to_qp_branch 9478 && (regdeps[i].file != CURR_SLOT.src_file 9479 || regdeps[i].line != CURR_SLOT.src_line)) 9480 { 9481 /* Treat like a taken branch */ 9482 print_dependency ("Removing", i); 9483 regdeps[i] = regdeps[--regdepslen]; 9484 } 9485 else 9486 ++i; 9487 } 9488 } 9489 } 9490} 9491 9492/* Examine the current instruction for dependency violations. */ 9493 9494static int 9495check_dv (idesc) 9496 struct ia64_opcode *idesc; 9497{ 9498 if (md.debug_dv) 9499 { 9500 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", 9501 idesc->name, CURR_SLOT.src_line, 9502 idesc->dependencies->nchks, 9503 idesc->dependencies->nregs); 9504 } 9505 9506 /* Look through the list of currently marked resources; if the current 9507 instruction has the dependency in its chks list which uses that resource, 9508 check against the specific resources used. */ 9509 check_dependencies (idesc); 9510 9511 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), 9512 then add them to the list of marked resources. */ 9513 mark_resources (idesc); 9514 9515 /* There are several types of dependency semantics, and each has its own 9516 requirements for being cleared 9517 9518 Instruction serialization (insns separated by interruption, rfi, or 9519 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. 9520 9521 Data serialization (instruction serialization, or writer + srlz.d + 9522 reader, where writer and srlz.d are in separate groups) clears 9523 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to 9524 always be the case). 9525 9526 Instruction group break (groups separated by stop, taken branch, 9527 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. 9528 */ 9529 update_dependencies (idesc); 9530 9531 /* Sometimes, knowing a register value allows us to avoid giving a false DV 9532 warning. Keep track of as many as possible that are useful. */ 9533 note_register_values (idesc); 9534 9535 /* We don't need or want this anymore. */ 9536 md.mem_offset.hint = 0; 9537 9538 return 0; 9539} 9540 9541/* Translate one line of assembly. Pseudo ops and labels do not show 9542 here. */ 9543void 9544md_assemble (str) 9545 char *str; 9546{ 9547 char *saved_input_line_pointer, *mnemonic; 9548 const struct pseudo_opcode *pdesc; 9549 struct ia64_opcode *idesc; 9550 unsigned char qp_regno; 9551 unsigned int flags; 9552 int ch; 9553 9554 saved_input_line_pointer = input_line_pointer; 9555 input_line_pointer = str; 9556 9557 /* extract the opcode (mnemonic): */ 9558 9559 mnemonic = input_line_pointer; 9560 ch = get_symbol_end (); 9561 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); 9562 if (pdesc) 9563 { 9564 *input_line_pointer = ch; 9565 (*pdesc->handler) (pdesc->arg); 9566 goto done; 9567 } 9568 9569 /* Find the instruction descriptor matching the arguments. */ 9570 9571 idesc = ia64_find_opcode (mnemonic); 9572 *input_line_pointer = ch; 9573 if (!idesc) 9574 { 9575 as_bad ("Unknown opcode `%s'", mnemonic); 9576 goto done; 9577 } 9578 9579 idesc = parse_operands (idesc); 9580 if (!idesc) 9581 goto done; 9582 9583 /* Handle the dynamic ops we can handle now: */ 9584 if (idesc->type == IA64_TYPE_DYN) 9585 { 9586 if (strcmp (idesc->name, "add") == 0) 9587 { 9588 if (CURR_SLOT.opnd[2].X_op == O_register 9589 && CURR_SLOT.opnd[2].X_add_number < 4) 9590 mnemonic = "addl"; 9591 else 9592 mnemonic = "adds"; 9593 ia64_free_opcode (idesc); 9594 idesc = ia64_find_opcode (mnemonic); 9595#if 0 9596 know (!idesc->next); 9597#endif 9598 } 9599 else if (strcmp (idesc->name, "mov") == 0) 9600 { 9601 enum ia64_opnd opnd1, opnd2; 9602 int rop; 9603 9604 opnd1 = idesc->operands[0]; 9605 opnd2 = idesc->operands[1]; 9606 if (opnd1 == IA64_OPND_AR3) 9607 rop = 0; 9608 else if (opnd2 == IA64_OPND_AR3) 9609 rop = 1; 9610 else 9611 abort (); 9612 if (CURR_SLOT.opnd[rop].X_op == O_register 9613 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) 9614 mnemonic = "mov.i"; 9615 else 9616 mnemonic = "mov.m"; 9617 ia64_free_opcode (idesc); 9618 idesc = ia64_find_opcode (mnemonic); 9619 while (idesc != NULL 9620 && (idesc->operands[0] != opnd1 9621 || idesc->operands[1] != opnd2)) 9622 idesc = get_next_opcode (idesc); 9623 } 9624 } 9625 9626 qp_regno = 0; 9627 if (md.qp.X_op == O_register) 9628 { 9629 qp_regno = md.qp.X_add_number - REG_P; 9630 md.qp.X_op = O_absent; 9631 } 9632 9633 flags = idesc->flags; 9634 9635 if ((flags & IA64_OPCODE_FIRST) != 0) 9636 insn_group_break (1, 0, 0); 9637 9638 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) 9639 { 9640 as_bad ("`%s' cannot be predicated", idesc->name); 9641 goto done; 9642 } 9643 9644 /* Build the instruction. */ 9645 CURR_SLOT.qp_regno = qp_regno; 9646 CURR_SLOT.idesc = idesc; 9647 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); 9648 dwarf2_where (&CURR_SLOT.debug_line); 9649 9650 /* Add unwind entry, if there is one. */ 9651 if (unwind.current_entry) 9652 { 9653 CURR_SLOT.unwind_record = unwind.current_entry; 9654 unwind.current_entry = NULL; 9655 } 9656 9657 /* Check for dependency violations. */ 9658 if (md.detect_dv) 9659 check_dv (idesc); 9660 9661 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 9662 if (++md.num_slots_in_use >= NUM_SLOTS) 9663 emit_one_bundle (); 9664 9665 if ((flags & IA64_OPCODE_LAST) != 0) 9666 insn_group_break (1, 0, 0); 9667 9668 md.last_text_seg = now_seg; 9669 9670 done: 9671 input_line_pointer = saved_input_line_pointer; 9672} 9673 9674/* Called when symbol NAME cannot be found in the symbol table. 9675 Should be used for dynamic valued symbols only. */ 9676 9677symbolS * 9678md_undefined_symbol (name) 9679 char *name ATTRIBUTE_UNUSED; 9680{ 9681 return 0; 9682} 9683 9684/* Called for any expression that can not be recognized. When the 9685 function is called, `input_line_pointer' will point to the start of 9686 the expression. */ 9687 9688void 9689md_operand (e) 9690 expressionS *e; 9691{ 9692 enum pseudo_type pseudo_type; 9693 const char *name; 9694 size_t len; 9695 int ch, i; 9696 9697 switch (*input_line_pointer) 9698 { 9699 case '@': 9700 /* Find what relocation pseudo-function we're dealing with. */ 9701 pseudo_type = 0; 9702 ch = *++input_line_pointer; 9703 for (i = 0; i < NELEMS (pseudo_func); ++i) 9704 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) 9705 { 9706 len = strlen (pseudo_func[i].name); 9707 if (strncmp (pseudo_func[i].name + 1, 9708 input_line_pointer + 1, len - 1) == 0 9709 && !is_part_of_name (input_line_pointer[len])) 9710 { 9711 input_line_pointer += len; 9712 pseudo_type = pseudo_func[i].type; 9713 break; 9714 } 9715 } 9716 switch (pseudo_type) 9717 { 9718 case PSEUDO_FUNC_RELOC: 9719 SKIP_WHITESPACE (); 9720 if (*input_line_pointer != '(') 9721 { 9722 as_bad ("Expected '('"); 9723 goto err; 9724 } 9725 /* Skip '('. */ 9726 ++input_line_pointer; 9727 expression (e); 9728 if (*input_line_pointer++ != ')') 9729 { 9730 as_bad ("Missing ')'"); 9731 goto err; 9732 } 9733 if (e->X_op != O_symbol) 9734 { 9735 if (e->X_op != O_pseudo_fixup) 9736 { 9737 as_bad ("Not a symbolic expression"); 9738 goto err; 9739 } 9740 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE 9741 && i == FUNC_LT_RELATIVE) 9742 i = FUNC_LT_FPTR_RELATIVE; 9743 else 9744 { 9745 as_bad ("Illegal combination of relocation functions"); 9746 goto err; 9747 } 9748 } 9749 /* Make sure gas doesn't get rid of local symbols that are used 9750 in relocs. */ 9751 e->X_op = O_pseudo_fixup; 9752 e->X_op_symbol = pseudo_func[i].u.sym; 9753 break; 9754 9755 case PSEUDO_FUNC_CONST: 9756 e->X_op = O_constant; 9757 e->X_add_number = pseudo_func[i].u.ival; 9758 break; 9759 9760 case PSEUDO_FUNC_REG: 9761 e->X_op = O_register; 9762 e->X_add_number = pseudo_func[i].u.ival; 9763 break; 9764 9765 default: 9766 name = input_line_pointer - 1; 9767 get_symbol_end (); 9768 as_bad ("Unknown pseudo function `%s'", name); 9769 goto err; 9770 } 9771 break; 9772 9773 case '[': 9774 ++input_line_pointer; 9775 expression (e); 9776 if (*input_line_pointer != ']') 9777 { 9778 as_bad ("Closing bracket misssing"); 9779 goto err; 9780 } 9781 else 9782 { 9783 if (e->X_op != O_register) 9784 as_bad ("Register expected as index"); 9785 9786 ++input_line_pointer; 9787 e->X_op = O_index; 9788 } 9789 break; 9790 9791 default: 9792 break; 9793 } 9794 return; 9795 9796 err: 9797 ignore_rest_of_line (); 9798} 9799 9800/* Return 1 if it's OK to adjust a reloc by replacing the symbol with 9801 a section symbol plus some offset. For relocs involving @fptr(), 9802 directives we don't want such adjustments since we need to have the 9803 original symbol's name in the reloc. */ 9804int 9805ia64_fix_adjustable (fix) 9806 fixS *fix; 9807{ 9808 /* Prevent all adjustments to global symbols */ 9809 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) 9810 return 0; 9811 9812 switch (fix->fx_r_type) 9813 { 9814 case BFD_RELOC_IA64_FPTR64I: 9815 case BFD_RELOC_IA64_FPTR32MSB: 9816 case BFD_RELOC_IA64_FPTR32LSB: 9817 case BFD_RELOC_IA64_FPTR64MSB: 9818 case BFD_RELOC_IA64_FPTR64LSB: 9819 case BFD_RELOC_IA64_LTOFF_FPTR22: 9820 case BFD_RELOC_IA64_LTOFF_FPTR64I: 9821 return 0; 9822 default: 9823 break; 9824 } 9825 9826 return 1; 9827} 9828 9829int 9830ia64_force_relocation (fix) 9831 fixS *fix; 9832{ 9833 switch (fix->fx_r_type) 9834 { 9835 case BFD_RELOC_IA64_FPTR64I: 9836 case BFD_RELOC_IA64_FPTR32MSB: 9837 case BFD_RELOC_IA64_FPTR32LSB: 9838 case BFD_RELOC_IA64_FPTR64MSB: 9839 case BFD_RELOC_IA64_FPTR64LSB: 9840 9841 case BFD_RELOC_IA64_LTOFF22: 9842 case BFD_RELOC_IA64_LTOFF64I: 9843 case BFD_RELOC_IA64_LTOFF_FPTR22: 9844 case BFD_RELOC_IA64_LTOFF_FPTR64I: 9845 case BFD_RELOC_IA64_PLTOFF22: 9846 case BFD_RELOC_IA64_PLTOFF64I: 9847 case BFD_RELOC_IA64_PLTOFF64MSB: 9848 case BFD_RELOC_IA64_PLTOFF64LSB: 9849 return 1; 9850 9851 default: 9852 return 0; 9853 } 9854 return 0; 9855} 9856 9857/* Decide from what point a pc-relative relocation is relative to, 9858 relative to the pc-relative fixup. Er, relatively speaking. */ 9859long 9860ia64_pcrel_from_section (fix, sec) 9861 fixS *fix; 9862 segT sec; 9863{ 9864 unsigned long off = fix->fx_frag->fr_address + fix->fx_where; 9865 9866 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) 9867 off &= ~0xfUL; 9868 9869 return off; 9870} 9871 9872/* This is called whenever some data item (not an instruction) needs a 9873 fixup. We pick the right reloc code depending on the byteorder 9874 currently in effect. */ 9875void 9876ia64_cons_fix_new (f, where, nbytes, exp) 9877 fragS *f; 9878 int where; 9879 int nbytes; 9880 expressionS *exp; 9881{ 9882 bfd_reloc_code_real_type code; 9883 fixS *fix; 9884 9885 switch (nbytes) 9886 { 9887 /* There are no reloc for 8 and 16 bit quantities, but we allow 9888 them here since they will work fine as long as the expression 9889 is fully defined at the end of the pass over the source file. */ 9890 case 1: code = BFD_RELOC_8; break; 9891 case 2: code = BFD_RELOC_16; break; 9892 case 4: 9893 if (target_big_endian) 9894 code = BFD_RELOC_IA64_DIR32MSB; 9895 else 9896 code = BFD_RELOC_IA64_DIR32LSB; 9897 break; 9898 9899 case 8: 9900 if (target_big_endian) 9901 code = BFD_RELOC_IA64_DIR64MSB; 9902 else 9903 code = BFD_RELOC_IA64_DIR64LSB; 9904 break; 9905 9906 case 16: 9907 if (exp->X_op == O_pseudo_fixup 9908 && exp->X_op_symbol 9909 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC) 9910 { 9911 if (target_big_endian) 9912 code = BFD_RELOC_IA64_IPLTMSB; 9913 else 9914 code = BFD_RELOC_IA64_IPLTLSB; 9915 9916 exp->X_op = O_symbol; 9917 break; 9918 } 9919 /* FALLTHRU */ 9920 9921 default: 9922 as_bad ("Unsupported fixup size %d", nbytes); 9923 ignore_rest_of_line (); 9924 return; 9925 } 9926 if (exp->X_op == O_pseudo_fixup) 9927 { 9928 /* ??? */ 9929 exp->X_op = O_symbol; 9930 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); 9931 } 9932 9933 fix = fix_new_exp (f, where, nbytes, exp, 0, code); 9934 /* We need to store the byte order in effect in case we're going 9935 to fix an 8 or 16 bit relocation (for which there no real 9936 relocs available). See md_apply_fix3(). */ 9937 fix->tc_fix_data.bigendian = target_big_endian; 9938} 9939 9940/* Return the actual relocation we wish to associate with the pseudo 9941 reloc described by SYM and R_TYPE. SYM should be one of the 9942 symbols in the pseudo_func array, or NULL. */ 9943 9944static bfd_reloc_code_real_type 9945ia64_gen_real_reloc_type (sym, r_type) 9946 struct symbol *sym; 9947 bfd_reloc_code_real_type r_type; 9948{ 9949 bfd_reloc_code_real_type new = 0; 9950 9951 if (sym == NULL) 9952 { 9953 return r_type; 9954 } 9955 9956 switch (S_GET_VALUE (sym)) 9957 { 9958 case FUNC_FPTR_RELATIVE: 9959 switch (r_type) 9960 { 9961 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; 9962 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; 9963 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; 9964 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; 9965 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; 9966 default: break; 9967 } 9968 break; 9969 9970 case FUNC_GP_RELATIVE: 9971 switch (r_type) 9972 { 9973 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; 9974 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; 9975 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; 9976 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; 9977 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; 9978 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; 9979 default: break; 9980 } 9981 break; 9982 9983 case FUNC_LT_RELATIVE: 9984 switch (r_type) 9985 { 9986 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; 9987 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; 9988 default: break; 9989 } 9990 break; 9991 9992 case FUNC_PC_RELATIVE: 9993 switch (r_type) 9994 { 9995 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; 9996 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; 9997 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; 9998 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; 9999 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; 10000 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; 10001 default: break; 10002 } 10003 break; 10004 10005 case FUNC_PLT_RELATIVE: 10006 switch (r_type) 10007 { 10008 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; 10009 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; 10010 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; 10011 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; 10012 default: break; 10013 } 10014 break; 10015 10016 case FUNC_SEC_RELATIVE: 10017 switch (r_type) 10018 { 10019 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; 10020 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; 10021 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; 10022 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; 10023 default: break; 10024 } 10025 break; 10026 10027 case FUNC_SEG_RELATIVE: 10028 switch (r_type) 10029 { 10030 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; 10031 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; 10032 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; 10033 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; 10034 default: break; 10035 } 10036 break; 10037 10038 case FUNC_LTV_RELATIVE: 10039 switch (r_type) 10040 { 10041 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; 10042 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; 10043 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; 10044 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; 10045 default: break; 10046 } 10047 break; 10048 10049 case FUNC_LT_FPTR_RELATIVE: 10050 switch (r_type) 10051 { 10052 case BFD_RELOC_IA64_IMM22: 10053 new = BFD_RELOC_IA64_LTOFF_FPTR22; break; 10054 case BFD_RELOC_IA64_IMM64: 10055 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; 10056 default: 10057 break; 10058 } 10059 break; 10060 10061 case FUNC_IPLT_RELOC: 10062 break; 10063 10064 default: 10065 abort (); 10066 } 10067 /* Hmmmm. Should this ever occur? */ 10068 if (new) 10069 return new; 10070 else 10071 return r_type; 10072} 10073 10074/* Here is where generate the appropriate reloc for pseudo relocation 10075 functions. */ 10076void 10077ia64_validate_fix (fix) 10078 fixS *fix; 10079{ 10080 switch (fix->fx_r_type) 10081 { 10082 case BFD_RELOC_IA64_FPTR64I: 10083 case BFD_RELOC_IA64_FPTR32MSB: 10084 case BFD_RELOC_IA64_FPTR64LSB: 10085 case BFD_RELOC_IA64_LTOFF_FPTR22: 10086 case BFD_RELOC_IA64_LTOFF_FPTR64I: 10087 if (fix->fx_offset != 0) 10088 as_bad_where (fix->fx_file, fix->fx_line, 10089 "No addend allowed in @fptr() relocation"); 10090 break; 10091 default: 10092 break; 10093 } 10094 10095 return; 10096} 10097 10098static void 10099fix_insn (fix, odesc, value) 10100 fixS *fix; 10101 const struct ia64_operand *odesc; 10102 valueT value; 10103{ 10104 bfd_vma insn[3], t0, t1, control_bits; 10105 const char *err; 10106 char *fixpos; 10107 long slot; 10108 10109 slot = fix->fx_where & 0x3; 10110 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); 10111 10112 /* Bundles are always in little-endian byte order */ 10113 t0 = bfd_getl64 (fixpos); 10114 t1 = bfd_getl64 (fixpos + 8); 10115 control_bits = t0 & 0x1f; 10116 insn[0] = (t0 >> 5) & 0x1ffffffffffLL; 10117 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); 10118 insn[2] = (t1 >> 23) & 0x1ffffffffffLL; 10119 10120 err = NULL; 10121 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) 10122 { 10123 insn[1] = (value >> 22) & 0x1ffffffffffLL; 10124 insn[2] |= (((value & 0x7f) << 13) 10125 | (((value >> 7) & 0x1ff) << 27) 10126 | (((value >> 16) & 0x1f) << 22) 10127 | (((value >> 21) & 0x1) << 21) 10128 | (((value >> 63) & 0x1) << 36)); 10129 } 10130 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) 10131 { 10132 if (value & ~0x3fffffffffffffffULL) 10133 err = "integer operand out of range"; 10134 insn[1] = (value >> 21) & 0x1ffffffffffLL; 10135 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); 10136 } 10137 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) 10138 { 10139 value >>= 4; 10140 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; 10141 insn[2] |= ((((value >> 59) & 0x1) << 36) 10142 | (((value >> 0) & 0xfffff) << 13)); 10143 } 10144 else 10145 err = (*odesc->insert) (odesc, value, insn + slot); 10146 10147 if (err) 10148 as_bad_where (fix->fx_file, fix->fx_line, err); 10149 10150 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); 10151 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 10152 number_to_chars_littleendian (fixpos + 0, t0, 8); 10153 number_to_chars_littleendian (fixpos + 8, t1, 8); 10154} 10155 10156/* Attempt to simplify or even eliminate a fixup. The return value is 10157 ignored; perhaps it was once meaningful, but now it is historical. 10158 To indicate that a fixup has been eliminated, set FIXP->FX_DONE. 10159 10160 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry 10161 (if possible). */ 10162 10163void 10164md_apply_fix3 (fix, valP, seg) 10165 fixS *fix; 10166 valueT * valP; 10167 segT seg ATTRIBUTE_UNUSED; 10168{ 10169 char *fixpos; 10170 valueT value = * valP; 10171 int adjust = 0; 10172 10173 fixpos = fix->fx_frag->fr_literal + fix->fx_where; 10174 10175 if (fix->fx_pcrel) 10176 { 10177 switch (fix->fx_r_type) 10178 { 10179 case BFD_RELOC_IA64_DIR32MSB: 10180 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; 10181 adjust = 1; 10182 break; 10183 10184 case BFD_RELOC_IA64_DIR32LSB: 10185 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; 10186 adjust = 1; 10187 break; 10188 10189 case BFD_RELOC_IA64_DIR64MSB: 10190 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; 10191 adjust = 1; 10192 break; 10193 10194 case BFD_RELOC_IA64_DIR64LSB: 10195 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; 10196 adjust = 1; 10197 break; 10198 10199 default: 10200 break; 10201 } 10202 } 10203 if (fix->fx_addsy) 10204 { 10205 if (fix->fx_r_type == (int) BFD_RELOC_UNUSED) 10206 { 10207 /* This must be a TAG13 or TAG13b operand. There are no external 10208 relocs defined for them, so we must give an error. */ 10209 as_bad_where (fix->fx_file, fix->fx_line, 10210 "%s must have a constant value", 10211 elf64_ia64_operands[fix->tc_fix_data.opnd].desc); 10212 fix->fx_done = 1; 10213 return; 10214 } 10215 10216 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs 10217 work. There should be a better way to handle this. */ 10218 if (adjust) 10219 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; 10220 } 10221 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) 10222 { 10223 if (fix->tc_fix_data.bigendian) 10224 number_to_chars_bigendian (fixpos, value, fix->fx_size); 10225 else 10226 number_to_chars_littleendian (fixpos, value, fix->fx_size); 10227 fix->fx_done = 1; 10228 } 10229 else 10230 { 10231 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); 10232 fix->fx_done = 1; 10233 } 10234} 10235 10236/* Generate the BFD reloc to be stuck in the object file from the 10237 fixup used internally in the assembler. */ 10238 10239arelent * 10240tc_gen_reloc (sec, fixp) 10241 asection *sec ATTRIBUTE_UNUSED; 10242 fixS *fixp; 10243{ 10244 arelent *reloc; 10245 10246 reloc = xmalloc (sizeof (*reloc)); 10247 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 10248 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 10249 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 10250 reloc->addend = fixp->fx_offset; 10251 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 10252 10253 if (!reloc->howto) 10254 { 10255 as_bad_where (fixp->fx_file, fixp->fx_line, 10256 "Cannot represent %s relocation in object file", 10257 bfd_get_reloc_code_name (fixp->fx_r_type)); 10258 } 10259 return reloc; 10260} 10261 10262/* Turn a string in input_line_pointer into a floating point constant 10263 of type TYPE, and store the appropriate bytes in *LIT. The number 10264 of LITTLENUMS emitted is stored in *SIZE. An error message is 10265 returned, or NULL on OK. */ 10266 10267#define MAX_LITTLENUMS 5 10268 10269char * 10270md_atof (type, lit, size) 10271 int type; 10272 char *lit; 10273 int *size; 10274{ 10275 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 10276 LITTLENUM_TYPE *word; 10277 char *t; 10278 int prec; 10279 10280 switch (type) 10281 { 10282 /* IEEE floats */ 10283 case 'f': 10284 case 'F': 10285 case 's': 10286 case 'S': 10287 prec = 2; 10288 break; 10289 10290 case 'd': 10291 case 'D': 10292 case 'r': 10293 case 'R': 10294 prec = 4; 10295 break; 10296 10297 case 'x': 10298 case 'X': 10299 case 'p': 10300 case 'P': 10301 prec = 5; 10302 break; 10303 10304 default: 10305 *size = 0; 10306 return "Bad call to MD_ATOF()"; 10307 } 10308 t = atof_ieee (input_line_pointer, type, words); 10309 if (t) 10310 input_line_pointer = t; 10311 *size = prec * sizeof (LITTLENUM_TYPE); 10312 10313 for (word = words + prec - 1; prec--;) 10314 { 10315 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); 10316 lit += sizeof (LITTLENUM_TYPE); 10317 } 10318 return 0; 10319} 10320 10321/* Round up a section's size to the appropriate boundary. */ 10322valueT 10323md_section_align (seg, size) 10324 segT seg; 10325 valueT size; 10326{ 10327 int align = bfd_get_section_alignment (stdoutput, seg); 10328 valueT mask = ((valueT) 1 << align) - 1; 10329 10330 return (size + mask) & ~mask; 10331} 10332 10333/* Handle ia64 specific semantics of the align directive. */ 10334 10335void 10336ia64_md_do_align (n, fill, len, max) 10337 int n ATTRIBUTE_UNUSED; 10338 const char *fill ATTRIBUTE_UNUSED; 10339 int len ATTRIBUTE_UNUSED; 10340 int max ATTRIBUTE_UNUSED; 10341{ 10342 if (subseg_text_p (now_seg)) 10343 ia64_flush_insns (); 10344} 10345 10346/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 10347 of an rs_align_code fragment. */ 10348 10349void 10350ia64_handle_align (fragp) 10351 fragS *fragp; 10352{ 10353 /* Use mfi bundle of nops with no stop bits. */ 10354 static const unsigned char be_nop[] 10355 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 10356 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; 10357 static const unsigned char le_nop[] 10358 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 10359 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; 10360 10361 int bytes; 10362 char *p; 10363 10364 if (fragp->fr_type != rs_align_code) 10365 return; 10366 10367 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 10368 p = fragp->fr_literal + fragp->fr_fix; 10369 10370 /* Make sure we are on a 16-byte boundary, in case someone has been 10371 putting data into a text section. */ 10372 if (bytes & 15) 10373 { 10374 int fix = bytes & 15; 10375 memset (p, 0, fix); 10376 p += fix; 10377 bytes -= fix; 10378 fragp->fr_fix += fix; 10379 } 10380 10381 memcpy (p, (target_big_endian ? be_nop : le_nop), 16); 10382 fragp->fr_var = 16; 10383} 10384