1/*- 2 * Copyright (C) 2007 3 * Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 23 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30#ifndef __IF_AREREG_H__ 31#define __IF_AREREG_H__ 32 33struct are_desc { 34 uint32_t are_stat; 35 uint32_t are_devcs; 36 uint32_t are_addr; 37 uint32_t are_link; 38}; 39 40#define ARE_DMASIZE(len) ((len) & ((1 << 11)-1)) 41#define ARE_PKTSIZE(len) ((len & 0xffff0000) >> 16) 42 43#define ARE_RX_RING_CNT 128 44#define ARE_TX_RING_CNT 128 45#define ARE_TX_RING_SIZE sizeof(struct are_desc) * ARE_TX_RING_CNT 46#define ARE_RX_RING_SIZE sizeof(struct are_desc) * ARE_RX_RING_CNT 47 48#define ARE_MIN_FRAMELEN 60 49#define ARE_RING_ALIGN sizeof(struct are_desc) 50#define ARE_RX_ALIGN sizeof(uint32_t) 51#define ARE_MAXFRAGS 8 52#define ARE_TX_INTR_THRESH 8 53 54#define ARE_TX_RING_ADDR(sc, i) \ 55 ((sc)->are_rdata.are_tx_ring_paddr + sizeof(struct are_desc) * (i)) 56#define ARE_RX_RING_ADDR(sc, i) \ 57 ((sc)->are_rdata.are_rx_ring_paddr + sizeof(struct are_desc) * (i)) 58#define ARE_INC(x,y) (x) = (((x) + 1) % y) 59 60struct are_txdesc { 61 struct mbuf *tx_m; 62 bus_dmamap_t tx_dmamap; 63}; 64 65struct are_rxdesc { 66 struct mbuf *rx_m; 67 bus_dmamap_t rx_dmamap; 68 struct are_desc *desc; 69 /* Use this values on error instead of allocating new mbuf */ 70 uint32_t saved_ctl, saved_ca; 71}; 72 73struct are_chain_data { 74 bus_dma_tag_t are_parent_tag; 75 bus_dma_tag_t are_tx_tag; 76 struct are_txdesc are_txdesc[ARE_TX_RING_CNT]; 77 bus_dma_tag_t are_rx_tag; 78 struct are_rxdesc are_rxdesc[ARE_RX_RING_CNT]; 79 bus_dma_tag_t are_tx_ring_tag; 80 bus_dma_tag_t are_rx_ring_tag; 81 bus_dmamap_t are_tx_ring_map; 82 bus_dmamap_t are_rx_ring_map; 83 bus_dmamap_t are_rx_sparemap; 84 int are_tx_pkts; 85 int are_tx_prod; 86 int are_tx_cons; 87 int are_tx_cnt; 88 int are_rx_cons; 89}; 90 91struct are_ring_data { 92 struct are_desc *are_rx_ring; 93 struct are_desc *are_tx_ring; 94 bus_addr_t are_rx_ring_paddr; 95 bus_addr_t are_tx_ring_paddr; 96}; 97 98struct are_softc { 99 struct ifnet *are_ifp; /* interface info */ 100 bus_space_handle_t are_bhandle; /* bus space handle */ 101 bus_space_tag_t are_btag; /* bus space tag */ 102 device_t are_dev; 103 uint8_t are_eaddr[ETHER_ADDR_LEN]; 104 struct resource *are_res; 105 int are_rid; 106 struct resource *are_irq; 107 void *are_intrhand; 108 u_int32_t sc_inten; /* copy of CSR_INTEN */ 109 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 110 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 111#ifdef ARE_MII 112 device_t are_miibus; 113#else 114 struct ifmedia are_ifmedia; 115#endif 116#ifdef ARE_MDIO 117 device_t are_miiproxy; 118#endif 119 bus_dma_tag_t are_parent_tag; 120 bus_dma_tag_t are_tag; 121 struct mtx are_mtx; 122 struct callout are_stat_callout; 123 struct task are_link_task; 124 struct are_chain_data are_cdata; 125 struct are_ring_data are_rdata; 126 int are_link_status; 127 int are_detach; 128 int are_if_flags; /* last if flags */ 129}; 130 131#define ARE_LOCK(_sc) mtx_lock(&(_sc)->are_mtx) 132#define ARE_UNLOCK(_sc) mtx_unlock(&(_sc)->are_mtx) 133#define ARE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->are_mtx, MA_OWNED) 134 135/* 136 * register space access macros 137 */ 138#define CSR_WRITE_4(sc, reg, val) \ 139 bus_space_write_4(sc->are_btag, sc->are_bhandle, reg, val) 140 141#define CSR_READ_4(sc, reg) \ 142 bus_space_read_4(sc->are_btag, sc->are_bhandle, reg) 143 144/* $NetBSD: aereg.h,v 1.2 2008/04/28 20:23:28 martin Exp $ */ 145 146/*- 147 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 148 * All rights reserved. 149 * 150 * This code is derived from software contributed to The NetBSD Foundation 151 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 152 * NASA Ames Research Center. 153 * 154 * Redistribution and use in source and binary forms, with or without 155 * modification, are permitted provided that the following conditions 156 * are met: 157 * 1. Redistributions of source code must retain the above copyright 158 * notice, this list of conditions and the following disclaimer. 159 * 2. Redistributions in binary form must reproduce the above copyright 160 * notice, this list of conditions and the following disclaimer in the 161 * documentation and/or other materials provided with the distribution. 162 * 163 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 164 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 165 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 166 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 167 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 168 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 169 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 170 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 171 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 172 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 173 * POSSIBILITY OF SUCH DAMAGE. 174 */ 175 176/* 177 * Descriptor Status bits common to transmit and receive. 178 */ 179#define ADSTAT_OWN 0x80000000 /* Tulip owns descriptor */ 180#define ADSTAT_ES 0x00008000 /* Error Summary */ 181 182/* 183 * Descriptor Status bits for Receive Descriptor. 184 */ 185#define ADSTAT_Rx_FF 0x40000000 /* Filtering Fail */ 186#define ADSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */ 187#define ADSTAT_Rx_DE 0x00004000 /* Descriptor Error */ 188#define ADSTAT_Rx_LE 0x00001000 /* Length Error */ 189#define ADSTAT_Rx_RF 0x00000800 /* Runt Frame */ 190#define ADSTAT_Rx_MF 0x00000400 /* Multicast Frame */ 191#define ADSTAT_Rx_FS 0x00000200 /* First Descriptor */ 192#define ADSTAT_Rx_LS 0x00000100 /* Last Descriptor */ 193#define ADSTAT_Rx_TL 0x00000080 /* Frame Too Long */ 194#define ADSTAT_Rx_CS 0x00000040 /* Collision Seen */ 195#define ADSTAT_Rx_RT 0x00000020 /* Frame Type */ 196#define ADSTAT_Rx_RW 0x00000010 /* Receive Watchdog */ 197#define ADSTAT_Rx_RE 0x00000008 /* Report on MII Error */ 198#define ADSTAT_Rx_DB 0x00000004 /* Dribbling Bit */ 199#define ADSTAT_Rx_CE 0x00000002 /* CRC Error */ 200#define ADSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */ 201 202#define ADSTAT_Rx_LENGTH(x) (((x) & ADSTAT_Rx_FL) >> 16) 203 204/* 205 * Descriptor Status bits for Transmit Descriptor. 206 */ 207#define ADSTAT_Tx_ES 0x00008000 /* Error Summary */ 208#define ADSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */ 209#define ADSTAT_Tx_LO 0x00000800 /* Loss of Carrier */ 210#define ADSTAT_Tx_NC 0x00000400 /* No Carrier */ 211#define ADSTAT_Tx_LC 0x00000200 /* Late Collision */ 212#define ADSTAT_Tx_EC 0x00000100 /* Excessive Collisions */ 213#define ADSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */ 214#define ADSTAT_Tx_CC 0x00000078 /* Collision Count */ 215#define ADSTAT_Tx_ED 0x00000004 /* Excessive Deferral */ 216#define ADSTAT_Tx_UF 0x00000002 /* Underflow Error */ 217#define ADSTAT_Tx_DE 0x00000001 /* Deferred */ 218 219#define ADSTAT_Tx_COLLISIONS(x) (((x) & ADSTAT_Tx_CC) >> 3) 220 221/* 222 * Descriptor Control bits common to transmit and receive. 223 */ 224#define ADCTL_SIZE1 0x000007ff /* Size of buffer 1 */ 225#define ADCTL_SIZE1_SHIFT 0 226 227#define ADCTL_SIZE2 0x003ff800 /* Size of buffer 2 */ 228#define ADCTL_SIZE2_SHIFT 11 229 230#define ADCTL_ER 0x02000000 /* End of Ring */ 231#define ADCTL_CH 0x01000000 /* Second Address Chained */ 232 233/* 234 * Descriptor Control bits for Transmit Descriptor. 235 */ 236#define ADCTL_Tx_IC 0x80000000 /* Interrupt on Completion */ 237#define ADCTL_Tx_LS 0x40000000 /* Last Segment */ 238#define ADCTL_Tx_FS 0x20000000 /* First Segment */ 239#define ADCTL_Tx_AC 0x04000000 /* Add CRC Disable */ 240#define ADCTL_Tx_DPD 0x00800000 /* Disabled Padding */ 241 242/* 243 * Control registers. 244 */ 245 246/* tese are registers only found on this part */ 247#define CSR_MACCTL 0x0000 /* mac control */ 248#define CSR_MACHI 0x0004 249#define CSR_MACLO 0x0008 250#define CSR_HTHI 0x000C /* multicast table high */ 251#define CSR_HTLO 0x0010 /* multicast table low */ 252#define CSR_MIIADDR 0x0014 /* mii address */ 253#define CSR_MIIDATA 0x0018 /* mii data */ 254#define CSR_FLOWC 0x001C /* flow control */ 255#define CSR_VL1 0x0020 /* vlan 1 tag */ 256 257/* these are more or less normal Tulip registers */ 258#define CSR_BUSMODE 0x1000 /* bus mode */ 259#define CSR_TXPOLL 0x1004 /* tx poll demand */ 260#define CSR_RXPOLL 0x1008 /* rx poll demand */ 261#define CSR_RXLIST 0x100C /* rx base descriptor address */ 262#define CSR_TXLIST 0x1010 /* tx base descriptor address */ 263#define CSR_STATUS 0x1014 /* (interrupt) status */ 264#define CSR_OPMODE 0x1018 /* operation mode */ 265#define CSR_INTEN 0x101C /* interrupt enable */ 266#define CSR_MISSED 0x1020 /* missed frame counter */ 267#define CSR_HTBA 0x1050 /* host tx buffer address (ro) */ 268#define CSR_HRBA 0x1054 /* host rx buffer address (ro) */ 269 270/* CSR_MACCTL - Mac Control */ 271#define MACCTL_RE 0x00000004 /* rx enable */ 272#define MACCTL_TE 0x00000008 /* tx enable */ 273#define MACCTL_DC 0x00000020 /* deferral check */ 274#define MACCTL_PSTR 0x00000100 /* automatic pad strip */ 275#define MACCTL_DTRY 0x00000400 /* disable retry */ 276#define MACCTL_DBF 0x00000800 /* disable broadcast frames */ 277#define MACCTL_LCC 0x00001000 /* late collision control */ 278#define MACCTL_HASH 0x00002000 /* hash filtering enable */ 279#define MACCTL_HO 0x00008000 /* disable perfect filtering */ 280#define MACCTL_PB 0x00010000 /* pass bad frames */ 281#define MACCTL_IF 0x00020000 /* inverse filtering */ 282#define MACCTL_PR 0x00040000 /* promiscuous mode */ 283#define MACCTL_PM 0x00080000 /* pass all multicast */ 284#define MACCTL_FDX 0x00100000 /* full duplex mode */ 285#define MACCTL_LOOP 0x00600000 /* loopback mask */ 286#define MACCTL_LOOP_INT 0x00200000 /* internal loopback */ 287#define MACCTL_LOOP_EXT 0x00400000 /* external loopback */ 288#define MACCTL_LOOP_NONE 0x00000000 289#define MACCTL_DRO 0x00800000 /* disable receive own */ 290#define MACCTL_PS 0x08000000 /* port select, 0 = mii */ 291#define MACCTL_HBD 0x10000000 /* heartbeat disable */ 292#define MACCTL_BLE 0x40000000 /* mac big endian */ 293#define MACCTL_RA 0x80000000 /* receive all packets */ 294 295/* CSR_MIIADDR - MII Addess */ 296#define MIIADDR_BUSY 0x00000001 /* mii busy */ 297#define MIIADDR_WRITE 0x00000002 /* mii write */ 298#define MIIADDR_REG_MASK 0x000007C0 /* mii register */ 299#define MIIADDR_REG_SHIFT 6 300#define MIIADDR_PHY_MASK 0x0000F800 /* mii phy */ 301#define MIIADDR_PHY_SHIFT 11 302 303#define MIIADDR_GETREG(x) (((x) & MIIADDR_REG) >> 6) 304#define MIIADDR_PUTREG(x) (((x) << 6) & MIIADR_REG) 305#define MIIADDR_GETPHY(x) (((x) & MIIADDR_PHY) >> 11) 306#define MIIADDR_PUTPHY(x) (((x) << 6) & MIIADR_PHY) 307 308/* CSR_FLOWC - Flow Control */ 309#define FLOWC_FCB 0x00000001 /* flow control busy */ 310#define FLOWC_FCE 0x00000002 /* flow control enable */ 311#define FLOWC_PCF 0x00000004 /* pass control frames */ 312#define FLOWC_PT 0xffff0000 /* pause time */ 313 314/* CSR_BUSMODE - Bus Mode */ 315#define BUSMODE_SWR 0x00000001 /* software reset */ 316#define BUSMODE_BAR 0x00000002 /* bus arbitration */ 317#define BUSMODE_DSL 0x0000007c /* descriptor skip length */ 318#define BUSMODE_BLE 0x00000080 /* data buf endian */ 319 /* programmable burst length */ 320#define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */ 321#define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */ 322#define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */ 323#define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */ 324#define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */ 325#define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */ 326#define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */ 327#define BUSMODE_DBO 0x00100000 /* descriptor endian */ 328#define BUSMODE_ALIGN_16B 0x01000000 /* force oddhw rx buf align */ 329 330/* CSR_TXPOLL - Transmit Poll Demand */ 331#define TXPOLL_TPD 0x00000001 /* transmit poll demand */ 332 333/* CSR_RXPOLL - Receive Poll Demand */ 334#define RXPOLL_RPD 0x00000001 /* receive poll demand */ 335 336/* CSR_STATUS - Status */ 337#define STATUS_TI 0x00000001 /* transmit interrupt */ 338#define STATUS_TPS 0x00000002 /* transmit process stopped */ 339#define STATUS_TU 0x00000004 /* transmit buffer unavail */ 340#define STATUS_TJT 0x00000008 /* transmit jabber timeout */ 341#define STATUS_UNF 0x00000020 /* transmit underflow */ 342#define STATUS_RI 0x00000040 /* receive interrupt */ 343#define STATUS_RU 0x00000080 /* receive buffer unavail */ 344#define STATUS_RPS 0x00000100 /* receive process stopped */ 345#define STATUS_ETI 0x00000400 /* early transmit interrupt */ 346#define STATUS_SE 0x00002000 /* system error */ 347#define STATUS_ER 0x00004000 /* early receive (21041) */ 348#define STATUS_AIS 0x00008000 /* abnormal intr summary */ 349#define STATUS_NIS 0x00010000 /* normal interrupt summary */ 350#define STATUS_RS 0x000e0000 /* receive process state */ 351#define STATUS_RS_STOPPED 0x00000000 /* Stopped */ 352#define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive 353 descriptor */ 354#define STATUS_RS_CHECK 0x00040000 /* Running - check for end 355 of receive */ 356#define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */ 357#define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */ 358#define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive 359 descriptor */ 360#define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current 361 frame from FIFO */ 362#define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current 363 frame from FIFO into 364 buffer */ 365#define STATUS_TS 0x00700000 /* transmit process state */ 366#define STATUS_TS_STOPPED 0x00000000 /* Stopped */ 367#define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit 368 descriptor */ 369#define STATUS_TS_WAIT 0x00200000 /* Running - wait for end 370 of transmission */ 371#define STATUS_TS_READING 0x00300000 /* Running - read buffer from 372 memory and queue into 373 FIFO */ 374#define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */ 375#define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit 376 descriptor */ 377#define STATUS_TX_ABORT 0x00800000 /* Transmit bus abort */ 378#define STATUS_RX_ABORT 0x01000000 /* Transmit bus abort */ 379 380/* CSR_OPMODE - Operation Mode */ 381#define OPMODE_SR 0x00000002 /* start receive */ 382#define OPMODE_OSF 0x00000004 /* operate on second frame */ 383#define OPMODE_ST 0x00002000 /* start transmitter */ 384#define OPMODE_TR 0x0000c000 /* threshold control */ 385#define OPMODE_TR_32 0x00000000 /* 32 words */ 386#define OPMODE_TR_64 0x00004000 /* 64 words */ 387#define OPMODE_TR_128 0x00008000 /* 128 words */ 388#define OPMODE_TR_256 0x0000c000 /* 256 words */ 389#define OPMODE_SF 0x00200000 /* store and forward mode */ 390 391/* CSR_INTEN - Interrupt Enable */ 392 /* See bits for CSR_STATUS -- Status */ 393 394/* CSR_MISSED - Missed Frames */ 395#define MISSED_MFC 0xffff0000 /* missed packet count */ 396#define MISSED_FOC 0x0000ffff /* fifo overflow counter */ 397 398#define MISSED_GETMFC(x) ((x) & MISSED_MFC) 399#define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 16) 400 401#endif /* __IF_AREREG_H__ */ 402