1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 5 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32#define PCIR_NAMBAR 0x10 33#define PCIR_NABMBAR 0x14 34 35#define PCIR_MMBAR 0x18 36#define PCIR_MBBAR 0x1C 37 38#define PCIR_ICH_LEGACY 0x41 39#define ICH_LEGACY_ENABLE 0x01 40 41/* Native Audio Bus Master Control Registers */ 42#define ICH_REG_X_BDBAR 0x00 43#define ICH_REG_X_CIV 0x04 44#define ICH_REG_X_LVI 0x05 45#define ICH_REG_X_SR 0x06 46#define ICH_REG_X_PICB 0x08 47#define ICH_REG_X_PIV 0x0a 48#define ICH_REG_X_CR 0x0b 49 50#define ICH_REG_PI_BASE 0x00 51#define ICH_REG_PO_BASE 0x10 52#define ICH_REG_MC_BASE 0x20 53 54#define ICH_REG_GLOB_CNT 0x2c 55#define ICH_REG_GLOB_STA 0x30 56#define ICH_REG_ACC_SEMA 0x34 57 58/* Status Register Values */ 59#define ICH_X_SR_DCH 0x0001 60#define ICH_X_SR_CELV 0x0002 61#define ICH_X_SR_LVBCI 0x0004 62#define ICH_X_SR_BCIS 0x0008 63#define ICH_X_SR_FIFOE 0x0010 64 65/* Control Register Values */ 66#define ICH_X_CR_RPBM 0x01 67#define ICH_X_CR_RR 0x02 68#define ICH_X_CR_LVBIE 0x04 69#define ICH_X_CR_FEIE 0x08 70#define ICH_X_CR_IOCE 0x10 71 72/* Global Control Register Values */ 73#define ICH_GLOB_CTL_GIE 0x00000001 74#define ICH_GLOB_CTL_COLD 0x00000002 /* negate */ 75#define ICH_GLOB_CTL_WARM 0x00000004 76#define ICH_GLOB_CTL_SHUT 0x00000008 77#define ICH_GLOB_CTL_PRES 0x00000010 78#define ICH_GLOB_CTL_SRES 0x00000020 79 80/* Global Status Register Values */ 81#define ICH_GLOB_STA_GSCI 0x00000001 82#define ICH_GLOB_STA_MIINT 0x00000002 83#define ICH_GLOB_STA_MOINT 0x00000004 84#define ICH_GLOB_STA_PIINT 0x00000020 85#define ICH_GLOB_STA_POINT 0x00000040 86#define ICH_GLOB_STA_MINT 0x00000080 87#define ICH_GLOB_STA_PCR 0x00000100 88#define ICH_GLOB_STA_SCR 0x00000200 89#define ICH_GLOB_STA_PRES 0x00000400 90#define ICH_GLOB_STA_SRES 0x00000800 91#define ICH_GLOB_STA_SLOT12 0x00007000 92#define ICH_GLOB_STA_RCODEC 0x00008000 93#define ICH_GLOB_STA_AD3 0x00010000 94#define ICH_GLOB_STA_MD3 0x00020000 95#define ICH_GLOB_STA_IMASK (ICH_GLOB_STA_MIINT | ICH_GLOB_STA_MOINT | ICH_GLOB_STA_PIINT | ICH_GLOB_STA_POINT | ICH_GLOB_STA_MINT | ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES) 96 97/* play/record buffer */ 98#define ICH_BDC_IOC 0x80000000 99#define ICH_BDC_BUP 0x40000000 100