1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1999 Seigo Tanimura 5 * All rights reserved. 6 * 7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/malloc.h> 38#include <sys/module.h> 39#include <machine/resource.h> 40#include <machine/bus.h> 41#include <sys/rman.h> 42 43#ifdef HAVE_KERNEL_OPTION_HEADERS 44#include "opt_snd.h" 45#endif 46 47#include <dev/sound/pcm/sound.h> 48#include <dev/sound/chip.h> 49#include <dev/sound/pci/csareg.h> 50#include <dev/sound/pci/csavar.h> 51 52#include <dev/pci/pcireg.h> 53#include <dev/pci/pcivar.h> 54 55#include <dev/sound/pci/cs461x_dsp.h> 56 57SND_DECLARE_FILE("$FreeBSD$"); 58 59/* This is the pci device id. */ 60#define CS4610_PCI_ID 0x60011013 61#define CS4614_PCI_ID 0x60031013 62#define CS4615_PCI_ID 0x60041013 63 64/* Here is the parameter structure per a device. */ 65struct csa_softc { 66 device_t dev; /* device */ 67 csa_res res; /* resources */ 68 69 device_t pcm; /* pcm device */ 70 driver_intr_t* pcmintr; /* pcm intr */ 71 void *pcmintr_arg; /* pcm intr arg */ 72 device_t midi; /* midi device */ 73 driver_intr_t* midiintr; /* midi intr */ 74 void *midiintr_arg; /* midi intr arg */ 75 void *ih; /* cookie */ 76 77 struct csa_card *card; 78 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 79}; 80 81typedef struct csa_softc *sc_p; 82 83static int csa_probe(device_t dev); 84static int csa_attach(device_t dev); 85static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 86 rman_res_t start, rman_res_t end, 87 rman_res_t count, u_int flags); 88static int csa_release_resource(device_t bus, device_t child, int type, int rid, 89 struct resource *r); 90static int csa_setup_intr(device_t bus, device_t child, 91 struct resource *irq, int flags, 92 driver_filter_t *filter, 93 driver_intr_t *intr, void *arg, void **cookiep); 94static int csa_teardown_intr(device_t bus, device_t child, 95 struct resource *irq, void *cookie); 96static driver_intr_t csa_intr; 97static int csa_initialize(sc_p scp); 98static int csa_downloadimage(csa_res *resp); 99static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 100 101static devclass_t csa_devclass; 102 103static void 104amp_none(void) 105{ 106} 107 108static void 109amp_voyetra(void) 110{ 111} 112 113static int 114clkrun_hack(int run) 115{ 116#ifdef __i386__ 117 devclass_t pci_devclass; 118 device_t *pci_devices, *pci_children, *busp, *childp; 119 int pci_count = 0, pci_childcount = 0; 120 int i, j, port; 121 u_int16_t control; 122 bus_space_tag_t btag; 123 124 if ((pci_devclass = devclass_find("pci")) == NULL) { 125 return ENXIO; 126 } 127 128 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 129 130 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 131 pci_childcount = 0; 132 if (device_get_children(*busp, &pci_children, &pci_childcount)) 133 continue; 134 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 135 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 136 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 137 /* XXX */ 138 btag = X86_BUS_SPACE_IO; 139 140 control = bus_space_read_2(btag, 0x0, port); 141 control &= ~0x2000; 142 control |= run? 0 : 0x2000; 143 bus_space_write_2(btag, 0x0, port, control); 144 free(pci_devices, M_TEMP); 145 free(pci_children, M_TEMP); 146 return 0; 147 } 148 } 149 free(pci_children, M_TEMP); 150 } 151 152 free(pci_devices, M_TEMP); 153 return ENXIO; 154#else 155 return 0; 156#endif 157} 158 159static struct csa_card cards_4610[] = { 160 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 161}; 162 163static struct csa_card cards_4614[] = { 164 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 165 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 166 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 167 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 168 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 169 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 170 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 171 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 172 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0}, 173 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 174}; 175 176static struct csa_card cards_4615[] = { 177 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 178}; 179 180static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 181 182struct card_type { 183 u_int32_t devid; 184 char *name; 185 struct csa_card *cards; 186}; 187 188static struct card_type cards[] = { 189 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 190 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 191 {CS4615_PCI_ID, "CS4615", cards_4615}, 192 {0, NULL, NULL}, 193}; 194 195static struct card_type * 196csa_findcard(device_t dev) 197{ 198 int i; 199 200 i = 0; 201 while (cards[i].devid != 0) { 202 if (pci_get_devid(dev) == cards[i].devid) 203 return &cards[i]; 204 i++; 205 } 206 return NULL; 207} 208 209struct csa_card * 210csa_findsubcard(device_t dev) 211{ 212 int i; 213 struct card_type *card; 214 struct csa_card *subcard; 215 216 card = csa_findcard(dev); 217 if (card == NULL) 218 return &nocard; 219 subcard = card->cards; 220 i = 0; 221 while (subcard[i].subvendor != 0) { 222 if (pci_get_subvendor(dev) == subcard[i].subvendor 223 && pci_get_subdevice(dev) == subcard[i].subdevice) { 224 return &subcard[i]; 225 } 226 i++; 227 } 228 return &subcard[i]; 229} 230 231static int 232csa_probe(device_t dev) 233{ 234 struct card_type *card; 235 236 card = csa_findcard(dev); 237 if (card) { 238 device_set_desc(dev, card->name); 239 return BUS_PROBE_DEFAULT; 240 } 241 return ENXIO; 242} 243 244static int 245csa_attach(device_t dev) 246{ 247 sc_p scp; 248 csa_res *resp; 249 struct sndcard_func *func; 250 int error = ENXIO; 251 252 scp = device_get_softc(dev); 253 254 /* Fill in the softc. */ 255 bzero(scp, sizeof(*scp)); 256 scp->dev = dev; 257 258 pci_enable_busmaster(dev); 259 260 /* Allocate the resources. */ 261 resp = &scp->res; 262 scp->card = csa_findsubcard(dev); 263 scp->binfo.card = scp->card; 264 printf("csa: card is %s\n", scp->card->name); 265 resp->io_rid = PCIR_BAR(0); 266 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 267 &resp->io_rid, RF_ACTIVE); 268 if (resp->io == NULL) 269 return (ENXIO); 270 resp->mem_rid = PCIR_BAR(1); 271 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 272 &resp->mem_rid, RF_ACTIVE); 273 if (resp->mem == NULL) 274 goto err_io; 275 resp->irq_rid = 0; 276 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 277 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 278 if (resp->irq == NULL) 279 goto err_mem; 280 281 /* Enable interrupt. */ 282 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 283 goto err_intr; 284#if 0 285 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 286 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 287#endif 288 289 /* Initialize the chip. */ 290 if (csa_initialize(scp)) 291 goto err_teardown; 292 293 /* Reset the Processor. */ 294 csa_resetdsp(resp); 295 296 /* Download the Processor Image to the processor. */ 297 if (csa_downloadimage(resp)) 298 goto err_teardown; 299 300 /* Attach the children. */ 301 302 /* PCM Audio */ 303 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 304 if (func == NULL) { 305 error = ENOMEM; 306 goto err_teardown; 307 } 308 func->varinfo = &scp->binfo; 309 func->func = SCF_PCM; 310 scp->pcm = device_add_child(dev, "pcm", -1); 311 device_set_ivars(scp->pcm, func); 312 313 /* Midi Interface */ 314 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 315 if (func == NULL) { 316 error = ENOMEM; 317 goto err_teardown; 318 } 319 func->varinfo = &scp->binfo; 320 func->func = SCF_MIDI; 321 scp->midi = device_add_child(dev, "midi", -1); 322 device_set_ivars(scp->midi, func); 323 324 bus_generic_attach(dev); 325 326 return (0); 327 328err_teardown: 329 bus_teardown_intr(dev, resp->irq, scp->ih); 330err_intr: 331 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 332err_mem: 333 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 334err_io: 335 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 336 return (error); 337} 338 339static int 340csa_detach(device_t dev) 341{ 342 csa_res *resp; 343 sc_p scp; 344 struct sndcard_func *func; 345 int err; 346 347 scp = device_get_softc(dev); 348 resp = &scp->res; 349 350 if (scp->midi != NULL) { 351 func = device_get_ivars(scp->midi); 352 err = device_delete_child(dev, scp->midi); 353 if (err != 0) 354 return err; 355 if (func != NULL) 356 free(func, M_DEVBUF); 357 scp->midi = NULL; 358 } 359 360 if (scp->pcm != NULL) { 361 func = device_get_ivars(scp->pcm); 362 err = device_delete_child(dev, scp->pcm); 363 if (err != 0) 364 return err; 365 if (func != NULL) 366 free(func, M_DEVBUF); 367 scp->pcm = NULL; 368 } 369 370 bus_teardown_intr(dev, resp->irq, scp->ih); 371 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 372 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 373 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 374 375 return bus_generic_detach(dev); 376} 377 378static int 379csa_resume(device_t dev) 380{ 381 csa_res *resp; 382 sc_p scp; 383 384 scp = device_get_softc(dev); 385 resp = &scp->res; 386 387 /* Initialize the chip. */ 388 if (csa_initialize(scp)) 389 return (ENXIO); 390 391 /* Reset the Processor. */ 392 csa_resetdsp(resp); 393 394 /* Download the Processor Image to the processor. */ 395 if (csa_downloadimage(resp)) 396 return (ENXIO); 397 398 return (bus_generic_resume(dev)); 399} 400 401static struct resource * 402csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 403 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 404{ 405 sc_p scp; 406 csa_res *resp; 407 struct resource *res; 408 409 scp = device_get_softc(bus); 410 resp = &scp->res; 411 switch (type) { 412 case SYS_RES_IRQ: 413 if (*rid != 0) 414 return (NULL); 415 res = resp->irq; 416 break; 417 case SYS_RES_MEMORY: 418 switch (*rid) { 419 case PCIR_BAR(0): 420 res = resp->io; 421 break; 422 case PCIR_BAR(1): 423 res = resp->mem; 424 break; 425 default: 426 return (NULL); 427 } 428 break; 429 default: 430 return (NULL); 431 } 432 433 return res; 434} 435 436static int 437csa_release_resource(device_t bus, device_t child, int type, int rid, 438 struct resource *r) 439{ 440 return (0); 441} 442 443/* 444 * The following three functions deal with interrupt handling. 445 * An interrupt is primarily handled by the bridge driver. 446 * The bridge driver then determines the child devices to pass 447 * the interrupt. Certain information of the device can be read 448 * only once(eg the value of HISR). The bridge driver is responsible 449 * to pass such the information to the children. 450 */ 451 452static int 453csa_setup_intr(device_t bus, device_t child, 454 struct resource *irq, int flags, 455 driver_filter_t *filter, 456 driver_intr_t *intr, void *arg, void **cookiep) 457{ 458 sc_p scp; 459 csa_res *resp; 460 struct sndcard_func *func; 461 462 if (filter != NULL) { 463 printf("ata-csa.c: we cannot use a filter here\n"); 464 return (EINVAL); 465 } 466 scp = device_get_softc(bus); 467 resp = &scp->res; 468 469 /* 470 * Look at the function code of the child to determine 471 * the appropriate hander for it. 472 */ 473 func = device_get_ivars(child); 474 if (func == NULL || irq != resp->irq) 475 return (EINVAL); 476 477 switch (func->func) { 478 case SCF_PCM: 479 scp->pcmintr = intr; 480 scp->pcmintr_arg = arg; 481 break; 482 483 case SCF_MIDI: 484 scp->midiintr = intr; 485 scp->midiintr_arg = arg; 486 break; 487 488 default: 489 return (EINVAL); 490 } 491 *cookiep = scp; 492 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 493 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 494 495 return (0); 496} 497 498static int 499csa_teardown_intr(device_t bus, device_t child, 500 struct resource *irq, void *cookie) 501{ 502 sc_p scp; 503 csa_res *resp; 504 struct sndcard_func *func; 505 506 scp = device_get_softc(bus); 507 resp = &scp->res; 508 509 /* 510 * Look at the function code of the child to determine 511 * the appropriate hander for it. 512 */ 513 func = device_get_ivars(child); 514 if (func == NULL || irq != resp->irq || cookie != scp) 515 return (EINVAL); 516 517 switch (func->func) { 518 case SCF_PCM: 519 scp->pcmintr = NULL; 520 scp->pcmintr_arg = NULL; 521 break; 522 523 case SCF_MIDI: 524 scp->midiintr = NULL; 525 scp->midiintr_arg = NULL; 526 break; 527 528 default: 529 return (EINVAL); 530 } 531 532 return (0); 533} 534 535/* The interrupt handler */ 536static void 537csa_intr(void *arg) 538{ 539 sc_p scp = arg; 540 csa_res *resp; 541 u_int32_t hisr; 542 543 resp = &scp->res; 544 545 /* Is this interrupt for us? */ 546 hisr = csa_readio(resp, BA0_HISR); 547 if ((hisr & 0x7fffffff) == 0) { 548 /* Throw an eoi. */ 549 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 550 return; 551 } 552 553 /* 554 * Pass the value of HISR via struct csa_bridgeinfo. 555 * The children get access through their ivars. 556 */ 557 scp->binfo.hisr = hisr; 558 559 /* Invoke the handlers of the children. */ 560 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 561 scp->pcmintr(scp->pcmintr_arg); 562 hisr &= ~(HISR_VC0 | HISR_VC1); 563 } 564 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 565 scp->midiintr(scp->midiintr_arg); 566 hisr &= ~HISR_MIDI; 567 } 568 569 /* Throw an eoi. */ 570 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 571} 572 573static int 574csa_initialize(sc_p scp) 575{ 576 int i; 577 u_int32_t acsts, acisv; 578 csa_res *resp; 579 580 resp = &scp->res; 581 582 /* 583 * First, blast the clock control register to zero so that the PLL starts 584 * out in a known state, and blast the master serial port control register 585 * to zero so that the serial ports also start out in a known state. 586 */ 587 csa_writeio(resp, BA0_CLKCR1, 0); 588 csa_writeio(resp, BA0_SERMC1, 0); 589 590 /* 591 * If we are in AC97 mode, then we must set the part to a host controlled 592 * AC-link. Otherwise, we won't be able to bring up the link. 593 */ 594#if 1 595 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 596#else 597 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 598#endif /* 1 */ 599 600 /* 601 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 602 * spec) and then drive it high. This is done for non AC97 modes since 603 * there might be logic external to the CS461x that uses the ARST# line 604 * for a reset. 605 */ 606 csa_writeio(resp, BA0_ACCTL, 1); 607 DELAY(50); 608 csa_writeio(resp, BA0_ACCTL, 0); 609 DELAY(50); 610 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 611 612 /* 613 * The first thing we do here is to enable sync generation. As soon 614 * as we start receiving bit clock, we'll start producing the SYNC 615 * signal. 616 */ 617 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 618 619 /* 620 * Now wait for a short while to allow the AC97 part to start 621 * generating bit clock (so we don't try to start the PLL without an 622 * input clock). 623 */ 624 DELAY(50000); 625 626 /* 627 * Set the serial port timing configuration, so that 628 * the clock control circuit gets its clock from the correct place. 629 */ 630 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 631 DELAY(700000); 632 633 /* 634 * Write the selected clock control setup to the hardware. Do not turn on 635 * SWCE yet (if requested), so that the devices clocked by the output of 636 * PLL are not clocked until the PLL is stable. 637 */ 638 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 639 csa_writeio(resp, BA0_PLLM, 0x3a); 640 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 641 642 /* 643 * Power up the PLL. 644 */ 645 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 646 647 /* 648 * Wait until the PLL has stabilized. 649 */ 650 DELAY(5000); 651 652 /* 653 * Turn on clocking of the core so that we can setup the serial ports. 654 */ 655 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 656 657 /* 658 * Fill the serial port FIFOs with silence. 659 */ 660 csa_clearserialfifos(resp); 661 662 /* 663 * Set the serial port FIFO pointer to the first sample in the FIFO. 664 */ 665#ifdef notdef 666 csa_writeio(resp, BA0_SERBSP, 0); 667#endif /* notdef */ 668 669 /* 670 * Write the serial port configuration to the part. The master 671 * enable bit is not set until all other values have been written. 672 */ 673 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 674 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 675 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 676 677 /* 678 * Wait for the codec ready signal from the AC97 codec. 679 */ 680 acsts = 0; 681 for (i = 0 ; i < 1000 ; i++) { 682 /* 683 * First, lets wait a short while to let things settle out a bit, 684 * and to prevent retrying the read too quickly. 685 */ 686 DELAY(125); 687 688 /* 689 * Read the AC97 status register to see if we've seen a CODEC READY 690 * signal from the AC97 codec. 691 */ 692 acsts = csa_readio(resp, BA0_ACSTS); 693 if ((acsts & ACSTS_CRDY) != 0) 694 break; 695 } 696 697 /* 698 * Make sure we sampled CODEC READY. 699 */ 700 if ((acsts & ACSTS_CRDY) == 0) 701 return (ENXIO); 702 703 /* 704 * Assert the vaid frame signal so that we can start sending commands 705 * to the AC97 codec. 706 */ 707 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 708 709 /* 710 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 711 * the codec is pumping ADC data across the AC-link. 712 */ 713 acisv = 0; 714 for (i = 0 ; i < 2000 ; i++) { 715 /* 716 * First, lets wait a short while to let things settle out a bit, 717 * and to prevent retrying the read too quickly. 718 */ 719#ifdef notdef 720 DELAY(10000000L); /* clw */ 721#else 722 DELAY(1000); 723#endif /* notdef */ 724 /* 725 * Read the input slot valid register and see if input slots 3 and 726 * 4 are valid yet. 727 */ 728 acisv = csa_readio(resp, BA0_ACISV); 729 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 730 break; 731 } 732 /* 733 * Make sure we sampled valid input slots 3 and 4. If not, then return 734 * an error. 735 */ 736 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 737 return (ENXIO); 738 739 /* 740 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 741 * commense the transfer of digital audio data to the AC97 codec. 742 */ 743 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 744 745 /* 746 * Power down the DAC and ADC. We will power them up (if) when we need 747 * them. 748 */ 749#ifdef notdef 750 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 751#endif /* notdef */ 752 753 /* 754 * Turn off the Processor by turning off the software clock enable flag in 755 * the clock control register. 756 */ 757#ifdef notdef 758 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 759 csa_writeio(resp, BA0_CLKCR1, clkcr1); 760#endif /* notdef */ 761 762 /* 763 * Enable interrupts on the part. 764 */ 765#if 0 766 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 767#endif /* notdef */ 768 769 return (0); 770} 771 772void 773csa_clearserialfifos(csa_res *resp) 774{ 775 int i, j, pwr; 776 u_int8_t clkcr1, serbst; 777 778 /* 779 * See if the devices are powered down. If so, we must power them up first 780 * or they will not respond. 781 */ 782 pwr = 1; 783 clkcr1 = csa_readio(resp, BA0_CLKCR1); 784 if ((clkcr1 & CLKCR1_SWCE) == 0) { 785 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 786 pwr = 0; 787 } 788 789 /* 790 * We want to clear out the serial port FIFOs so we don't end up playing 791 * whatever random garbage happens to be in them. We fill the sample FIFOs 792 * with zero (silence). 793 */ 794 csa_writeio(resp, BA0_SERBWP, 0); 795 796 /* Fill all 256 sample FIFO locations. */ 797 serbst = 0; 798 for (i = 0 ; i < 256 ; i++) { 799 /* Make sure the previous FIFO write operation has completed. */ 800 for (j = 0 ; j < 5 ; j++) { 801 DELAY(100); 802 serbst = csa_readio(resp, BA0_SERBST); 803 if ((serbst & SERBST_WBSY) == 0) 804 break; 805 } 806 if ((serbst & SERBST_WBSY) != 0) { 807 if (!pwr) 808 csa_writeio(resp, BA0_CLKCR1, clkcr1); 809 } 810 /* Write the serial port FIFO index. */ 811 csa_writeio(resp, BA0_SERBAD, i); 812 /* Tell the serial port to load the new value into the FIFO location. */ 813 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 814 } 815 /* 816 * Now, if we powered up the devices, then power them back down again. 817 * This is kinda ugly, but should never happen. 818 */ 819 if (!pwr) 820 csa_writeio(resp, BA0_CLKCR1, clkcr1); 821} 822 823void 824csa_resetdsp(csa_res *resp) 825{ 826 int i; 827 828 /* 829 * Write the reset bit of the SP control register. 830 */ 831 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 832 833 /* 834 * Write the control register. 835 */ 836 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 837 838 /* 839 * Clear the trap registers. 840 */ 841 for (i = 0 ; i < 8 ; i++) { 842 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 843 csa_writemem(resp, BA1_TWPR, 0xffff); 844 } 845 csa_writemem(resp, BA1_DREG, 0); 846 847 /* 848 * Set the frame timer to reflect the number of cycles per frame. 849 */ 850 csa_writemem(resp, BA1_FRMT, 0xadf); 851} 852 853static int 854csa_downloadimage(csa_res *resp) 855{ 856 int ret; 857 u_long ul, offset; 858 859 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 860 /* 861 * DMA this block from host memory to the appropriate 862 * memory on the CSDevice. 863 */ 864 ret = csa_transferimage(resp, 865 cs461x_firmware.BA1Array + offset, 866 cs461x_firmware.MemoryStat[ul].ulDestAddr, 867 cs461x_firmware.MemoryStat[ul].ulSourceSize); 868 if (ret) 869 return (ret); 870 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 871 } 872 return (0); 873} 874 875static int 876csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 877{ 878 u_long ul; 879 880 /* 881 * We do not allow DMAs from host memory to host memory (although the DMA 882 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 883 * in size (because that DMA can not do that). Return an error if either 884 * of these conditions exist. 885 */ 886 if ((len & 0x3) != 0) 887 return (EINVAL); 888 889 /* Check the destination address that it is a multiple of 4 */ 890 if ((dest & 0x3) != 0) 891 return (EINVAL); 892 893 /* Write the buffer out. */ 894 for (ul = 0 ; ul < len ; ul += 4) 895 csa_writemem(resp, dest + ul, src[ul >> 2]); 896 return (0); 897} 898 899int 900csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 901{ 902 int i; 903 u_int32_t acctl, acsts; 904 905 /* 906 * Make sure that there is not data sitting around from a previous 907 * uncompleted access. ACSDA = Status Data Register = 47Ch 908 */ 909 csa_readio(resp, BA0_ACSDA); 910 911 /* 912 * Setup the AC97 control registers on the CS461x to send the 913 * appropriate command to the AC97 to perform the read. 914 * ACCAD = Command Address Register = 46Ch 915 * ACCDA = Command Data Register = 470h 916 * ACCTL = Control Register = 460h 917 * set DCV - will clear when process completed 918 * set CRW - Read command 919 * set VFRM - valid frame enabled 920 * set ESYN - ASYNC generation enabled 921 * set RSTN - ARST# inactive, AC97 codec not reset 922 */ 923 924 /* 925 * Get the actual AC97 register from the offset 926 */ 927 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 928 csa_writeio(resp, BA0_ACCDA, 0); 929 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 930 931 /* 932 * Wait for the read to occur. 933 */ 934 acctl = 0; 935 for (i = 0 ; i < 10 ; i++) { 936 /* 937 * First, we want to wait for a short time. 938 */ 939 DELAY(25); 940 941 /* 942 * Now, check to see if the read has completed. 943 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 944 */ 945 acctl = csa_readio(resp, BA0_ACCTL); 946 if ((acctl & ACCTL_DCV) == 0) 947 break; 948 } 949 950 /* 951 * Make sure the read completed. 952 */ 953 if ((acctl & ACCTL_DCV) != 0) 954 return (EAGAIN); 955 956 /* 957 * Wait for the valid status bit to go active. 958 */ 959 acsts = 0; 960 for (i = 0 ; i < 10 ; i++) { 961 /* 962 * Read the AC97 status register. 963 * ACSTS = Status Register = 464h 964 */ 965 acsts = csa_readio(resp, BA0_ACSTS); 966 /* 967 * See if we have valid status. 968 * VSTS - Valid Status 969 */ 970 if ((acsts & ACSTS_VSTS) != 0) 971 break; 972 /* 973 * Wait for a short while. 974 */ 975 DELAY(25); 976 } 977 978 /* 979 * Make sure we got valid status. 980 */ 981 if ((acsts & ACSTS_VSTS) == 0) 982 return (EAGAIN); 983 984 /* 985 * Read the data returned from the AC97 register. 986 * ACSDA = Status Data Register = 474h 987 */ 988 *data = csa_readio(resp, BA0_ACSDA); 989 990 return (0); 991} 992 993int 994csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 995{ 996 int i; 997 u_int32_t acctl; 998 999 /* 1000 * Setup the AC97 control registers on the CS461x to send the 1001 * appropriate command to the AC97 to perform the write. 1002 * ACCAD = Command Address Register = 46Ch 1003 * ACCDA = Command Data Register = 470h 1004 * ACCTL = Control Register = 460h 1005 * set DCV - will clear when process completed 1006 * set VFRM - valid frame enabled 1007 * set ESYN - ASYNC generation enabled 1008 * set RSTN - ARST# inactive, AC97 codec not reset 1009 */ 1010 1011 /* 1012 * Get the actual AC97 register from the offset 1013 */ 1014 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 1015 csa_writeio(resp, BA0_ACCDA, data); 1016 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1017 1018 /* 1019 * Wait for the write to occur. 1020 */ 1021 acctl = 0; 1022 for (i = 0 ; i < 10 ; i++) { 1023 /* 1024 * First, we want to wait for a short time. 1025 */ 1026 DELAY(25); 1027 1028 /* 1029 * Now, check to see if the read has completed. 1030 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1031 */ 1032 acctl = csa_readio(resp, BA0_ACCTL); 1033 if ((acctl & ACCTL_DCV) == 0) 1034 break; 1035 } 1036 1037 /* 1038 * Make sure the write completed. 1039 */ 1040 if ((acctl & ACCTL_DCV) != 0) 1041 return (EAGAIN); 1042 1043 return (0); 1044} 1045 1046u_int32_t 1047csa_readio(csa_res *resp, u_long offset) 1048{ 1049 u_int32_t ul; 1050 1051 if (offset < BA0_AC97_RESET) 1052 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1053 else { 1054 if (csa_readcodec(resp, offset, &ul)) 1055 ul = 0; 1056 return (ul); 1057 } 1058} 1059 1060void 1061csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1062{ 1063 if (offset < BA0_AC97_RESET) 1064 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1065 else 1066 csa_writecodec(resp, offset, data); 1067} 1068 1069u_int32_t 1070csa_readmem(csa_res *resp, u_long offset) 1071{ 1072 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1073} 1074 1075void 1076csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1077{ 1078 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1079} 1080 1081static device_method_t csa_methods[] = { 1082 /* Device interface */ 1083 DEVMETHOD(device_probe, csa_probe), 1084 DEVMETHOD(device_attach, csa_attach), 1085 DEVMETHOD(device_detach, csa_detach), 1086 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1087 DEVMETHOD(device_suspend, bus_generic_suspend), 1088 DEVMETHOD(device_resume, csa_resume), 1089 1090 /* Bus interface */ 1091 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1092 DEVMETHOD(bus_release_resource, csa_release_resource), 1093 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1094 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1095 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1096 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1097 1098 DEVMETHOD_END 1099}; 1100 1101static driver_t csa_driver = { 1102 "csa", 1103 csa_methods, 1104 sizeof(struct csa_softc), 1105}; 1106 1107/* 1108 * csa can be attached to a pci bus. 1109 */ 1110DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1111MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1112MODULE_VERSION(snd_csa, 1); 1113