1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35#ifndef _SYS_SIENA_FLASH_H 36#define _SYS_SIENA_FLASH_H 37 38#pragma pack(1) 39 40/* Fixed locations near the start of flash (which may be in the internal PHY 41 * firmware header) point to the boot header. 42 * 43 * - parsed by MC boot ROM and firmware 44 * - reserved (but not parsed) by PHY firmware 45 * - opaque to driver 46 */ 47 48#define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20) 49 50#define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */ 51#define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */ 52 53#define SIENA_MC_BOOT_HDR_LEN (0x200) 54 55#define SIENA_MC_BOOT_MAGIC (0x51E4A001) 56#define SIENA_MC_BOOT_VERSION (1) 57 58/*Structures supporting an arbitrary number of binary blobs in the flash image 59 intended to house code and tables for the satellite cpus*/ 60/*thanks to random.org for:*/ 61#define BLOBS_HEADER_MAGIC (0xBDA3BBD4) 62#define BLOB_HEADER_MAGIC (0xA1478A91) 63 64typedef struct blobs_hdr_s { /* GENERATED BY scripts/genfwdef */ 65 efx_dword_t magic; 66 efx_dword_t no_of_blobs; 67} blobs_hdr_t; 68 69typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */ 70 efx_dword_t magic; 71 efx_dword_t cpu_type; 72 efx_dword_t build_variant; 73 efx_dword_t offset; 74 efx_dword_t length; 75 efx_dword_t checksum; 76} blob_hdr_t; 77 78#define BLOB_CPU_TYPE_TXDI_TEXT (0) 79#define BLOB_CPU_TYPE_RXDI_TEXT (1) 80#define BLOB_CPU_TYPE_TXDP_TEXT (2) 81#define BLOB_CPU_TYPE_RXDP_TEXT (3) 82#define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4) 83#define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5) 84#define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6) 85#define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7) 86#define BLOB_CPU_TYPE_RXHRSL_HR_PGM (8) 87#define BLOB_CPU_TYPE_RXHRSL_SL_PGM (9) 88#define BLOB_CPU_TYPE_TXHRSL_HR_PGM (10) 89#define BLOB_CPU_TYPE_TXHRSL_SL_PGM (11) 90#define BLOB_CPU_TYPE_RXDI_VTBL0 (12) 91#define BLOB_CPU_TYPE_TXDI_VTBL0 (13) 92#define BLOB_CPU_TYPE_RXDI_VTBL1 (14) 93#define BLOB_CPU_TYPE_TXDI_VTBL1 (15) 94#define BLOB_CPU_TYPE_DUMPSPEC (32) 95#define BLOB_CPU_TYPE_MC_XIP (33) 96 97#define BLOB_CPU_TYPE_INVALID (31) 98 99/* 100 * The upper four bits of the CPU type field specify the compression 101 * algorithm used for this blob. 102 */ 103#define BLOB_COMPRESSION_MASK (0xf0000000) 104#define BLOB_CPU_TYPE_MASK (0x0fffffff) 105 106#define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */ 107#define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */ 108 109typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ 110 efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */ 111 efx_word_t hdr_version; /* this structure definition is version 1 */ 112 efx_byte_t board_type; 113 efx_byte_t firmware_version_a; 114 efx_byte_t firmware_version_b; 115 efx_byte_t firmware_version_c; 116 efx_word_t checksum; /* of whole header area + firmware image */ 117 efx_word_t firmware_version_d; 118 efx_byte_t mcfw_subtype; 119 efx_byte_t generation; /* MC (Medford and later): MC partition generation when */ 120 /* written to NVRAM. */ 121 /* MUM & SUC images: subtype. */ 122 /* (Otherwise set to 0) */ 123 efx_dword_t firmware_text_offset; /* offset to firmware .text */ 124 efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ 125 efx_dword_t firmware_data_offset; /* offset to firmware .data */ 126 efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ 127 efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ 128 efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ 129 efx_word_t xpm_sector; /* XPM (MEDFORD and later): The sector that contains */ 130 /* the key, or 0xffff if unsigned. (Otherwise set to 0) */ 131 efx_byte_t mumfw_subtype; /* MUM & SUC images: subtype. (Otherwise set to 0) */ 132 efx_byte_t reserved_b[3]; /* (set to 0) */ 133 efx_dword_t security_level; /* This number increases every time a serious security flaw */ 134 /* is fixed. A secure NIC may not downgrade to any image */ 135 /* with a lower security level than the current image. */ 136 /* Note: The number in this header should only be used for */ 137 /* determining the level of new images, not to determine */ 138 /* the level of the current image as this header is not */ 139 /* protected by a CMAC. */ 140 efx_dword_t reserved_c[5]; /* (set to 0) */ 141} siena_mc_boot_hdr_t; 142 143#define SIENA_MC_BOOT_HDR_PADDING \ 144 (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t)) 145 146#define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555) 147#define SIENA_MC_STATIC_CONFIG_VERSION (0) 148 149typedef struct siena_mc_static_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 150 efx_dword_t magic; /* = SIENA_MC_STATIC_CONFIG_MAGIC */ 151 efx_word_t length; /* of header area (i.e. not including VPD) */ 152 efx_byte_t version; 153 efx_byte_t csum; /* over header area (i.e. not including VPD) */ 154 efx_dword_t static_vpd_offset; 155 efx_dword_t static_vpd_length; 156 efx_dword_t capabilities; 157 efx_byte_t mac_addr_base[6]; 158 efx_byte_t green_mode_cal; /* Green mode calibration result */ 159 efx_byte_t green_mode_valid; /* Whether cal holds a valid value */ 160 efx_word_t mac_addr_count; 161 efx_word_t mac_addr_stride; 162 efx_word_t calibrated_vref; /* Vref as measured during production */ 163 efx_word_t adc_vref; /* Vref as read by ADC */ 164 efx_dword_t reserved2[1]; /* (write as zero) */ 165 efx_dword_t num_dbi_items; 166 struct { 167 efx_word_t addr; 168 efx_word_t byte_enables; 169 efx_dword_t value; 170 } dbi[]; 171} siena_mc_static_config_hdr_t; 172 173#define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD) 174#define SIENA_MC_DYNAMIC_CONFIG_VERSION (0) 175 176typedef struct siena_mc_fw_version_s { /* GENERATED BY scripts/genfwdef */ 177 efx_dword_t fw_subtype; 178 efx_word_t version_w; 179 efx_word_t version_x; 180 efx_word_t version_y; 181 efx_word_t version_z; 182} siena_mc_fw_version_t; 183 184typedef struct siena_mc_dynamic_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 185 efx_dword_t magic; /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */ 186 efx_word_t length; /* of header area (i.e. not including VPD) */ 187 efx_byte_t version; 188 efx_byte_t csum; /* over header area (i.e. not including VPD) */ 189 efx_dword_t dynamic_vpd_offset; 190 efx_dword_t dynamic_vpd_length; 191 efx_dword_t num_fw_version_items; 192 siena_mc_fw_version_t fw_version[]; 193} siena_mc_dynamic_config_hdr_t; 194 195#define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55) /* little-endian uint16_t */ 196 197#define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102) /* little-endian uint32_t */ 198#define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103) /* little-endian uint32_t */ 199 200typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */ 201 efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */ 202 union { 203 struct { 204 efx_dword_t len1; /* length of first image */ 205 efx_dword_t len2; /* length of second image */ 206 efx_dword_t off1; /* offset of first byte to edit to combine images */ 207 efx_dword_t off2; /* offset of second byte to edit to combine images */ 208 efx_word_t infoblk0_off;/* infoblk offset */ 209 efx_word_t infoblk1_off;/* infoblk offset */ 210 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 211 efx_byte_t reserved[7];/* (set to 0) */ 212 } v1; 213 struct { 214 efx_dword_t len1; /* length of first image */ 215 efx_dword_t len2; /* length of second image */ 216 efx_dword_t off1; /* offset of first byte to edit to combine images */ 217 efx_dword_t off2; /* offset of second byte to edit to combine images */ 218 efx_word_t infoblk_off;/* infoblk start offset */ 219 efx_word_t infoblk_count;/* infoblk count */ 220 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 221 efx_byte_t reserved[7];/* (set to 0) */ 222 } v2; 223 } data; 224} siena_mc_combo_rom_hdr_t; 225 226#pragma pack() 227 228#endif /* _SYS_SIENA_FLASH_H */ 229