1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _SYS_EFX_REGS_MCDI_AOE_H 31#define _SYS_EFX_REGS_MCDI_AOE_H 32 33/***********************************/ 34/* MC_CMD_FC 35 * Perform an FC operation 36 */ 37#define MC_CMD_FC 0x9 38 39/* MC_CMD_FC_IN msgrequest */ 40#define MC_CMD_FC_IN_LEN 4 41#define MC_CMD_FC_IN_OP_HDR_OFST 0 42#define MC_CMD_FC_IN_OP_HDR_LEN 4 43#define MC_CMD_FC_IN_OP_LBN 0 44#define MC_CMD_FC_IN_OP_WIDTH 8 45/* enum: NULL MCDI command to FC. */ 46#define MC_CMD_FC_OP_NULL 0x1 47/* enum: Unused opcode */ 48#define MC_CMD_FC_OP_UNUSED 0x2 49/* enum: MAC driver commands */ 50#define MC_CMD_FC_OP_MAC 0x3 51/* enum: Read FC memory */ 52#define MC_CMD_FC_OP_READ32 0x4 53/* enum: Write to FC memory */ 54#define MC_CMD_FC_OP_WRITE32 0x5 55/* enum: Read FC memory */ 56#define MC_CMD_FC_OP_TRC_READ 0x6 57/* enum: Write to FC memory */ 58#define MC_CMD_FC_OP_TRC_WRITE 0x7 59/* enum: FC firmware Version */ 60#define MC_CMD_FC_OP_GET_VERSION 0x8 61/* enum: Read FC memory */ 62#define MC_CMD_FC_OP_TRC_RX_READ 0x9 63/* enum: Write to FC memory */ 64#define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 65/* enum: SFP parameters */ 66#define MC_CMD_FC_OP_SFP 0xb 67/* enum: DDR3 test */ 68#define MC_CMD_FC_OP_DDR_TEST 0xc 69/* enum: Get Crash context from FC */ 70#define MC_CMD_FC_OP_GET_ASSERT 0xd 71/* enum: Get FPGA Build registers */ 72#define MC_CMD_FC_OP_FPGA_BUILD 0xe 73/* enum: Read map support commands */ 74#define MC_CMD_FC_OP_READ_MAP 0xf 75/* enum: FC Capabilities */ 76#define MC_CMD_FC_OP_CAPABILITIES 0x10 77/* enum: FC Global flags */ 78#define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 79/* enum: FC IO using relative addressing modes */ 80#define MC_CMD_FC_OP_IO_REL 0x12 81/* enum: FPGA link information */ 82#define MC_CMD_FC_OP_UHLINK 0x13 83/* enum: Configure loopbacks and link on FPGA ports */ 84#define MC_CMD_FC_OP_SET_LINK 0x14 85/* enum: Licensing operations relating to AOE */ 86#define MC_CMD_FC_OP_LICENSE 0x15 87/* enum: Startup information to the FC */ 88#define MC_CMD_FC_OP_STARTUP 0x16 89/* enum: Configure a DMA read */ 90#define MC_CMD_FC_OP_DMA 0x17 91/* enum: Configure a timed read */ 92#define MC_CMD_FC_OP_TIMED_READ 0x18 93/* enum: Control UART logging */ 94#define MC_CMD_FC_OP_LOG 0x19 95/* enum: Get the value of a given clock_id */ 96#define MC_CMD_FC_OP_CLOCK 0x1a 97/* enum: DDR3/QDR3 parameters */ 98#define MC_CMD_FC_OP_DDR 0x1b 99/* enum: PTP and timestamp control */ 100#define MC_CMD_FC_OP_TIMESTAMP 0x1c 101/* enum: Commands for SPI Flash interface */ 102#define MC_CMD_FC_OP_SPI 0x1d 103/* enum: Commands for diagnostic components */ 104#define MC_CMD_FC_OP_DIAG 0x1e 105/* enum: External AOE port. */ 106#define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 107/* enum: Internal AOE port. */ 108#define MC_CMD_FC_IN_PORT_INT_OFST 0x40 109 110/* MC_CMD_FC_IN_NULL msgrequest */ 111#define MC_CMD_FC_IN_NULL_LEN 4 112#define MC_CMD_FC_IN_CMD_OFST 0 113#define MC_CMD_FC_IN_CMD_LEN 4 114 115/* MC_CMD_FC_IN_PHY msgrequest */ 116#define MC_CMD_FC_IN_PHY_LEN 5 117/* MC_CMD_FC_IN_CMD_OFST 0 */ 118/* MC_CMD_FC_IN_CMD_LEN 4 */ 119/* FC PHY driver operation code */ 120#define MC_CMD_FC_IN_PHY_OP_OFST 4 121#define MC_CMD_FC_IN_PHY_OP_LEN 1 122/* enum: PHY init handler */ 123#define MC_CMD_FC_OP_PHY_OP_INIT 0x1 124/* enum: PHY reconfigure handler */ 125#define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 126/* enum: PHY reboot handler */ 127#define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 128/* enum: PHY get_supported_cap handler */ 129#define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 130/* enum: PHY get_config handler */ 131#define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 132/* enum: PHY get_media_info handler */ 133#define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 134/* enum: PHY set_led handler */ 135#define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 136/* enum: PHY lasi_interrupt handler */ 137#define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 138/* enum: PHY check_link handler */ 139#define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 140/* enum: PHY fill_stats handler */ 141#define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 142/* enum: PHY bpx_link_state_changed handler */ 143#define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 144/* enum: PHY get_state handler */ 145#define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 146/* enum: PHY start_bist handler */ 147#define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 148/* enum: PHY poll_bist handler */ 149#define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 150/* enum: PHY nvram_test handler */ 151#define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 152/* enum: PHY relinquish handler */ 153#define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 154/* enum: PHY read connection from FC - may be not required */ 155#define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 156/* enum: PHY read flags from FC - may be not required */ 157#define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 158 159/* MC_CMD_FC_IN_PHY_INIT msgrequest */ 160#define MC_CMD_FC_IN_PHY_INIT_LEN 4 161#define MC_CMD_FC_IN_PHY_CMD_OFST 0 162#define MC_CMD_FC_IN_PHY_CMD_LEN 4 163 164/* MC_CMD_FC_IN_MAC msgrequest */ 165#define MC_CMD_FC_IN_MAC_LEN 8 166/* MC_CMD_FC_IN_CMD_OFST 0 */ 167/* MC_CMD_FC_IN_CMD_LEN 4 */ 168#define MC_CMD_FC_IN_MAC_HEADER_OFST 4 169#define MC_CMD_FC_IN_MAC_HEADER_LEN 4 170#define MC_CMD_FC_IN_MAC_OP_LBN 0 171#define MC_CMD_FC_IN_MAC_OP_WIDTH 8 172/* enum: MAC reconfigure handler */ 173#define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 174/* enum: MAC Set command - same as MC_CMD_SET_MAC */ 175#define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 176/* enum: MAC statistics */ 177#define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 178/* enum: MAC RX statistics */ 179#define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 180/* enum: MAC TX statistics */ 181#define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 182/* enum: MAC Read status */ 183#define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 184#define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 185#define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 186/* enum: External FPGA port. */ 187#define MC_CMD_FC_PORT_EXT 0x0 188/* enum: Internal Siena-facing FPGA ports. */ 189#define MC_CMD_FC_PORT_INT 0x1 190#define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 191#define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 192#define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 193#define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 194/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 195 * irrelevant. Port number is derived from pci_fn; passed in FC header. 196 */ 197#define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 198/* enum: Override default port number. Port number determined by fields 199 * PORT_TYPE and PORT_IDX. 200 */ 201#define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 202 203/* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 204#define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 205/* MC_CMD_FC_IN_CMD_OFST 0 */ 206/* MC_CMD_FC_IN_CMD_LEN 4 */ 207/* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 208/* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 209 210/* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 211#define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 212/* MC_CMD_FC_IN_CMD_OFST 0 */ 213/* MC_CMD_FC_IN_CMD_LEN 4 */ 214/* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 215/* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 216/* MTU size */ 217#define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 218#define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4 219/* Drain Tx FIFO */ 220#define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 221#define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4 222#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 223#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 224#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 225#define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 226#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 227#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4 228#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 229#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 230#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 231#define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 232#define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 233#define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4 234 235/* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 236#define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 237/* MC_CMD_FC_IN_CMD_OFST 0 */ 238/* MC_CMD_FC_IN_CMD_LEN 4 */ 239/* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 240/* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 241 242/* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 243#define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 244/* MC_CMD_FC_IN_CMD_OFST 0 */ 245/* MC_CMD_FC_IN_CMD_LEN 4 */ 246/* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 247/* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 248 249/* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 250#define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 251/* MC_CMD_FC_IN_CMD_OFST 0 */ 252/* MC_CMD_FC_IN_CMD_LEN 4 */ 253/* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 254/* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 255 256/* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 257#define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 258/* MC_CMD_FC_IN_CMD_OFST 0 */ 259/* MC_CMD_FC_IN_CMD_LEN 4 */ 260/* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 261/* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 262/* MC Statistics index */ 263#define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 264#define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4 265#define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 266#define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4 267#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 268#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 269#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 270#define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 271#define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 272#define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 273/* Number of statistics to read */ 274#define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 275#define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4 276#define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 277#define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 278 279/* MC_CMD_FC_IN_READ32 msgrequest */ 280#define MC_CMD_FC_IN_READ32_LEN 16 281/* MC_CMD_FC_IN_CMD_OFST 0 */ 282/* MC_CMD_FC_IN_CMD_LEN 4 */ 283#define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 284#define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4 285#define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 286#define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4 287#define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 288#define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4 289 290/* MC_CMD_FC_IN_WRITE32 msgrequest */ 291#define MC_CMD_FC_IN_WRITE32_LENMIN 16 292#define MC_CMD_FC_IN_WRITE32_LENMAX 252 293#define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 294/* MC_CMD_FC_IN_CMD_OFST 0 */ 295/* MC_CMD_FC_IN_CMD_LEN 4 */ 296#define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 297#define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4 298#define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 299#define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4 300#define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 301#define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 302#define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 303#define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 304 305/* MC_CMD_FC_IN_TRC_READ msgrequest */ 306#define MC_CMD_FC_IN_TRC_READ_LEN 12 307/* MC_CMD_FC_IN_CMD_OFST 0 */ 308/* MC_CMD_FC_IN_CMD_LEN 4 */ 309#define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 310#define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4 311#define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 312#define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4 313 314/* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 315#define MC_CMD_FC_IN_TRC_WRITE_LEN 28 316/* MC_CMD_FC_IN_CMD_OFST 0 */ 317/* MC_CMD_FC_IN_CMD_LEN 4 */ 318#define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 319#define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4 320#define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 321#define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4 322#define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 323#define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 324#define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 325 326/* MC_CMD_FC_IN_GET_VERSION msgrequest */ 327#define MC_CMD_FC_IN_GET_VERSION_LEN 4 328/* MC_CMD_FC_IN_CMD_OFST 0 */ 329/* MC_CMD_FC_IN_CMD_LEN 4 */ 330 331/* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 332#define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 333/* MC_CMD_FC_IN_CMD_OFST 0 */ 334/* MC_CMD_FC_IN_CMD_LEN 4 */ 335#define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 336#define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4 337#define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 338#define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4 339 340/* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 341#define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 342/* MC_CMD_FC_IN_CMD_OFST 0 */ 343/* MC_CMD_FC_IN_CMD_LEN 4 */ 344#define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 345#define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4 346#define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 347#define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4 348#define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 349#define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 350#define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 351 352/* MC_CMD_FC_IN_SFP msgrequest */ 353#define MC_CMD_FC_IN_SFP_LEN 28 354/* MC_CMD_FC_IN_CMD_OFST 0 */ 355/* MC_CMD_FC_IN_CMD_LEN 4 */ 356/* Link speed is 100, 1000, 10000, 40000 */ 357#define MC_CMD_FC_IN_SFP_SPEED_OFST 4 358#define MC_CMD_FC_IN_SFP_SPEED_LEN 4 359/* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 360#define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 361#define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4 362/* Not relevant for cards with QSFP modules. For older cards, true if module is 363 * a dual speed SFP+ module. 364 */ 365#define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 366#define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4 367/* True if an SFP Module is present (other fields valid when true) */ 368#define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 369#define MC_CMD_FC_IN_SFP_PRESENT_LEN 4 370/* The type of the SFP+ Module. For later cards with QSFP modules, this field 371 * is unused and the type is communicated by other means. 372 */ 373#define MC_CMD_FC_IN_SFP_TYPE_OFST 20 374#define MC_CMD_FC_IN_SFP_TYPE_LEN 4 375/* Capabilities corresponding to 1 bits. */ 376#define MC_CMD_FC_IN_SFP_CAPS_OFST 24 377#define MC_CMD_FC_IN_SFP_CAPS_LEN 4 378 379/* MC_CMD_FC_IN_DDR_TEST msgrequest */ 380#define MC_CMD_FC_IN_DDR_TEST_LEN 8 381/* MC_CMD_FC_IN_CMD_OFST 0 */ 382/* MC_CMD_FC_IN_CMD_LEN 4 */ 383#define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 384#define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 385#define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 386#define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 387/* enum: DRAM Test Start */ 388#define MC_CMD_FC_OP_DDR_TEST_START 0x1 389/* enum: DRAM Test Poll */ 390#define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 391 392/* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 393#define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 394/* MC_CMD_FC_IN_CMD_OFST 0 */ 395/* MC_CMD_FC_IN_CMD_LEN 4 */ 396/* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 397/* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 398#define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 399#define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4 400#define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 401#define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 402#define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 403#define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 404#define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 405#define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 406#define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 407#define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 408 409/* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 410#define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 411#define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 412#define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4 413/* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 414/* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 415/* Clear previous test result and prepare for restarting DDR test */ 416#define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 417#define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4 418 419/* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 420#define MC_CMD_FC_IN_GET_ASSERT_LEN 4 421/* MC_CMD_FC_IN_CMD_OFST 0 */ 422/* MC_CMD_FC_IN_CMD_LEN 4 */ 423 424/* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 425#define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 426/* MC_CMD_FC_IN_CMD_OFST 0 */ 427/* MC_CMD_FC_IN_CMD_LEN 4 */ 428/* FPGA build info operation code */ 429#define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 430#define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4 431/* enum: Get the build registers */ 432#define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 433/* enum: Get the services registers */ 434#define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 435/* enum: Get the BSP version */ 436#define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 437/* enum: Get build register for V2 (SFA974X) */ 438#define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 439/* enum: GEt the services register for V2 (SFA974X) */ 440#define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 441 442/* MC_CMD_FC_IN_READ_MAP msgrequest */ 443#define MC_CMD_FC_IN_READ_MAP_LEN 8 444/* MC_CMD_FC_IN_CMD_OFST 0 */ 445/* MC_CMD_FC_IN_CMD_LEN 4 */ 446#define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 447#define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 448#define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 449#define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 450/* enum: Get the number of map regions */ 451#define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 452/* enum: Get the specified map */ 453#define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 454 455/* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 456#define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 457/* MC_CMD_FC_IN_CMD_OFST 0 */ 458/* MC_CMD_FC_IN_CMD_LEN 4 */ 459/* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 460/* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 461 462/* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 463#define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 464/* MC_CMD_FC_IN_CMD_OFST 0 */ 465/* MC_CMD_FC_IN_CMD_LEN 4 */ 466/* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 467/* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 468#define MC_CMD_FC_IN_MAP_INDEX_OFST 8 469#define MC_CMD_FC_IN_MAP_INDEX_LEN 4 470 471/* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 472#define MC_CMD_FC_IN_CAPABILITIES_LEN 4 473/* MC_CMD_FC_IN_CMD_OFST 0 */ 474/* MC_CMD_FC_IN_CMD_LEN 4 */ 475 476/* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 477#define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 478/* MC_CMD_FC_IN_CMD_OFST 0 */ 479/* MC_CMD_FC_IN_CMD_LEN 4 */ 480#define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 481#define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4 482#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 483#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 484#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 485#define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 486#define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 487#define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 488#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 489#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 490#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 491#define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 492#define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 493#define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 494 495/* MC_CMD_FC_IN_IO_REL msgrequest */ 496#define MC_CMD_FC_IN_IO_REL_LEN 8 497/* MC_CMD_FC_IN_CMD_OFST 0 */ 498/* MC_CMD_FC_IN_CMD_LEN 4 */ 499#define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 500#define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 501#define MC_CMD_FC_IN_IO_REL_OP_LBN 0 502#define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 503/* enum: Get the base address that the FC applies to relative commands */ 504#define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 505/* enum: Read data */ 506#define MC_CMD_FC_IN_IO_REL_READ32 0x2 507/* enum: Write data */ 508#define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 509#define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 510#define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 511/* enum: Application address space */ 512#define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 513/* enum: Flash address space */ 514#define MC_CMD_FC_COMP_TYPE_FLASH 0x2 515 516/* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 517#define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 518/* MC_CMD_FC_IN_CMD_OFST 0 */ 519/* MC_CMD_FC_IN_CMD_LEN 4 */ 520/* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 521/* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 522 523/* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 524#define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 525/* MC_CMD_FC_IN_CMD_OFST 0 */ 526/* MC_CMD_FC_IN_CMD_LEN 4 */ 527/* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 528/* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 529#define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 530#define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4 531#define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 532#define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4 533#define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 534#define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4 535 536/* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 537#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 538#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 539#define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 540/* MC_CMD_FC_IN_CMD_OFST 0 */ 541/* MC_CMD_FC_IN_CMD_LEN 4 */ 542/* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 543/* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 544#define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 545#define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4 546#define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 547#define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4 548#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 549#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 550#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 551#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 552 553/* MC_CMD_FC_IN_UHLINK msgrequest */ 554#define MC_CMD_FC_IN_UHLINK_LEN 8 555/* MC_CMD_FC_IN_CMD_OFST 0 */ 556/* MC_CMD_FC_IN_CMD_LEN 4 */ 557#define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 558#define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 559#define MC_CMD_FC_IN_UHLINK_OP_LBN 0 560#define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 561/* enum: Get PHY configuration info */ 562#define MC_CMD_FC_OP_UHLINK_PHY 0x1 563/* enum: Get MAC configuration info */ 564#define MC_CMD_FC_OP_UHLINK_MAC 0x2 565/* enum: Get Rx eye table */ 566#define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 567/* enum: Get Rx eye plot */ 568#define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 569/* enum: Get Rx eye plot */ 570#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 571/* enum: Retune Rx settings */ 572#define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 573/* enum: Set loopback mode on fpga port */ 574#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 575/* enum: Get loopback mode config state on fpga port */ 576#define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 577#define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 578#define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 579#define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 580#define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 581#define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 582#define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 583/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 584 * irrelevant. Port number is derived from pci_fn; passed in FC header. 585 */ 586#define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 587/* enum: Override default port number. Port number determined by fields 588 * PORT_TYPE and PORT_IDX. 589 */ 590#define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 591 592/* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 593#define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 594/* MC_CMD_FC_IN_CMD_OFST 0 */ 595/* MC_CMD_FC_IN_CMD_LEN 4 */ 596/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 597/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 598 599/* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 600#define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 601/* MC_CMD_FC_IN_CMD_OFST 0 */ 602/* MC_CMD_FC_IN_CMD_LEN 4 */ 603/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 604/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 605 606/* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 607#define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 608/* MC_CMD_FC_IN_CMD_OFST 0 */ 609/* MC_CMD_FC_IN_CMD_LEN 4 */ 610/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 611/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 612#define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 613#define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4 614#define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 615 616/* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 617#define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 618/* MC_CMD_FC_IN_CMD_OFST 0 */ 619/* MC_CMD_FC_IN_CMD_LEN 4 */ 620/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 621/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 622 623/* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 624#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 625/* MC_CMD_FC_IN_CMD_OFST 0 */ 626/* MC_CMD_FC_IN_CMD_LEN 4 */ 627/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 628/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 629#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 630#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4 631#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 632#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4 633#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 634#define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4 635#define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 636 637/* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 638#define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 639/* MC_CMD_FC_IN_CMD_OFST 0 */ 640/* MC_CMD_FC_IN_CMD_LEN 4 */ 641/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 642/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 643 644/* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 645#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 646/* MC_CMD_FC_IN_CMD_OFST 0 */ 647/* MC_CMD_FC_IN_CMD_LEN 4 */ 648/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 649/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 650#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 651#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4 652#define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 653#define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 654#define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 655#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 656#define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4 657#define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 658#define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 659 660/* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 661#define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 662/* MC_CMD_FC_IN_CMD_OFST 0 */ 663/* MC_CMD_FC_IN_CMD_LEN 4 */ 664/* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 665/* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 666#define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 667#define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4 668 669/* MC_CMD_FC_IN_SET_LINK msgrequest */ 670#define MC_CMD_FC_IN_SET_LINK_LEN 16 671/* MC_CMD_FC_IN_CMD_OFST 0 */ 672/* MC_CMD_FC_IN_CMD_LEN 4 */ 673/* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 674#define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 675#define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4 676#define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 677#define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4 678#define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 679#define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4 680#define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 681#define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 682#define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 683#define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 684#define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 685#define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 686 687/* MC_CMD_FC_IN_LICENSE msgrequest */ 688#define MC_CMD_FC_IN_LICENSE_LEN 8 689/* MC_CMD_FC_IN_CMD_OFST 0 */ 690/* MC_CMD_FC_IN_CMD_LEN 4 */ 691#define MC_CMD_FC_IN_LICENSE_OP_OFST 4 692#define MC_CMD_FC_IN_LICENSE_OP_LEN 4 693#define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 694#define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 695 696/* MC_CMD_FC_IN_STARTUP msgrequest */ 697#define MC_CMD_FC_IN_STARTUP_LEN 40 698/* MC_CMD_FC_IN_CMD_OFST 0 */ 699/* MC_CMD_FC_IN_CMD_LEN 4 */ 700#define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 701#define MC_CMD_FC_IN_STARTUP_BASE_LEN 4 702#define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 703#define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4 704/* Length of identifier */ 705#define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 706#define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4 707/* Identifier for AOE FPGA */ 708#define MC_CMD_FC_IN_STARTUP_ID_OFST 16 709#define MC_CMD_FC_IN_STARTUP_ID_LEN 1 710#define MC_CMD_FC_IN_STARTUP_ID_NUM 24 711 712/* MC_CMD_FC_IN_DMA msgrequest */ 713#define MC_CMD_FC_IN_DMA_LEN 8 714/* MC_CMD_FC_IN_CMD_OFST 0 */ 715/* MC_CMD_FC_IN_CMD_LEN 4 */ 716#define MC_CMD_FC_IN_DMA_OP_OFST 4 717#define MC_CMD_FC_IN_DMA_OP_LEN 4 718#define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 719#define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 720 721/* MC_CMD_FC_IN_DMA_STOP msgrequest */ 722#define MC_CMD_FC_IN_DMA_STOP_LEN 12 723/* MC_CMD_FC_IN_CMD_OFST 0 */ 724/* MC_CMD_FC_IN_CMD_LEN 4 */ 725/* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 726/* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 727/* FC supplied handle */ 728#define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 729#define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4 730 731/* MC_CMD_FC_IN_DMA_READ msgrequest */ 732#define MC_CMD_FC_IN_DMA_READ_LEN 16 733/* MC_CMD_FC_IN_CMD_OFST 0 */ 734/* MC_CMD_FC_IN_CMD_LEN 4 */ 735/* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 736/* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 737#define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 738#define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4 739#define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 740#define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4 741 742/* MC_CMD_FC_IN_TIMED_READ msgrequest */ 743#define MC_CMD_FC_IN_TIMED_READ_LEN 8 744/* MC_CMD_FC_IN_CMD_OFST 0 */ 745/* MC_CMD_FC_IN_CMD_LEN 4 */ 746#define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 747#define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 748#define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 749#define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 750#define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 751 752/* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 753#define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 754/* MC_CMD_FC_IN_CMD_OFST 0 */ 755/* MC_CMD_FC_IN_CMD_LEN 4 */ 756/* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 757/* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 758/* Host supplied handle (unique) */ 759#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 760#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4 761/* Address into which to transfer data in host */ 762#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 763#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 764#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 765#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 766/* AOE address from which to transfer data */ 767#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 768#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 769#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 770#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 771/* Length of AOE transfer (total) */ 772#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 773#define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4 774/* Length of host transfer (total) */ 775#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 776#define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4 777/* Offset back from aoe_address to apply operation to */ 778#define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 779#define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4 780/* Data to apply at offset */ 781#define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 782#define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4 783#define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 784#define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4 785#define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 786#define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 787#define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 788#define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 789#define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 790#define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 791#define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 792#define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 793#define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 794#define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 795#define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 796#define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 797/* Period at which reads are performed (100ms units) */ 798#define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 799#define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4 800 801/* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 802#define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 803/* MC_CMD_FC_IN_CMD_OFST 0 */ 804/* MC_CMD_FC_IN_CMD_LEN 4 */ 805/* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 806/* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 807/* FC supplied handle */ 808#define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 809#define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4 810 811/* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 812#define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 813/* MC_CMD_FC_IN_CMD_OFST 0 */ 814/* MC_CMD_FC_IN_CMD_LEN 4 */ 815/* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 816/* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 817/* FC supplied handle */ 818#define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 819#define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4 820 821/* MC_CMD_FC_IN_LOG msgrequest */ 822#define MC_CMD_FC_IN_LOG_LEN 8 823/* MC_CMD_FC_IN_CMD_OFST 0 */ 824/* MC_CMD_FC_IN_CMD_LEN 4 */ 825#define MC_CMD_FC_IN_LOG_OP_OFST 4 826#define MC_CMD_FC_IN_LOG_OP_LEN 4 827#define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 828#define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 829 830/* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 831#define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 832/* MC_CMD_FC_IN_CMD_OFST 0 */ 833/* MC_CMD_FC_IN_CMD_LEN 4 */ 834/* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 835/* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 836/* Partition offset into flash */ 837#define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 838#define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4 839/* Partition length */ 840#define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 841#define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4 842/* Partition erase size */ 843#define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 844#define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4 845 846/* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 847#define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 848/* MC_CMD_FC_IN_CMD_OFST 0 */ 849/* MC_CMD_FC_IN_CMD_LEN 4 */ 850/* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 851/* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 852/* Enable/disable printing to JTAG UART */ 853#define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 854#define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4 855 856/* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */ 857#define MC_CMD_FC_IN_CLOCK_LEN 12 858/* MC_CMD_FC_IN_CMD_OFST 0 */ 859/* MC_CMD_FC_IN_CMD_LEN 4 */ 860#define MC_CMD_FC_IN_CLOCK_OP_OFST 4 861#define MC_CMD_FC_IN_CLOCK_OP_LEN 4 862#define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 863#define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 864#define MC_CMD_FC_IN_CLOCK_ID_OFST 8 865#define MC_CMD_FC_IN_CLOCK_ID_LEN 4 866#define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 867#define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 868 869/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the 870 * specified clock 871 */ 872#define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 873/* MC_CMD_FC_IN_CMD_OFST 0 */ 874/* MC_CMD_FC_IN_CMD_LEN 4 */ 875/* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 876/* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 877/* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 878/* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 879 880/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified 881 * clock 882 */ 883#define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 884/* MC_CMD_FC_IN_CMD_OFST 0 */ 885/* MC_CMD_FC_IN_CMD_LEN 4 */ 886/* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 887/* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 888/* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 889/* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 890#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 891#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 892#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 893#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 894#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 895#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4 896 897/* MC_CMD_FC_IN_DDR msgrequest */ 898#define MC_CMD_FC_IN_DDR_LEN 12 899/* MC_CMD_FC_IN_CMD_OFST 0 */ 900/* MC_CMD_FC_IN_CMD_LEN 4 */ 901#define MC_CMD_FC_IN_DDR_OP_OFST 4 902#define MC_CMD_FC_IN_DDR_OP_LEN 4 903#define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 904#define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 905#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 906#define MC_CMD_FC_IN_DDR_BANK_OFST 8 907#define MC_CMD_FC_IN_DDR_BANK_LEN 4 908#define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 909#define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 910#define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 911#define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 912#define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 913 914/* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 915#define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 916/* MC_CMD_FC_IN_CMD_OFST 0 */ 917/* MC_CMD_FC_IN_CMD_LEN 4 */ 918/* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 919/* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 920/* Affected bank */ 921/* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 922/* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 923/* Flags */ 924#define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 925#define MC_CMD_FC_IN_DDR_FLAGS_LEN 4 926#define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 927/* 128-byte page of serial presence detect data read from module's EEPROM */ 928#define MC_CMD_FC_IN_DDR_SPD_OFST 16 929#define MC_CMD_FC_IN_DDR_SPD_LEN 1 930#define MC_CMD_FC_IN_DDR_SPD_NUM 128 931/* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 932#define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 933#define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4 934 935/* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 936#define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 937/* MC_CMD_FC_IN_CMD_OFST 0 */ 938/* MC_CMD_FC_IN_CMD_LEN 4 */ 939/* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 940/* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 941/* Affected bank */ 942/* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 943/* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 944/* Size of DDR */ 945#define MC_CMD_FC_IN_DDR_SIZE_OFST 12 946#define MC_CMD_FC_IN_DDR_SIZE_LEN 4 947 948/* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 949#define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 950/* MC_CMD_FC_IN_CMD_OFST 0 */ 951/* MC_CMD_FC_IN_CMD_LEN 4 */ 952/* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 953/* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 954/* Affected bank */ 955/* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 956/* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 957 958/* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 959#define MC_CMD_FC_IN_TIMESTAMP_LEN 8 960/* MC_CMD_FC_IN_CMD_OFST 0 */ 961/* MC_CMD_FC_IN_CMD_LEN 4 */ 962/* FC timestamp operation code */ 963#define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 964#define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4 965/* enum: Read transmit timestamp(s) */ 966#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 967/* enum: Read snapshot timestamps */ 968#define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 969/* enum: Clear all transmit timestamps */ 970#define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 971 972/* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 973#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 974/* MC_CMD_FC_IN_CMD_OFST 0 */ 975/* MC_CMD_FC_IN_CMD_LEN 4 */ 976#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 977#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4 978/* Control filtering of the returned timestamp and sequence number specified 979 * here 980 */ 981#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 982#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4 983/* enum: Return most recent timestamp. No filtering */ 984#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 985/* enum: Match timestamp against the PTP clock ID, port number and sequence 986 * number specified 987 */ 988#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 989/* Clock identity of PTP packet for which timestamp required */ 990#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 991#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 992#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 993#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 994/* Port number of PTP packet for which timestamp required */ 995#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 996#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4 997/* Sequence number of PTP packet for which timestamp required */ 998#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 999#define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4 1000 1001/* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1002#define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1003/* MC_CMD_FC_IN_CMD_OFST 0 */ 1004/* MC_CMD_FC_IN_CMD_LEN 4 */ 1005#define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1006#define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4 1007 1008/* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1009#define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1010/* MC_CMD_FC_IN_CMD_OFST 0 */ 1011/* MC_CMD_FC_IN_CMD_LEN 4 */ 1012#define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1013#define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4 1014 1015/* MC_CMD_FC_IN_SPI msgrequest */ 1016#define MC_CMD_FC_IN_SPI_LEN 8 1017/* MC_CMD_FC_IN_CMD_OFST 0 */ 1018/* MC_CMD_FC_IN_CMD_LEN 4 */ 1019/* Basic commands for SPI Flash. */ 1020#define MC_CMD_FC_IN_SPI_OP_OFST 4 1021#define MC_CMD_FC_IN_SPI_OP_LEN 4 1022/* enum: SPI Flash read */ 1023#define MC_CMD_FC_IN_SPI_READ 0x0 1024/* enum: SPI Flash write */ 1025#define MC_CMD_FC_IN_SPI_WRITE 0x1 1026/* enum: SPI Flash erase */ 1027#define MC_CMD_FC_IN_SPI_ERASE 0x2 1028 1029/* MC_CMD_FC_IN_SPI_READ msgrequest */ 1030#define MC_CMD_FC_IN_SPI_READ_LEN 16 1031/* MC_CMD_FC_IN_CMD_OFST 0 */ 1032/* MC_CMD_FC_IN_CMD_LEN 4 */ 1033#define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1034#define MC_CMD_FC_IN_SPI_READ_OP_LEN 4 1035#define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1036#define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4 1037#define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1038#define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4 1039 1040/* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1041#define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1042#define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1043#define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1044/* MC_CMD_FC_IN_CMD_OFST 0 */ 1045/* MC_CMD_FC_IN_CMD_LEN 4 */ 1046#define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1047#define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4 1048#define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1049#define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4 1050#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1051#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1052#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1053#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1054 1055/* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1056#define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1057/* MC_CMD_FC_IN_CMD_OFST 0 */ 1058/* MC_CMD_FC_IN_CMD_LEN 4 */ 1059#define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1060#define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4 1061#define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1062#define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4 1063#define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1064#define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4 1065 1066/* MC_CMD_FC_IN_DIAG msgrequest */ 1067#define MC_CMD_FC_IN_DIAG_LEN 8 1068/* MC_CMD_FC_IN_CMD_OFST 0 */ 1069/* MC_CMD_FC_IN_CMD_LEN 4 */ 1070/* Operation code indicating component type */ 1071#define MC_CMD_FC_IN_DIAG_OP_OFST 4 1072#define MC_CMD_FC_IN_DIAG_OP_LEN 4 1073/* enum: Power noise generator. */ 1074#define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1075/* enum: DDR soak test component. */ 1076#define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1077/* enum: Diagnostics datapath control component. */ 1078#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1079 1080/* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1081#define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1082/* MC_CMD_FC_IN_CMD_OFST 0 */ 1083/* MC_CMD_FC_IN_CMD_LEN 4 */ 1084#define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1085#define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4 1086/* Sub-opcode describing the operation to be carried out */ 1087#define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1088#define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4 1089/* enum: Read the configuration (the 32-bit values in each of the clock enable 1090 * count and toggle count registers) 1091 */ 1092#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 1093/* enum: Write a new configuration to the clock enable count and toggle count 1094 * registers 1095 */ 1096#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 1097 1098/* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 1099#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 1100/* MC_CMD_FC_IN_CMD_OFST 0 */ 1101/* MC_CMD_FC_IN_CMD_LEN 4 */ 1102#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 1103#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4 1104#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 1105#define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4 1106 1107/* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 1108#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 1109/* MC_CMD_FC_IN_CMD_OFST 0 */ 1110/* MC_CMD_FC_IN_CMD_LEN 4 */ 1111#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 1112#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4 1113#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 1114#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4 1115/* The 32-bit value to be written to the toggle count register */ 1116#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 1117#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4 1118/* The 32-bit value to be written to the clock enable count register */ 1119#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 1120#define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4 1121 1122/* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 1123#define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 1124/* MC_CMD_FC_IN_CMD_OFST 0 */ 1125/* MC_CMD_FC_IN_CMD_LEN 4 */ 1126#define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 1127#define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4 1128/* Sub-opcode describing the operation to be carried out */ 1129#define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 1130#define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4 1131/* enum: Starts DDR soak test on selected banks */ 1132#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 1133/* enum: Read status of DDR soak test */ 1134#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 1135/* enum: Stop test */ 1136#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 1137/* enum: Set or clear bit that triggers fake errors. These cause subsequent 1138 * tests to fail until the bit is cleared. 1139 */ 1140#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 1141 1142/* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 1143#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 1144/* MC_CMD_FC_IN_CMD_OFST 0 */ 1145/* MC_CMD_FC_IN_CMD_LEN 4 */ 1146#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 1147#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4 1148#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 1149#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4 1150/* Mask of DDR banks to be tested */ 1151#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 1152#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4 1153/* Pattern to use in the soak test */ 1154#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 1155#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4 1156#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 1157#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 1158/* Either multiple automatic tests until a STOP command is issued, or one 1159 * single test 1160 */ 1161#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 1162#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4 1163#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 1164#define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 1165 1166/* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 1167#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 1168/* MC_CMD_FC_IN_CMD_OFST 0 */ 1169/* MC_CMD_FC_IN_CMD_LEN 4 */ 1170#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 1171#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4 1172#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 1173#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4 1174/* DDR bank to read status from */ 1175#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 1176#define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4 1177#define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 1178#define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 1179#define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 1180#define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 1181#define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 1182 1183/* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 1184#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 1185/* MC_CMD_FC_IN_CMD_OFST 0 */ 1186/* MC_CMD_FC_IN_CMD_LEN 4 */ 1187#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 1188#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4 1189#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 1190#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4 1191/* Mask of DDR banks to be tested */ 1192#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 1193#define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4 1194 1195/* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 1196#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 1197/* MC_CMD_FC_IN_CMD_OFST 0 */ 1198/* MC_CMD_FC_IN_CMD_LEN 4 */ 1199#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 1200#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4 1201#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 1202#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4 1203/* Mask of DDR banks to set/clear error flag on */ 1204#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 1205#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4 1206#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 1207#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4 1208#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 1209#define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 1210 1211/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 1212#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 1213/* MC_CMD_FC_IN_CMD_OFST 0 */ 1214/* MC_CMD_FC_IN_CMD_LEN 4 */ 1215#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 1216#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4 1217/* Sub-opcode describing the operation to be carried out */ 1218#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 1219#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4 1220/* enum: Set a known datapath configuration */ 1221#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 1222/* enum: Apply raw config to datapath control registers */ 1223#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 1224 1225/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 1226#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 1227/* MC_CMD_FC_IN_CMD_OFST 0 */ 1228/* MC_CMD_FC_IN_CMD_LEN 4 */ 1229#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 1230#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4 1231#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 1232#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4 1233/* Datapath configuration identifier */ 1234#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 1235#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4 1236#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 1237#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 1238 1239/* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 1240#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 1241/* MC_CMD_FC_IN_CMD_OFST 0 */ 1242/* MC_CMD_FC_IN_CMD_LEN 4 */ 1243#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 1244#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4 1245#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 1246#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4 1247/* Value to write into control register 1 */ 1248#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 1249#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4 1250/* Value to write into control register 2 */ 1251#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 1252#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4 1253/* Value to write into control register 3 */ 1254#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 1255#define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4 1256 1257/* MC_CMD_FC_OUT msgresponse */ 1258#define MC_CMD_FC_OUT_LEN 0 1259 1260/* MC_CMD_FC_OUT_NULL msgresponse */ 1261#define MC_CMD_FC_OUT_NULL_LEN 0 1262 1263/* MC_CMD_FC_OUT_READ32 msgresponse */ 1264#define MC_CMD_FC_OUT_READ32_LENMIN 4 1265#define MC_CMD_FC_OUT_READ32_LENMAX 252 1266#define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 1267#define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 1268#define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 1269#define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 1270#define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 1271 1272/* MC_CMD_FC_OUT_WRITE32 msgresponse */ 1273#define MC_CMD_FC_OUT_WRITE32_LEN 0 1274 1275/* MC_CMD_FC_OUT_TRC_READ msgresponse */ 1276#define MC_CMD_FC_OUT_TRC_READ_LEN 16 1277#define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 1278#define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 1279#define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 1280 1281/* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 1282#define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 1283 1284/* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 1285#define MC_CMD_FC_OUT_GET_VERSION_LEN 12 1286#define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 1287#define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4 1288#define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 1289#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 1290#define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 1291#define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 1292 1293/* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 1294#define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 1295#define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 1296#define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 1297#define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 1298 1299/* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 1300#define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 1301 1302/* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 1303#define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 1304 1305/* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 1306#define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 1307 1308/* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 1309#define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 1310#define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 1311#define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4 1312 1313/* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 1314#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 1315#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 1316#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 1317#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 1318#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 1319#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 1320#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 1321#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 1322#define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 1323#define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1324#define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 1325#define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 1326#define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 1327#define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 1328#define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 1329#define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 1330#define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 1331#define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 1332#define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 1333#define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1334#define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 1335#define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 1336#define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 1337#define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 1338#define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 1339#define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 1340#define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 1341#define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 1342#define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 1343#define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 1344#define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 1345/* enum: (Last entry) */ 1346#define MC_CMD_FC_MAC_RX_NSTATS 0x19 1347 1348/* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 1349#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 1350#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 1351#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 1352#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 1353#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 1354#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 1355#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 1356#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 1357#define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 1358#define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1359#define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 1360#define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 1361#define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 1362#define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 1363#define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 1364#define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 1365#define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 1366#define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 1367#define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 1368#define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1369#define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 1370#define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 1371#define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 1372#define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 1373#define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 1374#define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 1375#define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 1376#define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 1377/* enum: (Last entry) */ 1378#define MC_CMD_FC_MAC_TX_NSTATS 0x16 1379 1380/* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 1381#define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 1382/* MAC Statistics */ 1383#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 1384#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 1385#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 1386#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 1387#define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 1388 1389/* MC_CMD_FC_OUT_MAC msgresponse */ 1390#define MC_CMD_FC_OUT_MAC_LEN 0 1391 1392/* MC_CMD_FC_OUT_SFP msgresponse */ 1393#define MC_CMD_FC_OUT_SFP_LEN 0 1394 1395/* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 1396#define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 1397 1398/* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 1399#define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 1400#define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 1401#define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4 1402#define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 1403#define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 1404/* enum: Test not yet initiated */ 1405#define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 1406/* enum: Test is in progress */ 1407#define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 1408/* enum: Timed completed */ 1409#define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 1410/* enum: Test did not complete in specified time */ 1411#define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 1412#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 1413#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 1414#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 1415#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 1416#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 1417#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 1418#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 1419#define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 1420/* Test result from FPGA */ 1421#define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 1422#define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4 1423#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 1424#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 1425#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 1426#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 1427#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 1428#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 1429#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 1430#define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 1431#define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 1432#define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 1433#define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 1434#define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 1435#define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 1436#define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 1437#define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 1438#define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 1439#define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 1440#define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 1441#define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 1442#define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 1443#define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 1444 1445/* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 1446#define MC_CMD_FC_OUT_DDR_TEST_LEN 0 1447 1448/* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 1449#define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 1450/* Assertion status flag. */ 1451#define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 1452#define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4 1453#define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 1454#define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 1455/* enum: No crash data available */ 1456#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 1457/* enum: New crash data available */ 1458#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 1459/* enum: Crash data has been sent */ 1460#define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 1461#define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 1462#define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 1463/* enum: No crash has been recorded. */ 1464#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 1465/* enum: Crash due to exception. */ 1466#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 1467/* enum: Crash due to assertion. */ 1468#define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 1469/* Failing PC value */ 1470#define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 1471#define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4 1472/* Saved GP regs */ 1473#define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 1474#define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 1475#define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 1476/* Exception Type */ 1477#define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 1478#define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4 1479/* Instruction at which exception occurred */ 1480#define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 1481#define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4 1482/* BAD Address that triggered address-based exception */ 1483#define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 1484#define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4 1485 1486/* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 1487#define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 1488#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 1489#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4 1490#define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 1491#define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 1492#define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 1493#define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 1494#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 1495#define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 1496#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 1497#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 1498#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 1499#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 1500#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 1501#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 1502/* Build timestamp (seconds since epoch) */ 1503#define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 1504#define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4 1505#define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 1506#define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4 1507#define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 1508#define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 1509#define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 1510#define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 1511#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 1512#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 1513#define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 1514#define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 1515#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 1516#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 1517#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 1518#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 1519#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 1520#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 1521#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 1522#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 1523#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 1524#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 1525#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 1526#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 1527#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 1528#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 1529#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 1530#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 1531#define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 1532#define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 1533#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 1534#define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 1535#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 1536#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 1537#define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 1538#define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 1539#define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 1540#define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4 1541#define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 1542#define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 1543#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 1544#define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 1545#define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 1546#define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 1547#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 1548#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 1549#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 1550#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4 1551#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 1552#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1553#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 1554#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1555#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 1556#define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4 1557#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 1558#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1559#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 1560#define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1561#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 1562#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 1563#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 1564#define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 1565#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 1566#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4 1567#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 1568#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4 1569#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 1570#define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 1571 1572/* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 1573#define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 1574#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 1575#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4 1576#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 1577#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 1578#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 1579#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 1580#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 1581#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 1582#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 1583#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 1584#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 1585#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 1586#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 1587#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 1588/* Build timestamp (seconds since epoch) */ 1589#define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 1590#define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4 1591#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 1592#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4 1593#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 1594#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 1595#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 1596#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 1597#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 1598#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 1599#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 1600#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 1601#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 1602#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 1603#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 1604#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 1605#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 1606#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 1607#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 1608#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 1609#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 1610#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 1611#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 1612#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 1613#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 1614#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 1615#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 1616#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 1617#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 1618#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 1619#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 1620#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 1621#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 1622#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 1623#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 1624#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 1625#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 1626#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 1627#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 1628#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 1629#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 1630#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 1631#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 1632#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 1633#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 1634#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 1635#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 1636#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 1637#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 1638#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 1639#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 1640#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 1641#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 1642#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 1643#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 1644#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 1645#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 1646#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 1647#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 1648#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 1649#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 1650#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 1651#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 1652#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 1653#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 1654#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 1655#define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 1656#define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 1657#define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 1658#define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 1659#define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 1660#define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 1661#define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 1662#define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 1663#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 1664#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4 1665#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 1666#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 1667#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 1668#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 1669/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1670/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1671#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 1672#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4 1673#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 1674#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1675#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 1676#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1677#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 1678#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4 1679#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 1680#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1681#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 1682#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1683#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 1684#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4 1685#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 1686#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4 1687#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 1688#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 1689 1690/* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 1691#define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 1692#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 1693#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4 1694#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 1695#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 1696#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 1697#define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 1698#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 1699#define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 1700#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 1701#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 1702#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 1703#define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 1704#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 1705#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 1706/* Build timestamp (seconds since epoch) */ 1707#define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 1708#define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4 1709#define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 1710#define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4 1711#define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 1712#define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 1713#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 1714#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 1715#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 1716#define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 1717#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 1718#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 1719#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 1720#define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 1721#define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 1722#define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 1723#define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 1724#define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4 1725#define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 1726#define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 1727#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 1728#define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 1729#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 1730#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4 1731#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 1732#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 1733#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 1734#define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 1735#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 1736#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4 1737#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 1738#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 1739#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 1740#define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 1741#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 1742#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4 1743#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 1744#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4 1745#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 1746#define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 1747 1748/* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 1749#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 1750#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 1751#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4 1752#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 1753#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 1754#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 1755#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 1756#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 1757#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 1758#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 1759#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 1760#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 1761#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 1762#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 1763#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 1764/* Build timestamp (seconds since epoch) */ 1765#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 1766#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4 1767#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 1768#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4 1769#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 1770#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 1771#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 1772#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 1773#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 1774#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4 1775#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 1776#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 1777#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 1778#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 1779/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1780/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1781#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 1782#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4 1783#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 1784#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4 1785#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 1786#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 1787 1788/* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 1789#define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 1790/* Qsys system ID */ 1791#define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 1792#define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4 1793#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 1794#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 1795#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 1796#define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 1797#define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 1798#define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 1799 1800/* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 1801#define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 1802/* Number of maps */ 1803#define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 1804#define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4 1805 1806/* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 1807#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 1808/* Index of the map */ 1809#define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 1810#define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4 1811/* Options for the map */ 1812#define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 1813#define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4 1814#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 1815#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 1816#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 1817#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 1818#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 1819#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 1820#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 1821#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 1822#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 1823#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 1824#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 1825/* Address of start of map */ 1826#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 1827#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 1828#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 1829#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 1830/* Length of address map */ 1831#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 1832#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 1833#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 1834#define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 1835/* Component information field */ 1836#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 1837#define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4 1838/* License expiry data for map */ 1839#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 1840#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 1841#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 1842#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 1843/* Name of the component */ 1844#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 1845#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 1846#define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 1847 1848/* MC_CMD_FC_OUT_READ_MAP msgresponse */ 1849#define MC_CMD_FC_OUT_READ_MAP_LEN 0 1850 1851/* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 1852#define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 1853/* Number of internal ports */ 1854#define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 1855#define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4 1856/* Number of external ports */ 1857#define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 1858#define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4 1859 1860/* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 1861#define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 1862#define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 1863#define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4 1864 1865/* MC_CMD_FC_OUT_IO_REL msgresponse */ 1866#define MC_CMD_FC_OUT_IO_REL_LEN 0 1867 1868/* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 1869#define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 1870#define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 1871#define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4 1872#define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 1873#define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4 1874 1875/* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 1876#define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 1877#define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 1878#define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 1879#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 1880#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 1881#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 1882#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 1883 1884/* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 1885#define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 1886 1887/* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 1888#define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 1889#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 1890#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4 1891#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 1892#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 1893#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 1894#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 1895/* Transceiver Transmit settings */ 1896#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 1897#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4 1898#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 1899#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 1900#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 1901#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 1902/* Transceiver Receive settings */ 1903#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 1904#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4 1905#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 1906#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 1907#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 1908#define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 1909/* Rx eye opening */ 1910#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 1911#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4 1912#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 1913#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 1914#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 1915#define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 1916/* PCS status word */ 1917#define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 1918#define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4 1919/* Link status word */ 1920#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 1921#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4 1922#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 1923#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 1924#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 1925#define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 1926/* Current SFp parameters applied */ 1927#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 1928#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 1929/* Link speed is 100, 1000, 10000 */ 1930#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 1931#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4 1932/* Length of copper cable - zero when not relevant */ 1933#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 1934#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4 1935/* True if a dual speed SFP+ module */ 1936#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 1937#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4 1938/* True if an SFP Module is present (other fields valid when true) */ 1939#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 1940#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4 1941/* The type of the SFP+ Module */ 1942#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 1943#define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4 1944/* PHY config flags */ 1945#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 1946#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4 1947#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 1948#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 1949#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 1950#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 1951#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 1952#define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 1953 1954/* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 1955#define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 1956/* MAC configuration applied */ 1957#define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 1958#define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4 1959/* MTU size */ 1960#define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 1961#define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4 1962/* IF Mode status */ 1963#define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 1964#define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4 1965/* MAC address configured */ 1966#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 1967#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 1968#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 1969#define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 1970 1971/* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 1972#define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 1973/* Rx Eye measurements */ 1974#define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 1975#define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 1976#define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 1977 1978/* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 1979#define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 1980 1981/* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 1982#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 1983/* Has the eye plot dump completed and data returned is valid? */ 1984#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 1985#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4 1986/* Rx Eye binary plot */ 1987#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 1988#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 1989#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 1990#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 1991#define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 1992 1993/* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 1994#define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 1995 1996/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 1997#define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 1998 1999/* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2000#define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2001#define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2002#define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4 2003 2004/* MC_CMD_FC_OUT_UHLINK msgresponse */ 2005#define MC_CMD_FC_OUT_UHLINK_LEN 0 2006 2007/* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2008#define MC_CMD_FC_OUT_SET_LINK_LEN 0 2009 2010/* MC_CMD_FC_OUT_LICENSE msgresponse */ 2011#define MC_CMD_FC_OUT_LICENSE_LEN 12 2012/* Count of valid keys */ 2013#define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2014#define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4 2015/* Count of invalid keys */ 2016#define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2017#define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4 2018/* Count of blacklisted keys */ 2019#define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2020#define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4 2021 2022/* MC_CMD_FC_OUT_STARTUP msgresponse */ 2023#define MC_CMD_FC_OUT_STARTUP_LEN 4 2024/* Capabilities of the FPGA/FC */ 2025#define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2026#define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4 2027#define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2028#define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2029 2030/* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2031#define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2032#define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2033#define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2034/* The data read */ 2035#define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2036#define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2037#define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2038#define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2039 2040/* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2041#define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2042/* Timer handle */ 2043#define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2044#define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4 2045 2046/* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2047#define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2048/* Host supplied handle (unique) */ 2049#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2050#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4 2051/* Address into which to transfer data in host */ 2052#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2053#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2054#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2055#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2056/* AOE address from which to transfer data */ 2057#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2058#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2059#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2060#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2061/* Length of AOE transfer (total) */ 2062#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2063#define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4 2064/* Length of host transfer (total) */ 2065#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2066#define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4 2067/* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2068#define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2069#define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4 2070#define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2071#define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4 2072/* When active, start read time */ 2073#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2074#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2075#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2076#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2077/* When active, end read time */ 2078#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2079#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2080#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2081#define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2082 2083/* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2084#define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2085 2086/* MC_CMD_FC_OUT_LOG msgresponse */ 2087#define MC_CMD_FC_OUT_LOG_LEN 0 2088 2089/* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2090#define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2091#define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2092#define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4 2093#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2094#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2095#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2096#define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2097#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2098#define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4 2099#define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2100#define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4 2101#define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2102#define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4 2103 2104/* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2105#define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2106 2107/* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2108#define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2109 2110/* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2111#define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2112 2113/* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2114#define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2115#define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2116#define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4 2117#define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2118#define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2119#define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2120#define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2121 2122/* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2123#define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2124#define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2125#define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4 2126#define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2127#define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4 2128 2129/* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2130#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2131#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2132#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2133#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2134#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4 2135#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2136#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4 2137#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2138#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2139#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2140#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2141#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2142#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2143 2144/* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2145#define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2146#define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2147#define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2148#define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2149#define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2150#define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2151#define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2152 2153/* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2154#define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2155 2156/* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2157#define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2158 2159/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2160#define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2161/* The 32-bit value read from the toggle count register */ 2162#define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2163#define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4 2164/* The 32-bit value read from the clock enable count register */ 2165#define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2166#define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4 2167 2168/* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2169#define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2170 2171/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2172#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2173 2174/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2175#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2176/* DDR soak test status word; bits [4:0] are relevant. */ 2177#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2178#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4 2179#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2180#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2181#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2182#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2183#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2184#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2185#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2186#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2187#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2188#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2189/* DDR soak test error count */ 2190#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2191#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4 2192 2193/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2194#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2195 2196/* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2197#define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2198 2199/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2200#define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2201 2202/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2203#define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2204 2205/***********************************/ 2206/* MC_CMD_AOE 2207 * AOE operations on MC 2208 */ 2209#define MC_CMD_AOE 0xa 2210 2211/* MC_CMD_AOE_IN msgrequest */ 2212#define MC_CMD_AOE_IN_LEN 4 2213#define MC_CMD_AOE_IN_OP_HDR_OFST 0 2214#define MC_CMD_AOE_IN_OP_HDR_LEN 4 2215#define MC_CMD_AOE_IN_OP_LBN 0 2216#define MC_CMD_AOE_IN_OP_WIDTH 8 2217/* enum: FPGA and CPLD information */ 2218#define MC_CMD_AOE_OP_INFO 0x1 2219/* enum: Currents and voltages read from MCP3424s; DEBUG */ 2220#define MC_CMD_AOE_OP_CURRENTS 0x2 2221/* enum: Temperatures at locations around the PCB; DEBUG */ 2222#define MC_CMD_AOE_OP_TEMPERATURES 0x3 2223/* enum: Set CPLD to idle */ 2224#define MC_CMD_AOE_OP_CPLD_IDLE 0x4 2225/* enum: Read from CPLD register */ 2226#define MC_CMD_AOE_OP_CPLD_READ 0x5 2227/* enum: Write to CPLD register */ 2228#define MC_CMD_AOE_OP_CPLD_WRITE 0x6 2229/* enum: Execute CPLD instruction */ 2230#define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 2231/* enum: Reprogram the CPLD on the AOE device */ 2232#define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 2233/* enum: AOE power control */ 2234#define MC_CMD_AOE_OP_POWER 0x9 2235/* enum: AOE image loading */ 2236#define MC_CMD_AOE_OP_LOAD 0xa 2237/* enum: Fan monitoring */ 2238#define MC_CMD_AOE_OP_FAN_CONTROL 0xb 2239/* enum: Fan failures since last reset */ 2240#define MC_CMD_AOE_OP_FAN_FAILURES 0xc 2241/* enum: Get generic AOE MAC statistics */ 2242#define MC_CMD_AOE_OP_MAC_STATS 0xd 2243/* enum: Retrieve PHY specific information */ 2244#define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 2245/* enum: Write a number of JTAG primitive commands, return will give data */ 2246#define MC_CMD_AOE_OP_JTAG_WRITE 0xf 2247/* enum: Control access to the FPGA via the Siena JTAG Chain */ 2248#define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 2249/* enum: Set the MTU offset between Siena and AOE MACs */ 2250#define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 2251/* enum: How link state is handled */ 2252#define MC_CMD_AOE_OP_LINK_STATE 0x12 2253/* enum: How Siena MAC statistics are reported (deprecated - use 2254 * MC_CMD_AOE_OP_ASIC_STATS) 2255 */ 2256#define MC_CMD_AOE_OP_SIENA_STATS 0x13 2257/* enum: How native ASIC MAC statistics are reported - replaces the deprecated 2258 * command MC_CMD_AOE_OP_SIENA_STATS 2259 */ 2260#define MC_CMD_AOE_OP_ASIC_STATS 0x13 2261/* enum: DDR memory information */ 2262#define MC_CMD_AOE_OP_DDR 0x14 2263/* enum: FC control */ 2264#define MC_CMD_AOE_OP_FC 0x15 2265/* enum: DDR ECC status reads */ 2266#define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 2267/* enum: Commands for MC-SPI Master emulation */ 2268#define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 2269/* enum: Commands for FC boot control */ 2270#define MC_CMD_AOE_OP_FC_BOOT 0x18 2271/* enum: Get number of internal ports */ 2272#define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19 2273/* enum: Get FC assert information and register dump */ 2274#define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a 2275 2276/* MC_CMD_AOE_OUT msgresponse */ 2277#define MC_CMD_AOE_OUT_LEN 0 2278 2279/* MC_CMD_AOE_IN_INFO msgrequest */ 2280#define MC_CMD_AOE_IN_INFO_LEN 4 2281#define MC_CMD_AOE_IN_CMD_OFST 0 2282#define MC_CMD_AOE_IN_CMD_LEN 4 2283 2284/* MC_CMD_AOE_IN_CURRENTS msgrequest */ 2285#define MC_CMD_AOE_IN_CURRENTS_LEN 4 2286/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2287/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2288 2289/* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 2290#define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 2291/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2292/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2293 2294/* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 2295#define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 2296/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2297/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2298 2299/* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 2300#define MC_CMD_AOE_IN_CPLD_READ_LEN 12 2301/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2302/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2303#define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 2304#define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4 2305#define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 2306#define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4 2307 2308/* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 2309#define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 2310/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2311/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2312#define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 2313#define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4 2314#define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 2315#define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4 2316#define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 2317#define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4 2318 2319/* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 2320#define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 2321/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2322/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2323#define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 2324#define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4 2325 2326/* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 2327#define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 2328/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2329/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2330#define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 2331#define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4 2332/* enum: Reprogram CPLD, poll for completion */ 2333#define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 2334/* enum: Reprogram CPLD, send event on completion */ 2335#define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 2336/* enum: Get status of reprogramming operation */ 2337#define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 2338 2339/* MC_CMD_AOE_IN_POWER msgrequest */ 2340#define MC_CMD_AOE_IN_POWER_LEN 8 2341/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2342/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2343/* Turn on or off AOE power */ 2344#define MC_CMD_AOE_IN_POWER_OP_OFST 4 2345#define MC_CMD_AOE_IN_POWER_OP_LEN 4 2346/* enum: Turn off FPGA power */ 2347#define MC_CMD_AOE_IN_POWER_OFF 0x0 2348/* enum: Turn on FPGA power */ 2349#define MC_CMD_AOE_IN_POWER_ON 0x1 2350/* enum: Clear peak power measurement */ 2351#define MC_CMD_AOE_IN_POWER_CLEAR 0x2 2352/* enum: Show current power in sensors output */ 2353#define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 2354/* enum: Show peak power in sensors output */ 2355#define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 2356/* enum: Show current DDR current */ 2357#define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 2358/* enum: Show peak DDR current */ 2359#define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 2360/* enum: Clear peak DDR current */ 2361#define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 2362 2363/* MC_CMD_AOE_IN_LOAD msgrequest */ 2364#define MC_CMD_AOE_IN_LOAD_LEN 8 2365/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2366/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2367/* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 2368 */ 2369#define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 2370#define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4 2371 2372/* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 2373#define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 2374/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2375/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2376/* If non zero report measured fan RPM rather than nominal */ 2377#define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 2378#define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4 2379 2380/* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 2381#define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 2382/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2383/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2384 2385/* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 2386#define MC_CMD_AOE_IN_MAC_STATS_LEN 24 2387/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2388/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2389/* AOE port */ 2390#define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 2391#define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4 2392/* Host memory address for statistics */ 2393#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 2394#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 2395#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 2396#define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 2397#define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 2398#define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4 2399#define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 2400#define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 2401#define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 2402#define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 2403#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 2404#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 2405#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 2406#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 2407#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 2408#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 2409#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 2410#define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 2411#define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 2412#define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 2413/* Length of DMA data (optional) */ 2414#define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 2415#define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4 2416 2417/* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 2418#define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 2419/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2420/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2421/* AOE port */ 2422#define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 2423#define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4 2424#define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 2425#define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4 2426 2427/* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 2428#define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 2429#define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 2430#define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 2431/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2432/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2433#define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 2434#define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4 2435#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 2436#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 2437#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 2438#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 2439 2440/* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 2441#define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 2442/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2443/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2444/* Enable or disable access */ 2445#define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 2446#define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4 2447/* enum: Enable access */ 2448#define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 2449/* enum: Disable access */ 2450#define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 2451 2452/* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 2453#define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 2454/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2455/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2456/* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 2457#define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 2458#define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4 2459/* enum: Apply to all external ports */ 2460#define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 2461/* enum: Apply to all internal ports */ 2462#define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 2463/* The MTU offset to be applied to the external ports */ 2464#define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 2465#define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4 2466 2467/* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 2468#define MC_CMD_AOE_IN_LINK_STATE_LEN 8 2469/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2470/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2471#define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 2472#define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4 2473#define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 2474#define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 2475/* enum: AOE and associated external port */ 2476#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 2477/* enum: AOE and OR of all external ports */ 2478#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 2479/* enum: Individual ports */ 2480#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 2481/* enum: Configure link state mode on given AOE port */ 2482#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 2483#define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 2484#define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 2485/* enum: No-op */ 2486#define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 2487/* enum: logical OR of all SFP ports link status */ 2488#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 2489/* enum: logical AND of all SFP ports link status */ 2490#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 2491#define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 2492#define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 2493 2494/* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */ 2495#define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4 2496/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2497/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2498 2499/* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */ 2500#define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4 2501/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2502/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2503 2504/* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 2505#define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 2506/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2507/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2508/* How MAC statistics are reported */ 2509#define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 2510#define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4 2511/* enum: Statistics from Siena (default) */ 2512#define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 2513/* enum: Statistics from AOE external ports */ 2514#define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 2515 2516/* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 2517#define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 2518/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2519/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2520/* How MAC statistics are reported */ 2521#define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 2522#define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4 2523/* enum: Statistics from the ASIC (default) */ 2524#define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 2525/* enum: Statistics from AOE external ports */ 2526#define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 2527 2528/* MC_CMD_AOE_IN_DDR msgrequest */ 2529#define MC_CMD_AOE_IN_DDR_LEN 12 2530/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2531/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2532#define MC_CMD_AOE_IN_DDR_BANK_OFST 4 2533#define MC_CMD_AOE_IN_DDR_BANK_LEN 4 2534/* Enum values, see field(s): */ 2535/* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2536/* Page index of SPD data */ 2537#define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 2538#define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4 2539 2540/* MC_CMD_AOE_IN_FC msgrequest */ 2541#define MC_CMD_AOE_IN_FC_LEN 4 2542/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2543/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2544 2545/* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 2546#define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 2547/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2548/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2549#define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 2550#define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4 2551/* Enum values, see field(s): */ 2552/* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2553 2554/* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 2555#define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 2556/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2557/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2558/* Basic commands for MC SPI Master emulation. */ 2559#define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 2560#define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4 2561/* enum: MC SPI read */ 2562#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 2563/* enum: MC SPI write */ 2564#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 2565 2566/* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 2567#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 2568/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2569/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2570#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 2571#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4 2572#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 2573#define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4 2574 2575/* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 2576#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 2577/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2578/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2579#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 2580#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4 2581#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 2582#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4 2583#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 2584#define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4 2585 2586/* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 2587#define MC_CMD_AOE_IN_FC_BOOT_LEN 8 2588/* MC_CMD_AOE_IN_CMD_OFST 0 */ 2589/* MC_CMD_AOE_IN_CMD_LEN 4 */ 2590/* FC boot control flags */ 2591#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 2592#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4 2593#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 2594#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 2595 2596/* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */ 2597#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144 2598/* Assertion status flag. */ 2599#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0 2600#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4 2601#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8 2602#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8 2603/* enum: No crash data available */ 2604/* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */ 2605/* enum: New crash data available */ 2606/* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */ 2607/* enum: Crash data has been sent */ 2608/* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */ 2609#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0 2610#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8 2611/* enum: No crash has been recorded. */ 2612/* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */ 2613/* enum: Crash due to exception. */ 2614/* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */ 2615/* enum: Crash due to assertion. */ 2616/* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */ 2617/* Failing PC value */ 2618#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4 2619#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4 2620/* Saved GP regs */ 2621#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8 2622#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4 2623#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31 2624/* Exception Type */ 2625#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132 2626#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4 2627/* Instruction at which exception occurred */ 2628#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136 2629#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4 2630/* BAD Address that triggered address-based exception */ 2631#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2632#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4 2633 2634/* MC_CMD_AOE_OUT_INFO msgresponse */ 2635#define MC_CMD_AOE_OUT_INFO_LEN 44 2636/* JTAG IDCODE of CPLD */ 2637#define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 2638#define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4 2639/* Version of CPLD */ 2640#define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 2641#define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4 2642/* JTAG IDCODE of FPGA */ 2643#define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 2644#define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4 2645/* JTAG USERCODE of FPGA */ 2646#define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 2647#define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4 2648/* FPGA type - read from CPLD straps */ 2649#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 2650#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4 2651#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 2652#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 2653/* FPGA state (debug) */ 2654#define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 2655#define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4 2656/* FPGA image - partition from which loaded */ 2657#define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 2658#define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4 2659/* FC state */ 2660#define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 2661#define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4 2662/* enum: Set if watchdog working */ 2663#define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 2664/* enum: Set if MC-FC communications working */ 2665#define MC_CMD_AOE_OUT_INFO_COMMS 0x2 2666/* Random pieces of information */ 2667#define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 2668#define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4 2669/* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 2670#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 2671/* enum: CPLD apparently good */ 2672#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 2673/* enum: FPGA working normally */ 2674#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 2675/* enum: FPGA is powered */ 2676#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 2677/* enum: Board has incompatible SODIMMs fitted */ 2678#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 2679/* enum: Board has ByteBlaster connected */ 2680#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 2681/* enum: FPGA Boot flash has an invalid header. */ 2682#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 2683/* enum: FPGA Application flash is accessible. */ 2684#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 2685/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 2686#define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 2687#define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4 2688#define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 2689#define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 2690#define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 2691#define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 2692#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 2693/* Result of FC booting - not valid while a ByteBlaster is connected. */ 2694#define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 2695#define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4 2696/* enum: No error */ 2697#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 2698/* enum: Bad address set in CPLD */ 2699#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 2700/* enum: Bad header */ 2701#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 2702/* enum: Bad text section details */ 2703#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 2704/* enum: Bad checksum */ 2705#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 2706/* enum: Bad BSP */ 2707#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 2708/* enum: Flash mode is invalid */ 2709#define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 2710/* enum: FC application loaded and execution attempted */ 2711#define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 2712/* enum: FC application Started */ 2713#define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 2714/* enum: No bootrom in FPGA */ 2715#define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 2716 2717/* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 2718#define MC_CMD_AOE_OUT_CURRENTS_LEN 68 2719/* Set of currents and voltages (mA or mV as appropriate) */ 2720#define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 2721#define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 2722#define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 2723#define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 2724#define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 2725#define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 2726#define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 2727#define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 2728#define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 2729#define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 2730#define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 2731#define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 2732#define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 2733#define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 2734#define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 2735#define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 2736#define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 2737#define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 2738#define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 2739#define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 2740 2741/* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 2742#define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 2743/* Set of temperatures */ 2744#define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 2745#define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 2746#define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 2747/* enum: The first set of enum values are for Modena code. */ 2748#define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 2749#define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 2750#define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 2751#define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 2752#define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 2753#define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 2754#define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 2755#define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 2756#define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 2757#define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 2758/* enum: The second set of enum values are for Sorrento code. */ 2759#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 2760#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 2761#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 2762#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 2763#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 2764#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 2765#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 2766#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 2767#define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 2768 2769/* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 2770#define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 2771/* The value read from the CPLD */ 2772#define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 2773#define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4 2774 2775/* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 2776#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 2777#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 2778#define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 2779/* Failure counts for each fan */ 2780#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 2781#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 2782#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 2783#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 2784 2785/* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 2786#define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 2787/* Results of status command (only) */ 2788#define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 2789#define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4 2790 2791/* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 2792#define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 2793 2794/* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 2795#define MC_CMD_AOE_OUT_POWER_ON_LEN 0 2796 2797/* MC_CMD_AOE_OUT_LOAD msgresponse */ 2798#define MC_CMD_AOE_OUT_LOAD_LEN 0 2799 2800/* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 2801#define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 2802 2803/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 2804 * for details 2805 */ 2806#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 2807#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 2808#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 2809#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 2810#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 2811#define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 2812 2813/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 2814#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 2815#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 2816#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 2817/* in bytes */ 2818#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 2819#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4 2820#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 2821#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 2822#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 2823#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 2824 2825/* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 2826#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 2827#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 2828#define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 2829/* Used to align the in and out data blocks so the MC can re-use the cmd */ 2830#define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 2831#define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4 2832/* out bytes */ 2833#define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 2834#define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4 2835#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 2836#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 2837#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 2838#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 2839 2840/* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 2841#define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 2842 2843/* MC_CMD_AOE_OUT_DDR msgresponse */ 2844#define MC_CMD_AOE_OUT_DDR_LENMIN 17 2845#define MC_CMD_AOE_OUT_DDR_LENMAX 252 2846#define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 2847/* Information on the module. */ 2848#define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 2849#define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4 2850#define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 2851#define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 2852#define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 2853#define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 2854#define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 2855#define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 2856#define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 2857#define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 2858/* Memory size, in MB. */ 2859#define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 2860#define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4 2861/* The memory type, as reported from SPD information */ 2862#define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 2863#define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4 2864/* Nominal voltage of the module (as applied) */ 2865#define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 2866#define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4 2867/* SPD data read from the module */ 2868#define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 2869#define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 2870#define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 2871#define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 2872 2873/* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 2874#define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 2875 2876/* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 2877#define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 2878 2879/* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 2880#define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 2881 2882/* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 2883#define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 2884 2885/* MC_CMD_AOE_OUT_FC msgresponse */ 2886#define MC_CMD_AOE_OUT_FC_LEN 0 2887 2888/* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */ 2889#define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4 2890/* get the number of internal ports */ 2891#define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0 2892#define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4 2893 2894/* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 2895#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 2896/* Flags describing status info on the module. */ 2897#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 2898#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4 2899#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 2900#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 2901/* DDR ECC status on the module. */ 2902#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 2903#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4 2904#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 2905#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 2906#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 2907#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 2908#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 2909#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 2910#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 2911#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 2912#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 2913#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 2914#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 2915#define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 2916 2917/* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 2918#define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 2919#define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 2920#define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4 2921 2922/* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 2923#define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 2924 2925/* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 2926#define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 2927 2928/* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 2929#define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 2930 2931#endif /* _SYS_EFX_REGS_MCDI_AOE_H */ 2932