1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _SIENA_MC_DRIVER_PCOL_H 31#define _SIENA_MC_DRIVER_PCOL_H 32 33/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 34/* Power-on reset state */ 35#define MC_FW_STATE_POR (1) 36/* If this is set in MC_RESET_STATE_REG then it should be 37 * possible to jump into IMEM without loading code from flash. */ 38#define MC_FW_WARM_BOOT_OK (2) 39/* The MC main image has started to boot. */ 40#define MC_FW_STATE_BOOTING (4) 41/* The Scheduler has started. */ 42#define MC_FW_STATE_SCHED (8) 43/* If this is set in MC_RESET_STATE_REG then it should be 44 * possible to jump into IMEM without loading code from flash. 45 * Unlike a warm boot, assume DMEM has been reloaded, so that 46 * the MC persistent data must be reinitialised. */ 47#define MC_FW_TEPID_BOOT_OK (16) 48/* We have entered the main firmware via recovery mode. This 49 * means that MC persistent data must be reinitialised, but that 50 * we shouldn't touch PCIe config. */ 51#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 52/* BIST state has been initialized */ 53#define MC_FW_BIST_INIT_OK (128) 54 55/* Siena MC shared memmory offsets */ 56/* The 'doorbell' addresses are hard-wired to alert the MC when written */ 57#define MC_SMEM_P0_DOORBELL_OFST 0x000 58#define MC_SMEM_P1_DOORBELL_OFST 0x004 59/* The rest of these are firmware-defined */ 60#define MC_SMEM_P0_PDU_OFST 0x008 61#define MC_SMEM_P1_PDU_OFST 0x108 62#define MC_SMEM_PDU_LEN 0x100 63#define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 64#define MC_SMEM_P0_STATUS_OFST 0x7f8 65#define MC_SMEM_P1_STATUS_OFST 0x7fc 66 67/* Values to be written to the per-port status dword in shared 68 * memory on reboot and assert */ 69#define MC_STATUS_DWORD_REBOOT (0xb007b007) 70#define MC_STATUS_DWORD_ASSERT (0xdeaddead) 71 72/* Check whether an mcfw version (in host order) belongs to a bootloader */ 73#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 74 75/* The current version of the MCDI protocol. 76 * 77 * Note that the ROM burnt into the card only talks V0, so at the very 78 * least every driver must support version 0 and MCDI_PCOL_VERSION 79 */ 80#ifdef WITH_MCDI_V2 81#define MCDI_PCOL_VERSION 2 82#else 83#define MCDI_PCOL_VERSION 1 84#endif 85 86/* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 87 88/* MCDI version 1 89 * 90 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 91 * structure, filled in by the client. 92 * 93 * 0 7 8 16 20 22 23 24 31 94 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 95 * | | | 96 * | | \--- Response 97 * | \------- Error 98 * \------------------------------ Resync (always set) 99 * 100 * The client writes it's request into MC shared memory, and rings the 101 * doorbell. Each request is completed by either by the MC writting 102 * back into shared memory, or by writting out an event. 103 * 104 * All MCDI commands support completion by shared memory response. Each 105 * request may also contain additional data (accounted for by HEADER.LEN), 106 * and some response's may also contain additional data (again, accounted 107 * for by HEADER.LEN). 108 * 109 * Some MCDI commands support completion by event, in which any associated 110 * response data is included in the event. 111 * 112 * The protocol requires one response to be delivered for every request, a 113 * request should not be sent unless the response for the previous request 114 * has been received (either by polling shared memory, or by receiving 115 * an event). 116 */ 117 118/** Request/Response structure */ 119#define MCDI_HEADER_OFST 0 120#define MCDI_HEADER_CODE_LBN 0 121#define MCDI_HEADER_CODE_WIDTH 7 122#define MCDI_HEADER_RESYNC_LBN 7 123#define MCDI_HEADER_RESYNC_WIDTH 1 124#define MCDI_HEADER_DATALEN_LBN 8 125#define MCDI_HEADER_DATALEN_WIDTH 8 126#define MCDI_HEADER_SEQ_LBN 16 127#define MCDI_HEADER_SEQ_WIDTH 4 128#define MCDI_HEADER_RSVD_LBN 20 129#define MCDI_HEADER_RSVD_WIDTH 1 130#define MCDI_HEADER_NOT_EPOCH_LBN 21 131#define MCDI_HEADER_NOT_EPOCH_WIDTH 1 132#define MCDI_HEADER_ERROR_LBN 22 133#define MCDI_HEADER_ERROR_WIDTH 1 134#define MCDI_HEADER_RESPONSE_LBN 23 135#define MCDI_HEADER_RESPONSE_WIDTH 1 136#define MCDI_HEADER_XFLAGS_LBN 24 137#define MCDI_HEADER_XFLAGS_WIDTH 8 138/* Request response using event */ 139#define MCDI_HEADER_XFLAGS_EVREQ 0x01 140/* Request (and signal) early doorbell return */ 141#define MCDI_HEADER_XFLAGS_DBRET 0x02 142 143/* Maximum number of payload bytes */ 144#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 145#define MCDI_CTL_SDU_LEN_MAX_V2 0x400 146 147#ifdef WITH_MCDI_V2 148#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 149#else 150#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 151#endif 152 153/* The MC can generate events for two reasons: 154 * - To advance a shared memory request if XFLAGS_EVREQ was set 155 * - As a notification (link state, i2c event), controlled 156 * via MC_CMD_LOG_CTRL 157 * 158 * Both events share a common structure: 159 * 160 * 0 32 33 36 44 52 60 161 * | Data | Cont | Level | Src | Code | Rsvd | 162 * | 163 * \ There is another event pending in this notification 164 * 165 * If Code==CMDDONE, then the fields are further interpreted as: 166 * 167 * - LEVEL==INFO Command succeeded 168 * - LEVEL==ERR Command failed 169 * 170 * 0 8 16 24 32 171 * | Seq | Datalen | Errno | Rsvd | 172 * 173 * These fields are taken directly out of the standard MCDI header, i.e., 174 * LEVEL==ERR, Datalen == 0 => Reboot 175 * 176 * Events can be squirted out of the UART (using LOG_CTRL) without a 177 * MCDI header. An event can be distinguished from a MCDI response by 178 * examining the first byte which is 0xc0. This corresponds to the 179 * non-existent MCDI command MC_CMD_DEBUG_LOG. 180 * 181 * 0 7 8 182 * | command | Resync | = 0xc0 183 * 184 * Since the event is written in big-endian byte order, this works 185 * providing bits 56-63 of the event are 0xc0. 186 * 187 * 56 60 63 188 * | Rsvd | Code | = 0xc0 189 * 190 * Which means for convenience the event code is 0xc for all MC 191 * generated events. 192 */ 193#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 194 195/* Operation not permitted. */ 196#define MC_CMD_ERR_EPERM 1 197/* Non-existent command target */ 198#define MC_CMD_ERR_ENOENT 2 199/* assert() has killed the MC */ 200#define MC_CMD_ERR_EINTR 4 201/* I/O failure */ 202#define MC_CMD_ERR_EIO 5 203/* Already exists */ 204#define MC_CMD_ERR_EEXIST 6 205/* Try again */ 206#define MC_CMD_ERR_EAGAIN 11 207/* Out of memory */ 208#define MC_CMD_ERR_ENOMEM 12 209/* Caller does not hold required locks */ 210#define MC_CMD_ERR_EACCES 13 211/* Resource is currently unavailable (e.g. lock contention) */ 212#define MC_CMD_ERR_EBUSY 16 213/* No such device */ 214#define MC_CMD_ERR_ENODEV 19 215/* Invalid argument to target */ 216#define MC_CMD_ERR_EINVAL 22 217/* Broken pipe */ 218#define MC_CMD_ERR_EPIPE 32 219/* Read-only */ 220#define MC_CMD_ERR_EROFS 30 221/* Out of range */ 222#define MC_CMD_ERR_ERANGE 34 223/* Non-recursive resource is already acquired */ 224#define MC_CMD_ERR_EDEADLK 35 225/* Operation not implemented */ 226#define MC_CMD_ERR_ENOSYS 38 227/* Operation timed out */ 228#define MC_CMD_ERR_ETIME 62 229/* Link has been severed */ 230#define MC_CMD_ERR_ENOLINK 67 231/* Protocol error */ 232#define MC_CMD_ERR_EPROTO 71 233/* Operation not supported */ 234#define MC_CMD_ERR_ENOTSUP 95 235/* Address not available */ 236#define MC_CMD_ERR_EADDRNOTAVAIL 99 237/* Not connected */ 238#define MC_CMD_ERR_ENOTCONN 107 239/* Operation already in progress */ 240#define MC_CMD_ERR_EALREADY 114 241 242/* Resource allocation failed. */ 243#define MC_CMD_ERR_ALLOC_FAIL 0x1000 244/* V-adaptor not found. */ 245#define MC_CMD_ERR_NO_VADAPTOR 0x1001 246/* EVB port not found. */ 247#define MC_CMD_ERR_NO_EVB_PORT 0x1002 248/* V-switch not found. */ 249#define MC_CMD_ERR_NO_VSWITCH 0x1003 250/* Too many VLAN tags. */ 251#define MC_CMD_ERR_VLAN_LIMIT 0x1004 252/* Bad PCI function number. */ 253#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 254/* Invalid VLAN mode. */ 255#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 256/* Invalid v-switch type. */ 257#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 258/* Invalid v-port type. */ 259#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 260/* MAC address exists. */ 261#define MC_CMD_ERR_MAC_EXIST 0x1009 262/* Slave core not present */ 263#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 264/* The datapath is disabled. */ 265#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 266/* The requesting client is not a function */ 267#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 268/* The requested operation might require the 269 command to be passed between MCs, and the 270 transport doesn't support that. Should 271 only ever been seen over the UART. */ 272#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 273/* VLAN tag(s) exists */ 274#define MC_CMD_ERR_VLAN_EXIST 0x100e 275/* No MAC address assigned to an EVB port */ 276#define MC_CMD_ERR_NO_MAC_ADDR 0x100f 277/* Notifies the driver that the request has been relayed 278 * to an admin function for authorization. The driver should 279 * wait for a PROXY_RESPONSE event and then resend its request. 280 * This error code is followed by a 32-bit handle that 281 * helps matching it with the respective PROXY_RESPONSE event. */ 282#define MC_CMD_ERR_PROXY_PENDING 0x1010 283#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 284/* The request cannot be passed for authorization because 285 * another request from the same function is currently being 286 * authorized. The drvier should try again later. */ 287#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 288/* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 289 * that has enabled proxying or BLOCK_INDEX points to a function that 290 * doesn't await an authorization. */ 291#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 292/* This code is currently only used internally in FW. Its meaning is that 293 * an operation failed due to lack of SR-IOV privilege. 294 * Normally it is translated to EPERM by send_cmd_err(), 295 * but it may also be used to trigger some special mechanism 296 * for handling such case, e.g. to relay the failed request 297 * to a designated admin function for authorization. */ 298#define MC_CMD_ERR_NO_PRIVILEGE 0x1013 299/* Workaround 26807 could not be turned on/off because some functions 300 * have already installed filters. See the comment at 301 * MC_CMD_WORKAROUND_BUG26807. 302 * May also returned for other operations such as sub-variant switching. */ 303#define MC_CMD_ERR_FILTERS_PRESENT 0x1014 304/* The clock whose frequency you've attempted to set set 305 * doesn't exist on this NIC */ 306#define MC_CMD_ERR_NO_CLOCK 0x1015 307/* Returned by MC_CMD_TESTASSERT if the action that should 308 * have caused an assertion failed to do so. */ 309#define MC_CMD_ERR_UNREACHABLE 0x1016 310/* This command needs to be processed in the background but there were no 311 * resources to do so. Send it again after a command has completed. */ 312#define MC_CMD_ERR_QUEUE_FULL 0x1017 313/* The operation could not be completed because the PCIe link has gone 314 * away. This error code is never expected to be returned over the TLP 315 * transport. */ 316#define MC_CMD_ERR_NO_PCIE 0x1018 317/* The operation could not be completed because the datapath has gone 318 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the 319 * datapath absence may be temporary*/ 320#define MC_CMD_ERR_NO_DATAPATH 0x1019 321/* The operation could not complete because some VIs are allocated */ 322#define MC_CMD_ERR_VIS_PRESENT 0x101a 323/* The operation could not complete because some PIO buffers are allocated */ 324#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b 325 326#define MC_CMD_ERR_CODE_OFST 0 327 328/* We define 8 "escape" commands to allow 329 for command number space extension */ 330 331#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 332#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 333#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 334#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 335#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 336#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 337#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 338#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 339 340/* Vectors in the boot ROM */ 341/* Point to the copycode entry point. */ 342#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 343#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 344#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 345/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */ 346#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 347#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 348#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 349/* Points to the recovery mode entry point. Same as above, but the right name. */ 350#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4) 351#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4) 352#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4) 353 354/* Points to noflash mode entry point. */ 355#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4) 356 357/* The command set exported by the boot ROM (MCDI v0) */ 358#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 359 (1 << MC_CMD_READ32) | \ 360 (1 << MC_CMD_WRITE32) | \ 361 (1 << MC_CMD_COPYCODE) | \ 362 (1 << MC_CMD_GET_VERSION), \ 363 0, 0, 0 } 364 365#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 366 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 367 368#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 369 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 370 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 371 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 372 373#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 374 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 375 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 376 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 377 378#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 379 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 380 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 381 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 382 383/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 384 * stack ID (which must be in the range 1-255) along with an EVB port ID. 385 */ 386#define EVB_STACK_ID(n) (((n) & 0xff) << 16) 387 388#ifdef WITH_MCDI_V2 389 390/* Version 2 adds an optional argument to error returns: the errno value 391 * may be followed by the (0-based) number of the first argument that 392 * could not be processed. 393 */ 394#define MC_CMD_ERR_ARG_OFST 4 395 396/* No space */ 397#define MC_CMD_ERR_ENOSPC 28 398 399#endif 400 401/* MCDI_EVENT structuredef */ 402#define MCDI_EVENT_LEN 8 403#define MCDI_EVENT_CONT_LBN 32 404#define MCDI_EVENT_CONT_WIDTH 1 405#define MCDI_EVENT_LEVEL_LBN 33 406#define MCDI_EVENT_LEVEL_WIDTH 3 407/* enum: Info. */ 408#define MCDI_EVENT_LEVEL_INFO 0x0 409/* enum: Warning. */ 410#define MCDI_EVENT_LEVEL_WARN 0x1 411/* enum: Error. */ 412#define MCDI_EVENT_LEVEL_ERR 0x2 413/* enum: Fatal. */ 414#define MCDI_EVENT_LEVEL_FATAL 0x3 415#define MCDI_EVENT_DATA_OFST 0 416#define MCDI_EVENT_DATA_LEN 4 417#define MCDI_EVENT_CMDDONE_SEQ_LBN 0 418#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 419#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 420#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 421#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 422#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 423#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 424#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 425#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 426#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 427/* enum: Link is down or link speed could not be determined */ 428#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0 429/* enum: 100Mbs */ 430#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 431/* enum: 1Gbs */ 432#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 433/* enum: 10Gbs */ 434#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 435/* enum: 40Gbs */ 436#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 437/* enum: 25Gbs */ 438#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5 439/* enum: 50Gbs */ 440#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6 441/* enum: 100Gbs */ 442#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7 443#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 444#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 445#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 446#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 447#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 448#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 449#define MCDI_EVENT_SENSOREVT_STATE_LBN 8 450#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 451#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 452#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 453#define MCDI_EVENT_FWALERT_DATA_LBN 8 454#define MCDI_EVENT_FWALERT_DATA_WIDTH 24 455#define MCDI_EVENT_FWALERT_REASON_LBN 0 456#define MCDI_EVENT_FWALERT_REASON_WIDTH 8 457/* enum: SRAM Access. */ 458#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 459#define MCDI_EVENT_FLR_VF_LBN 0 460#define MCDI_EVENT_FLR_VF_WIDTH 8 461#define MCDI_EVENT_TX_ERR_TXQ_LBN 0 462#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 463#define MCDI_EVENT_TX_ERR_TYPE_LBN 12 464#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 465/* enum: Descriptor loader reported failure */ 466#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 467/* enum: Descriptor ring empty and no EOP seen for packet */ 468#define MCDI_EVENT_TX_ERR_NO_EOP 0x2 469/* enum: Overlength packet */ 470#define MCDI_EVENT_TX_ERR_2BIG 0x3 471/* enum: Malformed option descriptor */ 472#define MCDI_EVENT_TX_BAD_OPTDESC 0x5 473/* enum: Option descriptor part way through a packet */ 474#define MCDI_EVENT_TX_OPT_IN_PKT 0x8 475/* enum: DMA or PIO data access error */ 476#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 477#define MCDI_EVENT_TX_ERR_INFO_LBN 16 478#define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 479#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 480#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 481#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 482#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 483#define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 484#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 485/* enum: PLL lost lock */ 486#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 487/* enum: Filter overflow (PDMA) */ 488#define MCDI_EVENT_PTP_ERR_FILTER 0x2 489/* enum: FIFO overflow (FPGA) */ 490#define MCDI_EVENT_PTP_ERR_FIFO 0x3 491/* enum: Merge queue overflow */ 492#define MCDI_EVENT_PTP_ERR_QUEUE 0x4 493#define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 494#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 495/* enum: AOE failed to load - no valid image? */ 496#define MCDI_EVENT_AOE_NO_LOAD 0x1 497/* enum: AOE FC reported an exception */ 498#define MCDI_EVENT_AOE_FC_ASSERT 0x2 499/* enum: AOE FC watchdogged */ 500#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 501/* enum: AOE FC failed to start */ 502#define MCDI_EVENT_AOE_FC_NO_START 0x4 503/* enum: Generic AOE fault - likely to have been reported via other means too 504 * but intended for use by aoex driver. 505 */ 506#define MCDI_EVENT_AOE_FAULT 0x5 507/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 508#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 509/* enum: AOE loaded successfully */ 510#define MCDI_EVENT_AOE_LOAD 0x7 511/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 512#define MCDI_EVENT_AOE_DMA 0x8 513/* enum: AOE byteblaster connected/disconnected (Connection status in 514 * AOE_ERR_DATA) 515 */ 516#define MCDI_EVENT_AOE_BYTEBLASTER 0x9 517/* enum: DDR ECC status update */ 518#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 519/* enum: PTP status update */ 520#define MCDI_EVENT_AOE_PTP_STATUS 0xb 521/* enum: FPGA header incorrect */ 522#define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc 523/* enum: FPGA Powered Off due to error in powering up FPGA */ 524#define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd 525/* enum: AOE FPGA load failed due to MC to MUM communication failure */ 526#define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 527/* enum: Notify that invalid flash type detected */ 528#define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 529/* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 530#define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 531/* enum: Failure to probe one or more FPGA boot flash chips */ 532#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11 533/* enum: FPGA boot-flash contains an invalid image header */ 534#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12 535/* enum: Failed to program clocks required by the FPGA */ 536#define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13 537/* enum: Notify that FPGA Controller is alive to serve MCDI requests */ 538#define MCDI_EVENT_AOE_FC_RUNNING 0x14 539#define MCDI_EVENT_AOE_ERR_DATA_LBN 8 540#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 541#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8 542#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8 543/* enum: FC Assert happened, but the register information is not available */ 544#define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0 545/* enum: The register information for FC Assert is ready for readinng by driver 546 */ 547#define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 548#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 549#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 550/* enum: Reading from NV failed */ 551#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 552/* enum: Invalid Magic Number if FPGA header */ 553#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 554/* enum: Invalid Silicon type detected in header */ 555#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 556/* enum: Unsupported VRatio */ 557#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 558/* enum: Unsupported DDR Type */ 559#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 560/* enum: DDR Voltage out of supported range */ 561#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 562/* enum: Unsupported DDR speed */ 563#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 564/* enum: Unsupported DDR size */ 565#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 566/* enum: Unsupported DDR rank */ 567#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 568#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 569#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 570/* enum: Primary boot flash */ 571#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 572/* enum: Secondary boot flash */ 573#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 574#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 575#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 576#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 577#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 578#define MCDI_EVENT_RX_ERR_RXQ_LBN 0 579#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 580#define MCDI_EVENT_RX_ERR_TYPE_LBN 12 581#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 582#define MCDI_EVENT_RX_ERR_INFO_LBN 16 583#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 584#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 585#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 586#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 587#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 588#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 589#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 590#define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 591#define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 592/* enum: MUM failed to load - no valid image? */ 593#define MCDI_EVENT_MUM_NO_LOAD 0x1 594/* enum: MUM f/w reported an exception */ 595#define MCDI_EVENT_MUM_ASSERT 0x2 596/* enum: MUM not kicking watchdog */ 597#define MCDI_EVENT_MUM_WATCHDOG 0x3 598#define MCDI_EVENT_MUM_ERR_DATA_LBN 8 599#define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 600#define MCDI_EVENT_DBRET_SEQ_LBN 0 601#define MCDI_EVENT_DBRET_SEQ_WIDTH 8 602#define MCDI_EVENT_SUC_ERR_TYPE_LBN 0 603#define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8 604/* enum: Corrupted or bad SUC application. */ 605#define MCDI_EVENT_SUC_BAD_APP 0x1 606/* enum: SUC application reported an assert. */ 607#define MCDI_EVENT_SUC_ASSERT 0x2 608/* enum: SUC application reported an exception. */ 609#define MCDI_EVENT_SUC_EXCEPTION 0x3 610/* enum: SUC watchdog timer expired. */ 611#define MCDI_EVENT_SUC_WATCHDOG 0x4 612#define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8 613#define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24 614#define MCDI_EVENT_SUC_ERR_DATA_LBN 8 615#define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24 616#define MCDI_EVENT_DATA_LBN 0 617#define MCDI_EVENT_DATA_WIDTH 32 618#define MCDI_EVENT_SRC_LBN 36 619#define MCDI_EVENT_SRC_WIDTH 8 620#define MCDI_EVENT_EV_CODE_LBN 60 621#define MCDI_EVENT_EV_CODE_WIDTH 4 622#define MCDI_EVENT_CODE_LBN 44 623#define MCDI_EVENT_CODE_WIDTH 8 624/* enum: Event generated by host software */ 625#define MCDI_EVENT_SW_EVENT 0x0 626/* enum: Bad assert. */ 627#define MCDI_EVENT_CODE_BADSSERT 0x1 628/* enum: PM Notice. */ 629#define MCDI_EVENT_CODE_PMNOTICE 0x2 630/* enum: Command done. */ 631#define MCDI_EVENT_CODE_CMDDONE 0x3 632/* enum: Link change. */ 633#define MCDI_EVENT_CODE_LINKCHANGE 0x4 634/* enum: Sensor Event. */ 635#define MCDI_EVENT_CODE_SENSOREVT 0x5 636/* enum: Schedule error. */ 637#define MCDI_EVENT_CODE_SCHEDERR 0x6 638/* enum: Reboot. */ 639#define MCDI_EVENT_CODE_REBOOT 0x7 640/* enum: Mac stats DMA. */ 641#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 642/* enum: Firmware alert. */ 643#define MCDI_EVENT_CODE_FWALERT 0x9 644/* enum: Function level reset. */ 645#define MCDI_EVENT_CODE_FLR 0xa 646/* enum: Transmit error */ 647#define MCDI_EVENT_CODE_TX_ERR 0xb 648/* enum: Tx flush has completed */ 649#define MCDI_EVENT_CODE_TX_FLUSH 0xc 650/* enum: PTP packet received timestamp */ 651#define MCDI_EVENT_CODE_PTP_RX 0xd 652/* enum: PTP NIC failure */ 653#define MCDI_EVENT_CODE_PTP_FAULT 0xe 654/* enum: PTP PPS event */ 655#define MCDI_EVENT_CODE_PTP_PPS 0xf 656/* enum: Rx flush has completed */ 657#define MCDI_EVENT_CODE_RX_FLUSH 0x10 658/* enum: Receive error */ 659#define MCDI_EVENT_CODE_RX_ERR 0x11 660/* enum: AOE fault */ 661#define MCDI_EVENT_CODE_AOE 0x12 662/* enum: Network port calibration failed (VCAL). */ 663#define MCDI_EVENT_CODE_VCAL_FAIL 0x13 664/* enum: HW PPS event */ 665#define MCDI_EVENT_CODE_HW_PPS 0x14 666/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 667 * a different format) 668 */ 669#define MCDI_EVENT_CODE_MC_REBOOT 0x15 670/* enum: the MC has detected a parity error */ 671#define MCDI_EVENT_CODE_PAR_ERR 0x16 672/* enum: the MC has detected a correctable error */ 673#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 674/* enum: the MC has detected an uncorrectable error */ 675#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 676/* enum: The MC has entered offline BIST mode */ 677#define MCDI_EVENT_CODE_MC_BIST 0x19 678/* enum: PTP tick event providing current NIC time */ 679#define MCDI_EVENT_CODE_PTP_TIME 0x1a 680/* enum: MUM fault */ 681#define MCDI_EVENT_CODE_MUM 0x1b 682/* enum: notify the designated PF of a new authorization request */ 683#define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 684/* enum: notify a function that awaits an authorization that its request has 685 * been processed and it may now resend the command 686 */ 687#define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 688/* enum: MCDI command accepted. New commands can be issued but this command is 689 * not done yet. 690 */ 691#define MCDI_EVENT_CODE_DBRET 0x1e 692/* enum: The MC has detected a fault on the SUC */ 693#define MCDI_EVENT_CODE_SUC 0x1f 694/* enum: Artificial event generated by host and posted via MC for test 695 * purposes. 696 */ 697#define MCDI_EVENT_CODE_TESTGEN 0xfa 698#define MCDI_EVENT_CMDDONE_DATA_OFST 0 699#define MCDI_EVENT_CMDDONE_DATA_LEN 4 700#define MCDI_EVENT_CMDDONE_DATA_LBN 0 701#define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 702#define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 703#define MCDI_EVENT_LINKCHANGE_DATA_LEN 4 704#define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 705#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 706#define MCDI_EVENT_SENSOREVT_DATA_OFST 0 707#define MCDI_EVENT_SENSOREVT_DATA_LEN 4 708#define MCDI_EVENT_SENSOREVT_DATA_LBN 0 709#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 710#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 711#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4 712#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 713#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 714#define MCDI_EVENT_TX_ERR_DATA_OFST 0 715#define MCDI_EVENT_TX_ERR_DATA_LEN 4 716#define MCDI_EVENT_TX_ERR_DATA_LBN 0 717#define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 718/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 719 * timestamp 720 */ 721#define MCDI_EVENT_PTP_SECONDS_OFST 0 722#define MCDI_EVENT_PTP_SECONDS_LEN 4 723#define MCDI_EVENT_PTP_SECONDS_LBN 0 724#define MCDI_EVENT_PTP_SECONDS_WIDTH 32 725/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 726 * timestamp 727 */ 728#define MCDI_EVENT_PTP_MAJOR_OFST 0 729#define MCDI_EVENT_PTP_MAJOR_LEN 4 730#define MCDI_EVENT_PTP_MAJOR_LBN 0 731#define MCDI_EVENT_PTP_MAJOR_WIDTH 32 732/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 733 * of timestamp 734 */ 735#define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 736#define MCDI_EVENT_PTP_NANOSECONDS_LEN 4 737#define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 738#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 739/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 740 * timestamp 741 */ 742#define MCDI_EVENT_PTP_MINOR_OFST 0 743#define MCDI_EVENT_PTP_MINOR_LEN 4 744#define MCDI_EVENT_PTP_MINOR_LBN 0 745#define MCDI_EVENT_PTP_MINOR_WIDTH 32 746/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 747 */ 748#define MCDI_EVENT_PTP_UUID_OFST 0 749#define MCDI_EVENT_PTP_UUID_LEN 4 750#define MCDI_EVENT_PTP_UUID_LBN 0 751#define MCDI_EVENT_PTP_UUID_WIDTH 32 752#define MCDI_EVENT_RX_ERR_DATA_OFST 0 753#define MCDI_EVENT_RX_ERR_DATA_LEN 4 754#define MCDI_EVENT_RX_ERR_DATA_LBN 0 755#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 756#define MCDI_EVENT_PAR_ERR_DATA_OFST 0 757#define MCDI_EVENT_PAR_ERR_DATA_LEN 4 758#define MCDI_EVENT_PAR_ERR_DATA_LBN 0 759#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 760#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 761#define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4 762#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 763#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 764#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 765#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4 766#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 767#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 768/* For CODE_PTP_TIME events, the major value of the PTP clock */ 769#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 770#define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4 771#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 772#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 773/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 774#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 775#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 776/* For CODE_PTP_TIME events, most significant bits of the minor value of the 777 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19. 778 */ 779#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36 780#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8 781/* For CODE_PTP_TIME events where report sync status is enabled, indicates 782 * whether the NIC clock has ever been set 783 */ 784#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 785#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 786/* For CODE_PTP_TIME events where report sync status is enabled, indicates 787 * whether the NIC and System clocks are in sync 788 */ 789#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 790#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 791/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 792 * the minor value of the PTP clock 793 */ 794#define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 795#define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 796/* For CODE_PTP_TIME events, most significant bits of the minor value of the 797 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21. 798 */ 799#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38 800#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6 801#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 802#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4 803#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 804#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 805#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 806#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4 807#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 808#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 809/* Zero means that the request has been completed or authorized, and the driver 810 * should resend it. A non-zero value means that the authorization has been 811 * denied, and gives the reason. Typically it will be EPERM. 812 */ 813#define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 814#define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 815#define MCDI_EVENT_DBRET_DATA_OFST 0 816#define MCDI_EVENT_DBRET_DATA_LEN 4 817#define MCDI_EVENT_DBRET_DATA_LBN 0 818#define MCDI_EVENT_DBRET_DATA_WIDTH 32 819 820/* FCDI_EVENT structuredef */ 821#define FCDI_EVENT_LEN 8 822#define FCDI_EVENT_CONT_LBN 32 823#define FCDI_EVENT_CONT_WIDTH 1 824#define FCDI_EVENT_LEVEL_LBN 33 825#define FCDI_EVENT_LEVEL_WIDTH 3 826/* enum: Info. */ 827#define FCDI_EVENT_LEVEL_INFO 0x0 828/* enum: Warning. */ 829#define FCDI_EVENT_LEVEL_WARN 0x1 830/* enum: Error. */ 831#define FCDI_EVENT_LEVEL_ERR 0x2 832/* enum: Fatal. */ 833#define FCDI_EVENT_LEVEL_FATAL 0x3 834#define FCDI_EVENT_DATA_OFST 0 835#define FCDI_EVENT_DATA_LEN 4 836#define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 837#define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 838#define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 839#define FCDI_EVENT_LINK_UP 0x1 /* enum */ 840#define FCDI_EVENT_DATA_LBN 0 841#define FCDI_EVENT_DATA_WIDTH 32 842#define FCDI_EVENT_SRC_LBN 36 843#define FCDI_EVENT_SRC_WIDTH 8 844#define FCDI_EVENT_EV_CODE_LBN 60 845#define FCDI_EVENT_EV_CODE_WIDTH 4 846#define FCDI_EVENT_CODE_LBN 44 847#define FCDI_EVENT_CODE_WIDTH 8 848/* enum: The FC was rebooted. */ 849#define FCDI_EVENT_CODE_REBOOT 0x1 850/* enum: Bad assert. */ 851#define FCDI_EVENT_CODE_ASSERT 0x2 852/* enum: DDR3 test result. */ 853#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 854/* enum: Link status. */ 855#define FCDI_EVENT_CODE_LINK_STATE 0x4 856/* enum: A timed read is ready to be serviced. */ 857#define FCDI_EVENT_CODE_TIMED_READ 0x5 858/* enum: One or more PPS IN events */ 859#define FCDI_EVENT_CODE_PPS_IN 0x6 860/* enum: Tick event from PTP clock */ 861#define FCDI_EVENT_CODE_PTP_TICK 0x7 862/* enum: ECC error counters */ 863#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 864/* enum: Current status of PTP */ 865#define FCDI_EVENT_CODE_PTP_STATUS 0x9 866/* enum: Port id config to map MC-FC port idx */ 867#define FCDI_EVENT_CODE_PORT_CONFIG 0xa 868/* enum: Boot result or error code */ 869#define FCDI_EVENT_CODE_BOOT_RESULT 0xb 870#define FCDI_EVENT_REBOOT_SRC_LBN 36 871#define FCDI_EVENT_REBOOT_SRC_WIDTH 8 872#define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 873#define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 874#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 875#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4 876#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 877#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 878#define FCDI_EVENT_ASSERT_TYPE_LBN 36 879#define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 880#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 881#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 882#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 883#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4 884#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 885#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 886#define FCDI_EVENT_LINK_STATE_DATA_OFST 0 887#define FCDI_EVENT_LINK_STATE_DATA_LEN 4 888#define FCDI_EVENT_LINK_STATE_DATA_LBN 0 889#define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 890#define FCDI_EVENT_PTP_STATE_OFST 0 891#define FCDI_EVENT_PTP_STATE_LEN 4 892#define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 893#define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 894#define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 895#define FCDI_EVENT_PTP_STATE_LBN 0 896#define FCDI_EVENT_PTP_STATE_WIDTH 32 897#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 898#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 899#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 900#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4 901#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 902#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 903/* Index of MC port being referred to */ 904#define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 905#define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 906/* FC Port index that matches the MC port index in SRC */ 907#define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 908#define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4 909#define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 910#define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 911#define FCDI_EVENT_BOOT_RESULT_OFST 0 912#define FCDI_EVENT_BOOT_RESULT_LEN 4 913/* Enum values, see field(s): */ 914/* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 915#define FCDI_EVENT_BOOT_RESULT_LBN 0 916#define FCDI_EVENT_BOOT_RESULT_WIDTH 32 917 918/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 919 * to the MC. Note that this structure | is overlayed over a normal FCDI event 920 * such that bits 32-63 containing | event code, level, source etc remain the 921 * same. In this case the data | field of the header is defined to be the 922 * number of timestamps 923 */ 924#define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 925#define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 926#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 927/* Number of timestamps following */ 928#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 929#define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4 930#define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 931#define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 932/* Seconds field of a timestamp record */ 933#define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 934#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4 935#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 936#define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 937/* Nanoseconds field of a timestamp record */ 938#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 939#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4 940#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 941#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 942/* Timestamp records comprising the event */ 943#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 944#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 945#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 946#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 947#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 948#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 949#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 950#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 951 952/* MUM_EVENT structuredef */ 953#define MUM_EVENT_LEN 8 954#define MUM_EVENT_CONT_LBN 32 955#define MUM_EVENT_CONT_WIDTH 1 956#define MUM_EVENT_LEVEL_LBN 33 957#define MUM_EVENT_LEVEL_WIDTH 3 958/* enum: Info. */ 959#define MUM_EVENT_LEVEL_INFO 0x0 960/* enum: Warning. */ 961#define MUM_EVENT_LEVEL_WARN 0x1 962/* enum: Error. */ 963#define MUM_EVENT_LEVEL_ERR 0x2 964/* enum: Fatal. */ 965#define MUM_EVENT_LEVEL_FATAL 0x3 966#define MUM_EVENT_DATA_OFST 0 967#define MUM_EVENT_DATA_LEN 4 968#define MUM_EVENT_SENSOR_ID_LBN 0 969#define MUM_EVENT_SENSOR_ID_WIDTH 8 970/* Enum values, see field(s): */ 971/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 972#define MUM_EVENT_SENSOR_STATE_LBN 8 973#define MUM_EVENT_SENSOR_STATE_WIDTH 8 974#define MUM_EVENT_PORT_PHY_READY_LBN 0 975#define MUM_EVENT_PORT_PHY_READY_WIDTH 1 976#define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 977#define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 978#define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 979#define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 980#define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 981#define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 982#define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 983#define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 984#define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 985#define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 986#define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 987#define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 988#define MUM_EVENT_DATA_LBN 0 989#define MUM_EVENT_DATA_WIDTH 32 990#define MUM_EVENT_SRC_LBN 36 991#define MUM_EVENT_SRC_WIDTH 8 992#define MUM_EVENT_EV_CODE_LBN 60 993#define MUM_EVENT_EV_CODE_WIDTH 4 994#define MUM_EVENT_CODE_LBN 44 995#define MUM_EVENT_CODE_WIDTH 8 996/* enum: The MUM was rebooted. */ 997#define MUM_EVENT_CODE_REBOOT 0x1 998/* enum: Bad assert. */ 999#define MUM_EVENT_CODE_ASSERT 0x2 1000/* enum: Sensor failure. */ 1001#define MUM_EVENT_CODE_SENSOR 0x3 1002/* enum: Link fault has been asserted, or has cleared. */ 1003#define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 1004#define MUM_EVENT_SENSOR_DATA_OFST 0 1005#define MUM_EVENT_SENSOR_DATA_LEN 4 1006#define MUM_EVENT_SENSOR_DATA_LBN 0 1007#define MUM_EVENT_SENSOR_DATA_WIDTH 32 1008#define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 1009#define MUM_EVENT_PORT_PHY_FLAGS_LEN 4 1010#define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 1011#define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 1012#define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 1013#define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4 1014#define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 1015#define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 1016#define MUM_EVENT_PORT_PHY_CAPS_OFST 0 1017#define MUM_EVENT_PORT_PHY_CAPS_LEN 4 1018#define MUM_EVENT_PORT_PHY_CAPS_LBN 0 1019#define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 1020#define MUM_EVENT_PORT_PHY_TECH_OFST 0 1021#define MUM_EVENT_PORT_PHY_TECH_LEN 4 1022#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 1023#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 1024#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 1025#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 1026#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 1027#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 1028#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 1029#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 1030#define MUM_EVENT_PORT_PHY_TECH_LBN 0 1031#define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 1032#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 1033#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 1034#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 1035#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 1036#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 1037#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 1038#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 1039#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 1040#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 1041 1042/***********************************/ 1043/* MC_CMD_READ32 1044 * Read multiple 32byte words from MC memory. Note - this command really 1045 * belongs to INSECURE category but is required by shmboot. The command handler 1046 * has additional checks to reject insecure calls. 1047 */ 1048#define MC_CMD_READ32 0x1 1049#undef MC_CMD_0x1_PRIVILEGE_CTG 1050 1051#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1052 1053/* MC_CMD_READ32_IN msgrequest */ 1054#define MC_CMD_READ32_IN_LEN 8 1055#define MC_CMD_READ32_IN_ADDR_OFST 0 1056#define MC_CMD_READ32_IN_ADDR_LEN 4 1057#define MC_CMD_READ32_IN_NUMWORDS_OFST 4 1058#define MC_CMD_READ32_IN_NUMWORDS_LEN 4 1059 1060/* MC_CMD_READ32_OUT msgresponse */ 1061#define MC_CMD_READ32_OUT_LENMIN 4 1062#define MC_CMD_READ32_OUT_LENMAX 252 1063#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 1064#define MC_CMD_READ32_OUT_BUFFER_OFST 0 1065#define MC_CMD_READ32_OUT_BUFFER_LEN 4 1066#define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 1067#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 1068 1069/***********************************/ 1070/* MC_CMD_WRITE32 1071 * Write multiple 32byte words to MC memory. 1072 */ 1073#define MC_CMD_WRITE32 0x2 1074#undef MC_CMD_0x2_PRIVILEGE_CTG 1075 1076#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1077 1078/* MC_CMD_WRITE32_IN msgrequest */ 1079#define MC_CMD_WRITE32_IN_LENMIN 8 1080#define MC_CMD_WRITE32_IN_LENMAX 252 1081#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 1082#define MC_CMD_WRITE32_IN_ADDR_OFST 0 1083#define MC_CMD_WRITE32_IN_ADDR_LEN 4 1084#define MC_CMD_WRITE32_IN_BUFFER_OFST 4 1085#define MC_CMD_WRITE32_IN_BUFFER_LEN 4 1086#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 1087#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 1088 1089/* MC_CMD_WRITE32_OUT msgresponse */ 1090#define MC_CMD_WRITE32_OUT_LEN 0 1091 1092/***********************************/ 1093/* MC_CMD_COPYCODE 1094 * Copy MC code between two locations and jump. Note - this command really 1095 * belongs to INSECURE category but is required by shmboot. The command handler 1096 * has additional checks to reject insecure calls. 1097 */ 1098#define MC_CMD_COPYCODE 0x3 1099#undef MC_CMD_0x3_PRIVILEGE_CTG 1100 1101#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 1102 1103/* MC_CMD_COPYCODE_IN msgrequest */ 1104#define MC_CMD_COPYCODE_IN_LEN 16 1105/* Source address 1106 * 1107 * The main image should be entered via a copy of a single word from and to a 1108 * magic address, which controls various aspects of the boot. The magic address 1109 * is a bitfield, with each bit as documented below. 1110 */ 1111#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 1112#define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4 1113/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 1114#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 1115/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 1116 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1117 */ 1118#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1119/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1120 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1121 * below) 1122 */ 1123#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1124#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1125#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1126#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1127#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1128#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1129#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1130#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1131#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1132#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1133#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1134#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1135#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1136/* Destination address */ 1137#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1138#define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4 1139#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1140#define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4 1141/* Address of where to jump after copy. */ 1142#define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1143#define MC_CMD_COPYCODE_IN_JUMP_LEN 4 1144/* enum: Control should return to the caller rather than jumping */ 1145#define MC_CMD_COPYCODE_JUMP_NONE 0x1 1146 1147/* MC_CMD_COPYCODE_OUT msgresponse */ 1148#define MC_CMD_COPYCODE_OUT_LEN 0 1149 1150/***********************************/ 1151/* MC_CMD_SET_FUNC 1152 * Select function for function-specific commands. 1153 */ 1154#define MC_CMD_SET_FUNC 0x4 1155#undef MC_CMD_0x4_PRIVILEGE_CTG 1156 1157#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1158 1159/* MC_CMD_SET_FUNC_IN msgrequest */ 1160#define MC_CMD_SET_FUNC_IN_LEN 4 1161/* Set function */ 1162#define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1163#define MC_CMD_SET_FUNC_IN_FUNC_LEN 4 1164 1165/* MC_CMD_SET_FUNC_OUT msgresponse */ 1166#define MC_CMD_SET_FUNC_OUT_LEN 0 1167 1168/***********************************/ 1169/* MC_CMD_GET_BOOT_STATUS 1170 * Get the instruction address from which the MC booted. 1171 */ 1172#define MC_CMD_GET_BOOT_STATUS 0x5 1173#undef MC_CMD_0x5_PRIVILEGE_CTG 1174 1175#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1176 1177/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1178#define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1179 1180/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1181#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1182/* ?? */ 1183#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1184#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4 1185/* enum: indicates that the MC wasn't flash booted */ 1186#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1187#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1188#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4 1189#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1190#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1191#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1192#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1193#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1194#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1195 1196/***********************************/ 1197/* MC_CMD_GET_ASSERTS 1198 * Get (and optionally clear) the current assertion status. Only 1199 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1200 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1201 */ 1202#define MC_CMD_GET_ASSERTS 0x6 1203#undef MC_CMD_0x6_PRIVILEGE_CTG 1204 1205#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1206 1207/* MC_CMD_GET_ASSERTS_IN msgrequest */ 1208#define MC_CMD_GET_ASSERTS_IN_LEN 4 1209/* Set to clear assertion */ 1210#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1211#define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4 1212 1213/* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1214#define MC_CMD_GET_ASSERTS_OUT_LEN 140 1215/* Assertion status flag. */ 1216#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1217#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4 1218/* enum: No assertions have failed. */ 1219#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1220/* enum: A system-level assertion has failed. */ 1221#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1222/* enum: A thread-level assertion has failed. */ 1223#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1224/* enum: The system was reset by the watchdog. */ 1225#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1226/* enum: An illegal address trap stopped the system (huntington and later) */ 1227#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1228/* Failing PC value */ 1229#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1230#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4 1231/* Saved GP regs */ 1232#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1233#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1234#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1235/* enum: A magic value hinting that the value in this register at the time of 1236 * the failure has likely been lost. 1237 */ 1238#define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1239/* Failing thread address */ 1240#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1241#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4 1242#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1243#define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4 1244 1245/***********************************/ 1246/* MC_CMD_LOG_CTRL 1247 * Configure the output stream for log events such as link state changes, 1248 * sensor notifications and MCDI completions 1249 */ 1250#define MC_CMD_LOG_CTRL 0x7 1251#undef MC_CMD_0x7_PRIVILEGE_CTG 1252 1253#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1254 1255/* MC_CMD_LOG_CTRL_IN msgrequest */ 1256#define MC_CMD_LOG_CTRL_IN_LEN 8 1257/* Log destination */ 1258#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1259#define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4 1260/* enum: UART. */ 1261#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1262/* enum: Event queue. */ 1263#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1264/* Legacy argument. Must be zero. */ 1265#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1266#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4 1267 1268/* MC_CMD_LOG_CTRL_OUT msgresponse */ 1269#define MC_CMD_LOG_CTRL_OUT_LEN 0 1270 1271/***********************************/ 1272/* MC_CMD_GET_VERSION 1273 * Get version information about the MC firmware. 1274 */ 1275#define MC_CMD_GET_VERSION 0x8 1276#undef MC_CMD_0x8_PRIVILEGE_CTG 1277 1278#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1279 1280/* MC_CMD_GET_VERSION_IN msgrequest */ 1281#define MC_CMD_GET_VERSION_IN_LEN 0 1282 1283/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1284#define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1285/* placeholder, set to 0 */ 1286#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1287#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4 1288 1289/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1290#define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1291#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1292#define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 1293/* enum: Reserved version number to indicate "any" version. */ 1294#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1295/* enum: Bootrom version value for Siena. */ 1296#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1297/* enum: Bootrom version value for Huntington. */ 1298#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1299/* enum: Bootrom version value for Medford2. */ 1300#define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002 1301 1302/* MC_CMD_GET_VERSION_OUT msgresponse */ 1303#define MC_CMD_GET_VERSION_OUT_LEN 32 1304/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1305/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1306/* Enum values, see field(s): */ 1307/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1308#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1309#define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4 1310/* 128bit mask of functions supported by the current firmware */ 1311#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1312#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1313#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1314#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1315#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1316#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1317 1318/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1319#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1320/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1321/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1322/* Enum values, see field(s): */ 1323/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1324#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1325#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4 1326/* 128bit mask of functions supported by the current firmware */ 1327#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1328#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1329#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1330#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1331#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1332#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1333/* extra info */ 1334#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1335#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1336 1337/***********************************/ 1338/* MC_CMD_PTP 1339 * Perform PTP operation 1340 */ 1341#define MC_CMD_PTP 0xb 1342#undef MC_CMD_0xb_PRIVILEGE_CTG 1343 1344#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1345 1346/* MC_CMD_PTP_IN msgrequest */ 1347#define MC_CMD_PTP_IN_LEN 1 1348/* PTP operation code */ 1349#define MC_CMD_PTP_IN_OP_OFST 0 1350#define MC_CMD_PTP_IN_OP_LEN 1 1351/* enum: Enable PTP packet timestamping operation. */ 1352#define MC_CMD_PTP_OP_ENABLE 0x1 1353/* enum: Disable PTP packet timestamping operation. */ 1354#define MC_CMD_PTP_OP_DISABLE 0x2 1355/* enum: Send a PTP packet. This operation is used on Siena and Huntington. 1356 * From Medford onwards it is not supported: on those platforms PTP transmit 1357 * timestamping is done using the fast path. 1358 */ 1359#define MC_CMD_PTP_OP_TRANSMIT 0x3 1360/* enum: Read the current NIC time. */ 1361#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1362/* enum: Get the current PTP status. Note that the clock frequency returned (in 1363 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666). 1364 */ 1365#define MC_CMD_PTP_OP_STATUS 0x5 1366/* enum: Adjust the PTP NIC's time. */ 1367#define MC_CMD_PTP_OP_ADJUST 0x6 1368/* enum: Synchronize host and NIC time. */ 1369#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1370/* enum: Basic manufacturing tests. Siena PTP adapters only. */ 1371#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1372/* enum: Packet based manufacturing tests. Siena PTP adapters only. */ 1373#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1374/* enum: Reset some of the PTP related statistics */ 1375#define MC_CMD_PTP_OP_RESET_STATS 0xa 1376/* enum: Debug operations to MC. */ 1377#define MC_CMD_PTP_OP_DEBUG 0xb 1378/* enum: Read an FPGA register. Siena PTP adapters only. */ 1379#define MC_CMD_PTP_OP_FPGAREAD 0xc 1380/* enum: Write an FPGA register. Siena PTP adapters only. */ 1381#define MC_CMD_PTP_OP_FPGAWRITE 0xd 1382/* enum: Apply an offset to the NIC clock */ 1383#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1384/* enum: Change the frequency correction applied to the NIC clock */ 1385#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1386/* enum: Set the MC packet filter VLAN tags for received PTP packets. 1387 * Deprecated for Huntington onwards. 1388 */ 1389#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1390/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for 1391 * Huntington onwards. 1392 */ 1393#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1394/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated 1395 * for Huntington onwards. 1396 */ 1397#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1398/* enum: Set the clock source. Required for snapper tests on Huntington and 1399 * Medford. Not implemented for Siena or Medford2. 1400 */ 1401#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1402/* enum: Reset value of Timer Reg. Not implemented. */ 1403#define MC_CMD_PTP_OP_RST_CLK 0x14 1404/* enum: Enable the forwarding of PPS events to the host */ 1405#define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1406/* enum: Get the time format used by this NIC for PTP operations */ 1407#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1408/* enum: Get the clock attributes. NOTE- extended version of 1409 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1410 */ 1411#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1412/* enum: Get corrections that should be applied to the various different 1413 * timestamps 1414 */ 1415#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1416/* enum: Subscribe to receive periodic time events indicating the current NIC 1417 * time 1418 */ 1419#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1420/* enum: Unsubscribe to stop receiving time events */ 1421#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1422/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1423 * input on the same NIC. Siena PTP adapters only. 1424 */ 1425#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1426/* enum: Set the PTP sync status. Status is used by firmware to report to event 1427 * subscribers. 1428 */ 1429#define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1430/* enum: Above this for future use. */ 1431#define MC_CMD_PTP_OP_MAX 0x1c 1432 1433/* MC_CMD_PTP_IN_ENABLE msgrequest */ 1434#define MC_CMD_PTP_IN_ENABLE_LEN 16 1435#define MC_CMD_PTP_IN_CMD_OFST 0 1436#define MC_CMD_PTP_IN_CMD_LEN 4 1437#define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1438#define MC_CMD_PTP_IN_PERIPH_ID_LEN 4 1439/* Not used. Events are always sent to function relative queue 0. */ 1440#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1441#define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4 1442/* PTP timestamping mode. Not used from Huntington onwards. */ 1443#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1444#define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4 1445/* enum: PTP, version 1 */ 1446#define MC_CMD_PTP_MODE_V1 0x0 1447/* enum: PTP, version 1, with VLAN headers - deprecated */ 1448#define MC_CMD_PTP_MODE_V1_VLAN 0x1 1449/* enum: PTP, version 2 */ 1450#define MC_CMD_PTP_MODE_V2 0x2 1451/* enum: PTP, version 2, with VLAN headers - deprecated */ 1452#define MC_CMD_PTP_MODE_V2_VLAN 0x3 1453/* enum: PTP, version 2, with improved UUID filtering */ 1454#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1455/* enum: FCoE (seconds and microseconds) */ 1456#define MC_CMD_PTP_MODE_FCOE 0x5 1457 1458/* MC_CMD_PTP_IN_DISABLE msgrequest */ 1459#define MC_CMD_PTP_IN_DISABLE_LEN 8 1460/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1461/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1462/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1463/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1464 1465/* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1466#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1467#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1468#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1469/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1470/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1471/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1472/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1473/* Transmit packet length */ 1474#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1475#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4 1476/* Transmit packet data */ 1477#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1478#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1479#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1480#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1481 1482/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1483#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1484/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1485/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1486/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1487/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1488 1489/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */ 1490#define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8 1491/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1492/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1493/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1494/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1495 1496/* MC_CMD_PTP_IN_STATUS msgrequest */ 1497#define MC_CMD_PTP_IN_STATUS_LEN 8 1498/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1499/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1500/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1501/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1502 1503/* MC_CMD_PTP_IN_ADJUST msgrequest */ 1504#define MC_CMD_PTP_IN_ADJUST_LEN 24 1505/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1506/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1507/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1508/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1509/* Frequency adjustment 40 bit fixed point ns */ 1510#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1511#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1512#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1513#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1514/* enum: Number of fractional bits in frequency adjustment */ 1515#define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1516/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1517 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1518 * field. 1519 */ 1520#define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c 1521/* Time adjustment in seconds */ 1522#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1523#define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4 1524/* Time adjustment major value */ 1525#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1526#define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4 1527/* Time adjustment in nanoseconds */ 1528#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1529#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4 1530/* Time adjustment minor value */ 1531#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1532#define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4 1533 1534/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */ 1535#define MC_CMD_PTP_IN_ADJUST_V2_LEN 28 1536/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1537/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1538/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1539/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1540/* Frequency adjustment 40 bit fixed point ns */ 1541#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8 1542#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8 1543#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8 1544#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12 1545/* enum: Number of fractional bits in frequency adjustment */ 1546/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1547/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1548 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1549 * field. 1550 */ 1551/* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */ 1552/* Time adjustment in seconds */ 1553#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16 1554#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4 1555/* Time adjustment major value */ 1556#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16 1557#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4 1558/* Time adjustment in nanoseconds */ 1559#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20 1560#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4 1561/* Time adjustment minor value */ 1562#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20 1563#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4 1564/* Upper 32bits of major time offset adjustment */ 1565#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24 1566#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4 1567 1568/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1569#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1570/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1571/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1572/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1573/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1574/* Number of time readings to capture */ 1575#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1576#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4 1577/* Host address in which to write "synchronization started" indication (64 1578 * bits) 1579 */ 1580#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1581#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1582#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1583#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1584 1585/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1586#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1587/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1588/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1589/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1590/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1591 1592/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1593#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1594/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1595/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1596/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1597/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1598/* Enable or disable packet testing */ 1599#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1600#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4 1601 1602/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */ 1603#define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1604/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1605/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1606/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1607/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1608 1609/* MC_CMD_PTP_IN_DEBUG msgrequest */ 1610#define MC_CMD_PTP_IN_DEBUG_LEN 12 1611/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1612/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1613/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1614/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1615/* Debug operations */ 1616#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1617#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4 1618 1619/* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1620#define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1621/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1622/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1623/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1624/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1625#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1626#define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4 1627#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1628#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4 1629 1630/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1631#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1632#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1633#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1634/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1635/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1636/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1637/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1638#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1639#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4 1640#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1641#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1642#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1643#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1644 1645/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1646#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1647/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1648/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1649/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1650/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1651/* Time adjustment in seconds */ 1652#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1653#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4 1654/* Time adjustment major value */ 1655#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1656#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4 1657/* Time adjustment in nanoseconds */ 1658#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1659#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4 1660/* Time adjustment minor value */ 1661#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1662#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4 1663 1664/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */ 1665#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20 1666/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1667/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1668/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1669/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1670/* Time adjustment in seconds */ 1671#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8 1672#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4 1673/* Time adjustment major value */ 1674#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8 1675#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4 1676/* Time adjustment in nanoseconds */ 1677#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12 1678#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4 1679/* Time adjustment minor value */ 1680#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12 1681#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4 1682/* Upper 32bits of major time offset adjustment */ 1683#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16 1684#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4 1685 1686/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1687#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1688/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1689/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1690/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1691/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1692/* Frequency adjustment 40 bit fixed point ns */ 1693#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1694#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1695#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1696#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1697/* Enum values, see field(s): */ 1698/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */ 1699 1700/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1701#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1702/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1703/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1704/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1705/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1706/* Number of VLAN tags, 0 if not VLAN */ 1707#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1708#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4 1709/* Set of VLAN tags to filter against */ 1710#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1711#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1712#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1713 1714/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1715#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1716/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1717/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1718/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1719/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1720/* 1 to enable UUID filtering, 0 to disable */ 1721#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1722#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4 1723/* UUID to filter against */ 1724#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1725#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1726#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1727#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1728 1729/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1730#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1731/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1732/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1733/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1734/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1735/* 1 to enable Domain filtering, 0 to disable */ 1736#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1737#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4 1738/* Domain number to filter against */ 1739#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1740#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4 1741 1742/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1743#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1744/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1745/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1746/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1747/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1748/* Set the clock source. */ 1749#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1750#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4 1751/* enum: Internal. */ 1752#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1753/* enum: External. */ 1754#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1755 1756/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */ 1757#define MC_CMD_PTP_IN_RST_CLK_LEN 8 1758/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1759/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1760/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1761/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1762 1763/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1764#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1765/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1766/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1767/* Enable or disable */ 1768#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1769#define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4 1770/* enum: Enable */ 1771#define MC_CMD_PTP_ENABLE_PPS 0x0 1772/* enum: Disable */ 1773#define MC_CMD_PTP_DISABLE_PPS 0x1 1774/* Not used. Events are always sent to function relative queue 0. */ 1775#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1776#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4 1777 1778/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1779#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1780/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1781/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1782/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1783/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1784 1785/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1786#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1787/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1788/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1789/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1790/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1791 1792/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1793#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1794/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1795/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1796/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1797/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1798 1799/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1800#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1801/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1802/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1803/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1804/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1805/* Original field containing queue ID. Now extended to include flags. */ 1806#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1807#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4 1808#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 1809#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 1810#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 1811#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 1812 1813/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1814#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1815/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1816/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1817/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1818/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1819/* Unsubscribe options */ 1820#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1821#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4 1822/* enum: Unsubscribe a single queue */ 1823#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1824/* enum: Unsubscribe all queues */ 1825#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1826/* Event queue ID */ 1827#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1828#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4 1829 1830/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1831#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1832/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1833/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1834/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1835/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1836/* 1 to enable PPS test mode, 0 to disable and return result. */ 1837#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1838#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4 1839 1840/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 1841#define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 1842/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1843/* MC_CMD_PTP_IN_CMD_LEN 4 */ 1844/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1845/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1846/* NIC - Host System Clock Synchronization status */ 1847#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 1848#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4 1849/* enum: Host System clock and NIC clock are not in sync */ 1850#define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 1851/* enum: Host System clock and NIC clock are synchronized */ 1852#define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 1853/* If synchronized, number of seconds until clocks should be considered to be 1854 * no longer in sync. 1855 */ 1856#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 1857#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4 1858#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 1859#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4 1860#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 1861#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4 1862 1863/* MC_CMD_PTP_OUT msgresponse */ 1864#define MC_CMD_PTP_OUT_LEN 0 1865 1866/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1867#define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1868/* Value of seconds timestamp */ 1869#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1870#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4 1871/* Timestamp major value */ 1872#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1873#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4 1874/* Value of nanoseconds timestamp */ 1875#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1876#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4 1877/* Timestamp minor value */ 1878#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1879#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4 1880 1881/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1882#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1883 1884/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1885#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1886 1887/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1888#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1889/* Value of seconds timestamp */ 1890#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1891#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4 1892/* Timestamp major value */ 1893#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1894#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4 1895/* Value of nanoseconds timestamp */ 1896#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1897#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4 1898/* Timestamp minor value */ 1899#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1900#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4 1901 1902/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */ 1903#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12 1904/* Value of seconds timestamp */ 1905#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0 1906#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4 1907/* Timestamp major value */ 1908#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0 1909#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4 1910/* Value of nanoseconds timestamp */ 1911#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4 1912#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4 1913/* Timestamp minor value */ 1914#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4 1915#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4 1916/* Upper 32bits of major timestamp value */ 1917#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8 1918#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4 1919 1920/* MC_CMD_PTP_OUT_STATUS msgresponse */ 1921#define MC_CMD_PTP_OUT_STATUS_LEN 64 1922/* Frequency of NIC's hardware clock */ 1923#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1924#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4 1925/* Number of packets transmitted and timestamped */ 1926#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1927#define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4 1928/* Number of packets received and timestamped */ 1929#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1930#define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4 1931/* Number of packets timestamped by the FPGA */ 1932#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1933#define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4 1934/* Number of packets filter matched */ 1935#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1936#define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4 1937/* Number of packets not filter matched */ 1938#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1939#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4 1940/* Number of PPS overflows (noise on input?) */ 1941#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1942#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4 1943/* Number of PPS bad periods */ 1944#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1945#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4 1946/* Minimum period of PPS pulse in nanoseconds */ 1947#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1948#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4 1949/* Maximum period of PPS pulse in nanoseconds */ 1950#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1951#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4 1952/* Last period of PPS pulse in nanoseconds */ 1953#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1954#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4 1955/* Mean period of PPS pulse in nanoseconds */ 1956#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1957#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4 1958/* Minimum offset of PPS pulse in nanoseconds (signed) */ 1959#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1960#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4 1961/* Maximum offset of PPS pulse in nanoseconds (signed) */ 1962#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1963#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4 1964/* Last offset of PPS pulse in nanoseconds (signed) */ 1965#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1966#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4 1967/* Mean offset of PPS pulse in nanoseconds (signed) */ 1968#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1969#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4 1970 1971/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1972#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1973#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1974#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1975/* A set of host and NIC times */ 1976#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1977#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1978#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1979#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1980/* Host time immediately before NIC's hardware clock read */ 1981#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1982#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4 1983/* Value of seconds timestamp */ 1984#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1985#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4 1986/* Timestamp major value */ 1987#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 1988#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4 1989/* Value of nanoseconds timestamp */ 1990#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1991#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4 1992/* Timestamp minor value */ 1993#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 1994#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4 1995/* Host time immediately after NIC's hardware clock read */ 1996#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1997#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4 1998/* Number of nanoseconds waited after reading NIC's hardware clock */ 1999#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 2000#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4 2001 2002/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 2003#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 2004/* Results of testing */ 2005#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 2006#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4 2007/* enum: Successful test */ 2008#define MC_CMD_PTP_MANF_SUCCESS 0x0 2009/* enum: FPGA load failed */ 2010#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 2011/* enum: FPGA version invalid */ 2012#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 2013/* enum: FPGA registers incorrect */ 2014#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 2015/* enum: Oscillator possibly not working? */ 2016#define MC_CMD_PTP_MANF_OSCILLATOR 0x4 2017/* enum: Timestamps not increasing */ 2018#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 2019/* enum: Mismatched packet count */ 2020#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 2021/* enum: Mismatched packet count (Siena filter and FPGA) */ 2022#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 2023/* enum: Not enough packets to perform timestamp check */ 2024#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 2025/* enum: Timestamp trigger GPIO not working */ 2026#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 2027/* enum: Insufficient PPS events to perform checks */ 2028#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 2029/* enum: PPS time event period not sufficiently close to 1s. */ 2030#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 2031/* enum: PPS time event nS reading not sufficiently close to zero. */ 2032#define MC_CMD_PTP_MANF_PPS_NS 0xc 2033/* enum: PTP peripheral registers incorrect */ 2034#define MC_CMD_PTP_MANF_REGISTERS 0xd 2035/* enum: Failed to read time from PTP peripheral */ 2036#define MC_CMD_PTP_MANF_CLOCK_READ 0xe 2037/* Presence of external oscillator */ 2038#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 2039#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4 2040 2041/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 2042#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 2043/* Results of testing */ 2044#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 2045#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4 2046/* Number of packets received by FPGA */ 2047#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 2048#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4 2049/* Number of packets received by Siena filters */ 2050#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 2051#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4 2052 2053/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 2054#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 2055#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 2056#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 2057#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 2058#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 2059#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 2060#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 2061 2062/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 2063#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 2064/* Time format required/used by for this NIC. Applies to all PTP MCDI 2065 * operations that pass times between the host and firmware. If this operation 2066 * is not supported (older firmware) a format of seconds and nanoseconds should 2067 * be assumed. Note this enum is deprecated. Do not add to it- use the 2068 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead. 2069 */ 2070#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 2071#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4 2072/* enum: Times are in seconds and nanoseconds */ 2073#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 2074/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2075#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 2076/* enum: Major register has units of seconds, minor 2^-27s per tick */ 2077#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 2078 2079/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 2080#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 2081/* Time format required/used by for this NIC. Applies to all PTP MCDI 2082 * operations that pass times between the host and firmware. If this operation 2083 * is not supported (older firmware) a format of seconds and nanoseconds should 2084 * be assumed. 2085 */ 2086#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 2087#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4 2088/* enum: Times are in seconds and nanoseconds */ 2089#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 2090/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2091#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 2092/* enum: Major register has units of seconds, minor 2^-27s per tick */ 2093#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 2094/* enum: Major register units are seconds, minor units are quarter nanoseconds 2095 */ 2096#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3 2097/* Minimum acceptable value for a corrected synchronization timeset. When 2098 * comparing host and NIC clock times, the MC returns a set of samples that 2099 * contain the host start and end time, the MC time when the host start was 2100 * detected and the time the MC waited between reading the time and detecting 2101 * the host end. The corrected sync window is the difference between the host 2102 * end and start times minus the time that the MC waited for host end. 2103 */ 2104#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 2105#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4 2106/* Various PTP capabilities */ 2107#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 2108#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4 2109#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 2110#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 2111#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 2112#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 2113#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2 2114#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1 2115#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3 2116#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1 2117#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 2118#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4 2119#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 2120#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4 2121#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 2122#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4 2123 2124/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 2125#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 2126/* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2127#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 2128#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4 2129/* Uncorrected error on PTP receive timestamps in NIC clock format */ 2130#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 2131#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4 2132/* Uncorrected error on PPS output in NIC clock format */ 2133#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 2134#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4 2135/* Uncorrected error on PPS input in NIC clock format */ 2136#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 2137#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4 2138 2139/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 2140#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 2141/* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2142#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 2143#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4 2144/* Uncorrected error on PTP receive timestamps in NIC clock format */ 2145#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 2146#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4 2147/* Uncorrected error on PPS output in NIC clock format */ 2148#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 2149#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4 2150/* Uncorrected error on PPS input in NIC clock format */ 2151#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 2152#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4 2153/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 2154#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 2155#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4 2156/* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 2157#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 2158#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4 2159 2160/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 2161#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 2162/* Results of testing */ 2163#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 2164#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4 2165/* Enum values, see field(s): */ 2166/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 2167 2168/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 2169#define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 2170 2171/***********************************/ 2172/* MC_CMD_CSR_READ32 2173 * Read 32bit words from the indirect memory map. 2174 */ 2175#define MC_CMD_CSR_READ32 0xc 2176#undef MC_CMD_0xc_PRIVILEGE_CTG 2177 2178#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2179 2180/* MC_CMD_CSR_READ32_IN msgrequest */ 2181#define MC_CMD_CSR_READ32_IN_LEN 12 2182/* Address */ 2183#define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 2184#define MC_CMD_CSR_READ32_IN_ADDR_LEN 4 2185#define MC_CMD_CSR_READ32_IN_STEP_OFST 4 2186#define MC_CMD_CSR_READ32_IN_STEP_LEN 4 2187#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 2188#define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4 2189 2190/* MC_CMD_CSR_READ32_OUT msgresponse */ 2191#define MC_CMD_CSR_READ32_OUT_LENMIN 4 2192#define MC_CMD_CSR_READ32_OUT_LENMAX 252 2193#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 2194/* The last dword is the status, not a value read */ 2195#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 2196#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 2197#define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 2198#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 2199 2200/***********************************/ 2201/* MC_CMD_CSR_WRITE32 2202 * Write 32bit dwords to the indirect memory map. 2203 */ 2204#define MC_CMD_CSR_WRITE32 0xd 2205#undef MC_CMD_0xd_PRIVILEGE_CTG 2206 2207#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2208 2209/* MC_CMD_CSR_WRITE32_IN msgrequest */ 2210#define MC_CMD_CSR_WRITE32_IN_LENMIN 12 2211#define MC_CMD_CSR_WRITE32_IN_LENMAX 252 2212#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 2213/* Address */ 2214#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 2215#define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4 2216#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 2217#define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4 2218#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 2219#define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 2220#define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 2221#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 2222 2223/* MC_CMD_CSR_WRITE32_OUT msgresponse */ 2224#define MC_CMD_CSR_WRITE32_OUT_LEN 4 2225#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 2226#define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4 2227 2228/***********************************/ 2229/* MC_CMD_HP 2230 * These commands are used for HP related features. They are grouped under one 2231 * MCDI command to avoid creating too many MCDI commands. 2232 */ 2233#define MC_CMD_HP 0x54 2234#undef MC_CMD_0x54_PRIVILEGE_CTG 2235 2236#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 2237 2238/* MC_CMD_HP_IN msgrequest */ 2239#define MC_CMD_HP_IN_LEN 16 2240/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 2241 * the specified address with the specified interval.When address is NULL, 2242 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 2243 * state / 2: (debug) Show temperature reported by one of the supported 2244 * sensors. 2245 */ 2246#define MC_CMD_HP_IN_SUBCMD_OFST 0 2247#define MC_CMD_HP_IN_SUBCMD_LEN 4 2248/* enum: OCSD (Option Card Sensor Data) sub-command. */ 2249#define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 2250/* enum: Last known valid HP sub-command. */ 2251#define MC_CMD_HP_IN_LAST_SUBCMD 0x0 2252/* The address to the array of sensor fields. (Or NULL to use a sub-command.) 2253 */ 2254#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 2255#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 2256#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 2257#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 2258/* The requested update interval, in seconds. (Or the sub-command if ADDR is 2259 * NULL.) 2260 */ 2261#define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 2262#define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4 2263 2264/* MC_CMD_HP_OUT msgresponse */ 2265#define MC_CMD_HP_OUT_LEN 4 2266#define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 2267#define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4 2268/* enum: OCSD stopped for this card. */ 2269#define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 2270/* enum: OCSD was successfully started with the address provided. */ 2271#define MC_CMD_HP_OUT_OCSD_STARTED 0x2 2272/* enum: OCSD was already started for this card. */ 2273#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 2274 2275/***********************************/ 2276/* MC_CMD_STACKINFO 2277 * Get stack information. 2278 */ 2279#define MC_CMD_STACKINFO 0xf 2280#undef MC_CMD_0xf_PRIVILEGE_CTG 2281 2282#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2283 2284/* MC_CMD_STACKINFO_IN msgrequest */ 2285#define MC_CMD_STACKINFO_IN_LEN 0 2286 2287/* MC_CMD_STACKINFO_OUT msgresponse */ 2288#define MC_CMD_STACKINFO_OUT_LENMIN 12 2289#define MC_CMD_STACKINFO_OUT_LENMAX 252 2290#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 2291/* (thread ptr, stack size, free space) for each thread in system */ 2292#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 2293#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 2294#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 2295#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 2296 2297/***********************************/ 2298/* MC_CMD_MDIO_READ 2299 * MDIO register read. 2300 */ 2301#define MC_CMD_MDIO_READ 0x10 2302#undef MC_CMD_0x10_PRIVILEGE_CTG 2303 2304#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2305 2306/* MC_CMD_MDIO_READ_IN msgrequest */ 2307#define MC_CMD_MDIO_READ_IN_LEN 16 2308/* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2309 * external devices. 2310 */ 2311#define MC_CMD_MDIO_READ_IN_BUS_OFST 0 2312#define MC_CMD_MDIO_READ_IN_BUS_LEN 4 2313/* enum: Internal. */ 2314#define MC_CMD_MDIO_BUS_INTERNAL 0x0 2315/* enum: External. */ 2316#define MC_CMD_MDIO_BUS_EXTERNAL 0x1 2317/* Port address */ 2318#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 2319#define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4 2320/* Device Address or clause 22. */ 2321#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 2322#define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4 2323/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2324 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2325 */ 2326#define MC_CMD_MDIO_CLAUSE22 0x20 2327/* Address */ 2328#define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 2329#define MC_CMD_MDIO_READ_IN_ADDR_LEN 4 2330 2331/* MC_CMD_MDIO_READ_OUT msgresponse */ 2332#define MC_CMD_MDIO_READ_OUT_LEN 8 2333/* Value */ 2334#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 2335#define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4 2336/* Status the MDIO commands return the raw status bits from the MDIO block. A 2337 * "good" transaction should have the DONE bit set and all other bits clear. 2338 */ 2339#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 2340#define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4 2341/* enum: Good. */ 2342#define MC_CMD_MDIO_STATUS_GOOD 0x8 2343 2344/***********************************/ 2345/* MC_CMD_MDIO_WRITE 2346 * MDIO register write. 2347 */ 2348#define MC_CMD_MDIO_WRITE 0x11 2349#undef MC_CMD_0x11_PRIVILEGE_CTG 2350 2351#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2352 2353/* MC_CMD_MDIO_WRITE_IN msgrequest */ 2354#define MC_CMD_MDIO_WRITE_IN_LEN 20 2355/* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2356 * external devices. 2357 */ 2358#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 2359#define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4 2360/* enum: Internal. */ 2361/* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 2362/* enum: External. */ 2363/* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 2364/* Port address */ 2365#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 2366#define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4 2367/* Device Address or clause 22. */ 2368#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 2369#define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4 2370/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2371 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2372 */ 2373/* MC_CMD_MDIO_CLAUSE22 0x20 */ 2374/* Address */ 2375#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 2376#define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4 2377/* Value */ 2378#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 2379#define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4 2380 2381/* MC_CMD_MDIO_WRITE_OUT msgresponse */ 2382#define MC_CMD_MDIO_WRITE_OUT_LEN 4 2383/* Status; the MDIO commands return the raw status bits from the MDIO block. A 2384 * "good" transaction should have the DONE bit set and all other bits clear. 2385 */ 2386#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 2387#define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4 2388/* enum: Good. */ 2389/* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 2390 2391/***********************************/ 2392/* MC_CMD_DBI_WRITE 2393 * Write DBI register(s). 2394 */ 2395#define MC_CMD_DBI_WRITE 0x12 2396#undef MC_CMD_0x12_PRIVILEGE_CTG 2397 2398#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2399 2400/* MC_CMD_DBI_WRITE_IN msgrequest */ 2401#define MC_CMD_DBI_WRITE_IN_LENMIN 12 2402#define MC_CMD_DBI_WRITE_IN_LENMAX 252 2403#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 2404/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 2405 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 2406 */ 2407#define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 2408#define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 2409#define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 2410#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 2411 2412/* MC_CMD_DBI_WRITE_OUT msgresponse */ 2413#define MC_CMD_DBI_WRITE_OUT_LEN 0 2414 2415/* MC_CMD_DBIWROP_TYPEDEF structuredef */ 2416#define MC_CMD_DBIWROP_TYPEDEF_LEN 12 2417#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 2418#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4 2419#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 2420#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 2421#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 2422#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4 2423#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 2424#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 2425#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 2426#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 2427#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 2428#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 2429#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 2430#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 2431#define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 2432#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4 2433#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 2434#define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 2435 2436/***********************************/ 2437/* MC_CMD_PORT_READ32 2438 * Read a 32-bit register from the indirect port register map. The port to 2439 * access is implied by the Shared memory channel used. 2440 */ 2441#define MC_CMD_PORT_READ32 0x14 2442 2443/* MC_CMD_PORT_READ32_IN msgrequest */ 2444#define MC_CMD_PORT_READ32_IN_LEN 4 2445/* Address */ 2446#define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 2447#define MC_CMD_PORT_READ32_IN_ADDR_LEN 4 2448 2449/* MC_CMD_PORT_READ32_OUT msgresponse */ 2450#define MC_CMD_PORT_READ32_OUT_LEN 8 2451/* Value */ 2452#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 2453#define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4 2454/* Status */ 2455#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 2456#define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4 2457 2458/***********************************/ 2459/* MC_CMD_PORT_WRITE32 2460 * Write a 32-bit register to the indirect port register map. The port to 2461 * access is implied by the Shared memory channel used. 2462 */ 2463#define MC_CMD_PORT_WRITE32 0x15 2464 2465/* MC_CMD_PORT_WRITE32_IN msgrequest */ 2466#define MC_CMD_PORT_WRITE32_IN_LEN 8 2467/* Address */ 2468#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 2469#define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4 2470/* Value */ 2471#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 2472#define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4 2473 2474/* MC_CMD_PORT_WRITE32_OUT msgresponse */ 2475#define MC_CMD_PORT_WRITE32_OUT_LEN 4 2476/* Status */ 2477#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 2478#define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4 2479 2480/***********************************/ 2481/* MC_CMD_PORT_READ128 2482 * Read a 128-bit register from the indirect port register map. The port to 2483 * access is implied by the Shared memory channel used. 2484 */ 2485#define MC_CMD_PORT_READ128 0x16 2486 2487/* MC_CMD_PORT_READ128_IN msgrequest */ 2488#define MC_CMD_PORT_READ128_IN_LEN 4 2489/* Address */ 2490#define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 2491#define MC_CMD_PORT_READ128_IN_ADDR_LEN 4 2492 2493/* MC_CMD_PORT_READ128_OUT msgresponse */ 2494#define MC_CMD_PORT_READ128_OUT_LEN 20 2495/* Value */ 2496#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 2497#define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 2498/* Status */ 2499#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 2500#define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4 2501 2502/***********************************/ 2503/* MC_CMD_PORT_WRITE128 2504 * Write a 128-bit register to the indirect port register map. The port to 2505 * access is implied by the Shared memory channel used. 2506 */ 2507#define MC_CMD_PORT_WRITE128 0x17 2508 2509/* MC_CMD_PORT_WRITE128_IN msgrequest */ 2510#define MC_CMD_PORT_WRITE128_IN_LEN 20 2511/* Address */ 2512#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 2513#define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4 2514/* Value */ 2515#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 2516#define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 2517 2518/* MC_CMD_PORT_WRITE128_OUT msgresponse */ 2519#define MC_CMD_PORT_WRITE128_OUT_LEN 4 2520/* Status */ 2521#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 2522#define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4 2523 2524/* MC_CMD_CAPABILITIES structuredef */ 2525#define MC_CMD_CAPABILITIES_LEN 4 2526/* Small buf table. */ 2527#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 2528#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 2529/* Turbo mode (for Maranello). */ 2530#define MC_CMD_CAPABILITIES_TURBO_LBN 1 2531#define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2532/* Turbo mode active (for Maranello). */ 2533#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2534#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2535/* PTP offload. */ 2536#define MC_CMD_CAPABILITIES_PTP_LBN 3 2537#define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2538/* AOE mode. */ 2539#define MC_CMD_CAPABILITIES_AOE_LBN 4 2540#define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2541/* AOE mode active. */ 2542#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2543#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2544/* AOE mode active. */ 2545#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2546#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2547#define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2548#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2549 2550/***********************************/ 2551/* MC_CMD_GET_BOARD_CFG 2552 * Returns the MC firmware configuration structure. 2553 */ 2554#define MC_CMD_GET_BOARD_CFG 0x18 2555#undef MC_CMD_0x18_PRIVILEGE_CTG 2556 2557#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2558 2559/* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2560#define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2561 2562/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2563#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2564#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2565#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2566#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2567#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4 2568#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2569#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2570/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on 2571 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2572 */ 2573#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2574#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4 2575/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on 2576 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2577 */ 2578#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2579#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4 2580/* Base MAC address for Siena Port0. Unused on EF10 and later (use 2581 * MC_CMD_GET_MAC_ADDRESSES). 2582 */ 2583#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2584#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2585/* Base MAC address for Siena Port1. Unused on EF10 and later (use 2586 * MC_CMD_GET_MAC_ADDRESSES). 2587 */ 2588#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2589#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2590/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use 2591 * MC_CMD_GET_MAC_ADDRESSES). 2592 */ 2593#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2594#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4 2595/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use 2596 * MC_CMD_GET_MAC_ADDRESSES). 2597 */ 2598#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2599#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4 2600/* Increment between addresses in MAC address pool for Siena Port0. Unused on 2601 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 2602 */ 2603#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 2604#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4 2605/* Increment between addresses in MAC address pool for Siena Port1. Unused on 2606 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 2607 */ 2608#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 2609#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4 2610/* Siena only. This field contains a 16-bit value for each of the types of 2611 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a 2612 * specific board type, but otherwise have no meaning to the MC; they are used 2613 * by the driver to manage selection of appropriate firmware updates. Unused on 2614 * EF10 and later (use MC_CMD_NVRAM_METADATA). 2615 */ 2616#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 2617#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 2618#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 2619#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 2620 2621/***********************************/ 2622/* MC_CMD_DBI_READX 2623 * Read DBI register(s) -- extended functionality 2624 */ 2625#define MC_CMD_DBI_READX 0x19 2626#undef MC_CMD_0x19_PRIVILEGE_CTG 2627 2628#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2629 2630/* MC_CMD_DBI_READX_IN msgrequest */ 2631#define MC_CMD_DBI_READX_IN_LENMIN 8 2632#define MC_CMD_DBI_READX_IN_LENMAX 248 2633#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 2634/* Each Read op consists of an address (offset 0), VF/CS2) */ 2635#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 2636#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 2637#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 2638#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 2639#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 2640#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 2641 2642/* MC_CMD_DBI_READX_OUT msgresponse */ 2643#define MC_CMD_DBI_READX_OUT_LENMIN 4 2644#define MC_CMD_DBI_READX_OUT_LENMAX 252 2645#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 2646/* Value */ 2647#define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 2648#define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 2649#define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 2650#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 2651 2652/* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 2653#define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 2654#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 2655#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4 2656#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 2657#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 2658#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 2659#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4 2660#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 2661#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 2662#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 2663#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 2664#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 2665#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 2666#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 2667#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 2668 2669/***********************************/ 2670/* MC_CMD_SET_RAND_SEED 2671 * Set the 16byte seed for the MC pseudo-random generator. 2672 */ 2673#define MC_CMD_SET_RAND_SEED 0x1a 2674#undef MC_CMD_0x1a_PRIVILEGE_CTG 2675 2676#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2677 2678/* MC_CMD_SET_RAND_SEED_IN msgrequest */ 2679#define MC_CMD_SET_RAND_SEED_IN_LEN 16 2680/* Seed value. */ 2681#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 2682#define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 2683 2684/* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 2685#define MC_CMD_SET_RAND_SEED_OUT_LEN 0 2686 2687/***********************************/ 2688/* MC_CMD_LTSSM_HIST 2689 * Retrieve the history of the LTSSM, if the build supports it. 2690 */ 2691#define MC_CMD_LTSSM_HIST 0x1b 2692 2693/* MC_CMD_LTSSM_HIST_IN msgrequest */ 2694#define MC_CMD_LTSSM_HIST_IN_LEN 0 2695 2696/* MC_CMD_LTSSM_HIST_OUT msgresponse */ 2697#define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 2698#define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 2699#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 2700/* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 2701#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 2702#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 2703#define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 2704#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 2705 2706/***********************************/ 2707/* MC_CMD_DRV_ATTACH 2708 * Inform MCPU that this port is managed on the host (i.e. driver active). For 2709 * Huntington, also request the preferred datapath firmware to use if possible 2710 * (it may not be possible for this request to be fulfilled; the driver must 2711 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 2712 * features are actually available). The FIRMWARE_ID field is ignored by older 2713 * platforms. 2714 */ 2715#define MC_CMD_DRV_ATTACH 0x1c 2716#undef MC_CMD_0x1c_PRIVILEGE_CTG 2717 2718#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2719 2720/* MC_CMD_DRV_ATTACH_IN msgrequest */ 2721#define MC_CMD_DRV_ATTACH_IN_LEN 12 2722/* new state to set if UPDATE=1 */ 2723#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 2724#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4 2725#define MC_CMD_DRV_ATTACH_LBN 0 2726#define MC_CMD_DRV_ATTACH_WIDTH 1 2727#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0 2728#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1 2729#define MC_CMD_DRV_PREBOOT_LBN 1 2730#define MC_CMD_DRV_PREBOOT_WIDTH 1 2731#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1 2732#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1 2733#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2 2734#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1 2735#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3 2736#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1 2737/* 1 to set new state, or 0 to just report the existing state */ 2738#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 2739#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4 2740/* preferred datapath firmware (for Huntington; ignored for Siena) */ 2741#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 2742#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4 2743/* enum: Prefer to use full featured firmware */ 2744#define MC_CMD_FW_FULL_FEATURED 0x0 2745/* enum: Prefer to use firmware with fewer features but lower latency */ 2746#define MC_CMD_FW_LOW_LATENCY 0x1 2747/* enum: Prefer to use firmware for SolarCapture packed stream mode */ 2748#define MC_CMD_FW_PACKED_STREAM 0x2 2749/* enum: Prefer to use firmware with fewer features and simpler TX event 2750 * batching but higher TX packet rate 2751 */ 2752#define MC_CMD_FW_HIGH_TX_RATE 0x3 2753/* enum: Reserved value */ 2754#define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 2755/* enum: Prefer to use firmware with additional "rules engine" filtering 2756 * support 2757 */ 2758#define MC_CMD_FW_RULES_ENGINE 0x5 2759/* enum: Prefer to use firmware with additional DPDK support */ 2760#define MC_CMD_FW_DPDK 0x6 2761/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and 2762 * bug69716) 2763 */ 2764#define MC_CMD_FW_L3XUDP 0x7 2765/* enum: Requests that the MC keep whatever datapath firmware is currently 2766 * running. It's used for test purposes, where we want to be able to shmboot 2767 * special test firmware variants. This option is only recognised in eftest 2768 * (i.e. non-production) builds. 2769 */ 2770#define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe 2771/* enum: Only this option is allowed for non-admin functions */ 2772#define MC_CMD_FW_DONT_CARE 0xffffffff 2773 2774/* MC_CMD_DRV_ATTACH_OUT msgresponse */ 2775#define MC_CMD_DRV_ATTACH_OUT_LEN 4 2776/* previous or existing state, see the bitmask at NEW_STATE */ 2777#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 2778#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4 2779 2780/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 2781#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 2782/* previous or existing state, see the bitmask at NEW_STATE */ 2783#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 2784#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4 2785/* Flags associated with this function */ 2786#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 2787#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4 2788/* enum: Labels the lowest-numbered function visible to the OS */ 2789#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 2790/* enum: The function can control the link state of the physical port it is 2791 * bound to. 2792 */ 2793#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 2794/* enum: The function can perform privileged operations */ 2795#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 2796/* enum: The function does not have an active port associated with it. The port 2797 * refers to the Sorrento external FPGA port. 2798 */ 2799#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 2800/* enum: If set, indicates that VI spreading is currently enabled. Will always 2801 * indicate the current state, regardless of the value in the WANT_VI_SPREADING 2802 * input. 2803 */ 2804#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4 2805 2806/***********************************/ 2807/* MC_CMD_SHMUART 2808 * Route UART output to circular buffer in shared memory instead. 2809 */ 2810#define MC_CMD_SHMUART 0x1f 2811 2812/* MC_CMD_SHMUART_IN msgrequest */ 2813#define MC_CMD_SHMUART_IN_LEN 4 2814/* ??? */ 2815#define MC_CMD_SHMUART_IN_FLAG_OFST 0 2816#define MC_CMD_SHMUART_IN_FLAG_LEN 4 2817 2818/* MC_CMD_SHMUART_OUT msgresponse */ 2819#define MC_CMD_SHMUART_OUT_LEN 0 2820 2821/***********************************/ 2822/* MC_CMD_PORT_RESET 2823 * Generic per-port reset. There is no equivalent for per-board reset. Locks 2824 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 2825 * use MC_CMD_ENTITY_RESET instead. 2826 */ 2827#define MC_CMD_PORT_RESET 0x20 2828#undef MC_CMD_0x20_PRIVILEGE_CTG 2829 2830#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2831 2832/* MC_CMD_PORT_RESET_IN msgrequest */ 2833#define MC_CMD_PORT_RESET_IN_LEN 0 2834 2835/* MC_CMD_PORT_RESET_OUT msgresponse */ 2836#define MC_CMD_PORT_RESET_OUT_LEN 0 2837 2838/***********************************/ 2839/* MC_CMD_ENTITY_RESET 2840 * Generic per-resource reset. There is no equivalent for per-board reset. 2841 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 2842 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 2843 */ 2844#define MC_CMD_ENTITY_RESET 0x20 2845/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 2846 2847/* MC_CMD_ENTITY_RESET_IN msgrequest */ 2848#define MC_CMD_ENTITY_RESET_IN_LEN 4 2849/* Optional flags field. Omitting this will perform a "legacy" reset action 2850 * (TBD). 2851 */ 2852#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 2853#define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4 2854#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 2855#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 2856 2857/* MC_CMD_ENTITY_RESET_OUT msgresponse */ 2858#define MC_CMD_ENTITY_RESET_OUT_LEN 0 2859 2860/***********************************/ 2861/* MC_CMD_PCIE_CREDITS 2862 * Read instantaneous and minimum flow control thresholds. 2863 */ 2864#define MC_CMD_PCIE_CREDITS 0x21 2865 2866/* MC_CMD_PCIE_CREDITS_IN msgrequest */ 2867#define MC_CMD_PCIE_CREDITS_IN_LEN 8 2868/* poll period. 0 is disabled */ 2869#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 2870#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4 2871/* wipe statistics */ 2872#define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 2873#define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4 2874 2875/* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 2876#define MC_CMD_PCIE_CREDITS_OUT_LEN 16 2877#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 2878#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 2879#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 2880#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 2881#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 2882#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 2883#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 2884#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 2885#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 2886#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 2887#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 2888#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 2889#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 2890#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 2891#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 2892#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 2893 2894/***********************************/ 2895/* MC_CMD_RXD_MONITOR 2896 * Get histogram of RX queue fill level. 2897 */ 2898#define MC_CMD_RXD_MONITOR 0x22 2899 2900/* MC_CMD_RXD_MONITOR_IN msgrequest */ 2901#define MC_CMD_RXD_MONITOR_IN_LEN 12 2902#define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 2903#define MC_CMD_RXD_MONITOR_IN_QID_LEN 4 2904#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 2905#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4 2906#define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 2907#define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4 2908 2909/* MC_CMD_RXD_MONITOR_OUT msgresponse */ 2910#define MC_CMD_RXD_MONITOR_OUT_LEN 80 2911#define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 2912#define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4 2913#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2914#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4 2915#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2916#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4 2917#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2918#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4 2919#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2920#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4 2921#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2922#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4 2923#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2924#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4 2925#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2926#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4 2927#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2928#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4 2929#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2930#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4 2931#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2932#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4 2933#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2934#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4 2935#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2936#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4 2937#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2938#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4 2939#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2940#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4 2941#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2942#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4 2943#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2944#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4 2945#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2946#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4 2947#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2948#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4 2949#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2950#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4 2951 2952/***********************************/ 2953/* MC_CMD_PUTS 2954 * Copy the given ASCII string out onto UART and/or out of the network port. 2955 */ 2956#define MC_CMD_PUTS 0x23 2957#undef MC_CMD_0x23_PRIVILEGE_CTG 2958 2959#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2960 2961/* MC_CMD_PUTS_IN msgrequest */ 2962#define MC_CMD_PUTS_IN_LENMIN 13 2963#define MC_CMD_PUTS_IN_LENMAX 252 2964#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 2965#define MC_CMD_PUTS_IN_DEST_OFST 0 2966#define MC_CMD_PUTS_IN_DEST_LEN 4 2967#define MC_CMD_PUTS_IN_UART_LBN 0 2968#define MC_CMD_PUTS_IN_UART_WIDTH 1 2969#define MC_CMD_PUTS_IN_PORT_LBN 1 2970#define MC_CMD_PUTS_IN_PORT_WIDTH 1 2971#define MC_CMD_PUTS_IN_DHOST_OFST 4 2972#define MC_CMD_PUTS_IN_DHOST_LEN 6 2973#define MC_CMD_PUTS_IN_STRING_OFST 12 2974#define MC_CMD_PUTS_IN_STRING_LEN 1 2975#define MC_CMD_PUTS_IN_STRING_MINNUM 1 2976#define MC_CMD_PUTS_IN_STRING_MAXNUM 240 2977 2978/* MC_CMD_PUTS_OUT msgresponse */ 2979#define MC_CMD_PUTS_OUT_LEN 0 2980 2981/***********************************/ 2982/* MC_CMD_GET_PHY_CFG 2983 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 2984 * 'zombie' state. Locks required: None 2985 */ 2986#define MC_CMD_GET_PHY_CFG 0x24 2987#undef MC_CMD_0x24_PRIVILEGE_CTG 2988 2989#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2990 2991/* MC_CMD_GET_PHY_CFG_IN msgrequest */ 2992#define MC_CMD_GET_PHY_CFG_IN_LEN 0 2993 2994/* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 2995#define MC_CMD_GET_PHY_CFG_OUT_LEN 72 2996/* flags */ 2997#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 2998#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4 2999#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 3000#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 3001#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 3002#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 3003#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 3004#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 3005#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 3006#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 3007#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 3008#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 3009#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 3010#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 3011#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 3012#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 3013/* ?? */ 3014#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 3015#define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4 3016/* Bitmask of supported capabilities */ 3017#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 3018#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4 3019#define MC_CMD_PHY_CAP_10HDX_LBN 1 3020#define MC_CMD_PHY_CAP_10HDX_WIDTH 1 3021#define MC_CMD_PHY_CAP_10FDX_LBN 2 3022#define MC_CMD_PHY_CAP_10FDX_WIDTH 1 3023#define MC_CMD_PHY_CAP_100HDX_LBN 3 3024#define MC_CMD_PHY_CAP_100HDX_WIDTH 1 3025#define MC_CMD_PHY_CAP_100FDX_LBN 4 3026#define MC_CMD_PHY_CAP_100FDX_WIDTH 1 3027#define MC_CMD_PHY_CAP_1000HDX_LBN 5 3028#define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 3029#define MC_CMD_PHY_CAP_1000FDX_LBN 6 3030#define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 3031#define MC_CMD_PHY_CAP_10000FDX_LBN 7 3032#define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 3033#define MC_CMD_PHY_CAP_PAUSE_LBN 8 3034#define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 3035#define MC_CMD_PHY_CAP_ASYM_LBN 9 3036#define MC_CMD_PHY_CAP_ASYM_WIDTH 1 3037#define MC_CMD_PHY_CAP_AN_LBN 10 3038#define MC_CMD_PHY_CAP_AN_WIDTH 1 3039#define MC_CMD_PHY_CAP_40000FDX_LBN 11 3040#define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 3041#define MC_CMD_PHY_CAP_DDM_LBN 12 3042#define MC_CMD_PHY_CAP_DDM_WIDTH 1 3043#define MC_CMD_PHY_CAP_100000FDX_LBN 13 3044#define MC_CMD_PHY_CAP_100000FDX_WIDTH 1 3045#define MC_CMD_PHY_CAP_25000FDX_LBN 14 3046#define MC_CMD_PHY_CAP_25000FDX_WIDTH 1 3047#define MC_CMD_PHY_CAP_50000FDX_LBN 15 3048#define MC_CMD_PHY_CAP_50000FDX_WIDTH 1 3049#define MC_CMD_PHY_CAP_BASER_FEC_LBN 16 3050#define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1 3051#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17 3052#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1 3053#define MC_CMD_PHY_CAP_RS_FEC_LBN 18 3054#define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1 3055#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19 3056#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1 3057#define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20 3058#define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1 3059#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21 3060#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1 3061/* ?? */ 3062#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 3063#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4 3064/* ?? */ 3065#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 3066#define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4 3067/* ?? */ 3068#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 3069#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4 3070/* ?? */ 3071#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 3072#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 3073/* ?? */ 3074#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 3075#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4 3076/* enum: Xaui. */ 3077#define MC_CMD_MEDIA_XAUI 0x1 3078/* enum: CX4. */ 3079#define MC_CMD_MEDIA_CX4 0x2 3080/* enum: KX4. */ 3081#define MC_CMD_MEDIA_KX4 0x3 3082/* enum: XFP Far. */ 3083#define MC_CMD_MEDIA_XFP 0x4 3084/* enum: SFP+. */ 3085#define MC_CMD_MEDIA_SFP_PLUS 0x5 3086/* enum: 10GBaseT. */ 3087#define MC_CMD_MEDIA_BASE_T 0x6 3088/* enum: QSFP+. */ 3089#define MC_CMD_MEDIA_QSFP_PLUS 0x7 3090#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 3091#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4 3092/* enum: Native clause 22 */ 3093#define MC_CMD_MMD_CLAUSE22 0x0 3094#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 3095#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 3096#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 3097#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 3098#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 3099#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 3100#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 3101/* enum: Clause22 proxied over clause45 by PHY. */ 3102#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 3103#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 3104#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 3105#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 3106#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 3107 3108/***********************************/ 3109/* MC_CMD_START_BIST 3110 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 3111 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 3112 */ 3113#define MC_CMD_START_BIST 0x25 3114#undef MC_CMD_0x25_PRIVILEGE_CTG 3115 3116#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 3117 3118/* MC_CMD_START_BIST_IN msgrequest */ 3119#define MC_CMD_START_BIST_IN_LEN 4 3120/* Type of test. */ 3121#define MC_CMD_START_BIST_IN_TYPE_OFST 0 3122#define MC_CMD_START_BIST_IN_TYPE_LEN 4 3123/* enum: Run the PHY's short cable BIST. */ 3124#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 3125/* enum: Run the PHY's long cable BIST. */ 3126#define MC_CMD_PHY_BIST_CABLE_LONG 0x2 3127/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 3128#define MC_CMD_BPX_SERDES_BIST 0x3 3129/* enum: Run the MC loopback tests. */ 3130#define MC_CMD_MC_LOOPBACK_BIST 0x4 3131/* enum: Run the PHY's standard BIST. */ 3132#define MC_CMD_PHY_BIST 0x5 3133/* enum: Run MC RAM test. */ 3134#define MC_CMD_MC_MEM_BIST 0x6 3135/* enum: Run Port RAM test. */ 3136#define MC_CMD_PORT_MEM_BIST 0x7 3137/* enum: Run register test. */ 3138#define MC_CMD_REG_BIST 0x8 3139 3140/* MC_CMD_START_BIST_OUT msgresponse */ 3141#define MC_CMD_START_BIST_OUT_LEN 0 3142 3143/***********************************/ 3144/* MC_CMD_POLL_BIST 3145 * Poll for BIST completion. Returns a single status code, and optionally some 3146 * PHY specific bist output. The driver should only consume the BIST output 3147 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 3148 * successfully parse the BIST output, it should still respect the pass/Fail in 3149 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 3150 * EACCES (if PHY_LOCK is not held). 3151 */ 3152#define MC_CMD_POLL_BIST 0x26 3153#undef MC_CMD_0x26_PRIVILEGE_CTG 3154 3155#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 3156 3157/* MC_CMD_POLL_BIST_IN msgrequest */ 3158#define MC_CMD_POLL_BIST_IN_LEN 0 3159 3160/* MC_CMD_POLL_BIST_OUT msgresponse */ 3161#define MC_CMD_POLL_BIST_OUT_LEN 8 3162/* result */ 3163#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 3164#define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 3165/* enum: Running. */ 3166#define MC_CMD_POLL_BIST_RUNNING 0x1 3167/* enum: Passed. */ 3168#define MC_CMD_POLL_BIST_PASSED 0x2 3169/* enum: Failed. */ 3170#define MC_CMD_POLL_BIST_FAILED 0x3 3171/* enum: Timed-out. */ 3172#define MC_CMD_POLL_BIST_TIMEOUT 0x4 3173#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 3174#define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4 3175 3176/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 3177#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 3178/* result */ 3179/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3180/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3181/* Enum values, see field(s): */ 3182/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3183#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 3184#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4 3185#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 3186#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4 3187#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 3188#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4 3189#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 3190#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4 3191/* Status of each channel A */ 3192#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 3193#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4 3194/* enum: Ok. */ 3195#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 3196/* enum: Open. */ 3197#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 3198/* enum: Intra-pair short. */ 3199#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 3200/* enum: Inter-pair short. */ 3201#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 3202/* enum: Busy. */ 3203#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 3204/* Status of each channel B */ 3205#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 3206#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4 3207/* Enum values, see field(s): */ 3208/* CABLE_STATUS_A */ 3209/* Status of each channel C */ 3210#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 3211#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4 3212/* Enum values, see field(s): */ 3213/* CABLE_STATUS_A */ 3214/* Status of each channel D */ 3215#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 3216#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4 3217/* Enum values, see field(s): */ 3218/* CABLE_STATUS_A */ 3219 3220/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 3221#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 3222/* result */ 3223/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3224/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3225/* Enum values, see field(s): */ 3226/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3227#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 3228#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4 3229/* enum: Complete. */ 3230#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 3231/* enum: Bus switch off I2C write. */ 3232#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 3233/* enum: Bus switch off I2C no access IO exp. */ 3234#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 3235/* enum: Bus switch off I2C no access module. */ 3236#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 3237/* enum: IO exp I2C configure. */ 3238#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 3239/* enum: Bus switch I2C no cross talk. */ 3240#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 3241/* enum: Module presence. */ 3242#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 3243/* enum: Module ID I2C access. */ 3244#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 3245/* enum: Module ID sane value. */ 3246#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 3247 3248/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 3249#define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 3250/* result */ 3251/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3252/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3253/* Enum values, see field(s): */ 3254/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3255#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 3256#define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4 3257/* enum: Test has completed. */ 3258#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 3259/* enum: RAM test - walk ones. */ 3260#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 3261/* enum: RAM test - walk zeros. */ 3262#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 3263/* enum: RAM test - walking inversions zeros/ones. */ 3264#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 3265/* enum: RAM test - walking inversions checkerboard. */ 3266#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 3267/* enum: Register test - set / clear individual bits. */ 3268#define MC_CMD_POLL_BIST_MEM_REG 0x5 3269/* enum: ECC error detected. */ 3270#define MC_CMD_POLL_BIST_MEM_ECC 0x6 3271/* Failure address, only valid if result is POLL_BIST_FAILED */ 3272#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 3273#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4 3274/* Bus or address space to which the failure address corresponds */ 3275#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 3276#define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4 3277/* enum: MC MIPS bus. */ 3278#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 3279/* enum: CSR IREG bus. */ 3280#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 3281/* enum: RX0 DPCPU bus. */ 3282#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 3283/* enum: TX0 DPCPU bus. */ 3284#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 3285/* enum: TX1 DPCPU bus. */ 3286#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 3287/* enum: RX0 DICPU bus. */ 3288#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 3289/* enum: TX DICPU bus. */ 3290#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 3291/* enum: RX1 DPCPU bus. */ 3292#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 3293/* enum: RX1 DICPU bus. */ 3294#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 3295/* Pattern written to RAM / register */ 3296#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 3297#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4 3298/* Actual value read from RAM / register */ 3299#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 3300#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4 3301/* ECC error mask */ 3302#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 3303#define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4 3304/* ECC parity error mask */ 3305#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 3306#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4 3307/* ECC fatal error mask */ 3308#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 3309#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4 3310 3311/***********************************/ 3312/* MC_CMD_FLUSH_RX_QUEUES 3313 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 3314 * flushes should be initiated via this MCDI operation, rather than via 3315 * directly writing FLUSH_CMD. 3316 * 3317 * The flush is completed (either done/fail) asynchronously (after this command 3318 * returns). The driver must still wait for flush done/failure events as usual. 3319 */ 3320#define MC_CMD_FLUSH_RX_QUEUES 0x27 3321 3322/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 3323#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 3324#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 3325#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 3326#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 3327#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 3328#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 3329#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 3330 3331/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 3332#define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 3333 3334/***********************************/ 3335/* MC_CMD_GET_LOOPBACK_MODES 3336 * Returns a bitmask of loopback modes available at each speed. 3337 */ 3338#define MC_CMD_GET_LOOPBACK_MODES 0x28 3339#undef MC_CMD_0x28_PRIVILEGE_CTG 3340 3341#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3342 3343/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 3344#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 3345 3346/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 3347#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 3348/* Supported loopbacks. */ 3349#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 3350#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 3351#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 3352#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 3353/* enum: None. */ 3354#define MC_CMD_LOOPBACK_NONE 0x0 3355/* enum: Data. */ 3356#define MC_CMD_LOOPBACK_DATA 0x1 3357/* enum: GMAC. */ 3358#define MC_CMD_LOOPBACK_GMAC 0x2 3359/* enum: XGMII. */ 3360#define MC_CMD_LOOPBACK_XGMII 0x3 3361/* enum: XGXS. */ 3362#define MC_CMD_LOOPBACK_XGXS 0x4 3363/* enum: XAUI. */ 3364#define MC_CMD_LOOPBACK_XAUI 0x5 3365/* enum: GMII. */ 3366#define MC_CMD_LOOPBACK_GMII 0x6 3367/* enum: SGMII. */ 3368#define MC_CMD_LOOPBACK_SGMII 0x7 3369/* enum: XGBR. */ 3370#define MC_CMD_LOOPBACK_XGBR 0x8 3371/* enum: XFI. */ 3372#define MC_CMD_LOOPBACK_XFI 0x9 3373/* enum: XAUI Far. */ 3374#define MC_CMD_LOOPBACK_XAUI_FAR 0xa 3375/* enum: GMII Far. */ 3376#define MC_CMD_LOOPBACK_GMII_FAR 0xb 3377/* enum: SGMII Far. */ 3378#define MC_CMD_LOOPBACK_SGMII_FAR 0xc 3379/* enum: XFI Far. */ 3380#define MC_CMD_LOOPBACK_XFI_FAR 0xd 3381/* enum: GPhy. */ 3382#define MC_CMD_LOOPBACK_GPHY 0xe 3383/* enum: PhyXS. */ 3384#define MC_CMD_LOOPBACK_PHYXS 0xf 3385/* enum: PCS. */ 3386#define MC_CMD_LOOPBACK_PCS 0x10 3387/* enum: PMA-PMD. */ 3388#define MC_CMD_LOOPBACK_PMAPMD 0x11 3389/* enum: Cross-Port. */ 3390#define MC_CMD_LOOPBACK_XPORT 0x12 3391/* enum: XGMII-Wireside. */ 3392#define MC_CMD_LOOPBACK_XGMII_WS 0x13 3393/* enum: XAUI Wireside. */ 3394#define MC_CMD_LOOPBACK_XAUI_WS 0x14 3395/* enum: XAUI Wireside Far. */ 3396#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 3397/* enum: XAUI Wireside near. */ 3398#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 3399/* enum: GMII Wireside. */ 3400#define MC_CMD_LOOPBACK_GMII_WS 0x17 3401/* enum: XFI Wireside. */ 3402#define MC_CMD_LOOPBACK_XFI_WS 0x18 3403/* enum: XFI Wireside Far. */ 3404#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 3405/* enum: PhyXS Wireside. */ 3406#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 3407/* enum: PMA lanes MAC-Serdes. */ 3408#define MC_CMD_LOOPBACK_PMA_INT 0x1b 3409/* enum: KR Serdes Parallel (Encoder). */ 3410#define MC_CMD_LOOPBACK_SD_NEAR 0x1c 3411/* enum: KR Serdes Serial. */ 3412#define MC_CMD_LOOPBACK_SD_FAR 0x1d 3413/* enum: PMA lanes MAC-Serdes Wireside. */ 3414#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 3415/* enum: KR Serdes Parallel Wireside (Full PCS). */ 3416#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 3417/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3418#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 3419/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3420#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 3421/* enum: KR Serdes Serial Wireside. */ 3422#define MC_CMD_LOOPBACK_SD_FES_WS 0x22 3423/* enum: Near side of AOE Siena side port */ 3424#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 3425/* enum: Medford Wireside datapath loopback */ 3426#define MC_CMD_LOOPBACK_DATA_WS 0x24 3427/* enum: Force link up without setting up any physical loopback (snapper use 3428 * only) 3429 */ 3430#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 3431/* Supported loopbacks. */ 3432#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 3433#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 3434#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 3435#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 3436/* Enum values, see field(s): */ 3437/* 100M */ 3438/* Supported loopbacks. */ 3439#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 3440#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 3441#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 3442#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 3443/* Enum values, see field(s): */ 3444/* 100M */ 3445/* Supported loopbacks. */ 3446#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 3447#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 3448#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 3449#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 3450/* Enum values, see field(s): */ 3451/* 100M */ 3452/* Supported loopbacks. */ 3453#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 3454#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 3455#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 3456#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 3457/* Enum values, see field(s): */ 3458/* 100M */ 3459 3460/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for 3461 * newer NICs with 25G/50G/100G support 3462 */ 3463#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64 3464/* Supported loopbacks. */ 3465#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0 3466#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8 3467#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0 3468#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4 3469/* enum: None. */ 3470/* MC_CMD_LOOPBACK_NONE 0x0 */ 3471/* enum: Data. */ 3472/* MC_CMD_LOOPBACK_DATA 0x1 */ 3473/* enum: GMAC. */ 3474/* MC_CMD_LOOPBACK_GMAC 0x2 */ 3475/* enum: XGMII. */ 3476/* MC_CMD_LOOPBACK_XGMII 0x3 */ 3477/* enum: XGXS. */ 3478/* MC_CMD_LOOPBACK_XGXS 0x4 */ 3479/* enum: XAUI. */ 3480/* MC_CMD_LOOPBACK_XAUI 0x5 */ 3481/* enum: GMII. */ 3482/* MC_CMD_LOOPBACK_GMII 0x6 */ 3483/* enum: SGMII. */ 3484/* MC_CMD_LOOPBACK_SGMII 0x7 */ 3485/* enum: XGBR. */ 3486/* MC_CMD_LOOPBACK_XGBR 0x8 */ 3487/* enum: XFI. */ 3488/* MC_CMD_LOOPBACK_XFI 0x9 */ 3489/* enum: XAUI Far. */ 3490/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */ 3491/* enum: GMII Far. */ 3492/* MC_CMD_LOOPBACK_GMII_FAR 0xb */ 3493/* enum: SGMII Far. */ 3494/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */ 3495/* enum: XFI Far. */ 3496/* MC_CMD_LOOPBACK_XFI_FAR 0xd */ 3497/* enum: GPhy. */ 3498/* MC_CMD_LOOPBACK_GPHY 0xe */ 3499/* enum: PhyXS. */ 3500/* MC_CMD_LOOPBACK_PHYXS 0xf */ 3501/* enum: PCS. */ 3502/* MC_CMD_LOOPBACK_PCS 0x10 */ 3503/* enum: PMA-PMD. */ 3504/* MC_CMD_LOOPBACK_PMAPMD 0x11 */ 3505/* enum: Cross-Port. */ 3506/* MC_CMD_LOOPBACK_XPORT 0x12 */ 3507/* enum: XGMII-Wireside. */ 3508/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */ 3509/* enum: XAUI Wireside. */ 3510/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */ 3511/* enum: XAUI Wireside Far. */ 3512/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */ 3513/* enum: XAUI Wireside near. */ 3514/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */ 3515/* enum: GMII Wireside. */ 3516/* MC_CMD_LOOPBACK_GMII_WS 0x17 */ 3517/* enum: XFI Wireside. */ 3518/* MC_CMD_LOOPBACK_XFI_WS 0x18 */ 3519/* enum: XFI Wireside Far. */ 3520/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */ 3521/* enum: PhyXS Wireside. */ 3522/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */ 3523/* enum: PMA lanes MAC-Serdes. */ 3524/* MC_CMD_LOOPBACK_PMA_INT 0x1b */ 3525/* enum: KR Serdes Parallel (Encoder). */ 3526/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */ 3527/* enum: KR Serdes Serial. */ 3528/* MC_CMD_LOOPBACK_SD_FAR 0x1d */ 3529/* enum: PMA lanes MAC-Serdes Wireside. */ 3530/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */ 3531/* enum: KR Serdes Parallel Wireside (Full PCS). */ 3532/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */ 3533/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3534/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */ 3535/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3536/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */ 3537/* enum: KR Serdes Serial Wireside. */ 3538/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */ 3539/* enum: Near side of AOE Siena side port */ 3540/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */ 3541/* enum: Medford Wireside datapath loopback */ 3542/* MC_CMD_LOOPBACK_DATA_WS 0x24 */ 3543/* enum: Force link up without setting up any physical loopback (snapper use 3544 * only) 3545 */ 3546/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */ 3547/* Supported loopbacks. */ 3548#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8 3549#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8 3550#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8 3551#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12 3552/* Enum values, see field(s): */ 3553/* 100M */ 3554/* Supported loopbacks. */ 3555#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16 3556#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8 3557#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16 3558#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20 3559/* Enum values, see field(s): */ 3560/* 100M */ 3561/* Supported loopbacks. */ 3562#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24 3563#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8 3564#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24 3565#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28 3566/* Enum values, see field(s): */ 3567/* 100M */ 3568/* Supported loopbacks. */ 3569#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32 3570#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8 3571#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32 3572#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36 3573/* Enum values, see field(s): */ 3574/* 100M */ 3575/* Supported 25G loopbacks. */ 3576#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40 3577#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8 3578#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40 3579#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44 3580/* Enum values, see field(s): */ 3581/* 100M */ 3582/* Supported 50 loopbacks. */ 3583#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48 3584#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8 3585#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48 3586#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52 3587/* Enum values, see field(s): */ 3588/* 100M */ 3589/* Supported 100G loopbacks. */ 3590#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56 3591#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8 3592#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56 3593#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60 3594/* Enum values, see field(s): */ 3595/* 100M */ 3596 3597/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */ 3598#define AN_TYPE_LEN 4 3599#define AN_TYPE_TYPE_OFST 0 3600#define AN_TYPE_TYPE_LEN 4 3601/* enum: None, AN disabled or not supported */ 3602#define MC_CMD_AN_NONE 0x0 3603/* enum: Clause 28 - BASE-T */ 3604#define MC_CMD_AN_CLAUSE28 0x1 3605/* enum: Clause 37 - BASE-X */ 3606#define MC_CMD_AN_CLAUSE37 0x2 3607/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable 3608 * assemblies. Includes Clause 72/Clause 92 link-training. 3609 */ 3610#define MC_CMD_AN_CLAUSE73 0x3 3611#define AN_TYPE_TYPE_LBN 0 3612#define AN_TYPE_TYPE_WIDTH 32 3613 3614/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3 3615 */ 3616#define FEC_TYPE_LEN 4 3617#define FEC_TYPE_TYPE_OFST 0 3618#define FEC_TYPE_TYPE_LEN 4 3619/* enum: No FEC */ 3620#define MC_CMD_FEC_NONE 0x0 3621/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */ 3622#define MC_CMD_FEC_BASER 0x1 3623/* enum: Clause 91/Clause 108 Reed-Solomon FEC */ 3624#define MC_CMD_FEC_RS 0x2 3625#define FEC_TYPE_TYPE_LBN 0 3626#define FEC_TYPE_TYPE_WIDTH 32 3627 3628/***********************************/ 3629/* MC_CMD_GET_LINK 3630 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 3631 * ETIME. 3632 */ 3633#define MC_CMD_GET_LINK 0x29 3634#undef MC_CMD_0x29_PRIVILEGE_CTG 3635 3636#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3637 3638/* MC_CMD_GET_LINK_IN msgrequest */ 3639#define MC_CMD_GET_LINK_IN_LEN 0 3640 3641/* MC_CMD_GET_LINK_OUT msgresponse */ 3642#define MC_CMD_GET_LINK_OUT_LEN 28 3643/* Near-side advertised capabilities. Refer to 3644 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3645 */ 3646#define MC_CMD_GET_LINK_OUT_CAP_OFST 0 3647#define MC_CMD_GET_LINK_OUT_CAP_LEN 4 3648/* Link-partner advertised capabilities. Refer to 3649 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3650 */ 3651#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 3652#define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4 3653/* Autonegotiated speed in mbit/s. The link may still be down even if this 3654 * reads non-zero. 3655 */ 3656#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 3657#define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4 3658/* Current loopback setting. */ 3659#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 3660#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4 3661/* Enum values, see field(s): */ 3662/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3663#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 3664#define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4 3665#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 3666#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 3667#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 3668#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 3669#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 3670#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 3671#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 3672#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 3673#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 3674#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 3675#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 3676#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 3677/* This returns the negotiated flow control value. */ 3678#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 3679#define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4 3680/* Enum values, see field(s): */ 3681/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 3682#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 3683#define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4 3684#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 3685#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 3686#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 3687#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 3688#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 3689#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 3690#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 3691#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 3692 3693/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */ 3694#define MC_CMD_GET_LINK_OUT_V2_LEN 44 3695/* Near-side advertised capabilities. Refer to 3696 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3697 */ 3698#define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0 3699#define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4 3700/* Link-partner advertised capabilities. Refer to 3701 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3702 */ 3703#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4 3704#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4 3705/* Autonegotiated speed in mbit/s. The link may still be down even if this 3706 * reads non-zero. 3707 */ 3708#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8 3709#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4 3710/* Current loopback setting. */ 3711#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12 3712#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4 3713/* Enum values, see field(s): */ 3714/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3715#define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16 3716#define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4 3717#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0 3718#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1 3719#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1 3720#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1 3721#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2 3722#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1 3723#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3 3724#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1 3725#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6 3726#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1 3727#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7 3728#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1 3729/* This returns the negotiated flow control value. */ 3730#define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20 3731#define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4 3732/* Enum values, see field(s): */ 3733/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 3734#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24 3735#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4 3736/* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */ 3737/* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */ 3738/* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */ 3739/* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */ 3740/* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */ 3741/* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */ 3742/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */ 3743/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */ 3744/* True local device capabilities (taking into account currently used PMD/MDI, 3745 * e.g. plugged-in module). In general, subset of 3746 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST 3747 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal 3748 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to 3749 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3750 */ 3751#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28 3752#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4 3753/* Auto-negotiation type used on the link */ 3754#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32 3755#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4 3756/* Enum values, see field(s): */ 3757/* AN_TYPE/TYPE */ 3758/* Forward error correction used on the link */ 3759#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36 3760#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4 3761/* Enum values, see field(s): */ 3762/* FEC_TYPE/TYPE */ 3763#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40 3764#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4 3765#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0 3766#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1 3767#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1 3768#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1 3769#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2 3770#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1 3771#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3 3772#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1 3773#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4 3774#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1 3775#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5 3776#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1 3777#define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6 3778#define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1 3779#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7 3780#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1 3781#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8 3782#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1 3783 3784/***********************************/ 3785/* MC_CMD_SET_LINK 3786 * Write the unified MAC/PHY link configuration. Locks required: None. Return 3787 * code: 0, EINVAL, ETIME 3788 */ 3789#define MC_CMD_SET_LINK 0x2a 3790#undef MC_CMD_0x2a_PRIVILEGE_CTG 3791 3792#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 3793 3794/* MC_CMD_SET_LINK_IN msgrequest */ 3795#define MC_CMD_SET_LINK_IN_LEN 16 3796/* Near-side advertised capabilities. Refer to 3797 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3798 */ 3799#define MC_CMD_SET_LINK_IN_CAP_OFST 0 3800#define MC_CMD_SET_LINK_IN_CAP_LEN 4 3801/* Flags */ 3802#define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 3803#define MC_CMD_SET_LINK_IN_FLAGS_LEN 4 3804#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 3805#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 3806#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 3807#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 3808#define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 3809#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 3810/* Loopback mode. */ 3811#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 3812#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4 3813/* Enum values, see field(s): */ 3814/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3815/* A loopback speed of "0" is supported, and means (choose any available 3816 * speed). 3817 */ 3818#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 3819#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4 3820 3821/* MC_CMD_SET_LINK_OUT msgresponse */ 3822#define MC_CMD_SET_LINK_OUT_LEN 0 3823 3824/***********************************/ 3825/* MC_CMD_SET_ID_LED 3826 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 3827 */ 3828#define MC_CMD_SET_ID_LED 0x2b 3829#undef MC_CMD_0x2b_PRIVILEGE_CTG 3830 3831#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 3832 3833/* MC_CMD_SET_ID_LED_IN msgrequest */ 3834#define MC_CMD_SET_ID_LED_IN_LEN 4 3835/* Set LED state. */ 3836#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 3837#define MC_CMD_SET_ID_LED_IN_STATE_LEN 4 3838#define MC_CMD_LED_OFF 0x0 /* enum */ 3839#define MC_CMD_LED_ON 0x1 /* enum */ 3840#define MC_CMD_LED_DEFAULT 0x2 /* enum */ 3841 3842/* MC_CMD_SET_ID_LED_OUT msgresponse */ 3843#define MC_CMD_SET_ID_LED_OUT_LEN 0 3844 3845/***********************************/ 3846/* MC_CMD_SET_MAC 3847 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 3848 */ 3849#define MC_CMD_SET_MAC 0x2c 3850#undef MC_CMD_0x2c_PRIVILEGE_CTG 3851 3852#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3853 3854/* MC_CMD_SET_MAC_IN msgrequest */ 3855#define MC_CMD_SET_MAC_IN_LEN 28 3856/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3857 * EtherII, VLAN, bug16011 padding). 3858 */ 3859#define MC_CMD_SET_MAC_IN_MTU_OFST 0 3860#define MC_CMD_SET_MAC_IN_MTU_LEN 4 3861#define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 3862#define MC_CMD_SET_MAC_IN_DRAIN_LEN 4 3863#define MC_CMD_SET_MAC_IN_ADDR_OFST 8 3864#define MC_CMD_SET_MAC_IN_ADDR_LEN 8 3865#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 3866#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 3867#define MC_CMD_SET_MAC_IN_REJECT_OFST 16 3868#define MC_CMD_SET_MAC_IN_REJECT_LEN 4 3869#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 3870#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 3871#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 3872#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 3873#define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 3874#define MC_CMD_SET_MAC_IN_FCNTL_LEN 4 3875/* enum: Flow control is off. */ 3876#define MC_CMD_FCNTL_OFF 0x0 3877/* enum: Respond to flow control. */ 3878#define MC_CMD_FCNTL_RESPOND 0x1 3879/* enum: Respond to and Issue flow control. */ 3880#define MC_CMD_FCNTL_BIDIR 0x2 3881/* enum: Auto neg flow control. */ 3882#define MC_CMD_FCNTL_AUTO 0x3 3883/* enum: Priority flow control (eftest builds only). */ 3884#define MC_CMD_FCNTL_QBB 0x4 3885/* enum: Issue flow control. */ 3886#define MC_CMD_FCNTL_GENERATE 0x5 3887#define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 3888#define MC_CMD_SET_MAC_IN_FLAGS_LEN 4 3889#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 3890#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 3891 3892/* MC_CMD_SET_MAC_EXT_IN msgrequest */ 3893#define MC_CMD_SET_MAC_EXT_IN_LEN 32 3894/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3895 * EtherII, VLAN, bug16011 padding). 3896 */ 3897#define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 3898#define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4 3899#define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 3900#define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4 3901#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 3902#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 3903#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 3904#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 3905#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 3906#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4 3907#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 3908#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 3909#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 3910#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 3911#define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 3912#define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4 3913/* enum: Flow control is off. */ 3914/* MC_CMD_FCNTL_OFF 0x0 */ 3915/* enum: Respond to flow control. */ 3916/* MC_CMD_FCNTL_RESPOND 0x1 */ 3917/* enum: Respond to and Issue flow control. */ 3918/* MC_CMD_FCNTL_BIDIR 0x2 */ 3919/* enum: Auto neg flow control. */ 3920/* MC_CMD_FCNTL_AUTO 0x3 */ 3921/* enum: Priority flow control (eftest builds only). */ 3922/* MC_CMD_FCNTL_QBB 0x4 */ 3923/* enum: Issue flow control. */ 3924/* MC_CMD_FCNTL_GENERATE 0x5 */ 3925#define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 3926#define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4 3927#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 3928#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 3929/* Select which parameters to configure. A parameter will only be modified if 3930 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 3931 * capabilities then this field is ignored (and all flags are assumed to be 3932 * set). 3933 */ 3934#define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 3935#define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4 3936#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 3937#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 3938#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 3939#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 3940#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 3941#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 3942#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 3943#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 3944#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 3945#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 3946 3947/* MC_CMD_SET_MAC_OUT msgresponse */ 3948#define MC_CMD_SET_MAC_OUT_LEN 0 3949 3950/* MC_CMD_SET_MAC_V2_OUT msgresponse */ 3951#define MC_CMD_SET_MAC_V2_OUT_LEN 4 3952/* MTU as configured after processing the request. See comment at 3953 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 3954 * to 0. 3955 */ 3956#define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 3957#define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4 3958 3959/***********************************/ 3960/* MC_CMD_PHY_STATS 3961 * Get generic PHY statistics. This call returns the statistics for a generic 3962 * PHY in a sparse array (indexed by the enumerate). Each value is represented 3963 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 3964 * statistics may be read from the message response. If DMA_ADDR != 0, then the 3965 * statistics are dmad to that (page-aligned location). Locks required: None. 3966 * Returns: 0, ETIME 3967 */ 3968#define MC_CMD_PHY_STATS 0x2d 3969#undef MC_CMD_0x2d_PRIVILEGE_CTG 3970 3971#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 3972 3973/* MC_CMD_PHY_STATS_IN msgrequest */ 3974#define MC_CMD_PHY_STATS_IN_LEN 8 3975/* ??? */ 3976#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 3977#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 3978#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 3979#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 3980 3981/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 3982#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 3983 3984/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 3985#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 3986#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3987#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 3988#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 3989/* enum: OUI. */ 3990#define MC_CMD_OUI 0x0 3991/* enum: PMA-PMD Link Up. */ 3992#define MC_CMD_PMA_PMD_LINK_UP 0x1 3993/* enum: PMA-PMD RX Fault. */ 3994#define MC_CMD_PMA_PMD_RX_FAULT 0x2 3995/* enum: PMA-PMD TX Fault. */ 3996#define MC_CMD_PMA_PMD_TX_FAULT 0x3 3997/* enum: PMA-PMD Signal */ 3998#define MC_CMD_PMA_PMD_SIGNAL 0x4 3999/* enum: PMA-PMD SNR A. */ 4000#define MC_CMD_PMA_PMD_SNR_A 0x5 4001/* enum: PMA-PMD SNR B. */ 4002#define MC_CMD_PMA_PMD_SNR_B 0x6 4003/* enum: PMA-PMD SNR C. */ 4004#define MC_CMD_PMA_PMD_SNR_C 0x7 4005/* enum: PMA-PMD SNR D. */ 4006#define MC_CMD_PMA_PMD_SNR_D 0x8 4007/* enum: PCS Link Up. */ 4008#define MC_CMD_PCS_LINK_UP 0x9 4009/* enum: PCS RX Fault. */ 4010#define MC_CMD_PCS_RX_FAULT 0xa 4011/* enum: PCS TX Fault. */ 4012#define MC_CMD_PCS_TX_FAULT 0xb 4013/* enum: PCS BER. */ 4014#define MC_CMD_PCS_BER 0xc 4015/* enum: PCS Block Errors. */ 4016#define MC_CMD_PCS_BLOCK_ERRORS 0xd 4017/* enum: PhyXS Link Up. */ 4018#define MC_CMD_PHYXS_LINK_UP 0xe 4019/* enum: PhyXS RX Fault. */ 4020#define MC_CMD_PHYXS_RX_FAULT 0xf 4021/* enum: PhyXS TX Fault. */ 4022#define MC_CMD_PHYXS_TX_FAULT 0x10 4023/* enum: PhyXS Align. */ 4024#define MC_CMD_PHYXS_ALIGN 0x11 4025/* enum: PhyXS Sync. */ 4026#define MC_CMD_PHYXS_SYNC 0x12 4027/* enum: AN link-up. */ 4028#define MC_CMD_AN_LINK_UP 0x13 4029/* enum: AN Complete. */ 4030#define MC_CMD_AN_COMPLETE 0x14 4031/* enum: AN 10GBaseT Status. */ 4032#define MC_CMD_AN_10GBT_STATUS 0x15 4033/* enum: Clause 22 Link-Up. */ 4034#define MC_CMD_CL22_LINK_UP 0x16 4035/* enum: (Last entry) */ 4036#define MC_CMD_PHY_NSTATS 0x17 4037 4038/***********************************/ 4039/* MC_CMD_MAC_STATS 4040 * Get generic MAC statistics. This call returns unified statistics maintained 4041 * by the MC as it switches between the GMAC and XMAC. The MC will write out 4042 * all supported stats. The driver should zero initialise the buffer to 4043 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 4044 * performed, and the statistics may be read from the message response. If 4045 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 4046 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 4047 * effect. Returns: 0, ETIME 4048 */ 4049#define MC_CMD_MAC_STATS 0x2e 4050#undef MC_CMD_0x2e_PRIVILEGE_CTG 4051 4052#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4053 4054/* MC_CMD_MAC_STATS_IN msgrequest */ 4055#define MC_CMD_MAC_STATS_IN_LEN 20 4056/* ??? */ 4057#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 4058#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 4059#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 4060#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 4061#define MC_CMD_MAC_STATS_IN_CMD_OFST 8 4062#define MC_CMD_MAC_STATS_IN_CMD_LEN 4 4063#define MC_CMD_MAC_STATS_IN_DMA_LBN 0 4064#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 4065#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 4066#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 4067#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 4068#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 4069#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 4070#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 4071#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 4072#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 4073#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 4074#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 4075#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 4076#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 4077/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as 4078 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not 4079 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to 4080 * MC_CMD_MAC_NSTATS * sizeof(uint64_t) 4081 */ 4082#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 4083#define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4 4084/* port id so vadapter stats can be provided */ 4085#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 4086#define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4 4087 4088/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 4089#define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 4090 4091/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 4092#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 4093#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 4094#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 4095#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 4096#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 4097#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 4098#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 4099#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 4100#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 4101#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 4102#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 4103#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 4104#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 4105#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 4106#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 4107#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 4108#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 4109#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 4110#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 4111#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 4112#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 4113#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 4114#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 4115#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 4116#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 4117#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 4118#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 4119#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 4120#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 4121#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 4122#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 4123#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 4124#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 4125#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 4126#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 4127#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 4128#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 4129#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 4130#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 4131#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 4132#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 4133#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 4134#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 4135#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 4136#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 4137#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 4138#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 4139#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 4140#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 4141#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 4142#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 4143#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 4144#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 4145#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 4146#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 4147#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 4148#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 4149#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 4150#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 4151#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 4152#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 4153#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 4154#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 4155#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 4156#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 4157#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 4158#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 4159/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4160 * capability only. 4161 */ 4162#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 4163/* enum: PM discard_bb_overflow counter. Valid for EF10 with 4164 * PM_AND_RXDP_COUNTERS capability only. 4165 */ 4166#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 4167/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4168 * capability only. 4169 */ 4170#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 4171/* enum: PM discard_vfifo_full counter. Valid for EF10 with 4172 * PM_AND_RXDP_COUNTERS capability only. 4173 */ 4174#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 4175/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4176 * capability only. 4177 */ 4178#define MC_CMD_MAC_PM_TRUNC_QBB 0x40 4179/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4180 * capability only. 4181 */ 4182#define MC_CMD_MAC_PM_DISCARD_QBB 0x41 4183/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4184 * capability only. 4185 */ 4186#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 4187/* enum: RXDP counter: Number of packets dropped due to the queue being 4188 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4189 */ 4190#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 4191/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 4192 * with PM_AND_RXDP_COUNTERS capability only. 4193 */ 4194#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 4195/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 4196 * PM_AND_RXDP_COUNTERS capability only. 4197 */ 4198#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 4199/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 4200 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4201 */ 4202#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 4203/* enum: RXDP counter: Number of times the DPCPU waited for an existing 4204 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4205 */ 4206#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 4207#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 4208#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 4209#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 4210#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 4211#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 4212#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 4213#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 4214#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 4215#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 4216#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 4217#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 4218#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 4219#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 4220#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 4221#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 4222#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 4223#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 4224#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 4225#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 4226#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 4227/* enum: Start of GMAC stats buffer space, for Siena only. */ 4228#define MC_CMD_GMAC_DMABUF_START 0x40 4229/* enum: End of GMAC stats buffer space, for Siena only. */ 4230#define MC_CMD_GMAC_DMABUF_END 0x5f 4231/* enum: GENERATION_END value, used together with GENERATION_START to verify 4232 * consistency of DMAd data. For legacy firmware / drivers without extended 4233 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS * 4234 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise, 4235 * this value is invalid/ reserved and GENERATION_END is written as the last 4236 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that 4237 * this is consistent with the legacy behaviour, in the sense that entry 96 is 4238 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS * 4239 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details. 4240 */ 4241#define MC_CMD_MAC_GENERATION_END 0x60 4242#define MC_CMD_MAC_NSTATS 0x61 /* enum */ 4243 4244/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */ 4245#define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0 4246 4247/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */ 4248#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3) 4249#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0 4250#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8 4251#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0 4252#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4 4253#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2 4254/* enum: Start of FEC stats buffer space, Medford2 and up */ 4255#define MC_CMD_MAC_FEC_DMABUF_START 0x61 4256/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2) 4257 */ 4258#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61 4259/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2) 4260 */ 4261#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62 4262/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */ 4263#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63 4264/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */ 4265#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64 4266/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */ 4267#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65 4268/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */ 4269#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66 4270/* enum: This includes the space at offset 103 which is the final 4271 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused. 4272 */ 4273#define MC_CMD_MAC_NSTATS_V2 0x68 4274/* Other enum values, see field(s): */ 4275/* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */ 4276 4277/* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */ 4278#define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0 4279 4280/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */ 4281#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3) 4282#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0 4283#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8 4284#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0 4285#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4 4286#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3 4287/* enum: Start of CTPIO stats buffer space, Medford2 and up */ 4288#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68 4289/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the 4290 * target VI 4291 */ 4292#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68 4293/* enum: Number of times a CTPIO send wrote beyond frame end (informational 4294 * only) 4295 */ 4296#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69 4297/* enum: Number of CTPIO failures because the TX doorbell was written before 4298 * the end of the frame data 4299 */ 4300#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a 4301/* enum: Number of CTPIO failures because the internal FIFO overflowed */ 4302#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b 4303/* enum: Number of CTPIO failures because the host did not deliver data fast 4304 * enough to avoid MAC underflow 4305 */ 4306#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c 4307/* enum: Number of CTPIO failures because the host did not deliver all the 4308 * frame data within the timeout 4309 */ 4310#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d 4311/* enum: Number of CTPIO failures because the frame data arrived out of order 4312 * or with gaps 4313 */ 4314#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e 4315/* enum: Number of CTPIO failures because the host started a new frame before 4316 * completing the previous one 4317 */ 4318#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f 4319/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits 4320 * or not 32-bit aligned 4321 */ 4322#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70 4323/* enum: Number of CTPIO fallbacks because another VI on the same port was 4324 * sending a CTPIO frame 4325 */ 4326#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71 4327/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled 4328 */ 4329#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72 4330/* enum: Number of CTPIO fallbacks because length in header was less than 29 4331 * bytes 4332 */ 4333#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73 4334/* enum: Total number of successful CTPIO sends on this port */ 4335#define MC_CMD_MAC_CTPIO_SUCCESS 0x74 4336/* enum: Total number of CTPIO fallbacks on this port */ 4337#define MC_CMD_MAC_CTPIO_FALLBACK 0x75 4338/* enum: Total number of CTPIO poisoned frames on this port, whether erased or 4339 * not 4340 */ 4341#define MC_CMD_MAC_CTPIO_POISON 0x76 4342/* enum: Total number of CTPIO erased frames on this port */ 4343#define MC_CMD_MAC_CTPIO_ERASE 0x77 4344/* enum: This includes the space at offset 120 which is the final 4345 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused. 4346 */ 4347#define MC_CMD_MAC_NSTATS_V3 0x79 4348/* Other enum values, see field(s): */ 4349/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */ 4350 4351/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */ 4352#define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0 4353 4354/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */ 4355#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3) 4356#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0 4357#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8 4358#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0 4359#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4 4360#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4 4361/* enum: Start of V4 stats buffer space */ 4362#define MC_CMD_MAC_V4_DMABUF_START 0x79 4363/* enum: RXDP counter: Number of packets truncated because scattering was 4364 * disabled. 4365 */ 4366#define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79 4367/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting 4368 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set. 4369 */ 4370#define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a 4371/* enum: RXDP counter: Number of times the RXDP timed out while head of line 4372 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set. 4373 */ 4374#define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b 4375/* enum: This includes the space at offset 124 which is the final 4376 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused. 4377 */ 4378#define MC_CMD_MAC_NSTATS_V4 0x7d 4379/* Other enum values, see field(s): */ 4380/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */ 4381 4382/***********************************/ 4383/* MC_CMD_SRIOV 4384 * to be documented 4385 */ 4386#define MC_CMD_SRIOV 0x30 4387 4388/* MC_CMD_SRIOV_IN msgrequest */ 4389#define MC_CMD_SRIOV_IN_LEN 12 4390#define MC_CMD_SRIOV_IN_ENABLE_OFST 0 4391#define MC_CMD_SRIOV_IN_ENABLE_LEN 4 4392#define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 4393#define MC_CMD_SRIOV_IN_VI_BASE_LEN 4 4394#define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 4395#define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4 4396 4397/* MC_CMD_SRIOV_OUT msgresponse */ 4398#define MC_CMD_SRIOV_OUT_LEN 8 4399#define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 4400#define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4 4401#define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 4402#define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4 4403 4404/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 4405#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 4406/* this is only used for the first record */ 4407#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 4408#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4 4409#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 4410#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 4411#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 4412#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4 4413#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 4414#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 4415#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 4416#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 4417#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 4418#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 4419#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 4420#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 4421#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 4422#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4 4423#define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 4424#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 4425#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 4426#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 4427#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 4428#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 4429#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 4430#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 4431#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 4432#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 4433#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4 4434#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 4435#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 4436 4437/***********************************/ 4438/* MC_CMD_MEMCPY 4439 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 4440 * embedded directly in the command. 4441 * 4442 * A common pattern is for a client to use generation counts to signal a dma 4443 * update of a datastructure. To facilitate this, this MCDI operation can 4444 * contain multiple requests which are executed in strict order. Requests take 4445 * the form of duplicating the entire MCDI request continuously (including the 4446 * requests record, which is ignored in all but the first structure) 4447 * 4448 * The source data can either come from a DMA from the host, or it can be 4449 * embedded within the request directly, thereby eliminating a DMA read. To 4450 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 4451 * ADDR_LO=offset, and inserts the data at %offset from the start of the 4452 * payload. It's the callers responsibility to ensure that the embedded data 4453 * doesn't overlap the records. 4454 * 4455 * Returns: 0, EINVAL (invalid RID) 4456 */ 4457#define MC_CMD_MEMCPY 0x31 4458 4459/* MC_CMD_MEMCPY_IN msgrequest */ 4460#define MC_CMD_MEMCPY_IN_LENMIN 32 4461#define MC_CMD_MEMCPY_IN_LENMAX 224 4462#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 4463/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 4464#define MC_CMD_MEMCPY_IN_RECORD_OFST 0 4465#define MC_CMD_MEMCPY_IN_RECORD_LEN 32 4466#define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 4467#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 4468 4469/* MC_CMD_MEMCPY_OUT msgresponse */ 4470#define MC_CMD_MEMCPY_OUT_LEN 0 4471 4472/***********************************/ 4473/* MC_CMD_WOL_FILTER_SET 4474 * Set a WoL filter. 4475 */ 4476#define MC_CMD_WOL_FILTER_SET 0x32 4477#undef MC_CMD_0x32_PRIVILEGE_CTG 4478 4479#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 4480 4481/* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 4482#define MC_CMD_WOL_FILTER_SET_IN_LEN 192 4483#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 4484#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 4485#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 4486#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 4487/* A type value of 1 is unused. */ 4488#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 4489#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 4490/* enum: Magic */ 4491#define MC_CMD_WOL_TYPE_MAGIC 0x0 4492/* enum: MS Windows Magic */ 4493#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 4494/* enum: IPv4 Syn */ 4495#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 4496/* enum: IPv6 Syn */ 4497#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 4498/* enum: Bitmap */ 4499#define MC_CMD_WOL_TYPE_BITMAP 0x5 4500/* enum: Link */ 4501#define MC_CMD_WOL_TYPE_LINK 0x6 4502/* enum: (Above this for future use) */ 4503#define MC_CMD_WOL_TYPE_MAX 0x7 4504#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 4505#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 4506#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 4507 4508/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 4509#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 4510/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4511/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4512/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4513/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4514#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 4515#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 4516#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 4517#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 4518 4519/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 4520#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 4521/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4522/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4523/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4524/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4525#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 4526#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4 4527#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 4528#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4 4529#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 4530#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 4531#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 4532#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 4533 4534/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 4535#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 4536/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4537/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4538/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4539/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4540#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 4541#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 4542#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 4543#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 4544#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 4545#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 4546#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 4547#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 4548 4549/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 4550#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 4551/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4552/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4553/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4554/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4555#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 4556#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 4557#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 4558#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 4559#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 4560#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 4561#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 4562#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 4563#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 4564#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 4565 4566/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 4567#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 4568/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4569/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4570/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4571/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4572#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 4573#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4 4574#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 4575#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 4576#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 4577#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 4578 4579/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 4580#define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 4581#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 4582#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4 4583 4584/***********************************/ 4585/* MC_CMD_WOL_FILTER_REMOVE 4586 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 4587 */ 4588#define MC_CMD_WOL_FILTER_REMOVE 0x33 4589#undef MC_CMD_0x33_PRIVILEGE_CTG 4590 4591#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 4592 4593/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 4594#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 4595#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 4596#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4 4597 4598/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 4599#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 4600 4601/***********************************/ 4602/* MC_CMD_WOL_FILTER_RESET 4603 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 4604 * ENOSYS 4605 */ 4606#define MC_CMD_WOL_FILTER_RESET 0x34 4607#undef MC_CMD_0x34_PRIVILEGE_CTG 4608 4609#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 4610 4611/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 4612#define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 4613#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 4614#define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4 4615#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 4616#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 4617 4618/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 4619#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 4620 4621/***********************************/ 4622/* MC_CMD_SET_MCAST_HASH 4623 * Set the MCAST hash value without otherwise reconfiguring the MAC 4624 */ 4625#define MC_CMD_SET_MCAST_HASH 0x35 4626 4627/* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 4628#define MC_CMD_SET_MCAST_HASH_IN_LEN 32 4629#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 4630#define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 4631#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 4632#define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 4633 4634/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 4635#define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 4636 4637/***********************************/ 4638/* MC_CMD_NVRAM_TYPES 4639 * Return bitfield indicating available types of virtual NVRAM partitions. 4640 * Locks required: none. Returns: 0 4641 */ 4642#define MC_CMD_NVRAM_TYPES 0x36 4643#undef MC_CMD_0x36_PRIVILEGE_CTG 4644 4645#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4646 4647/* MC_CMD_NVRAM_TYPES_IN msgrequest */ 4648#define MC_CMD_NVRAM_TYPES_IN_LEN 0 4649 4650/* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 4651#define MC_CMD_NVRAM_TYPES_OUT_LEN 4 4652/* Bit mask of supported types. */ 4653#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 4654#define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4 4655/* enum: Disabled callisto. */ 4656#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 4657/* enum: MC firmware. */ 4658#define MC_CMD_NVRAM_TYPE_MC_FW 0x1 4659/* enum: MC backup firmware. */ 4660#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 4661/* enum: Static configuration Port0. */ 4662#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 4663/* enum: Static configuration Port1. */ 4664#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 4665/* enum: Dynamic configuration Port0. */ 4666#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 4667/* enum: Dynamic configuration Port1. */ 4668#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 4669/* enum: Expansion Rom. */ 4670#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 4671/* enum: Expansion Rom Configuration Port0. */ 4672#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 4673/* enum: Expansion Rom Configuration Port1. */ 4674#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 4675/* enum: Phy Configuration Port0. */ 4676#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 4677/* enum: Phy Configuration Port1. */ 4678#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 4679/* enum: Log. */ 4680#define MC_CMD_NVRAM_TYPE_LOG 0xc 4681/* enum: FPGA image. */ 4682#define MC_CMD_NVRAM_TYPE_FPGA 0xd 4683/* enum: FPGA backup image */ 4684#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 4685/* enum: FC firmware. */ 4686#define MC_CMD_NVRAM_TYPE_FC_FW 0xf 4687/* enum: FC backup firmware. */ 4688#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 4689/* enum: CPLD image. */ 4690#define MC_CMD_NVRAM_TYPE_CPLD 0x11 4691/* enum: Licensing information. */ 4692#define MC_CMD_NVRAM_TYPE_LICENSE 0x12 4693/* enum: FC Log. */ 4694#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 4695/* enum: Additional flash on FPGA. */ 4696#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 4697 4698/***********************************/ 4699/* MC_CMD_NVRAM_INFO 4700 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 4701 * EINVAL (bad type). 4702 */ 4703#define MC_CMD_NVRAM_INFO 0x37 4704#undef MC_CMD_0x37_PRIVILEGE_CTG 4705 4706#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4707 4708/* MC_CMD_NVRAM_INFO_IN msgrequest */ 4709#define MC_CMD_NVRAM_INFO_IN_LEN 4 4710#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 4711#define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4 4712/* Enum values, see field(s): */ 4713/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4714 4715/* MC_CMD_NVRAM_INFO_OUT msgresponse */ 4716#define MC_CMD_NVRAM_INFO_OUT_LEN 24 4717#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 4718#define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4 4719/* Enum values, see field(s): */ 4720/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4721#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 4722#define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4 4723#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 4724#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4 4725#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 4726#define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4 4727#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 4728#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 4729#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 4730#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 4731#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2 4732#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1 4733#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5 4734#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1 4735#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 4736#define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 4737#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 4738#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 4739#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 4740#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4 4741#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 4742#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4 4743 4744/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 4745#define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 4746#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 4747#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4 4748/* Enum values, see field(s): */ 4749/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4750#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 4751#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4 4752#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 4753#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4 4754#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 4755#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4 4756#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 4757#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 4758#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 4759#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 4760#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2 4761#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1 4762#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5 4763#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1 4764#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 4765#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 4766#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 4767#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4 4768#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 4769#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4 4770/* Writes must be multiples of this size. Added to support the MUM on Sorrento. 4771 */ 4772#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 4773#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4 4774 4775/***********************************/ 4776/* MC_CMD_NVRAM_UPDATE_START 4777 * Start a group of update operations on a virtual NVRAM partition. Locks 4778 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 4779 * PHY_LOCK required and not held). In an adapter bound to a TSA controller, 4780 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types 4781 * i.e. static config, dynamic config and expansion ROM config. Attempting to 4782 * perform this operation on a restricted partition will return the error 4783 * EPERM. 4784 */ 4785#define MC_CMD_NVRAM_UPDATE_START 0x38 4786#undef MC_CMD_0x38_PRIVILEGE_CTG 4787 4788#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4789 4790/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 4791 * Use NVRAM_UPDATE_START_V2_IN in new code 4792 */ 4793#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 4794#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 4795#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4 4796/* Enum values, see field(s): */ 4797/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4798 4799/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 4800 * request with additional flags indicating version of command in use. See 4801 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 4802 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 4803 */ 4804#define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 4805#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 4806#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4 4807/* Enum values, see field(s): */ 4808/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4809#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 4810#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4 4811#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 4812#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 4813 4814/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 4815#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 4816 4817/***********************************/ 4818/* MC_CMD_NVRAM_READ 4819 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 4820 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4821 * PHY_LOCK required and not held) 4822 */ 4823#define MC_CMD_NVRAM_READ 0x39 4824#undef MC_CMD_0x39_PRIVILEGE_CTG 4825 4826#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4827 4828/* MC_CMD_NVRAM_READ_IN msgrequest */ 4829#define MC_CMD_NVRAM_READ_IN_LEN 12 4830#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 4831#define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4 4832/* Enum values, see field(s): */ 4833/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4834#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 4835#define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4 4836/* amount to read in bytes */ 4837#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 4838#define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4 4839 4840/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 4841#define MC_CMD_NVRAM_READ_IN_V2_LEN 16 4842#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 4843#define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4 4844/* Enum values, see field(s): */ 4845/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4846#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 4847#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4 4848/* amount to read in bytes */ 4849#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 4850#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4 4851/* Optional control info. If a partition is stored with an A/B versioning 4852 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 4853 * this to control which underlying physical partition is used to read data 4854 * from. This allows it to perform a read-modify-write-verify with the write 4855 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 4856 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 4857 * verifying by reading with MODE=TARGET_BACKUP. 4858 */ 4859#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 4860#define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4 4861/* enum: Same as omitting MODE: caller sees data in current partition unless it 4862 * holds the write lock in which case it sees data in the partition it is 4863 * updating. 4864 */ 4865#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 4866/* enum: Read from the current partition of an A/B pair, even if holding the 4867 * write lock. 4868 */ 4869#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 4870/* enum: Read from the non-current (i.e. to be updated) partition of an A/B 4871 * pair 4872 */ 4873#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 4874 4875/* MC_CMD_NVRAM_READ_OUT msgresponse */ 4876#define MC_CMD_NVRAM_READ_OUT_LENMIN 1 4877#define MC_CMD_NVRAM_READ_OUT_LENMAX 252 4878#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 4879#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 4880#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 4881#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 4882#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 4883 4884/***********************************/ 4885/* MC_CMD_NVRAM_WRITE 4886 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 4887 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4888 * PHY_LOCK required and not held) 4889 */ 4890#define MC_CMD_NVRAM_WRITE 0x3a 4891#undef MC_CMD_0x3a_PRIVILEGE_CTG 4892 4893#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4894 4895/* MC_CMD_NVRAM_WRITE_IN msgrequest */ 4896#define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 4897#define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 4898#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 4899#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 4900#define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4 4901/* Enum values, see field(s): */ 4902/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4903#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 4904#define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4 4905#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 4906#define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4 4907#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 4908#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 4909#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 4910#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 4911 4912/* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 4913#define MC_CMD_NVRAM_WRITE_OUT_LEN 0 4914 4915/***********************************/ 4916/* MC_CMD_NVRAM_ERASE 4917 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 4918 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4919 * PHY_LOCK required and not held) 4920 */ 4921#define MC_CMD_NVRAM_ERASE 0x3b 4922#undef MC_CMD_0x3b_PRIVILEGE_CTG 4923 4924#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4925 4926/* MC_CMD_NVRAM_ERASE_IN msgrequest */ 4927#define MC_CMD_NVRAM_ERASE_IN_LEN 12 4928#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 4929#define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4 4930/* Enum values, see field(s): */ 4931/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4932#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 4933#define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4 4934#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 4935#define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4 4936 4937/* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 4938#define MC_CMD_NVRAM_ERASE_OUT_LEN 0 4939 4940/***********************************/ 4941/* MC_CMD_NVRAM_UPDATE_FINISH 4942 * Finish a group of update operations on a virtual NVRAM partition. Locks 4943 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/ 4944 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to 4945 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of 4946 * partition types i.e. static config, dynamic config and expansion ROM config. 4947 * Attempting to perform this operation on a restricted partition will return 4948 * the error EPERM. 4949 */ 4950#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 4951#undef MC_CMD_0x3c_PRIVILEGE_CTG 4952 4953#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4954 4955/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 4956 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 4957 */ 4958#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 4959#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 4960#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4 4961/* Enum values, see field(s): */ 4962/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4963#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 4964#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4 4965 4966/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 4967 * request with additional flags indicating version of NVRAM_UPDATE commands in 4968 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 4969 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 4970 */ 4971#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 4972#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 4973#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4 4974/* Enum values, see field(s): */ 4975/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4976#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 4977#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4 4978#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 4979#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4 4980#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 4981#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 4982 4983/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 4984 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 4985 */ 4986#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 4987 4988/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 4989 * 4990 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 4991 * firmware validation where applicable back to the host. 4992 * 4993 * Medford only: For signed firmware images, such as those for medford, the MC 4994 * firmware verifies the signature before marking the firmware image as valid. 4995 * This process takes a few seconds to complete. So is likely to take more than 4996 * the MCDI timeout. Hence signature verification is initiated when 4997 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 4998 * MCDI command is run in a background MCDI processing thread. This response 4999 * payload includes the results of the signature verification. Note that the 5000 * per-partition nvram lock in firmware is only released after the verification 5001 * has completed. 5002 */ 5003#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 5004/* Result of nvram update completion processing */ 5005#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 5006#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4 5007/* enum: Invalid return code; only non-zero values are defined. Defined as 5008 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 5009 */ 5010#define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 5011/* enum: Verify succeeded without any errors. */ 5012#define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 5013/* enum: CMS format verification failed due to an internal error. */ 5014#define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 5015/* enum: Invalid CMS format in image metadata. */ 5016#define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 5017/* enum: Message digest verification failed due to an internal error. */ 5018#define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 5019/* enum: Error in message digest calculated over the reflash-header, payload 5020 * and reflash-trailer. 5021 */ 5022#define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 5023/* enum: Signature verification failed due to an internal error. */ 5024#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 5025/* enum: There are no valid signatures in the image. */ 5026#define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 5027/* enum: Trusted approvers verification failed due to an internal error. */ 5028#define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 5029/* enum: The Trusted approver's list is empty. */ 5030#define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 5031/* enum: Signature chain verification failed due to an internal error. */ 5032#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 5033/* enum: The signers of the signatures in the image are not listed in the 5034 * Trusted approver's list. 5035 */ 5036#define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 5037/* enum: The image contains a test-signed certificate, but the adapter accepts 5038 * only production signed images. 5039 */ 5040#define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc 5041/* enum: The image has a lower security level than the current firmware. */ 5042#define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd 5043 5044/***********************************/ 5045/* MC_CMD_REBOOT 5046 * Reboot the MC. 5047 * 5048 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 5049 * assertion failure (at which point it is expected to perform a complete tear 5050 * down and reinitialise), to allow both ports to reset the MC once in an 5051 * atomic fashion. 5052 * 5053 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 5054 * which means that they will automatically reboot out of the assertion 5055 * handler, so this is in practise an optional operation. It is still 5056 * recommended that drivers execute this to support custom firmwares with 5057 * REBOOT_ON_ASSERT=0. 5058 * 5059 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 5060 * DATALEN=0 5061 */ 5062#define MC_CMD_REBOOT 0x3d 5063#undef MC_CMD_0x3d_PRIVILEGE_CTG 5064 5065#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 5066 5067/* MC_CMD_REBOOT_IN msgrequest */ 5068#define MC_CMD_REBOOT_IN_LEN 4 5069#define MC_CMD_REBOOT_IN_FLAGS_OFST 0 5070#define MC_CMD_REBOOT_IN_FLAGS_LEN 4 5071#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 5072 5073/* MC_CMD_REBOOT_OUT msgresponse */ 5074#define MC_CMD_REBOOT_OUT_LEN 0 5075 5076/***********************************/ 5077/* MC_CMD_SCHEDINFO 5078 * Request scheduler info. Locks required: NONE. Returns: An array of 5079 * (timeslice,maximum overrun), one for each thread, in ascending order of 5080 * thread address. 5081 */ 5082#define MC_CMD_SCHEDINFO 0x3e 5083#undef MC_CMD_0x3e_PRIVILEGE_CTG 5084 5085#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5086 5087/* MC_CMD_SCHEDINFO_IN msgrequest */ 5088#define MC_CMD_SCHEDINFO_IN_LEN 0 5089 5090/* MC_CMD_SCHEDINFO_OUT msgresponse */ 5091#define MC_CMD_SCHEDINFO_OUT_LENMIN 4 5092#define MC_CMD_SCHEDINFO_OUT_LENMAX 252 5093#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 5094#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 5095#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 5096#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 5097#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 5098 5099/***********************************/ 5100/* MC_CMD_REBOOT_MODE 5101 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 5102 * mode to the specified value. Returns the old mode. 5103 */ 5104#define MC_CMD_REBOOT_MODE 0x3f 5105#undef MC_CMD_0x3f_PRIVILEGE_CTG 5106 5107#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5108 5109/* MC_CMD_REBOOT_MODE_IN msgrequest */ 5110#define MC_CMD_REBOOT_MODE_IN_LEN 4 5111#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 5112#define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4 5113/* enum: Normal. */ 5114#define MC_CMD_REBOOT_MODE_NORMAL 0x0 5115/* enum: Power-on Reset. */ 5116#define MC_CMD_REBOOT_MODE_POR 0x2 5117/* enum: Snapper. */ 5118#define MC_CMD_REBOOT_MODE_SNAPPER 0x3 5119/* enum: snapper fake POR */ 5120#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 5121#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 5122#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 5123 5124/* MC_CMD_REBOOT_MODE_OUT msgresponse */ 5125#define MC_CMD_REBOOT_MODE_OUT_LEN 4 5126#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 5127#define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4 5128 5129/***********************************/ 5130/* MC_CMD_SENSOR_INFO 5131 * Returns information about every available sensor. 5132 * 5133 * Each sensor has a single (16bit) value, and a corresponding state. The 5134 * mapping between value and state is nominally determined by the MC, but may 5135 * be implemented using up to 2 ranges per sensor. 5136 * 5137 * This call returns a mask (32bit) of the sensors that are supported by this 5138 * platform, then an array of sensor information structures, in order of sensor 5139 * type (but without gaps for unimplemented sensors). Each structure defines 5140 * the ranges for the corresponding sensor. An unused range is indicated by 5141 * equal limit values. If one range is used, a value outside that range results 5142 * in STATE_FATAL. If two ranges are used, a value outside the second range 5143 * results in STATE_FATAL while a value outside the first and inside the second 5144 * range results in STATE_WARNING. 5145 * 5146 * Sensor masks and sensor information arrays are organised into pages. For 5147 * backward compatibility, older host software can only use sensors in page 0. 5148 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 5149 * as the next page flag. 5150 * 5151 * If the request does not contain a PAGE value then firmware will only return 5152 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 5153 * 5154 * If the request contains a PAGE value then firmware responds with the sensor 5155 * mask and sensor information array for that page of sensors. In this case bit 5156 * 31 in the mask is set if another page exists. 5157 * 5158 * Locks required: None Returns: 0 5159 */ 5160#define MC_CMD_SENSOR_INFO 0x41 5161#undef MC_CMD_0x41_PRIVILEGE_CTG 5162 5163#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5164 5165/* MC_CMD_SENSOR_INFO_IN msgrequest */ 5166#define MC_CMD_SENSOR_INFO_IN_LEN 0 5167 5168/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 5169#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 5170/* Which page of sensors to report. 5171 * 5172 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 5173 * 5174 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 5175 */ 5176#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 5177#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4 5178 5179/* MC_CMD_SENSOR_INFO_OUT msgresponse */ 5180#define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 5181#define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 5182#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 5183#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 5184#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4 5185/* enum: Controller temperature: degC */ 5186#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 5187/* enum: Phy common temperature: degC */ 5188#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 5189/* enum: Controller cooling: bool */ 5190#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 5191/* enum: Phy 0 temperature: degC */ 5192#define MC_CMD_SENSOR_PHY0_TEMP 0x3 5193/* enum: Phy 0 cooling: bool */ 5194#define MC_CMD_SENSOR_PHY0_COOLING 0x4 5195/* enum: Phy 1 temperature: degC */ 5196#define MC_CMD_SENSOR_PHY1_TEMP 0x5 5197/* enum: Phy 1 cooling: bool */ 5198#define MC_CMD_SENSOR_PHY1_COOLING 0x6 5199/* enum: 1.0v power: mV */ 5200#define MC_CMD_SENSOR_IN_1V0 0x7 5201/* enum: 1.2v power: mV */ 5202#define MC_CMD_SENSOR_IN_1V2 0x8 5203/* enum: 1.8v power: mV */ 5204#define MC_CMD_SENSOR_IN_1V8 0x9 5205/* enum: 2.5v power: mV */ 5206#define MC_CMD_SENSOR_IN_2V5 0xa 5207/* enum: 3.3v power: mV */ 5208#define MC_CMD_SENSOR_IN_3V3 0xb 5209/* enum: 12v power: mV */ 5210#define MC_CMD_SENSOR_IN_12V0 0xc 5211/* enum: 1.2v analogue power: mV */ 5212#define MC_CMD_SENSOR_IN_1V2A 0xd 5213/* enum: reference voltage: mV */ 5214#define MC_CMD_SENSOR_IN_VREF 0xe 5215/* enum: AOE FPGA power: mV */ 5216#define MC_CMD_SENSOR_OUT_VAOE 0xf 5217/* enum: AOE FPGA temperature: degC */ 5218#define MC_CMD_SENSOR_AOE_TEMP 0x10 5219/* enum: AOE FPGA PSU temperature: degC */ 5220#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 5221/* enum: AOE PSU temperature: degC */ 5222#define MC_CMD_SENSOR_PSU_TEMP 0x12 5223/* enum: Fan 0 speed: RPM */ 5224#define MC_CMD_SENSOR_FAN_0 0x13 5225/* enum: Fan 1 speed: RPM */ 5226#define MC_CMD_SENSOR_FAN_1 0x14 5227/* enum: Fan 2 speed: RPM */ 5228#define MC_CMD_SENSOR_FAN_2 0x15 5229/* enum: Fan 3 speed: RPM */ 5230#define MC_CMD_SENSOR_FAN_3 0x16 5231/* enum: Fan 4 speed: RPM */ 5232#define MC_CMD_SENSOR_FAN_4 0x17 5233/* enum: AOE FPGA input power: mV */ 5234#define MC_CMD_SENSOR_IN_VAOE 0x18 5235/* enum: AOE FPGA current: mA */ 5236#define MC_CMD_SENSOR_OUT_IAOE 0x19 5237/* enum: AOE FPGA input current: mA */ 5238#define MC_CMD_SENSOR_IN_IAOE 0x1a 5239/* enum: NIC power consumption: W */ 5240#define MC_CMD_SENSOR_NIC_POWER 0x1b 5241/* enum: 0.9v power voltage: mV */ 5242#define MC_CMD_SENSOR_IN_0V9 0x1c 5243/* enum: 0.9v power current: mA */ 5244#define MC_CMD_SENSOR_IN_I0V9 0x1d 5245/* enum: 1.2v power current: mA */ 5246#define MC_CMD_SENSOR_IN_I1V2 0x1e 5247/* enum: Not a sensor: reserved for the next page flag */ 5248#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 5249/* enum: 0.9v power voltage (at ADC): mV */ 5250#define MC_CMD_SENSOR_IN_0V9_ADC 0x20 5251/* enum: Controller temperature 2: degC */ 5252#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 5253/* enum: Voltage regulator internal temperature: degC */ 5254#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 5255/* enum: 0.9V voltage regulator temperature: degC */ 5256#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 5257/* enum: 1.2V voltage regulator temperature: degC */ 5258#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 5259/* enum: controller internal temperature sensor voltage (internal ADC): mV */ 5260#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 5261/* enum: controller internal temperature (internal ADC): degC */ 5262#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 5263/* enum: controller internal temperature sensor voltage (external ADC): mV */ 5264#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 5265/* enum: controller internal temperature (external ADC): degC */ 5266#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 5267/* enum: ambient temperature: degC */ 5268#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 5269/* enum: air flow: bool */ 5270#define MC_CMD_SENSOR_AIRFLOW 0x2a 5271/* enum: voltage between VSS08D and VSS08D at CSR: mV */ 5272#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 5273/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 5274#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 5275/* enum: Hotpoint temperature: degC */ 5276#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 5277/* enum: Port 0 PHY power switch over-current: bool */ 5278#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 5279/* enum: Port 1 PHY power switch over-current: bool */ 5280#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 5281/* enum: Mop-up microcontroller reference voltage: mV */ 5282#define MC_CMD_SENSOR_MUM_VCC 0x30 5283/* enum: 0.9v power phase A voltage: mV */ 5284#define MC_CMD_SENSOR_IN_0V9_A 0x31 5285/* enum: 0.9v power phase A current: mA */ 5286#define MC_CMD_SENSOR_IN_I0V9_A 0x32 5287/* enum: 0.9V voltage regulator phase A temperature: degC */ 5288#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 5289/* enum: 0.9v power phase B voltage: mV */ 5290#define MC_CMD_SENSOR_IN_0V9_B 0x34 5291/* enum: 0.9v power phase B current: mA */ 5292#define MC_CMD_SENSOR_IN_I0V9_B 0x35 5293/* enum: 0.9V voltage regulator phase B temperature: degC */ 5294#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 5295/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 5296#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 5297/* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 5298#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 5299/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 5300#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 5301/* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 5302#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 5303/* enum: CCOM RTS temperature: degC */ 5304#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 5305/* enum: Not a sensor: reserved for the next page flag */ 5306#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 5307/* enum: controller internal temperature sensor voltage on master core 5308 * (internal ADC): mV 5309 */ 5310#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 5311/* enum: controller internal temperature on master core (internal ADC): degC */ 5312#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 5313/* enum: controller internal temperature sensor voltage on master core 5314 * (external ADC): mV 5315 */ 5316#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 5317/* enum: controller internal temperature on master core (external ADC): degC */ 5318#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 5319/* enum: controller internal temperature on slave core sensor voltage (internal 5320 * ADC): mV 5321 */ 5322#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 5323/* enum: controller internal temperature on slave core (internal ADC): degC */ 5324#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 5325/* enum: controller internal temperature on slave core sensor voltage (external 5326 * ADC): mV 5327 */ 5328#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 5329/* enum: controller internal temperature on slave core (external ADC): degC */ 5330#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 5331/* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 5332#define MC_CMD_SENSOR_SODIMM_VOUT 0x49 5333/* enum: Temperature of SODIMM 0 (if installed): degC */ 5334#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 5335/* enum: Temperature of SODIMM 1 (if installed): degC */ 5336#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 5337/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 5338#define MC_CMD_SENSOR_PHY0_VCC 0x4c 5339/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 5340#define MC_CMD_SENSOR_PHY1_VCC 0x4d 5341/* enum: Controller die temperature (TDIODE): degC */ 5342#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 5343/* enum: Board temperature (front): degC */ 5344#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 5345/* enum: Board temperature (back): degC */ 5346#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 5347/* enum: 1.8v power current: mA */ 5348#define MC_CMD_SENSOR_IN_I1V8 0x51 5349/* enum: 2.5v power current: mA */ 5350#define MC_CMD_SENSOR_IN_I2V5 0x52 5351/* enum: 3.3v power current: mA */ 5352#define MC_CMD_SENSOR_IN_I3V3 0x53 5353/* enum: 12v power current: mA */ 5354#define MC_CMD_SENSOR_IN_I12V0 0x54 5355/* enum: 1.3v power: mV */ 5356#define MC_CMD_SENSOR_IN_1V3 0x55 5357/* enum: 1.3v power current: mA */ 5358#define MC_CMD_SENSOR_IN_I1V3 0x56 5359/* enum: Not a sensor: reserved for the next page flag */ 5360#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f 5361/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5362#define MC_CMD_SENSOR_ENTRY_OFST 4 5363#define MC_CMD_SENSOR_ENTRY_LEN 8 5364#define MC_CMD_SENSOR_ENTRY_LO_OFST 4 5365#define MC_CMD_SENSOR_ENTRY_HI_OFST 8 5366#define MC_CMD_SENSOR_ENTRY_MINNUM 0 5367#define MC_CMD_SENSOR_ENTRY_MAXNUM 31 5368 5369/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 5370#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 5371#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 5372#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 5373#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 5374#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4 5375/* Enum values, see field(s): */ 5376/* MC_CMD_SENSOR_INFO_OUT */ 5377#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 5378#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 5379/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5380/* MC_CMD_SENSOR_ENTRY_OFST 4 */ 5381/* MC_CMD_SENSOR_ENTRY_LEN 8 */ 5382/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 5383/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 5384/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 5385/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 5386 5387/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 5388#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 5389#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 5390#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 5391#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 5392#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 5393#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 5394#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 5395#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 5396#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 5397#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 5398#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 5399#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 5400#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 5401#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 5402#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 5403#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 5404#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 5405 5406/***********************************/ 5407/* MC_CMD_READ_SENSORS 5408 * Returns the current reading from each sensor. DMAs an array of sensor 5409 * readings, in order of sensor type (but without gaps for unimplemented 5410 * sensors), into host memory. Each array element is a 5411 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 5412 * 5413 * If the request does not contain the LENGTH field then only sensors 0 to 30 5414 * are reported, to avoid DMA buffer overflow in older host software. If the 5415 * sensor reading require more space than the LENGTH allows, then return 5416 * EINVAL. 5417 * 5418 * The MC will send a SENSOREVT event every time any sensor changes state. The 5419 * driver is responsible for ensuring that it doesn't miss any events. The 5420 * board will function normally if all sensors are in STATE_OK or 5421 * STATE_WARNING. Otherwise the board should not be expected to function. 5422 */ 5423#define MC_CMD_READ_SENSORS 0x42 5424#undef MC_CMD_0x42_PRIVILEGE_CTG 5425 5426#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5427 5428/* MC_CMD_READ_SENSORS_IN msgrequest */ 5429#define MC_CMD_READ_SENSORS_IN_LEN 8 5430/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5431#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 5432#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 5433#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 5434#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 5435 5436/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 5437#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 5438/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5439#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 5440#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 5441#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 5442#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 5443/* Size in bytes of host buffer. */ 5444#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 5445#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4 5446 5447/* MC_CMD_READ_SENSORS_OUT msgresponse */ 5448#define MC_CMD_READ_SENSORS_OUT_LEN 0 5449 5450/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 5451#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 5452 5453/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 5454#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 5455#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 5456#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 5457#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 5458#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 5459#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 5460#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 5461/* enum: Ok. */ 5462#define MC_CMD_SENSOR_STATE_OK 0x0 5463/* enum: Breached warning threshold. */ 5464#define MC_CMD_SENSOR_STATE_WARNING 0x1 5465/* enum: Breached fatal threshold. */ 5466#define MC_CMD_SENSOR_STATE_FATAL 0x2 5467/* enum: Fault with sensor. */ 5468#define MC_CMD_SENSOR_STATE_BROKEN 0x3 5469/* enum: Sensor is working but does not currently have a reading. */ 5470#define MC_CMD_SENSOR_STATE_NO_READING 0x4 5471/* enum: Sensor initialisation failed. */ 5472#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 5473#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 5474#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 5475#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 5476#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 5477/* Enum values, see field(s): */ 5478/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5479#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 5480#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 5481 5482/***********************************/ 5483/* MC_CMD_GET_PHY_STATE 5484 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 5485 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 5486 * code: 0 5487 */ 5488#define MC_CMD_GET_PHY_STATE 0x43 5489#undef MC_CMD_0x43_PRIVILEGE_CTG 5490 5491#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5492 5493/* MC_CMD_GET_PHY_STATE_IN msgrequest */ 5494#define MC_CMD_GET_PHY_STATE_IN_LEN 0 5495 5496/* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 5497#define MC_CMD_GET_PHY_STATE_OUT_LEN 4 5498#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 5499#define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4 5500/* enum: Ok. */ 5501#define MC_CMD_PHY_STATE_OK 0x1 5502/* enum: Faulty. */ 5503#define MC_CMD_PHY_STATE_ZOMBIE 0x2 5504 5505/***********************************/ 5506/* MC_CMD_SETUP_8021QBB 5507 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 5508 * disable 802.Qbb for a given priority. 5509 */ 5510#define MC_CMD_SETUP_8021QBB 0x44 5511 5512/* MC_CMD_SETUP_8021QBB_IN msgrequest */ 5513#define MC_CMD_SETUP_8021QBB_IN_LEN 32 5514#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 5515#define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 5516 5517/* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 5518#define MC_CMD_SETUP_8021QBB_OUT_LEN 0 5519 5520/***********************************/ 5521/* MC_CMD_WOL_FILTER_GET 5522 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 5523 */ 5524#define MC_CMD_WOL_FILTER_GET 0x45 5525#undef MC_CMD_0x45_PRIVILEGE_CTG 5526 5527#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 5528 5529/* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 5530#define MC_CMD_WOL_FILTER_GET_IN_LEN 0 5531 5532/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 5533#define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 5534#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 5535#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4 5536 5537/***********************************/ 5538/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 5539 * Add a protocol offload to NIC for lights-out state. Locks required: None. 5540 * Returns: 0, ENOSYS 5541 */ 5542#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 5543#undef MC_CMD_0x46_PRIVILEGE_CTG 5544 5545#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 5546 5547/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5548#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 5549#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 5550#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 5551#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5552#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5553#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 5554#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 5555#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 5556#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 5557#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 5558#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 5559 5560/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 5561#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 5562/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5563/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5564#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 5565#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 5566#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 5567#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4 5568 5569/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 5570#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 5571/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5572/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5573#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 5574#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 5575#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 5576#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 5577#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 5578#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 5579 5580/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5581#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 5582#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 5583#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4 5584 5585/***********************************/ 5586/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 5587 * Remove a protocol offload from NIC for lights-out state. Locks required: 5588 * None. Returns: 0, ENOSYS 5589 */ 5590#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 5591#undef MC_CMD_0x47_PRIVILEGE_CTG 5592 5593#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 5594 5595/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5596#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 5597#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5598#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5599#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 5600#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4 5601 5602/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5603#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 5604 5605/***********************************/ 5606/* MC_CMD_MAC_RESET_RESTORE 5607 * Restore MAC after block reset. Locks required: None. Returns: 0. 5608 */ 5609#define MC_CMD_MAC_RESET_RESTORE 0x48 5610 5611/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 5612#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 5613 5614/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 5615#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 5616 5617/***********************************/ 5618/* MC_CMD_TESTASSERT 5619 * Deliberately trigger an assert-detonation in the firmware for testing 5620 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 5621 * required: None Returns: 0 5622 */ 5623#define MC_CMD_TESTASSERT 0x49 5624#undef MC_CMD_0x49_PRIVILEGE_CTG 5625 5626#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 5627 5628/* MC_CMD_TESTASSERT_IN msgrequest */ 5629#define MC_CMD_TESTASSERT_IN_LEN 0 5630 5631/* MC_CMD_TESTASSERT_OUT msgresponse */ 5632#define MC_CMD_TESTASSERT_OUT_LEN 0 5633 5634/* MC_CMD_TESTASSERT_V2_IN msgrequest */ 5635#define MC_CMD_TESTASSERT_V2_IN_LEN 4 5636/* How to provoke the assertion */ 5637#define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 5638#define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4 5639/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 5640 * you're testing firmware, this is what you want. 5641 */ 5642#define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 5643/* enum: Assert using assert(0); */ 5644#define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 5645/* enum: Deliberately trigger a watchdog */ 5646#define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 5647/* enum: Deliberately trigger a trap by loading from an invalid address */ 5648#define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 5649/* enum: Deliberately trigger a trap by storing to an invalid address */ 5650#define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 5651/* enum: Jump to an invalid address */ 5652#define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 5653 5654/* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 5655#define MC_CMD_TESTASSERT_V2_OUT_LEN 0 5656 5657/***********************************/ 5658/* MC_CMD_WORKAROUND 5659 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 5660 * understand the given workaround number - which should not be treated as a 5661 * hard error by client code. This op does not imply any semantics about each 5662 * workaround, that's between the driver and the mcfw on a per-workaround 5663 * basis. Locks required: None. Returns: 0, EINVAL . 5664 */ 5665#define MC_CMD_WORKAROUND 0x4a 5666#undef MC_CMD_0x4a_PRIVILEGE_CTG 5667 5668#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5669 5670/* MC_CMD_WORKAROUND_IN msgrequest */ 5671#define MC_CMD_WORKAROUND_IN_LEN 8 5672/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 5673#define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 5674#define MC_CMD_WORKAROUND_IN_TYPE_LEN 4 5675/* enum: Bug 17230 work around. */ 5676#define MC_CMD_WORKAROUND_BUG17230 0x1 5677/* enum: Bug 35388 work around (unsafe EVQ writes). */ 5678#define MC_CMD_WORKAROUND_BUG35388 0x2 5679/* enum: Bug35017 workaround (A64 tables must be identity map) */ 5680#define MC_CMD_WORKAROUND_BUG35017 0x3 5681/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 5682#define MC_CMD_WORKAROUND_BUG41750 0x4 5683/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 5684 * - before adding code that queries this workaround, remember that there's 5685 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 5686 * and will hence (incorrectly) report that the bug doesn't exist. 5687 */ 5688#define MC_CMD_WORKAROUND_BUG42008 0x5 5689/* enum: Bug 26807 features present in firmware (multicast filter chaining) 5690 * This feature cannot be turned on/off while there are any filters already 5691 * present. The behaviour in such case depends on the acting client's privilege 5692 * level. If the client has the admin privilege, then all functions that have 5693 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 5694 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 5695 */ 5696#define MC_CMD_WORKAROUND_BUG26807 0x6 5697/* enum: Bug 61265 work around (broken EVQ TMR writes). */ 5698#define MC_CMD_WORKAROUND_BUG61265 0x7 5699/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 5700 * the workaround 5701 */ 5702#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 5703#define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4 5704 5705/* MC_CMD_WORKAROUND_OUT msgresponse */ 5706#define MC_CMD_WORKAROUND_OUT_LEN 0 5707 5708/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 5709 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 5710 */ 5711#define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 5712#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 5713#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4 5714#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 5715#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 5716 5717/***********************************/ 5718/* MC_CMD_GET_PHY_MEDIA_INFO 5719 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 5720 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 5721 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 5722 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 5723 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 5724 * Anything else: currently undefined. Locks required: None. Return code: 0. 5725 */ 5726#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 5727#undef MC_CMD_0x4b_PRIVILEGE_CTG 5728 5729#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5730 5731/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 5732#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 5733#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 5734#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4 5735 5736/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 5737#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 5738#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 5739#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 5740/* in bytes */ 5741#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 5742#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4 5743#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 5744#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 5745#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 5746#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 5747 5748/***********************************/ 5749/* MC_CMD_NVRAM_TEST 5750 * Test a particular NVRAM partition for valid contents (where "valid" depends 5751 * on the type of partition). 5752 */ 5753#define MC_CMD_NVRAM_TEST 0x4c 5754#undef MC_CMD_0x4c_PRIVILEGE_CTG 5755 5756#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 5757 5758/* MC_CMD_NVRAM_TEST_IN msgrequest */ 5759#define MC_CMD_NVRAM_TEST_IN_LEN 4 5760#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 5761#define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4 5762/* Enum values, see field(s): */ 5763/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5764 5765/* MC_CMD_NVRAM_TEST_OUT msgresponse */ 5766#define MC_CMD_NVRAM_TEST_OUT_LEN 4 5767#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 5768#define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4 5769/* enum: Passed. */ 5770#define MC_CMD_NVRAM_TEST_PASS 0x0 5771/* enum: Failed. */ 5772#define MC_CMD_NVRAM_TEST_FAIL 0x1 5773/* enum: Not supported. */ 5774#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 5775 5776/***********************************/ 5777/* MC_CMD_MRSFP_TWEAK 5778 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 5779 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 5780 * they are configured first. Locks required: None. Return code: 0, EINVAL. 5781 */ 5782#define MC_CMD_MRSFP_TWEAK 0x4d 5783 5784/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 5785#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 5786/* 0-6 low->high de-emph. */ 5787#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 5788#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4 5789/* 0-8 low->high ref.V */ 5790#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 5791#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4 5792/* 0-8 0-8 low->high boost */ 5793#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 5794#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4 5795/* 0-8 low->high ref.V */ 5796#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 5797#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4 5798 5799/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 5800#define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 5801 5802/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 5803#define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 5804/* input bits */ 5805#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 5806#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4 5807/* output bits */ 5808#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 5809#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4 5810/* direction */ 5811#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 5812#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4 5813/* enum: Out. */ 5814#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 5815/* enum: In. */ 5816#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 5817 5818/***********************************/ 5819/* MC_CMD_SENSOR_SET_LIMS 5820 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 5821 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 5822 * of range. 5823 */ 5824#define MC_CMD_SENSOR_SET_LIMS 0x4e 5825#undef MC_CMD_0x4e_PRIVILEGE_CTG 5826 5827#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5828 5829/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 5830#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 5831#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 5832#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4 5833/* Enum values, see field(s): */ 5834/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5835/* interpretation is is sensor-specific. */ 5836#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 5837#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4 5838/* interpretation is is sensor-specific. */ 5839#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 5840#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4 5841/* interpretation is is sensor-specific. */ 5842#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 5843#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4 5844/* interpretation is is sensor-specific. */ 5845#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 5846#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4 5847 5848/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 5849#define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 5850 5851/***********************************/ 5852/* MC_CMD_GET_RESOURCE_LIMITS 5853 */ 5854#define MC_CMD_GET_RESOURCE_LIMITS 0x4f 5855 5856/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 5857#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 5858 5859/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 5860#define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 5861#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 5862#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4 5863#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 5864#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4 5865#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 5866#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4 5867#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 5868#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4 5869 5870/***********************************/ 5871/* MC_CMD_NVRAM_PARTITIONS 5872 * Reads the list of available virtual NVRAM partition types. Locks required: 5873 * none. Returns: 0, EINVAL (bad type). 5874 */ 5875#define MC_CMD_NVRAM_PARTITIONS 0x51 5876#undef MC_CMD_0x51_PRIVILEGE_CTG 5877 5878#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5879 5880/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 5881#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 5882 5883/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 5884#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 5885#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 5886#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 5887/* total number of partitions */ 5888#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 5889#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4 5890/* type ID code for each of NUM_PARTITIONS partitions */ 5891#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 5892#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 5893#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 5894#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 5895 5896/***********************************/ 5897/* MC_CMD_NVRAM_METADATA 5898 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 5899 * none. Returns: 0, EINVAL (bad type). 5900 */ 5901#define MC_CMD_NVRAM_METADATA 0x52 5902#undef MC_CMD_0x52_PRIVILEGE_CTG 5903 5904#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5905 5906/* MC_CMD_NVRAM_METADATA_IN msgrequest */ 5907#define MC_CMD_NVRAM_METADATA_IN_LEN 4 5908/* Partition type ID code */ 5909#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 5910#define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4 5911 5912/* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 5913#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 5914#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 5915#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 5916/* Partition type ID code */ 5917#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 5918#define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4 5919#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 5920#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4 5921#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 5922#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 5923#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 5924#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 5925#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 5926#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 5927/* Subtype ID code for content of this partition */ 5928#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 5929#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4 5930/* 1st component of W.X.Y.Z version number for content of this partition */ 5931#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 5932#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 5933/* 2nd component of W.X.Y.Z version number for content of this partition */ 5934#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 5935#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 5936/* 3rd component of W.X.Y.Z version number for content of this partition */ 5937#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 5938#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 5939/* 4th component of W.X.Y.Z version number for content of this partition */ 5940#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 5941#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 5942/* Zero-terminated string describing the content of this partition */ 5943#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 5944#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 5945#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 5946#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 5947 5948/***********************************/ 5949/* MC_CMD_GET_MAC_ADDRESSES 5950 * Returns the base MAC, count and stride for the requesting function 5951 */ 5952#define MC_CMD_GET_MAC_ADDRESSES 0x55 5953#undef MC_CMD_0x55_PRIVILEGE_CTG 5954 5955#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5956 5957/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 5958#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 5959 5960/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 5961#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 5962/* Base MAC address */ 5963#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 5964#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 5965/* Padding */ 5966#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 5967#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 5968/* Number of allocated MAC addresses */ 5969#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 5970#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4 5971/* Spacing of allocated MAC addresses */ 5972#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 5973#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4 5974 5975/***********************************/ 5976/* MC_CMD_CLP 5977 * Perform a CLP related operation 5978 */ 5979#define MC_CMD_CLP 0x56 5980#undef MC_CMD_0x56_PRIVILEGE_CTG 5981 5982#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 5983 5984/* MC_CMD_CLP_IN msgrequest */ 5985#define MC_CMD_CLP_IN_LEN 4 5986/* Sub operation */ 5987#define MC_CMD_CLP_IN_OP_OFST 0 5988#define MC_CMD_CLP_IN_OP_LEN 4 5989/* enum: Return to factory default settings */ 5990#define MC_CMD_CLP_OP_DEFAULT 0x1 5991/* enum: Set MAC address */ 5992#define MC_CMD_CLP_OP_SET_MAC 0x2 5993/* enum: Get MAC address */ 5994#define MC_CMD_CLP_OP_GET_MAC 0x3 5995/* enum: Set UEFI/GPXE boot mode */ 5996#define MC_CMD_CLP_OP_SET_BOOT 0x4 5997/* enum: Get UEFI/GPXE boot mode */ 5998#define MC_CMD_CLP_OP_GET_BOOT 0x5 5999 6000/* MC_CMD_CLP_OUT msgresponse */ 6001#define MC_CMD_CLP_OUT_LEN 0 6002 6003/* MC_CMD_CLP_IN_DEFAULT msgrequest */ 6004#define MC_CMD_CLP_IN_DEFAULT_LEN 4 6005/* MC_CMD_CLP_IN_OP_OFST 0 */ 6006/* MC_CMD_CLP_IN_OP_LEN 4 */ 6007 6008/* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 6009#define MC_CMD_CLP_OUT_DEFAULT_LEN 0 6010 6011/* MC_CMD_CLP_IN_SET_MAC msgrequest */ 6012#define MC_CMD_CLP_IN_SET_MAC_LEN 12 6013/* MC_CMD_CLP_IN_OP_OFST 0 */ 6014/* MC_CMD_CLP_IN_OP_LEN 4 */ 6015/* MAC address assigned to port */ 6016#define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 6017#define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 6018/* Padding */ 6019#define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 6020#define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 6021 6022/* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 6023#define MC_CMD_CLP_OUT_SET_MAC_LEN 0 6024 6025/* MC_CMD_CLP_IN_GET_MAC msgrequest */ 6026#define MC_CMD_CLP_IN_GET_MAC_LEN 4 6027/* MC_CMD_CLP_IN_OP_OFST 0 */ 6028/* MC_CMD_CLP_IN_OP_LEN 4 */ 6029 6030/* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 6031#define MC_CMD_CLP_OUT_GET_MAC_LEN 8 6032/* MAC address assigned to port */ 6033#define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 6034#define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 6035/* Padding */ 6036#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 6037#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 6038 6039/* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 6040#define MC_CMD_CLP_IN_SET_BOOT_LEN 5 6041/* MC_CMD_CLP_IN_OP_OFST 0 */ 6042/* MC_CMD_CLP_IN_OP_LEN 4 */ 6043/* Boot flag */ 6044#define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 6045#define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 6046 6047/* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 6048#define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 6049 6050/* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 6051#define MC_CMD_CLP_IN_GET_BOOT_LEN 4 6052/* MC_CMD_CLP_IN_OP_OFST 0 */ 6053/* MC_CMD_CLP_IN_OP_LEN 4 */ 6054 6055/* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 6056#define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 6057/* Boot flag */ 6058#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 6059#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 6060/* Padding */ 6061#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 6062#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 6063 6064/***********************************/ 6065/* MC_CMD_MUM 6066 * Perform a MUM operation 6067 */ 6068#define MC_CMD_MUM 0x57 6069#undef MC_CMD_0x57_PRIVILEGE_CTG 6070 6071#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE 6072 6073/* MC_CMD_MUM_IN msgrequest */ 6074#define MC_CMD_MUM_IN_LEN 4 6075#define MC_CMD_MUM_IN_OP_HDR_OFST 0 6076#define MC_CMD_MUM_IN_OP_HDR_LEN 4 6077#define MC_CMD_MUM_IN_OP_LBN 0 6078#define MC_CMD_MUM_IN_OP_WIDTH 8 6079/* enum: NULL MCDI command to MUM */ 6080#define MC_CMD_MUM_OP_NULL 0x1 6081/* enum: Get MUM version */ 6082#define MC_CMD_MUM_OP_GET_VERSION 0x2 6083/* enum: Issue raw I2C command to MUM */ 6084#define MC_CMD_MUM_OP_RAW_CMD 0x3 6085/* enum: Read from registers on devices connected to MUM. */ 6086#define MC_CMD_MUM_OP_READ 0x4 6087/* enum: Write to registers on devices connected to MUM. */ 6088#define MC_CMD_MUM_OP_WRITE 0x5 6089/* enum: Control UART logging. */ 6090#define MC_CMD_MUM_OP_LOG 0x6 6091/* enum: Operations on MUM GPIO lines */ 6092#define MC_CMD_MUM_OP_GPIO 0x7 6093/* enum: Get sensor readings from MUM */ 6094#define MC_CMD_MUM_OP_READ_SENSORS 0x8 6095/* enum: Initiate clock programming on the MUM */ 6096#define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 6097/* enum: Initiate FPGA load from flash on the MUM */ 6098#define MC_CMD_MUM_OP_FPGA_LOAD 0xa 6099/* enum: Request sensor reading from MUM ADC resulting from earlier request via 6100 * MUM ATB 6101 */ 6102#define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 6103/* enum: Send commands relating to the QSFP ports via the MUM for PHY 6104 * operations 6105 */ 6106#define MC_CMD_MUM_OP_QSFP 0xc 6107/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 6108 * level) from MUM 6109 */ 6110#define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 6111 6112/* MC_CMD_MUM_IN_NULL msgrequest */ 6113#define MC_CMD_MUM_IN_NULL_LEN 4 6114/* MUM cmd header */ 6115#define MC_CMD_MUM_IN_CMD_OFST 0 6116#define MC_CMD_MUM_IN_CMD_LEN 4 6117 6118/* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 6119#define MC_CMD_MUM_IN_GET_VERSION_LEN 4 6120/* MUM cmd header */ 6121/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6122/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6123 6124/* MC_CMD_MUM_IN_READ msgrequest */ 6125#define MC_CMD_MUM_IN_READ_LEN 16 6126/* MUM cmd header */ 6127/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6128/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6129/* ID of (device connected to MUM) to read from registers of */ 6130#define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 6131#define MC_CMD_MUM_IN_READ_DEVICE_LEN 4 6132/* enum: Hittite HMC1035 clock generator on Sorrento board */ 6133#define MC_CMD_MUM_DEV_HITTITE 0x1 6134/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 6135#define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 6136/* 32-bit address to read from */ 6137#define MC_CMD_MUM_IN_READ_ADDR_OFST 8 6138#define MC_CMD_MUM_IN_READ_ADDR_LEN 4 6139/* Number of words to read. */ 6140#define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 6141#define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4 6142 6143/* MC_CMD_MUM_IN_WRITE msgrequest */ 6144#define MC_CMD_MUM_IN_WRITE_LENMIN 16 6145#define MC_CMD_MUM_IN_WRITE_LENMAX 252 6146#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 6147/* MUM cmd header */ 6148/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6149/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6150/* ID of (device connected to MUM) to write to registers of */ 6151#define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 6152#define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4 6153/* enum: Hittite HMC1035 clock generator on Sorrento board */ 6154/* MC_CMD_MUM_DEV_HITTITE 0x1 */ 6155/* 32-bit address to write to */ 6156#define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 6157#define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4 6158/* Words to write */ 6159#define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 6160#define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 6161#define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 6162#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 6163 6164/* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 6165#define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 6166#define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 6167#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 6168/* MUM cmd header */ 6169/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6170/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6171/* MUM I2C cmd code */ 6172#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 6173#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4 6174/* Number of bytes to write */ 6175#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 6176#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4 6177/* Number of bytes to read */ 6178#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 6179#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4 6180/* Bytes to write */ 6181#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 6182#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 6183#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 6184#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 6185 6186/* MC_CMD_MUM_IN_LOG msgrequest */ 6187#define MC_CMD_MUM_IN_LOG_LEN 8 6188/* MUM cmd header */ 6189/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6190/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6191#define MC_CMD_MUM_IN_LOG_OP_OFST 4 6192#define MC_CMD_MUM_IN_LOG_OP_LEN 4 6193#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 6194 6195/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 6196#define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 6197/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6198/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6199/* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 6200/* MC_CMD_MUM_IN_LOG_OP_LEN 4 */ 6201/* Enable/disable debug output to UART */ 6202#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 6203#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4 6204 6205/* MC_CMD_MUM_IN_GPIO msgrequest */ 6206#define MC_CMD_MUM_IN_GPIO_LEN 8 6207/* MUM cmd header */ 6208/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6209/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6210#define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 6211#define MC_CMD_MUM_IN_GPIO_HDR_LEN 4 6212#define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 6213#define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 6214#define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 6215#define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 6216#define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 6217#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 6218#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 6219#define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 6220 6221/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 6222#define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 6223/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6224/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6225#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 6226#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4 6227 6228/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 6229#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 6230/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6231/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6232#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 6233#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4 6234/* The first 32-bit word to be written to the GPIO OUT register. */ 6235#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 6236#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4 6237/* The second 32-bit word to be written to the GPIO OUT register. */ 6238#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 6239#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4 6240 6241/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 6242#define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 6243/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6244/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6245#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 6246#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4 6247 6248/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 6249#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 6250/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6251/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6252#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 6253#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4 6254/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 6255#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 6256#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4 6257/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 6258#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 6259#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4 6260 6261/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 6262#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 6263/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6264/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6265#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 6266#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4 6267 6268/* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 6269#define MC_CMD_MUM_IN_GPIO_OP_LEN 8 6270/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6271/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6272#define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 6273#define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4 6274#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 6275#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 6276#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 6277#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 6278#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 6279#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 6280#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 6281#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 6282 6283/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 6284#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 6285/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6286/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6287#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 6288#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4 6289 6290/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 6291#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 6292/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6293/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6294#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 6295#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4 6296#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 6297#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 6298 6299/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 6300#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 6301/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6302/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6303#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 6304#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4 6305#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 6306#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 6307 6308/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 6309#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 6310/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6311/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6312#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 6313#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4 6314#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 6315#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 6316 6317/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 6318#define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 6319/* MUM cmd header */ 6320/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6321/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6322#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 6323#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4 6324#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 6325#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 6326#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 6327#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 6328 6329/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 6330#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 6331/* MUM cmd header */ 6332/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6333/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6334/* Bit-mask of clocks to be programmed */ 6335#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 6336#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4 6337#define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 6338#define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 6339#define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 6340/* Control flags for clock programming */ 6341#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 6342#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4 6343#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 6344#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 6345#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 6346#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 6347#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 6348#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 6349 6350/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 6351#define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 6352/* MUM cmd header */ 6353/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6354/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6355/* Enable/Disable FPGA config from flash */ 6356#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 6357#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4 6358 6359/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 6360#define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 6361/* MUM cmd header */ 6362/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6363/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6364 6365/* MC_CMD_MUM_IN_QSFP msgrequest */ 6366#define MC_CMD_MUM_IN_QSFP_LEN 12 6367/* MUM cmd header */ 6368/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6369/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6370#define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 6371#define MC_CMD_MUM_IN_QSFP_HDR_LEN 4 6372#define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 6373#define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 6374#define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 6375#define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 6376#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 6377#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 6378#define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 6379#define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 6380#define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 6381#define MC_CMD_MUM_IN_QSFP_IDX_LEN 4 6382 6383/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 6384#define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 6385/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6386/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6387#define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 6388#define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4 6389#define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 6390#define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4 6391#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 6392#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4 6393 6394/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 6395#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 6396/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6397/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6398#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 6399#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4 6400#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 6401#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4 6402#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 6403#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4 6404#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 6405#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4 6406#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 6407#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4 6408 6409/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 6410#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 6411/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6412/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6413#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 6414#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4 6415#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 6416#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4 6417 6418/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 6419#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 6420/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6421/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6422#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 6423#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4 6424#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 6425#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4 6426#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 6427#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4 6428 6429/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 6430#define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 6431/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6432/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6433#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 6434#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4 6435#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 6436#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4 6437 6438/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 6439#define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 6440/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6441/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6442#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 6443#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4 6444#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 6445#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4 6446 6447/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 6448#define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 6449/* MUM cmd header */ 6450/* MC_CMD_MUM_IN_CMD_OFST 0 */ 6451/* MC_CMD_MUM_IN_CMD_LEN 4 */ 6452 6453/* MC_CMD_MUM_OUT msgresponse */ 6454#define MC_CMD_MUM_OUT_LEN 0 6455 6456/* MC_CMD_MUM_OUT_NULL msgresponse */ 6457#define MC_CMD_MUM_OUT_NULL_LEN 0 6458 6459/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 6460#define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 6461#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 6462#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4 6463#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 6464#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 6465#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 6466#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 6467 6468/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 6469#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 6470#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 6471#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 6472/* returned data */ 6473#define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 6474#define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 6475#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 6476#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 6477 6478/* MC_CMD_MUM_OUT_READ msgresponse */ 6479#define MC_CMD_MUM_OUT_READ_LENMIN 4 6480#define MC_CMD_MUM_OUT_READ_LENMAX 252 6481#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 6482#define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 6483#define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 6484#define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 6485#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 6486 6487/* MC_CMD_MUM_OUT_WRITE msgresponse */ 6488#define MC_CMD_MUM_OUT_WRITE_LEN 0 6489 6490/* MC_CMD_MUM_OUT_LOG msgresponse */ 6491#define MC_CMD_MUM_OUT_LOG_LEN 0 6492 6493/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 6494#define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 6495 6496/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 6497#define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 6498/* The first 32-bit word read from the GPIO IN register. */ 6499#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 6500#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4 6501/* The second 32-bit word read from the GPIO IN register. */ 6502#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 6503#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4 6504 6505/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 6506#define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 6507 6508/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 6509#define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 6510/* The first 32-bit word read from the GPIO OUT register. */ 6511#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 6512#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4 6513/* The second 32-bit word read from the GPIO OUT register. */ 6514#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 6515#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4 6516 6517/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 6518#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 6519 6520/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 6521#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 6522#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 6523#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4 6524#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 6525#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4 6526 6527/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 6528#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 6529#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 6530#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4 6531 6532/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 6533#define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 6534 6535/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 6536#define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 6537 6538/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 6539#define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 6540 6541/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 6542#define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 6543#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 6544#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 6545#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 6546#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 6547#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 6548#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 6549#define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 6550#define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 6551#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 6552#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 6553#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 6554#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 6555 6556/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 6557#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 6558#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 6559#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4 6560 6561/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 6562#define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 6563 6564/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 6565#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 6566#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 6567#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4 6568 6569/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 6570#define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 6571 6572/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 6573#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 6574#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 6575#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4 6576#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 6577#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4 6578#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 6579#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 6580#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 6581#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 6582 6583/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 6584#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 6585#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 6586#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4 6587 6588/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 6589#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 6590#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 6591#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 6592/* in bytes */ 6593#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 6594#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4 6595#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 6596#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 6597#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 6598#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 6599 6600/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 6601#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 6602#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 6603#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4 6604#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 6605#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4 6606 6607/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 6608#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 6609#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 6610#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4 6611 6612/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 6613#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 6614#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 6615#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 6616/* Discrete (soldered) DDR resistor strap info */ 6617#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 6618#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4 6619#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 6620#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 6621#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 6622#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 6623/* Number of SODIMM info records */ 6624#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 6625#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4 6626/* Array of SODIMM info records */ 6627#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 6628#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 6629#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 6630#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 6631#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 6632#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 6633#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 6634#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 6635/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 6636#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 6637/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 6638#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 6639/* enum: Total number of SODIMM banks */ 6640#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 6641#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 6642#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 6643#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 6644#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 6645#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 6646#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 6647#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 6648#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 6649#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 6650#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 6651/* enum: Values 5-15 are reserved for future usage */ 6652#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 6653#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 6654#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 6655#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 6656#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 6657#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 6658#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 6659/* enum: No module present */ 6660#define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 6661/* enum: Module present supported and powered on */ 6662#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 6663/* enum: Module present but bad type */ 6664#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 6665/* enum: Module present but incompatible voltage */ 6666#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 6667/* enum: Module present but unknown SPD */ 6668#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 6669/* enum: Module present but slot cannot support it */ 6670#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 6671/* enum: Modules may or may not be present, but cannot establish contact by I2C 6672 */ 6673#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 6674#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 6675#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 6676 6677/* MC_CMD_RESOURCE_SPECIFIER enum */ 6678/* enum: Any */ 6679#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 6680/* enum: None */ 6681#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 6682 6683/* EVB_PORT_ID structuredef */ 6684#define EVB_PORT_ID_LEN 4 6685#define EVB_PORT_ID_PORT_ID_OFST 0 6686#define EVB_PORT_ID_PORT_ID_LEN 4 6687/* enum: An invalid port handle. */ 6688#define EVB_PORT_ID_NULL 0x0 6689/* enum: The port assigned to this function.. */ 6690#define EVB_PORT_ID_ASSIGNED 0x1000000 6691/* enum: External network port 0 */ 6692#define EVB_PORT_ID_MAC0 0x2000000 6693/* enum: External network port 1 */ 6694#define EVB_PORT_ID_MAC1 0x2000001 6695/* enum: External network port 2 */ 6696#define EVB_PORT_ID_MAC2 0x2000002 6697/* enum: External network port 3 */ 6698#define EVB_PORT_ID_MAC3 0x2000003 6699#define EVB_PORT_ID_PORT_ID_LBN 0 6700#define EVB_PORT_ID_PORT_ID_WIDTH 32 6701 6702/* EVB_VLAN_TAG structuredef */ 6703#define EVB_VLAN_TAG_LEN 2 6704/* The VLAN tag value */ 6705#define EVB_VLAN_TAG_VLAN_ID_LBN 0 6706#define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 6707#define EVB_VLAN_TAG_MODE_LBN 12 6708#define EVB_VLAN_TAG_MODE_WIDTH 4 6709/* enum: Insert the VLAN. */ 6710#define EVB_VLAN_TAG_INSERT 0x0 6711/* enum: Replace the VLAN if already present. */ 6712#define EVB_VLAN_TAG_REPLACE 0x1 6713 6714/* BUFTBL_ENTRY structuredef */ 6715#define BUFTBL_ENTRY_LEN 12 6716/* the owner ID */ 6717#define BUFTBL_ENTRY_OID_OFST 0 6718#define BUFTBL_ENTRY_OID_LEN 2 6719#define BUFTBL_ENTRY_OID_LBN 0 6720#define BUFTBL_ENTRY_OID_WIDTH 16 6721/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 6722#define BUFTBL_ENTRY_PGSZ_OFST 2 6723#define BUFTBL_ENTRY_PGSZ_LEN 2 6724#define BUFTBL_ENTRY_PGSZ_LBN 16 6725#define BUFTBL_ENTRY_PGSZ_WIDTH 16 6726/* the raw 64-bit address field from the SMC, not adjusted for page size */ 6727#define BUFTBL_ENTRY_RAWADDR_OFST 4 6728#define BUFTBL_ENTRY_RAWADDR_LEN 8 6729#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 6730#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 6731#define BUFTBL_ENTRY_RAWADDR_LBN 32 6732#define BUFTBL_ENTRY_RAWADDR_WIDTH 64 6733 6734/* NVRAM_PARTITION_TYPE structuredef */ 6735#define NVRAM_PARTITION_TYPE_LEN 2 6736#define NVRAM_PARTITION_TYPE_ID_OFST 0 6737#define NVRAM_PARTITION_TYPE_ID_LEN 2 6738/* enum: Primary MC firmware partition */ 6739#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 6740/* enum: Secondary MC firmware partition */ 6741#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 6742/* enum: Expansion ROM partition */ 6743#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 6744/* enum: Static configuration TLV partition */ 6745#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 6746/* enum: Dynamic configuration TLV partition */ 6747#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 6748/* enum: Expansion ROM configuration data for port 0 */ 6749#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 6750/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 6751#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 6752/* enum: Expansion ROM configuration data for port 1 */ 6753#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 6754/* enum: Expansion ROM configuration data for port 2 */ 6755#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 6756/* enum: Expansion ROM configuration data for port 3 */ 6757#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 6758/* enum: Non-volatile log output partition */ 6759#define NVRAM_PARTITION_TYPE_LOG 0x700 6760/* enum: Non-volatile log output of second core on dual-core device */ 6761#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 6762/* enum: Device state dump output partition */ 6763#define NVRAM_PARTITION_TYPE_DUMP 0x800 6764/* enum: Application license key storage partition */ 6765#define NVRAM_PARTITION_TYPE_LICENSE 0x900 6766/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 6767#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 6768/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 6769#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 6770/* enum: Primary FPGA partition */ 6771#define NVRAM_PARTITION_TYPE_FPGA 0xb00 6772/* enum: Secondary FPGA partition */ 6773#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 6774/* enum: FC firmware partition */ 6775#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 6776/* enum: FC License partition */ 6777#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 6778/* enum: Non-volatile log output partition for FC */ 6779#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 6780/* enum: MUM firmware partition */ 6781#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 6782/* enum: SUC firmware partition (this is intentionally an alias of 6783 * MUM_FIRMWARE) 6784 */ 6785#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00 6786/* enum: MUM Non-volatile log output partition. */ 6787#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 6788/* enum: MUM Application table partition. */ 6789#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 6790/* enum: MUM boot rom partition. */ 6791#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 6792/* enum: MUM production signatures & calibration rom partition. */ 6793#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 6794/* enum: MUM user signatures & calibration rom partition. */ 6795#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 6796/* enum: MUM fuses and lockbits partition. */ 6797#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 6798/* enum: UEFI expansion ROM if separate from PXE */ 6799#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 6800/* enum: Used by the expansion ROM for logging */ 6801#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000 6802/* enum: Used for XIP code of shmbooted images */ 6803#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 6804/* enum: Spare partition 2 */ 6805#define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 6806/* enum: Manufacturing partition. Used during manufacture to pass information 6807 * between XJTAG and Manftest. 6808 */ 6809#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 6810/* enum: Spare partition 4 */ 6811#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 6812/* enum: Spare partition 5 */ 6813#define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 6814/* enum: Partition for reporting MC status. See mc_flash_layout.h 6815 * medford_mc_status_hdr_t for layout on Medford. 6816 */ 6817#define NVRAM_PARTITION_TYPE_STATUS 0x1600 6818/* enum: Spare partition 13 */ 6819#define NVRAM_PARTITION_TYPE_SPARE_13 0x1700 6820/* enum: Spare partition 14 */ 6821#define NVRAM_PARTITION_TYPE_SPARE_14 0x1800 6822/* enum: Spare partition 15 */ 6823#define NVRAM_PARTITION_TYPE_SPARE_15 0x1900 6824/* enum: Spare partition 16 */ 6825#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00 6826/* enum: Factory defaults for dynamic configuration */ 6827#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00 6828/* enum: Factory defaults for expansion ROM configuration */ 6829#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00 6830/* enum: Field Replaceable Unit inventory information for use on IPMI 6831 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a 6832 * subset of the information stored in this partition. 6833 */ 6834#define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00 6835/* enum: Start of reserved value range (firmware may use for any purpose) */ 6836#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 6837/* enum: End of reserved value range (firmware may use for any purpose) */ 6838#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 6839/* enum: Recovery partition map (provided if real map is missing or corrupt) */ 6840#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 6841/* enum: Partition map (real map as stored in flash) */ 6842#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 6843#define NVRAM_PARTITION_TYPE_ID_LBN 0 6844#define NVRAM_PARTITION_TYPE_ID_WIDTH 16 6845 6846/* LICENSED_APP_ID structuredef */ 6847#define LICENSED_APP_ID_LEN 4 6848#define LICENSED_APP_ID_ID_OFST 0 6849#define LICENSED_APP_ID_ID_LEN 4 6850/* enum: OpenOnload */ 6851#define LICENSED_APP_ID_ONLOAD 0x1 6852/* enum: PTP timestamping */ 6853#define LICENSED_APP_ID_PTP 0x2 6854/* enum: SolarCapture Pro */ 6855#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 6856/* enum: SolarSecure filter engine */ 6857#define LICENSED_APP_ID_SOLARSECURE 0x8 6858/* enum: Performance monitor */ 6859#define LICENSED_APP_ID_PERF_MONITOR 0x10 6860/* enum: SolarCapture Live */ 6861#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 6862/* enum: Capture SolarSystem */ 6863#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 6864/* enum: Network Access Control */ 6865#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 6866/* enum: TCP Direct */ 6867#define LICENSED_APP_ID_TCP_DIRECT 0x100 6868/* enum: Low Latency */ 6869#define LICENSED_APP_ID_LOW_LATENCY 0x200 6870/* enum: SolarCapture Tap */ 6871#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 6872/* enum: Capture SolarSystem 40G */ 6873#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 6874/* enum: Capture SolarSystem 1G */ 6875#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000 6876/* enum: ScaleOut Onload */ 6877#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000 6878/* enum: SCS Network Analytics Dashboard */ 6879#define LICENSED_APP_ID_DSHBRD 0x4000 6880/* enum: SolarCapture Trading Analytics */ 6881#define LICENSED_APP_ID_SCATRD 0x8000 6882#define LICENSED_APP_ID_ID_LBN 0 6883#define LICENSED_APP_ID_ID_WIDTH 32 6884 6885/* LICENSED_FEATURES structuredef */ 6886#define LICENSED_FEATURES_LEN 8 6887/* Bitmask of licensed firmware features */ 6888#define LICENSED_FEATURES_MASK_OFST 0 6889#define LICENSED_FEATURES_MASK_LEN 8 6890#define LICENSED_FEATURES_MASK_LO_OFST 0 6891#define LICENSED_FEATURES_MASK_HI_OFST 4 6892#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 6893#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 6894#define LICENSED_FEATURES_PIO_LBN 1 6895#define LICENSED_FEATURES_PIO_WIDTH 1 6896#define LICENSED_FEATURES_EVQ_TIMER_LBN 2 6897#define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 6898#define LICENSED_FEATURES_CLOCK_LBN 3 6899#define LICENSED_FEATURES_CLOCK_WIDTH 1 6900#define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 6901#define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 6902#define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 6903#define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 6904#define LICENSED_FEATURES_RX_SNIFF_LBN 6 6905#define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 6906#define LICENSED_FEATURES_TX_SNIFF_LBN 7 6907#define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 6908#define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 6909#define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 6910#define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 6911#define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 6912#define LICENSED_FEATURES_MASK_LBN 0 6913#define LICENSED_FEATURES_MASK_WIDTH 64 6914 6915/* LICENSED_V3_APPS structuredef */ 6916#define LICENSED_V3_APPS_LEN 8 6917/* Bitmask of licensed applications */ 6918#define LICENSED_V3_APPS_MASK_OFST 0 6919#define LICENSED_V3_APPS_MASK_LEN 8 6920#define LICENSED_V3_APPS_MASK_LO_OFST 0 6921#define LICENSED_V3_APPS_MASK_HI_OFST 4 6922#define LICENSED_V3_APPS_ONLOAD_LBN 0 6923#define LICENSED_V3_APPS_ONLOAD_WIDTH 1 6924#define LICENSED_V3_APPS_PTP_LBN 1 6925#define LICENSED_V3_APPS_PTP_WIDTH 1 6926#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 6927#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 6928#define LICENSED_V3_APPS_SOLARSECURE_LBN 3 6929#define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 6930#define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 6931#define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 6932#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 6933#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 6934#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 6935#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 6936#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 6937#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 6938#define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 6939#define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 6940#define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 6941#define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 6942#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 6943#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 6944#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 6945#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 6946#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 6947#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 6948#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13 6949#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1 6950#define LICENSED_V3_APPS_DSHBRD_LBN 14 6951#define LICENSED_V3_APPS_DSHBRD_WIDTH 1 6952#define LICENSED_V3_APPS_SCATRD_LBN 15 6953#define LICENSED_V3_APPS_SCATRD_WIDTH 1 6954#define LICENSED_V3_APPS_MASK_LBN 0 6955#define LICENSED_V3_APPS_MASK_WIDTH 64 6956 6957/* LICENSED_V3_FEATURES structuredef */ 6958#define LICENSED_V3_FEATURES_LEN 8 6959/* Bitmask of licensed firmware features */ 6960#define LICENSED_V3_FEATURES_MASK_OFST 0 6961#define LICENSED_V3_FEATURES_MASK_LEN 8 6962#define LICENSED_V3_FEATURES_MASK_LO_OFST 0 6963#define LICENSED_V3_FEATURES_MASK_HI_OFST 4 6964#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 6965#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 6966#define LICENSED_V3_FEATURES_PIO_LBN 1 6967#define LICENSED_V3_FEATURES_PIO_WIDTH 1 6968#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 6969#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 6970#define LICENSED_V3_FEATURES_CLOCK_LBN 3 6971#define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 6972#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 6973#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 6974#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 6975#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 6976#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 6977#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 6978#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 6979#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 6980#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 6981#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 6982#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 6983#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 6984#define LICENSED_V3_FEATURES_MASK_LBN 0 6985#define LICENSED_V3_FEATURES_MASK_WIDTH 64 6986 6987/* TX_TIMESTAMP_EVENT structuredef */ 6988#define TX_TIMESTAMP_EVENT_LEN 6 6989/* lower 16 bits of timestamp data */ 6990#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 6991#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 6992#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 6993#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 6994/* Type of TX event, ordinary TX completion, low or high part of TX timestamp 6995 */ 6996#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 6997#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 6998/* enum: This is a TX completion event, not a timestamp */ 6999#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 7000/* enum: This is a TX completion event for a CTPIO transmit. The event format 7001 * is the same as for TX_EV_COMPLETION. 7002 */ 7003#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11 7004/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The 7005 * event format is the same as for TX_EV_TSTAMP_LO 7006 */ 7007#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12 7008/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The 7009 * event format is the same as for TX_EV_TSTAMP_HI 7010 */ 7011#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13 7012/* enum: This is the low part of a TX timestamp event */ 7013#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 7014/* enum: This is the high part of a TX timestamp event */ 7015#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 7016#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 7017#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 7018/* upper 16 bits of timestamp data */ 7019#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 7020#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 7021#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 7022#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 7023 7024/* RSS_MODE structuredef */ 7025#define RSS_MODE_LEN 1 7026/* The RSS mode for a particular packet type is a value from 0 - 15 which can 7027 * be considered as 4 bits selecting which fields are included in the hash. (A 7028 * value 0 effectively disables RSS spreading for the packet type.) The YAML 7029 * generation tools require this structure to be a whole number of bytes wide, 7030 * but only 4 bits are relevant. 7031 */ 7032#define RSS_MODE_HASH_SELECTOR_OFST 0 7033#define RSS_MODE_HASH_SELECTOR_LEN 1 7034#define RSS_MODE_HASH_SRC_ADDR_LBN 0 7035#define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 7036#define RSS_MODE_HASH_DST_ADDR_LBN 1 7037#define RSS_MODE_HASH_DST_ADDR_WIDTH 1 7038#define RSS_MODE_HASH_SRC_PORT_LBN 2 7039#define RSS_MODE_HASH_SRC_PORT_WIDTH 1 7040#define RSS_MODE_HASH_DST_PORT_LBN 3 7041#define RSS_MODE_HASH_DST_PORT_WIDTH 1 7042#define RSS_MODE_HASH_SELECTOR_LBN 0 7043#define RSS_MODE_HASH_SELECTOR_WIDTH 8 7044 7045/* CTPIO_STATS_MAP structuredef */ 7046#define CTPIO_STATS_MAP_LEN 4 7047/* The (function relative) VI number */ 7048#define CTPIO_STATS_MAP_VI_OFST 0 7049#define CTPIO_STATS_MAP_VI_LEN 2 7050#define CTPIO_STATS_MAP_VI_LBN 0 7051#define CTPIO_STATS_MAP_VI_WIDTH 16 7052/* The target bucket for the VI */ 7053#define CTPIO_STATS_MAP_BUCKET_OFST 2 7054#define CTPIO_STATS_MAP_BUCKET_LEN 2 7055#define CTPIO_STATS_MAP_BUCKET_LBN 16 7056#define CTPIO_STATS_MAP_BUCKET_WIDTH 16 7057 7058/* MESSAGE_TYPE structuredef: When present this defines the meaning of a 7059 * message, and is used to protect against chosen message attacks in signed 7060 * messages, regardless their origin. The message type also defines the 7061 * signature cryptographic algorithm, encoding, and message fields included in 7062 * the signature. The values are used in different commands but must be unique 7063 * across all commands, e.g. MC_CMD_TSA_BIND_IN_SECURE_UNBIND uses different 7064 * message type than MC_CMD_SECURE_NIC_INFO_IN_STATUS. 7065 */ 7066#define MESSAGE_TYPE_LEN 4 7067#define MESSAGE_TYPE_MESSAGE_TYPE_OFST 0 7068#define MESSAGE_TYPE_MESSAGE_TYPE_LEN 4 7069#define MESSAGE_TYPE_UNUSED 0x0 /* enum */ 7070/* enum: Message type value for the response to a 7071 * MC_CMD_TSA_BIND_IN_SECURE_UNBIND message. TSA_SECURE_UNBIND messages are 7072 * ECDSA SECP384R1 signed using SHA384 message digest algorithm over fields 7073 * MESSAGE_TYPE, TSANID, TSAID, and UNBINDTOKEN, and encoded as suggested by 7074 * RFC6979 (section 2.4). 7075 */ 7076#define MESSAGE_TYPE_TSA_SECURE_UNBIND 0x1 7077/* enum: Message type value for the response to a 7078 * MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION message. TSA_SECURE_DECOMMISSION 7079 * messages are ECDSA SECP384R1 signed using SHA384 message digest algorithm 7080 * over fields MESSAGE_TYPE, TSAID, USER, and REASON, and encoded as suggested 7081 * by RFC6979 (section 2.4). 7082 */ 7083#define MESSAGE_TYPE_TSA_SECURE_DECOMMISSION 0x2 7084/* enum: Message type value for the response to a 7085 * MC_CMD_SECURE_NIC_INFO_IN_STATUS message. This enum value is not sequential 7086 * to other message types for backwards compatibility as the message type for 7087 * MC_CMD_SECURE_NIC_INFO_IN_STATUS was defined before the existence of this 7088 * global enum. 7089 */ 7090#define MESSAGE_TYPE_SECURE_NIC_INFO_STATUS 0xdb4 7091#define MESSAGE_TYPE_MESSAGE_TYPE_LBN 0 7092#define MESSAGE_TYPE_MESSAGE_TYPE_WIDTH 32 7093 7094/***********************************/ 7095/* MC_CMD_READ_REGS 7096 * Get a dump of the MCPU registers 7097 */ 7098#define MC_CMD_READ_REGS 0x50 7099#undef MC_CMD_0x50_PRIVILEGE_CTG 7100 7101#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE 7102 7103/* MC_CMD_READ_REGS_IN msgrequest */ 7104#define MC_CMD_READ_REGS_IN_LEN 0 7105 7106/* MC_CMD_READ_REGS_OUT msgresponse */ 7107#define MC_CMD_READ_REGS_OUT_LEN 308 7108/* Whether the corresponding register entry contains a valid value */ 7109#define MC_CMD_READ_REGS_OUT_MASK_OFST 0 7110#define MC_CMD_READ_REGS_OUT_MASK_LEN 16 7111/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 7112 * fir, fp) 7113 */ 7114#define MC_CMD_READ_REGS_OUT_REGS_OFST 16 7115#define MC_CMD_READ_REGS_OUT_REGS_LEN 4 7116#define MC_CMD_READ_REGS_OUT_REGS_NUM 73 7117 7118/***********************************/ 7119/* MC_CMD_INIT_EVQ 7120 * Set up an event queue according to the supplied parameters. The IN arguments 7121 * end with an address for each 4k of host memory required to back the EVQ. 7122 */ 7123#define MC_CMD_INIT_EVQ 0x80 7124#undef MC_CMD_0x80_PRIVILEGE_CTG 7125 7126#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7127 7128/* MC_CMD_INIT_EVQ_IN msgrequest */ 7129#define MC_CMD_INIT_EVQ_IN_LENMIN 44 7130#define MC_CMD_INIT_EVQ_IN_LENMAX 548 7131#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 7132/* Size, in entries */ 7133#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 7134#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4 7135/* Desired instance. Must be set to a specific instance, which is a function 7136 * local queue index. 7137 */ 7138#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 7139#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4 7140/* The initial timer value. The load value is ignored if the timer mode is DIS. 7141 */ 7142#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 7143#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4 7144/* The reload value is ignored in one-shot modes */ 7145#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 7146#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4 7147/* tbd */ 7148#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 7149#define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4 7150#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 7151#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 7152#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 7153#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 7154#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 7155#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 7156#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 7157#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 7158#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 7159#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 7160#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 7161#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 7162#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 7163#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 7164#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 7165#define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4 7166/* enum: Disabled */ 7167#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 7168/* enum: Immediate */ 7169#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 7170/* enum: Triggered */ 7171#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 7172/* enum: Hold-off */ 7173#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 7174/* Target EVQ for wakeups if in wakeup mode. */ 7175#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 7176#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4 7177/* Target interrupt if in interrupting mode (note union with target EVQ). Use 7178 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 7179 * purposes. 7180 */ 7181#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 7182#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4 7183/* Event Counter Mode. */ 7184#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 7185#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4 7186/* enum: Disabled */ 7187#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 7188/* enum: Disabled */ 7189#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 7190/* enum: Disabled */ 7191#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 7192/* enum: Disabled */ 7193#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 7194/* Event queue packet count threshold. */ 7195#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 7196#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4 7197/* 64-bit address of 4k of 4k-aligned host memory buffer */ 7198#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 7199#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 7200#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 7201#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 7202#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 7203#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 7204 7205/* MC_CMD_INIT_EVQ_OUT msgresponse */ 7206#define MC_CMD_INIT_EVQ_OUT_LEN 4 7207/* Only valid if INTRFLAG was true */ 7208#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 7209#define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4 7210 7211/* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 7212#define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 7213#define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 7214#define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 7215/* Size, in entries */ 7216#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 7217#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4 7218/* Desired instance. Must be set to a specific instance, which is a function 7219 * local queue index. 7220 */ 7221#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 7222#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4 7223/* The initial timer value. The load value is ignored if the timer mode is DIS. 7224 */ 7225#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 7226#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4 7227/* The reload value is ignored in one-shot modes */ 7228#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 7229#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4 7230/* tbd */ 7231#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 7232#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4 7233#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 7234#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 7235#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 7236#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 7237#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 7238#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 7239#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 7240#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 7241#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 7242#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 7243#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 7244#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 7245#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 7246#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 7247#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 7248#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 7249/* enum: All initialisation flags specified by host. */ 7250#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 7251/* enum: MEDFORD only. Certain initialisation flags specified by host may be 7252 * over-ridden by firmware based on licenses and firmware variant in order to 7253 * provide the lowest latency achievable. See 7254 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7255 */ 7256#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 7257/* enum: MEDFORD only. Certain initialisation flags specified by host may be 7258 * over-ridden by firmware based on licenses and firmware variant in order to 7259 * provide the best throughput achievable. See 7260 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7261 */ 7262#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 7263/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 7264 * firmware based on licenses and firmware variant. See 7265 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7266 */ 7267#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 7268#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 7269#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4 7270/* enum: Disabled */ 7271#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 7272/* enum: Immediate */ 7273#define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 7274/* enum: Triggered */ 7275#define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 7276/* enum: Hold-off */ 7277#define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 7278/* Target EVQ for wakeups if in wakeup mode. */ 7279#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 7280#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4 7281/* Target interrupt if in interrupting mode (note union with target EVQ). Use 7282 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 7283 * purposes. 7284 */ 7285#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 7286#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4 7287/* Event Counter Mode. */ 7288#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 7289#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4 7290/* enum: Disabled */ 7291#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 7292/* enum: Disabled */ 7293#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 7294/* enum: Disabled */ 7295#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 7296/* enum: Disabled */ 7297#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 7298/* Event queue packet count threshold. */ 7299#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 7300#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4 7301/* 64-bit address of 4k of 4k-aligned host memory buffer */ 7302#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 7303#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 7304#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 7305#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 7306#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 7307#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 7308 7309/* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 7310#define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 7311/* Only valid if INTRFLAG was true */ 7312#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 7313#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4 7314/* Actual configuration applied on the card */ 7315#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 7316#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4 7317#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 7318#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 7319#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 7320#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 7321#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 7322#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 7323#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 7324#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 7325 7326/* QUEUE_CRC_MODE structuredef */ 7327#define QUEUE_CRC_MODE_LEN 1 7328#define QUEUE_CRC_MODE_MODE_LBN 0 7329#define QUEUE_CRC_MODE_MODE_WIDTH 4 7330/* enum: No CRC. */ 7331#define QUEUE_CRC_MODE_NONE 0x0 7332/* enum: CRC Fiber channel over ethernet. */ 7333#define QUEUE_CRC_MODE_FCOE 0x1 7334/* enum: CRC (digest) iSCSI header only. */ 7335#define QUEUE_CRC_MODE_ISCSI_HDR 0x2 7336/* enum: CRC (digest) iSCSI header and payload. */ 7337#define QUEUE_CRC_MODE_ISCSI 0x3 7338/* enum: CRC Fiber channel over IP over ethernet. */ 7339#define QUEUE_CRC_MODE_FCOIPOE 0x4 7340/* enum: CRC MPA. */ 7341#define QUEUE_CRC_MODE_MPA 0x5 7342#define QUEUE_CRC_MODE_SPARE_LBN 4 7343#define QUEUE_CRC_MODE_SPARE_WIDTH 4 7344 7345/***********************************/ 7346/* MC_CMD_INIT_RXQ 7347 * set up a receive queue according to the supplied parameters. The IN 7348 * arguments end with an address for each 4k of host memory required to back 7349 * the RXQ. 7350 */ 7351#define MC_CMD_INIT_RXQ 0x81 7352#undef MC_CMD_0x81_PRIVILEGE_CTG 7353 7354#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7355 7356/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 7357 * in new code. 7358 */ 7359#define MC_CMD_INIT_RXQ_IN_LENMIN 36 7360#define MC_CMD_INIT_RXQ_IN_LENMAX 252 7361#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 7362/* Size, in entries */ 7363#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 7364#define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4 7365/* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7366 */ 7367#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 7368#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4 7369/* The value to put in the event data. Check hardware spec. for valid range. */ 7370#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 7371#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4 7372/* Desired instance. Must be set to a specific instance, which is a function 7373 * local queue index. 7374 */ 7375#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 7376#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4 7377/* There will be more flags here. */ 7378#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 7379#define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4 7380#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 7381#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7382#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 7383#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 7384#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 7385#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7386#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 7387#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 7388#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 7389#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 7390#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 7391#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 7392#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 7393#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7394#define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 7395#define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 7396/* Owner ID to use if in buffer mode (zero if physical) */ 7397#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 7398#define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4 7399/* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7400#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 7401#define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4 7402/* 64-bit address of 4k of 4k-aligned host memory buffer */ 7403#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 7404#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 7405#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 7406#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 7407#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 7408#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 7409 7410/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 7411 * flags 7412 */ 7413#define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 7414/* Size, in entries */ 7415#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 7416#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4 7417/* The EVQ to send events to. This is an index originally specified to 7418 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 7419 */ 7420#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 7421#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4 7422/* The value to put in the event data. Check hardware spec. for valid range. 7423 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 7424 * == PACKED_STREAM. 7425 */ 7426#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 7427#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4 7428/* Desired instance. Must be set to a specific instance, which is a function 7429 * local queue index. 7430 */ 7431#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 7432#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4 7433/* There will be more flags here. */ 7434#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 7435#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4 7436#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7437#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7438#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 7439#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 7440#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 7441#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7442#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 7443#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 7444#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 7445#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 7446#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 7447#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 7448#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 7449#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7450#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 7451#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 7452/* enum: One packet per descriptor (for normal networking) */ 7453#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 7454/* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 7455#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 7456/* enum: Pack multiple packets into large descriptors using the format designed 7457 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 7458 * multiple fixed-size packet buffers within each bucket. For a full 7459 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 7460 * firmware. 7461 */ 7462#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 7463/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 7464#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 7465#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 7466#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 7467#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 7468#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 7469#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 7470#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 7471#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 7472#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 7473#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 7474#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 7475#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 7476#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 7477#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 7478/* Owner ID to use if in buffer mode (zero if physical) */ 7479#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 7480#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4 7481/* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7482#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 7483#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4 7484/* 64-bit address of 4k of 4k-aligned host memory buffer */ 7485#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 7486#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 7487#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7488#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7489#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 7490/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 7491#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 7492#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4 7493 7494/* MC_CMD_INIT_RXQ_V3_IN msgrequest */ 7495#define MC_CMD_INIT_RXQ_V3_IN_LEN 560 7496/* Size, in entries */ 7497#define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0 7498#define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4 7499/* The EVQ to send events to. This is an index originally specified to 7500 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 7501 */ 7502#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4 7503#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4 7504/* The value to put in the event data. Check hardware spec. for valid range. 7505 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 7506 * == PACKED_STREAM. 7507 */ 7508#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8 7509#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4 7510/* Desired instance. Must be set to a specific instance, which is a function 7511 * local queue index. 7512 */ 7513#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12 7514#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4 7515/* There will be more flags here. */ 7516#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16 7517#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4 7518#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0 7519#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1 7520#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1 7521#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1 7522#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2 7523#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1 7524#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3 7525#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4 7526#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7 7527#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1 7528#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8 7529#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1 7530#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9 7531#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7532#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10 7533#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4 7534/* enum: One packet per descriptor (for normal networking) */ 7535#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0 7536/* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 7537#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1 7538/* enum: Pack multiple packets into large descriptors using the format designed 7539 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 7540 * multiple fixed-size packet buffers within each bucket. For a full 7541 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 7542 * firmware. 7543 */ 7544#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 7545/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 7546#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 7547#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14 7548#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 7549#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 7550#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 7551#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */ 7552#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */ 7553#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */ 7554#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */ 7555#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */ 7556#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 7557#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 7558#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19 7559#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 7560/* Owner ID to use if in buffer mode (zero if physical) */ 7561#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20 7562#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4 7563/* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7564#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24 7565#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4 7566/* 64-bit address of 4k of 4k-aligned host memory buffer */ 7567#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28 7568#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8 7569#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28 7570#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32 7571#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64 7572/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 7573#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540 7574#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4 7575/* The number of packet buffers that will be contained within each 7576 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field 7577 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7578 */ 7579#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 7580#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 7581/* The length in bytes of the area in each packet buffer that can be written to 7582 * by the adapter. This is used to store the packet prefix and the packet 7583 * payload. This length does not include any end padding added by the driver. 7584 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7585 */ 7586#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548 7587#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4 7588/* The length in bytes of a single packet buffer within a 7589 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless 7590 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7591 */ 7592#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552 7593#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4 7594/* The maximum time in nanoseconds that the datapath will be backpressured if 7595 * there are no RX descriptors available. If the timeout is reached and there 7596 * are still no descriptors then the packet will be dropped. A timeout of 0 7597 * means the datapath will never be blocked. This field is ignored unless 7598 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7599 */ 7600#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 7601#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4 7602 7603/* MC_CMD_INIT_RXQ_OUT msgresponse */ 7604#define MC_CMD_INIT_RXQ_OUT_LEN 0 7605 7606/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 7607#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 7608 7609/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */ 7610#define MC_CMD_INIT_RXQ_V3_OUT_LEN 0 7611 7612/***********************************/ 7613/* MC_CMD_INIT_TXQ 7614 */ 7615#define MC_CMD_INIT_TXQ 0x82 7616#undef MC_CMD_0x82_PRIVILEGE_CTG 7617 7618#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7619 7620/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 7621 * in new code. 7622 */ 7623#define MC_CMD_INIT_TXQ_IN_LENMIN 36 7624#define MC_CMD_INIT_TXQ_IN_LENMAX 252 7625#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 7626/* Size, in entries */ 7627#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 7628#define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4 7629/* The EVQ to send events to. This is an index originally specified to 7630 * INIT_EVQ. 7631 */ 7632#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 7633#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4 7634/* The value to put in the event data. Check hardware spec. for valid range. */ 7635#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 7636#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4 7637/* Desired instance. Must be set to a specific instance, which is a function 7638 * local queue index. 7639 */ 7640#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 7641#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4 7642/* There will be more flags here. */ 7643#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 7644#define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4 7645#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 7646#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7647#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 7648#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7649#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 7650#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7651#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 7652#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7653#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 7654#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 7655#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 7656#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7657#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 7658#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 7659#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7660#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7661#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7662#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7663/* Owner ID to use if in buffer mode (zero if physical) */ 7664#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 7665#define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4 7666/* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7667#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 7668#define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4 7669/* 64-bit address of 4k of 4k-aligned host memory buffer */ 7670#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 7671#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 7672#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 7673#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 7674#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 7675#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 7676 7677/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 7678 * flags 7679 */ 7680#define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 7681/* Size, in entries */ 7682#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 7683#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4 7684/* The EVQ to send events to. This is an index originally specified to 7685 * INIT_EVQ. 7686 */ 7687#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 7688#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4 7689/* The value to put in the event data. Check hardware spec. for valid range. */ 7690#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 7691#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4 7692/* Desired instance. Must be set to a specific instance, which is a function 7693 * local queue index. 7694 */ 7695#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 7696#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4 7697/* There will be more flags here. */ 7698#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 7699#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4 7700#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7701#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7702#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 7703#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7704#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 7705#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7706#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 7707#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7708#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 7709#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 7710#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 7711#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7712#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 7713#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 7714#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7715#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7716#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7717#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7718#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 7719#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 7720#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 7721#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 7722#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14 7723#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1 7724/* Owner ID to use if in buffer mode (zero if physical) */ 7725#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 7726#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4 7727/* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7728#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 7729#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4 7730/* 64-bit address of 4k of 4k-aligned host memory buffer */ 7731#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 7732#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 7733#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7734#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7735#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 7736#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 7737/* Flags related to Qbb flow control mode. */ 7738#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 7739#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4 7740#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 7741#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 7742#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 7743#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 7744 7745/* MC_CMD_INIT_TXQ_OUT msgresponse */ 7746#define MC_CMD_INIT_TXQ_OUT_LEN 0 7747 7748/***********************************/ 7749/* MC_CMD_FINI_EVQ 7750 * Teardown an EVQ. 7751 * 7752 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 7753 * or the operation will fail with EBUSY 7754 */ 7755#define MC_CMD_FINI_EVQ 0x83 7756#undef MC_CMD_0x83_PRIVILEGE_CTG 7757 7758#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7759 7760/* MC_CMD_FINI_EVQ_IN msgrequest */ 7761#define MC_CMD_FINI_EVQ_IN_LEN 4 7762/* Instance of EVQ to destroy. Should be the same instance as that previously 7763 * passed to INIT_EVQ 7764 */ 7765#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 7766#define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4 7767 7768/* MC_CMD_FINI_EVQ_OUT msgresponse */ 7769#define MC_CMD_FINI_EVQ_OUT_LEN 0 7770 7771/***********************************/ 7772/* MC_CMD_FINI_RXQ 7773 * Teardown a RXQ. 7774 */ 7775#define MC_CMD_FINI_RXQ 0x84 7776#undef MC_CMD_0x84_PRIVILEGE_CTG 7777 7778#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7779 7780/* MC_CMD_FINI_RXQ_IN msgrequest */ 7781#define MC_CMD_FINI_RXQ_IN_LEN 4 7782/* Instance of RXQ to destroy */ 7783#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 7784#define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4 7785 7786/* MC_CMD_FINI_RXQ_OUT msgresponse */ 7787#define MC_CMD_FINI_RXQ_OUT_LEN 0 7788 7789/***********************************/ 7790/* MC_CMD_FINI_TXQ 7791 * Teardown a TXQ. 7792 */ 7793#define MC_CMD_FINI_TXQ 0x85 7794#undef MC_CMD_0x85_PRIVILEGE_CTG 7795 7796#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7797 7798/* MC_CMD_FINI_TXQ_IN msgrequest */ 7799#define MC_CMD_FINI_TXQ_IN_LEN 4 7800/* Instance of TXQ to destroy */ 7801#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 7802#define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4 7803 7804/* MC_CMD_FINI_TXQ_OUT msgresponse */ 7805#define MC_CMD_FINI_TXQ_OUT_LEN 0 7806 7807/***********************************/ 7808/* MC_CMD_DRIVER_EVENT 7809 * Generate an event on an EVQ belonging to the function issuing the command. 7810 */ 7811#define MC_CMD_DRIVER_EVENT 0x86 7812#undef MC_CMD_0x86_PRIVILEGE_CTG 7813 7814#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7815 7816/* MC_CMD_DRIVER_EVENT_IN msgrequest */ 7817#define MC_CMD_DRIVER_EVENT_IN_LEN 12 7818/* Handle of target EVQ */ 7819#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 7820#define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4 7821/* Bits 0 - 63 of event */ 7822#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 7823#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 7824#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 7825#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 7826 7827/* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 7828#define MC_CMD_DRIVER_EVENT_OUT_LEN 0 7829 7830/***********************************/ 7831/* MC_CMD_PROXY_CMD 7832 * Execute an arbitrary MCDI command on behalf of a different function, subject 7833 * to security restrictions. The command to be proxied follows immediately 7834 * afterward in the host buffer (or on the UART). This command supercedes 7835 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 7836 */ 7837#define MC_CMD_PROXY_CMD 0x5b 7838#undef MC_CMD_0x5b_PRIVILEGE_CTG 7839 7840#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7841 7842/* MC_CMD_PROXY_CMD_IN msgrequest */ 7843#define MC_CMD_PROXY_CMD_IN_LEN 4 7844/* The handle of the target function. */ 7845#define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 7846#define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4 7847#define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 7848#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 7849#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 7850#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 7851#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 7852 7853/* MC_CMD_PROXY_CMD_OUT msgresponse */ 7854#define MC_CMD_PROXY_CMD_OUT_LEN 0 7855 7856/* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 7857 * manage proxied requests 7858 */ 7859#define MC_PROXY_STATUS_BUFFER_LEN 16 7860/* Handle allocated by the firmware for this proxy transaction */ 7861#define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 7862#define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4 7863/* enum: An invalid handle. */ 7864#define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 7865#define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 7866#define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 7867/* The requesting physical function number */ 7868#define MC_PROXY_STATUS_BUFFER_PF_OFST 4 7869#define MC_PROXY_STATUS_BUFFER_PF_LEN 2 7870#define MC_PROXY_STATUS_BUFFER_PF_LBN 32 7871#define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 7872/* The requesting virtual function number. Set to VF_NULL if the target is a 7873 * PF. 7874 */ 7875#define MC_PROXY_STATUS_BUFFER_VF_OFST 6 7876#define MC_PROXY_STATUS_BUFFER_VF_LEN 2 7877#define MC_PROXY_STATUS_BUFFER_VF_LBN 48 7878#define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 7879/* The target function RID. */ 7880#define MC_PROXY_STATUS_BUFFER_RID_OFST 8 7881#define MC_PROXY_STATUS_BUFFER_RID_LEN 2 7882#define MC_PROXY_STATUS_BUFFER_RID_LBN 64 7883#define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 7884/* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 7885#define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 7886#define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 7887#define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 7888#define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 7889/* If a request is authorized rather than carried out by the host, this is the 7890 * elevated privilege mask granted to the requesting function. 7891 */ 7892#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 7893#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4 7894#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 7895#define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 7896 7897/***********************************/ 7898/* MC_CMD_PROXY_CONFIGURE 7899 * Enable/disable authorization of MCDI requests from unprivileged functions by 7900 * a designated admin function 7901 */ 7902#define MC_CMD_PROXY_CONFIGURE 0x58 7903#undef MC_CMD_0x58_PRIVILEGE_CTG 7904 7905#define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7906 7907/* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 7908#define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 7909#define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 7910#define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4 7911#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 7912#define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 7913/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7914 * of blocks, each of the size REQUEST_BLOCK_SIZE. 7915 */ 7916#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 7917#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 7918#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 7919#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 7920/* Must be a power of 2 */ 7921#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 7922#define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4 7923/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7924 * of blocks, each of the size REPLY_BLOCK_SIZE. 7925 */ 7926#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 7927#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 7928#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 7929#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 7930/* Must be a power of 2 */ 7931#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 7932#define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4 7933/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7934 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 7935 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 7936 */ 7937#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 7938#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 7939#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 7940#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 7941/* Must be a power of 2, or zero if this buffer is not provided */ 7942#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 7943#define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4 7944/* Applies to all three buffers */ 7945#define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 7946#define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4 7947/* A bit mask defining which MCDI operations may be proxied */ 7948#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 7949#define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 7950 7951/* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 7952#define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 7953#define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 7954#define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4 7955#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 7956#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 7957/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7958 * of blocks, each of the size REQUEST_BLOCK_SIZE. 7959 */ 7960#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 7961#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 7962#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 7963#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 7964/* Must be a power of 2 */ 7965#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 7966#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4 7967/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7968 * of blocks, each of the size REPLY_BLOCK_SIZE. 7969 */ 7970#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 7971#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 7972#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 7973#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 7974/* Must be a power of 2 */ 7975#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 7976#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4 7977/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7978 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 7979 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 7980 */ 7981#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 7982#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 7983#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 7984#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 7985/* Must be a power of 2, or zero if this buffer is not provided */ 7986#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 7987#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4 7988/* Applies to all three buffers */ 7989#define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 7990#define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4 7991/* A bit mask defining which MCDI operations may be proxied */ 7992#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 7993#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 7994#define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 7995#define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4 7996 7997/* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 7998#define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 7999 8000/***********************************/ 8001/* MC_CMD_PROXY_COMPLETE 8002 * Tells FW that a requested proxy operation has either been completed (by 8003 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 8004 * function that enabled proxying/authorization (by using 8005 * MC_CMD_PROXY_CONFIGURE). 8006 */ 8007#define MC_CMD_PROXY_COMPLETE 0x5f 8008#undef MC_CMD_0x5f_PRIVILEGE_CTG 8009 8010#define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8011 8012/* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 8013#define MC_CMD_PROXY_COMPLETE_IN_LEN 12 8014#define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 8015#define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4 8016#define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 8017#define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4 8018/* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 8019 * is stored in the REPLY_BUFF. 8020 */ 8021#define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 8022/* enum: The operation has been authorized. The originating function may now 8023 * try again. 8024 */ 8025#define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 8026/* enum: The operation has been declined. */ 8027#define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 8028/* enum: The authorization failed because the relevant application did not 8029 * respond in time. 8030 */ 8031#define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 8032#define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 8033#define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4 8034 8035/* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 8036#define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 8037 8038/***********************************/ 8039/* MC_CMD_ALLOC_BUFTBL_CHUNK 8040 * Allocate a set of buffer table entries using the specified owner ID. This 8041 * operation allocates the required buffer table entries (and fails if it 8042 * cannot do so). The buffer table entries will initially be zeroed. 8043 */ 8044#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 8045#undef MC_CMD_0x87_PRIVILEGE_CTG 8046 8047#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8048 8049/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 8050#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 8051/* Owner ID to use */ 8052#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 8053#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4 8054/* Size of buffer table pages to use, in bytes (note that only a few values are 8055 * legal on any specific hardware). 8056 */ 8057#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 8058#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4 8059 8060/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 8061#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 8062#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 8063#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4 8064#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 8065#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4 8066/* Buffer table IDs for use in DMA descriptors. */ 8067#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 8068#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4 8069 8070/***********************************/ 8071/* MC_CMD_PROGRAM_BUFTBL_ENTRIES 8072 * Reprogram a set of buffer table entries in the specified chunk. 8073 */ 8074#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 8075#undef MC_CMD_0x88_PRIVILEGE_CTG 8076 8077#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8078 8079/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 8080#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 8081#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 8082#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 8083#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 8084#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4 8085/* ID */ 8086#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 8087#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 8088/* Num entries */ 8089#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 8090#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 8091/* Buffer table entry address */ 8092#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 8093#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 8094#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 8095#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 8096#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 8097#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 8098 8099/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 8100#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 8101 8102/***********************************/ 8103/* MC_CMD_FREE_BUFTBL_CHUNK 8104 */ 8105#define MC_CMD_FREE_BUFTBL_CHUNK 0x89 8106#undef MC_CMD_0x89_PRIVILEGE_CTG 8107 8108#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8109 8110/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 8111#define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 8112#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 8113#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4 8114 8115/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 8116#define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 8117 8118/***********************************/ 8119/* MC_CMD_FILTER_OP 8120 * Multiplexed MCDI call for filter operations 8121 */ 8122#define MC_CMD_FILTER_OP 0x8a 8123#undef MC_CMD_0x8a_PRIVILEGE_CTG 8124 8125#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8126 8127/* MC_CMD_FILTER_OP_IN msgrequest */ 8128#define MC_CMD_FILTER_OP_IN_LEN 108 8129/* identifies the type of operation requested */ 8130#define MC_CMD_FILTER_OP_IN_OP_OFST 0 8131#define MC_CMD_FILTER_OP_IN_OP_LEN 4 8132/* enum: single-recipient filter insert */ 8133#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 8134/* enum: single-recipient filter remove */ 8135#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 8136/* enum: multi-recipient filter subscribe */ 8137#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 8138/* enum: multi-recipient filter unsubscribe */ 8139#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 8140/* enum: replace one recipient with another (warning - the filter handle may 8141 * change) 8142 */ 8143#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 8144/* filter handle (for remove / unsubscribe operations) */ 8145#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 8146#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 8147#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 8148#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 8149/* The port ID associated with the v-adaptor which should contain this filter. 8150 */ 8151#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 8152#define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4 8153/* fields to include in match criteria */ 8154#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 8155#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4 8156#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 8157#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 8158#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 8159#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 8160#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 8161#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 8162#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 8163#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 8164#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 8165#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 8166#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 8167#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 8168#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 8169#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 8170#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 8171#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 8172#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 8173#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 8174#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 8175#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 8176#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 8177#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 8178#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 8179#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 8180#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8181#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8182#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8183#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8184/* receive destination */ 8185#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 8186#define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4 8187/* enum: drop packets */ 8188#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 8189/* enum: receive to host */ 8190#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 8191/* enum: receive to MC */ 8192#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 8193/* enum: loop back to TXDP 0 */ 8194#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 8195/* enum: loop back to TXDP 1 */ 8196#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 8197/* receive queue handle (for multiple queue modes, this is the base queue) */ 8198#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 8199#define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4 8200/* receive mode */ 8201#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 8202#define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4 8203/* enum: receive to just the specified queue */ 8204#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 8205/* enum: receive to multiple queues using RSS context */ 8206#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 8207/* enum: receive to multiple queues using .1p mapping */ 8208#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 8209/* enum: install a filter entry that will never match; for test purposes only 8210 */ 8211#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8212/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8213 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8214 * MC_CMD_DOT1P_MAPPING_ALLOC. 8215 */ 8216#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 8217#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4 8218/* transmit domain (reserved; set to 0) */ 8219#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 8220#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4 8221/* transmit destination (either set the MAC and/or PM bits for explicit 8222 * control, or set this field to TX_DEST_DEFAULT for sensible default 8223 * behaviour) 8224 */ 8225#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 8226#define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4 8227/* enum: request default behaviour (based on filter type) */ 8228#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 8229#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 8230#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 8231#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 8232#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 8233/* source MAC address to match (as bytes in network order) */ 8234#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 8235#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 8236/* source port to match (as bytes in network order) */ 8237#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 8238#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 8239/* destination MAC address to match (as bytes in network order) */ 8240#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 8241#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 8242/* destination port to match (as bytes in network order) */ 8243#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 8244#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 8245/* Ethernet type to match (as bytes in network order) */ 8246#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 8247#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 8248/* Inner VLAN tag to match (as bytes in network order) */ 8249#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 8250#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 8251/* Outer VLAN tag to match (as bytes in network order) */ 8252#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 8253#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 8254/* IP protocol to match (in low byte; set high byte to 0) */ 8255#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 8256#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 8257/* Firmware defined register 0 to match (reserved; set to 0) */ 8258#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 8259#define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4 8260/* Firmware defined register 1 to match (reserved; set to 0) */ 8261#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 8262#define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4 8263/* source IP address to match (as bytes in network order; set last 12 bytes to 8264 * 0 for IPv4 address) 8265 */ 8266#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 8267#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 8268/* destination IP address to match (as bytes in network order; set last 12 8269 * bytes to 0 for IPv4 address) 8270 */ 8271#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 8272#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 8273 8274/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 8275 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 8276 * supported on Medford only). 8277 */ 8278#define MC_CMD_FILTER_OP_EXT_IN_LEN 172 8279/* identifies the type of operation requested */ 8280#define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 8281#define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4 8282/* Enum values, see field(s): */ 8283/* MC_CMD_FILTER_OP_IN/OP */ 8284/* filter handle (for remove / unsubscribe operations) */ 8285#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 8286#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 8287#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 8288#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 8289/* The port ID associated with the v-adaptor which should contain this filter. 8290 */ 8291#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 8292#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4 8293/* fields to include in match criteria */ 8294#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 8295#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4 8296#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 8297#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 8298#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 8299#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 8300#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 8301#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 8302#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 8303#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 8304#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 8305#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 8306#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 8307#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 8308#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 8309#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 8310#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 8311#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 8312#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 8313#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 8314#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 8315#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 8316#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 8317#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 8318#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 8319#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 8320#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 8321#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 8322#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 8323#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 8324#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 8325#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 8326#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 8327#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 8328#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 8329#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 8330#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 8331#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 8332#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 8333#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 8334#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 8335#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 8336#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 8337#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 8338#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 8339#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 8340#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 8341#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 8342#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 8343#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 8344#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 8345#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 8346#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 8347#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 8348#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8349#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8350#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8351#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8352/* receive destination */ 8353#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 8354#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4 8355/* enum: drop packets */ 8356#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 8357/* enum: receive to host */ 8358#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 8359/* enum: receive to MC */ 8360#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 8361/* enum: loop back to TXDP 0 */ 8362#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 8363/* enum: loop back to TXDP 1 */ 8364#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 8365/* receive queue handle (for multiple queue modes, this is the base queue) */ 8366#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 8367#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4 8368/* receive mode */ 8369#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 8370#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4 8371/* enum: receive to just the specified queue */ 8372#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 8373/* enum: receive to multiple queues using RSS context */ 8374#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 8375/* enum: receive to multiple queues using .1p mapping */ 8376#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 8377/* enum: install a filter entry that will never match; for test purposes only 8378 */ 8379#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8380/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8381 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8382 * MC_CMD_DOT1P_MAPPING_ALLOC. 8383 */ 8384#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 8385#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4 8386/* transmit domain (reserved; set to 0) */ 8387#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 8388#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4 8389/* transmit destination (either set the MAC and/or PM bits for explicit 8390 * control, or set this field to TX_DEST_DEFAULT for sensible default 8391 * behaviour) 8392 */ 8393#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 8394#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4 8395/* enum: request default behaviour (based on filter type) */ 8396#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 8397#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 8398#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 8399#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 8400#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 8401/* source MAC address to match (as bytes in network order) */ 8402#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 8403#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 8404/* source port to match (as bytes in network order) */ 8405#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 8406#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 8407/* destination MAC address to match (as bytes in network order) */ 8408#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 8409#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 8410/* destination port to match (as bytes in network order) */ 8411#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 8412#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 8413/* Ethernet type to match (as bytes in network order) */ 8414#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 8415#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 8416/* Inner VLAN tag to match (as bytes in network order) */ 8417#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 8418#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 8419/* Outer VLAN tag to match (as bytes in network order) */ 8420#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 8421#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 8422/* IP protocol to match (in low byte; set high byte to 0) */ 8423#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 8424#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 8425/* Firmware defined register 0 to match (reserved; set to 0) */ 8426#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 8427#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4 8428/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 8429 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 8430 * VXLAN/NVGRE, or 1 for Geneve) 8431 */ 8432#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 8433#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4 8434#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 8435#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 8436#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 8437#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 8438/* enum: Match VXLAN traffic with this VNI */ 8439#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 8440/* enum: Match Geneve traffic with this VNI */ 8441#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 8442/* enum: Reserved for experimental development use */ 8443#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 8444#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 8445#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 8446#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 8447#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 8448/* enum: Match NVGRE traffic with this VSID */ 8449#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 8450/* source IP address to match (as bytes in network order; set last 12 bytes to 8451 * 0 for IPv4 address) 8452 */ 8453#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 8454#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 8455/* destination IP address to match (as bytes in network order; set last 12 8456 * bytes to 0 for IPv4 address) 8457 */ 8458#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 8459#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 8460/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 8461 * order) 8462 */ 8463#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 8464#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 8465/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 8466#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 8467#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 8468/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 8469 * network order) 8470 */ 8471#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 8472#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 8473/* VXLAN/NVGRE inner frame destination port to match (as bytes in network 8474 * order) 8475 */ 8476#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 8477#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 8478/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 8479 */ 8480#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 8481#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 8482/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 8483 */ 8484#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 8485#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 8486/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 8487 */ 8488#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 8489#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 8490/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 8491 * 0) 8492 */ 8493#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 8494#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 8495/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 8496 * to 0) 8497 */ 8498#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 8499#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4 8500/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 8501 * to 0) 8502 */ 8503#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 8504#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4 8505/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 8506 * order; set last 12 bytes to 0 for IPv4 address) 8507 */ 8508#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 8509#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 8510/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 8511 * order; set last 12 bytes to 0 for IPv4 address) 8512 */ 8513#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 8514#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 8515 8516/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional 8517 * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via 8518 * its rte_flow API. This extension is only useful with the sfc_efx driver 8519 * included as part of DPDK, used in conjunction with the dpdk datapath 8520 * firmware variant. 8521 */ 8522#define MC_CMD_FILTER_OP_V3_IN_LEN 180 8523/* identifies the type of operation requested */ 8524#define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0 8525#define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4 8526/* Enum values, see field(s): */ 8527/* MC_CMD_FILTER_OP_IN/OP */ 8528/* filter handle (for remove / unsubscribe operations) */ 8529#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4 8530#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8 8531#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4 8532#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8 8533/* The port ID associated with the v-adaptor which should contain this filter. 8534 */ 8535#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12 8536#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4 8537/* fields to include in match criteria */ 8538#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16 8539#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4 8540#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0 8541#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1 8542#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1 8543#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1 8544#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2 8545#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1 8546#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3 8547#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1 8548#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4 8549#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1 8550#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5 8551#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1 8552#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6 8553#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1 8554#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7 8555#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1 8556#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8 8557#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1 8558#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9 8559#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1 8560#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10 8561#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1 8562#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11 8563#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1 8564#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12 8565#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1 8566#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13 8567#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1 8568#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14 8569#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 8570#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15 8571#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 8572#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16 8573#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1 8574#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17 8575#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1 8576#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 8577#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 8578#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19 8579#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 8580#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 8581#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 8582#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21 8583#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 8584#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22 8585#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1 8586#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23 8587#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1 8588#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 8589#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 8590#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 8591#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 8592#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8593#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8594#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8595#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8596/* receive destination */ 8597#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20 8598#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4 8599/* enum: drop packets */ 8600#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0 8601/* enum: receive to host */ 8602#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1 8603/* enum: receive to MC */ 8604#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2 8605/* enum: loop back to TXDP 0 */ 8606#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3 8607/* enum: loop back to TXDP 1 */ 8608#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4 8609/* receive queue handle (for multiple queue modes, this is the base queue) */ 8610#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24 8611#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4 8612/* receive mode */ 8613#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28 8614#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4 8615/* enum: receive to just the specified queue */ 8616#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0 8617/* enum: receive to multiple queues using RSS context */ 8618#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1 8619/* enum: receive to multiple queues using .1p mapping */ 8620#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2 8621/* enum: install a filter entry that will never match; for test purposes only 8622 */ 8623#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8624/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8625 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8626 * MC_CMD_DOT1P_MAPPING_ALLOC. 8627 */ 8628#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32 8629#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4 8630/* transmit domain (reserved; set to 0) */ 8631#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36 8632#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4 8633/* transmit destination (either set the MAC and/or PM bits for explicit 8634 * control, or set this field to TX_DEST_DEFAULT for sensible default 8635 * behaviour) 8636 */ 8637#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40 8638#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4 8639/* enum: request default behaviour (based on filter type) */ 8640#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff 8641#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0 8642#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1 8643#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1 8644#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1 8645/* source MAC address to match (as bytes in network order) */ 8646#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44 8647#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6 8648/* source port to match (as bytes in network order) */ 8649#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50 8650#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2 8651/* destination MAC address to match (as bytes in network order) */ 8652#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52 8653#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6 8654/* destination port to match (as bytes in network order) */ 8655#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58 8656#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2 8657/* Ethernet type to match (as bytes in network order) */ 8658#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60 8659#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2 8660/* Inner VLAN tag to match (as bytes in network order) */ 8661#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62 8662#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2 8663/* Outer VLAN tag to match (as bytes in network order) */ 8664#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64 8665#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2 8666/* IP protocol to match (in low byte; set high byte to 0) */ 8667#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66 8668#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2 8669/* Firmware defined register 0 to match (reserved; set to 0) */ 8670#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68 8671#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4 8672/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 8673 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 8674 * VXLAN/NVGRE, or 1 for Geneve) 8675 */ 8676#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72 8677#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4 8678#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0 8679#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24 8680#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24 8681#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8 8682/* enum: Match VXLAN traffic with this VNI */ 8683#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0 8684/* enum: Match Geneve traffic with this VNI */ 8685#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1 8686/* enum: Reserved for experimental development use */ 8687#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe 8688#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0 8689#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24 8690#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24 8691#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8 8692/* enum: Match NVGRE traffic with this VSID */ 8693#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0 8694/* source IP address to match (as bytes in network order; set last 12 bytes to 8695 * 0 for IPv4 address) 8696 */ 8697#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76 8698#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16 8699/* destination IP address to match (as bytes in network order; set last 12 8700 * bytes to 0 for IPv4 address) 8701 */ 8702#define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92 8703#define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16 8704/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 8705 * order) 8706 */ 8707#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108 8708#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6 8709/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 8710#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114 8711#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2 8712/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 8713 * network order) 8714 */ 8715#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116 8716#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6 8717/* VXLAN/NVGRE inner frame destination port to match (as bytes in network 8718 * order) 8719 */ 8720#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122 8721#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2 8722/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 8723 */ 8724#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124 8725#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2 8726/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 8727 */ 8728#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126 8729#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2 8730/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 8731 */ 8732#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128 8733#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2 8734/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 8735 * 0) 8736 */ 8737#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130 8738#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2 8739/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 8740 * to 0) 8741 */ 8742#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132 8743#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4 8744/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 8745 * to 0) 8746 */ 8747#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136 8748#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4 8749/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 8750 * order; set last 12 bytes to 0 for IPv4 address) 8751 */ 8752#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140 8753#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16 8754/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 8755 * order; set last 12 bytes to 0 for IPv4 address) 8756 */ 8757#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156 8758#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16 8759/* Set an action for all packets matching this filter. The DPDK driver and dpdk 8760 * f/w variant use their own specific delivery structures, which are documented 8761 * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything 8762 * other than MATCH_ACTION_NONE when the NIC is running another f/w variant 8763 * will cause the filter insertion to fail with ENOTSUP. 8764 */ 8765#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172 8766#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4 8767/* enum: do nothing extra */ 8768#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0 8769/* enum: Set the match flag in the packet prefix for packets matching the 8770 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to 8771 * support the DPDK rte_flow "FLAG" action. 8772 */ 8773#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1 8774/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching 8775 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to 8776 * support the DPDK rte_flow "MARK" action. 8777 */ 8778#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2 8779/* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the 8780 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX) 8781 * will cause the filter insertion to fail with EINVAL. 8782 */ 8783#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176 8784#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4 8785 8786/* MC_CMD_FILTER_OP_OUT msgresponse */ 8787#define MC_CMD_FILTER_OP_OUT_LEN 12 8788/* identifies the type of operation requested */ 8789#define MC_CMD_FILTER_OP_OUT_OP_OFST 0 8790#define MC_CMD_FILTER_OP_OUT_OP_LEN 4 8791/* Enum values, see field(s): */ 8792/* MC_CMD_FILTER_OP_IN/OP */ 8793/* Returned filter handle (for insert / subscribe operations). Note that these 8794 * handles should be considered opaque to the host, although a value of 8795 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8796 */ 8797#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 8798#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 8799#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 8800#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 8801/* enum: guaranteed invalid filter handle (low 32 bits) */ 8802#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 8803/* enum: guaranteed invalid filter handle (high 32 bits) */ 8804#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 8805 8806/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 8807#define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 8808/* identifies the type of operation requested */ 8809#define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 8810#define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4 8811/* Enum values, see field(s): */ 8812/* MC_CMD_FILTER_OP_EXT_IN/OP */ 8813/* Returned filter handle (for insert / subscribe operations). Note that these 8814 * handles should be considered opaque to the host, although a value of 8815 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8816 */ 8817#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 8818#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 8819#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 8820#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 8821/* Enum values, see field(s): */ 8822/* MC_CMD_FILTER_OP_OUT/HANDLE */ 8823 8824/***********************************/ 8825/* MC_CMD_GET_PARSER_DISP_INFO 8826 * Get information related to the parser-dispatcher subsystem 8827 */ 8828#define MC_CMD_GET_PARSER_DISP_INFO 0xe4 8829#undef MC_CMD_0xe4_PRIVILEGE_CTG 8830 8831#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8832 8833/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 8834#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 8835/* identifies the type of operation requested */ 8836#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 8837#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4 8838/* enum: read the list of supported RX filter matches */ 8839#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 8840/* enum: read flags indicating restrictions on filter insertion for the calling 8841 * client 8842 */ 8843#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 8844/* enum: read properties relating to security rules (Medford-only; for use by 8845 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 8846 */ 8847#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 8848/* enum: read the list of supported RX filter matches for VXLAN/NVGRE 8849 * encapsulated frames, which follow a different match sequence to normal 8850 * frames (Medford only) 8851 */ 8852#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 8853 8854/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 8855#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 8856#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 8857#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 8858/* identifies the type of operation requested */ 8859#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 8860#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4 8861/* Enum values, see field(s): */ 8862/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8863/* number of supported match types */ 8864#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 8865#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4 8866/* array of supported match types (valid MATCH_FIELDS values for 8867 * MC_CMD_FILTER_OP) sorted in decreasing priority order 8868 */ 8869#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 8870#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 8871#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 8872#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 8873 8874/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 8875#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 8876/* identifies the type of operation requested */ 8877#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 8878#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4 8879/* Enum values, see field(s): */ 8880/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8881/* bitfield of filter insertion restrictions */ 8882#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 8883#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4 8884#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 8885#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 8886 8887/* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse: 8888 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO. 8889 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 8890 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 8891 * been used in any released code and may change during development. This note 8892 * will be removed once it is regarded as stable. 8893 */ 8894#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36 8895/* identifies the type of operation requested */ 8896#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0 8897#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4 8898/* Enum values, see field(s): */ 8899/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8900/* a version number representing the set of rule lookups that are implemented 8901 * by the currently running firmware 8902 */ 8903#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4 8904#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4 8905/* enum: implements lookup sequences described in SF-114946-SW draft C */ 8906#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0 8907/* the number of nodes in the subnet map */ 8908#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8 8909#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4 8910/* the number of entries in one subnet map node */ 8911#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12 8912#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4 8913/* minimum valid value for a subnet ID in a subnet map leaf */ 8914#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16 8915#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4 8916/* maximum valid value for a subnet ID in a subnet map leaf */ 8917#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20 8918#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4 8919/* the number of entries in the local and remote port range maps */ 8920#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24 8921#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4 8922/* minimum valid value for a portrange ID in a port range map leaf */ 8923#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28 8924#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4 8925/* maximum valid value for a portrange ID in a port range map leaf */ 8926#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 8927#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4 8928 8929/***********************************/ 8930/* MC_CMD_PARSER_DISP_RW 8931 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 8932 * Please note that this interface is only of use to debug tools which have 8933 * knowledge of firmware and hardware data structures; nothing here is intended 8934 * for use by normal driver code. Note that although this command is in the 8935 * Admin privilege group, in tamperproof adapters, only read operations are 8936 * permitted. 8937 */ 8938#define MC_CMD_PARSER_DISP_RW 0xe5 8939#undef MC_CMD_0xe5_PRIVILEGE_CTG 8940 8941#define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8942 8943/* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 8944#define MC_CMD_PARSER_DISP_RW_IN_LEN 32 8945/* identifies the target of the operation */ 8946#define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 8947#define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4 8948/* enum: RX dispatcher CPU */ 8949#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 8950/* enum: TX dispatcher CPU */ 8951#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 8952/* enum: Lookup engine (with original metadata format). Deprecated; used only 8953 * by cmdclient as a fallback for very old Huntington firmware, and not 8954 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 8955 * instead. 8956 */ 8957#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 8958/* enum: Lookup engine (with requested metadata format) */ 8959#define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 8960/* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 8961#define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 8962/* enum: RX1 dispatcher CPU (only valid for Medford) */ 8963#define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 8964/* enum: Miscellaneous other state (only valid for Medford) */ 8965#define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 8966/* identifies the type of operation requested */ 8967#define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 8968#define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4 8969/* enum: Read a word of DICPU DMEM or a LUE entry */ 8970#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 8971/* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on 8972 * tamperproof adapters. 8973 */ 8974#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 8975/* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not 8976 * permitted on tamperproof adapters. 8977 */ 8978#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 8979/* data memory address (DICPU targets) or LUE index (LUE targets) */ 8980#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 8981#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4 8982/* selector (for MISC_STATE target) */ 8983#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 8984#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4 8985/* enum: Port to datapath mapping */ 8986#define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 8987/* value to write (for DMEM writes) */ 8988#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 8989#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4 8990/* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8991#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 8992#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4 8993/* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8994#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 8995#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4 8996/* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 8997#define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 8998#define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4 8999/* value to write (for LUE writes) */ 9000#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 9001#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 9002 9003/* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 9004#define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 9005/* value read (for DMEM reads) */ 9006#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 9007#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4 9008/* value read (for LUE reads) */ 9009#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 9010#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 9011/* up to 8 32-bit words of additional soft state from the LUE manager (the 9012 * exact content is firmware-dependent and intended only for debug use) 9013 */ 9014#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 9015#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 9016/* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 9017#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 9018#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 9019#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 9020#define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 9021#define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 9022 9023/***********************************/ 9024/* MC_CMD_GET_PF_COUNT 9025 * Get number of PFs on the device. 9026 */ 9027#define MC_CMD_GET_PF_COUNT 0xb6 9028#undef MC_CMD_0xb6_PRIVILEGE_CTG 9029 9030#define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9031 9032/* MC_CMD_GET_PF_COUNT_IN msgrequest */ 9033#define MC_CMD_GET_PF_COUNT_IN_LEN 0 9034 9035/* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 9036#define MC_CMD_GET_PF_COUNT_OUT_LEN 1 9037/* Identifies the number of PFs on the device. */ 9038#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 9039#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 9040 9041/***********************************/ 9042/* MC_CMD_SET_PF_COUNT 9043 * Set number of PFs on the device. 9044 */ 9045#define MC_CMD_SET_PF_COUNT 0xb7 9046 9047/* MC_CMD_SET_PF_COUNT_IN msgrequest */ 9048#define MC_CMD_SET_PF_COUNT_IN_LEN 4 9049/* New number of PFs on the device. */ 9050#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 9051#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4 9052 9053/* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 9054#define MC_CMD_SET_PF_COUNT_OUT_LEN 0 9055 9056/***********************************/ 9057/* MC_CMD_GET_PORT_ASSIGNMENT 9058 * Get port assignment for current PCI function. 9059 */ 9060#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 9061#undef MC_CMD_0xb8_PRIVILEGE_CTG 9062 9063#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9064 9065/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 9066#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 9067 9068/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 9069#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 9070/* Identifies the port assignment for this function. */ 9071#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 9072#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4 9073 9074/***********************************/ 9075/* MC_CMD_SET_PORT_ASSIGNMENT 9076 * Set port assignment for current PCI function. 9077 */ 9078#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 9079#undef MC_CMD_0xb9_PRIVILEGE_CTG 9080 9081#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9082 9083/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 9084#define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 9085/* Identifies the port assignment for this function. */ 9086#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 9087#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4 9088 9089/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 9090#define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 9091 9092/***********************************/ 9093/* MC_CMD_ALLOC_VIS 9094 * Allocate VIs for current PCI function. 9095 */ 9096#define MC_CMD_ALLOC_VIS 0x8b 9097#undef MC_CMD_0x8b_PRIVILEGE_CTG 9098 9099#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9100 9101/* MC_CMD_ALLOC_VIS_IN msgrequest */ 9102#define MC_CMD_ALLOC_VIS_IN_LEN 8 9103/* The minimum number of VIs that is acceptable */ 9104#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 9105#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4 9106/* The maximum number of VIs that would be useful */ 9107#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 9108#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4 9109 9110/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 9111 * Use extended version in new code. 9112 */ 9113#define MC_CMD_ALLOC_VIS_OUT_LEN 8 9114/* The number of VIs allocated on this function */ 9115#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 9116#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4 9117/* The base absolute VI number allocated to this function. Required to 9118 * correctly interpret wakeup events. 9119 */ 9120#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 9121#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4 9122 9123/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 9124#define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 9125/* The number of VIs allocated on this function */ 9126#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 9127#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4 9128/* The base absolute VI number allocated to this function. Required to 9129 * correctly interpret wakeup events. 9130 */ 9131#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 9132#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4 9133/* Function's port vi_shift value (always 0 on Huntington) */ 9134#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 9135#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4 9136 9137/***********************************/ 9138/* MC_CMD_FREE_VIS 9139 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 9140 * but not freed. 9141 */ 9142#define MC_CMD_FREE_VIS 0x8c 9143#undef MC_CMD_0x8c_PRIVILEGE_CTG 9144 9145#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9146 9147/* MC_CMD_FREE_VIS_IN msgrequest */ 9148#define MC_CMD_FREE_VIS_IN_LEN 0 9149 9150/* MC_CMD_FREE_VIS_OUT msgresponse */ 9151#define MC_CMD_FREE_VIS_OUT_LEN 0 9152 9153/***********************************/ 9154/* MC_CMD_GET_SRIOV_CFG 9155 * Get SRIOV config for this PF. 9156 */ 9157#define MC_CMD_GET_SRIOV_CFG 0xba 9158#undef MC_CMD_0xba_PRIVILEGE_CTG 9159 9160#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9161 9162/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 9163#define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 9164 9165/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 9166#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 9167/* Number of VFs currently enabled. */ 9168#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 9169#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4 9170/* Max number of VFs before sriov stride and offset may need to be changed. */ 9171#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 9172#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4 9173#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 9174#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4 9175#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 9176#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 9177/* RID offset of first VF from PF. */ 9178#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 9179#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4 9180/* RID offset of each subsequent VF from the previous. */ 9181#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 9182#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4 9183 9184/***********************************/ 9185/* MC_CMD_SET_SRIOV_CFG 9186 * Set SRIOV config for this PF. 9187 */ 9188#define MC_CMD_SET_SRIOV_CFG 0xbb 9189#undef MC_CMD_0xbb_PRIVILEGE_CTG 9190 9191#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9192 9193/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 9194#define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 9195/* Number of VFs currently enabled. */ 9196#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 9197#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4 9198/* Max number of VFs before sriov stride and offset may need to be changed. */ 9199#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 9200#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4 9201#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 9202#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4 9203#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 9204#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 9205/* RID offset of first VF from PF, or 0 for no change, or 9206 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 9207 */ 9208#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 9209#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4 9210/* RID offset of each subsequent VF from the previous, 0 for no change, or 9211 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 9212 */ 9213#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 9214#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4 9215 9216/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 9217#define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 9218 9219/***********************************/ 9220/* MC_CMD_GET_VI_ALLOC_INFO 9221 * Get information about number of VI's and base VI number allocated to this 9222 * function. 9223 */ 9224#define MC_CMD_GET_VI_ALLOC_INFO 0x8d 9225#undef MC_CMD_0x8d_PRIVILEGE_CTG 9226 9227#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9228 9229/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 9230#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 9231 9232/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 9233#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 9234/* The number of VIs allocated on this function */ 9235#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 9236#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4 9237/* The base absolute VI number allocated to this function. Required to 9238 * correctly interpret wakeup events. 9239 */ 9240#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 9241#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4 9242/* Function's port vi_shift value (always 0 on Huntington) */ 9243#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 9244#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4 9245 9246/***********************************/ 9247/* MC_CMD_DUMP_VI_STATE 9248 * For CmdClient use. Dump pertinent information on a specific absolute VI. 9249 */ 9250#define MC_CMD_DUMP_VI_STATE 0x8e 9251#undef MC_CMD_0x8e_PRIVILEGE_CTG 9252 9253#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9254 9255/* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 9256#define MC_CMD_DUMP_VI_STATE_IN_LEN 4 9257/* The VI number to query. */ 9258#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 9259#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4 9260 9261/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 9262#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 9263/* The PF part of the function owning this VI. */ 9264#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 9265#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 9266/* The VF part of the function owning this VI. */ 9267#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 9268#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 9269/* Base of VIs allocated to this function. */ 9270#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 9271#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 9272/* Count of VIs allocated to the owner function. */ 9273#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 9274#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 9275/* Base interrupt vector allocated to this function. */ 9276#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 9277#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 9278/* Number of interrupt vectors allocated to this function. */ 9279#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 9280#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 9281/* Raw evq ptr table data. */ 9282#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 9283#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 9284#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 9285#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 9286/* Raw evq timer table data. */ 9287#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 9288#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 9289#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 9290#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 9291/* Combined metadata field. */ 9292#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 9293#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4 9294#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 9295#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 9296#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 9297#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 9298#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 9299#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 9300/* TXDPCPU raw table data for queue. */ 9301#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 9302#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 9303#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 9304#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 9305/* TXDPCPU raw table data for queue. */ 9306#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 9307#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 9308#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 9309#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 9310/* TXDPCPU raw table data for queue. */ 9311#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 9312#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 9313#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 9314#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 9315/* Combined metadata field. */ 9316#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 9317#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 9318#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 9319#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 9320#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 9321#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 9322#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 9323#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 9324#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 9325#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 9326#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 9327#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 9328#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 9329#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 9330/* RXDPCPU raw table data for queue. */ 9331#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 9332#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 9333#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 9334#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 9335/* RXDPCPU raw table data for queue. */ 9336#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 9337#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 9338#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 9339#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 9340/* Reserved, currently 0. */ 9341#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 9342#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 9343#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 9344#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 9345/* Combined metadata field. */ 9346#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 9347#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 9348#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 9349#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 9350#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 9351#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 9352#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 9353#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 9354#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 9355#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 9356#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 9357#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 9358 9359/***********************************/ 9360/* MC_CMD_ALLOC_PIOBUF 9361 * Allocate a push I/O buffer for later use with a tx queue. 9362 */ 9363#define MC_CMD_ALLOC_PIOBUF 0x8f 9364#undef MC_CMD_0x8f_PRIVILEGE_CTG 9365 9366#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9367 9368/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 9369#define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 9370 9371/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 9372#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 9373/* Handle for allocated push I/O buffer. */ 9374#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 9375#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4 9376 9377/***********************************/ 9378/* MC_CMD_FREE_PIOBUF 9379 * Free a push I/O buffer. 9380 */ 9381#define MC_CMD_FREE_PIOBUF 0x90 9382#undef MC_CMD_0x90_PRIVILEGE_CTG 9383 9384#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9385 9386/* MC_CMD_FREE_PIOBUF_IN msgrequest */ 9387#define MC_CMD_FREE_PIOBUF_IN_LEN 4 9388/* Handle for allocated push I/O buffer. */ 9389#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 9390#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 9391 9392/* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 9393#define MC_CMD_FREE_PIOBUF_OUT_LEN 0 9394 9395/***********************************/ 9396/* MC_CMD_GET_VI_TLP_PROCESSING 9397 * Get TLP steering and ordering information for a VI. 9398 */ 9399#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 9400#undef MC_CMD_0xb0_PRIVILEGE_CTG 9401 9402#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9403 9404/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 9405#define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 9406/* VI number to get information for. */ 9407#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9408#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 9409 9410/* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 9411#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 9412/* Transaction processing steering hint 1 for use with the Rx Queue. */ 9413#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 9414#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 9415/* Transaction processing steering hint 2 for use with the Ev Queue. */ 9416#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 9417#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 9418/* Use Relaxed ordering model for TLPs on this VI. */ 9419#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 9420#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 9421/* Use ID based ordering for TLPs on this VI. */ 9422#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 9423#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 9424/* Set no snoop bit for TLPs on this VI. */ 9425#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 9426#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 9427/* Enable TPH for TLPs on this VI. */ 9428#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 9429#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 9430#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 9431#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4 9432 9433/***********************************/ 9434/* MC_CMD_SET_VI_TLP_PROCESSING 9435 * Set TLP steering and ordering information for a VI. 9436 */ 9437#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 9438#undef MC_CMD_0xb1_PRIVILEGE_CTG 9439 9440#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9441 9442/* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 9443#define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 9444/* VI number to set information for. */ 9445#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9446#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 9447/* Transaction processing steering hint 1 for use with the Rx Queue. */ 9448#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 9449#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 9450/* Transaction processing steering hint 2 for use with the Ev Queue. */ 9451#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 9452#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 9453/* Use Relaxed ordering model for TLPs on this VI. */ 9454#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 9455#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 9456/* Use ID based ordering for TLPs on this VI. */ 9457#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 9458#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 9459/* Set the no snoop bit for TLPs on this VI. */ 9460#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 9461#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 9462/* Enable TPH for TLPs on this VI. */ 9463#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 9464#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 9465#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 9466#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4 9467 9468/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 9469#define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 9470 9471/***********************************/ 9472/* MC_CMD_GET_TLP_PROCESSING_GLOBALS 9473 * Get global PCIe steering and transaction processing configuration. 9474 */ 9475#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 9476#undef MC_CMD_0xbc_PRIVILEGE_CTG 9477 9478#define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9479 9480/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9481#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 9482#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9483#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 9484/* enum: MISC. */ 9485#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 9486/* enum: IDO. */ 9487#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 9488/* enum: RO. */ 9489#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 9490/* enum: TPH Type. */ 9491#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 9492 9493/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9494#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 9495#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 9496#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4 9497/* Enum values, see field(s): */ 9498/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9499/* Amalgamated TLP info word. */ 9500#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 9501#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4 9502#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 9503#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9504#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 9505#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 9506#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 9507#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 9508#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 9509#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 9510#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 9511#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 9512#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 9513#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 9514#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 9515#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 9516#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 9517#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9518#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 9519#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9520#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 9521#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 9522#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 9523#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 9524#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9525#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9526#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 9527#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9528#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 9529#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9530#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 9531#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9532#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 9533#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9534#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 9535#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 9536 9537/***********************************/ 9538/* MC_CMD_SET_TLP_PROCESSING_GLOBALS 9539 * Set global PCIe steering and transaction processing configuration. 9540 */ 9541#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 9542#undef MC_CMD_0xbd_PRIVILEGE_CTG 9543 9544#define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9545 9546/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9547#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 9548#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9549#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 9550/* Enum values, see field(s): */ 9551/* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9552/* Amalgamated TLP info word. */ 9553#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 9554#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4 9555#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 9556#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9557#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 9558#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 9559#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 9560#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 9561#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 9562#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 9563#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 9564#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 9565#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 9566#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9567#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 9568#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9569#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 9570#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 9571#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9572#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9573#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 9574#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9575#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 9576#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9577#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 9578#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9579#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 9580#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9581#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 9582#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 9583 9584/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9585#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 9586 9587/***********************************/ 9588/* MC_CMD_SATELLITE_DOWNLOAD 9589 * Download a new set of images to the satellite CPUs from the host. 9590 */ 9591#define MC_CMD_SATELLITE_DOWNLOAD 0x91 9592#undef MC_CMD_0x91_PRIVILEGE_CTG 9593 9594#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 9595 9596/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 9597 * are subtle, and so downloads must proceed in a number of phases. 9598 * 9599 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 9600 * 9601 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 9602 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 9603 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 9604 * download may be aborted using CHUNK_ID_ABORT. 9605 * 9606 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 9607 * similar to PHASE_IMEMS. 9608 * 9609 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 9610 * 9611 * After any error (a requested abort is not considered to be an error) the 9612 * sequence must be restarted from PHASE_RESET. 9613 */ 9614#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 9615#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 9616#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 9617/* Download phase. (Note: the IDLE phase is used internally and is never valid 9618 * in a command from the host.) 9619 */ 9620#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 9621#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4 9622#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 9623#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 9624#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 9625#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 9626#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 9627/* Target for download. (These match the blob numbers defined in 9628 * mc_flash_layout.h.) 9629 */ 9630#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 9631#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4 9632/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9633#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 9634/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9635#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 9636/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9637#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 9638/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9639#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 9640/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9641#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 9642/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9643#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 9644/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9645#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 9646/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9647#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 9648/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9649#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 9650/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9651#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 9652/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9653#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 9654/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9655#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 9656/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9657#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 9658/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9659#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 9660/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9661#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 9662/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9663#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 9664/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 9665#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 9666/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 9667#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 9668#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4 9669/* enum: Last chunk, containing checksum rather than data */ 9670#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 9671/* enum: Abort download of this item */ 9672#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 9673/* Length of this chunk in bytes */ 9674#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 9675#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4 9676/* Data for this chunk */ 9677#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 9678#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 9679#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 9680#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 9681 9682/* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 9683#define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 9684/* Same as MC_CMD_ERR field, but included as 0 in success cases */ 9685#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 9686#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4 9687/* Extra status information */ 9688#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 9689#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4 9690/* enum: Code download OK, completed. */ 9691#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 9692/* enum: Code download aborted as requested. */ 9693#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 9694/* enum: Code download OK so far, send next chunk. */ 9695#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 9696/* enum: Download phases out of sequence */ 9697#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 9698/* enum: Bad target for this phase */ 9699#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 9700/* enum: Chunk ID out of sequence */ 9701#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 9702/* enum: Chunk length zero or too large */ 9703#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 9704/* enum: Checksum was incorrect */ 9705#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 9706 9707/***********************************/ 9708/* MC_CMD_GET_CAPABILITIES 9709 * Get device capabilities. 9710 * 9711 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 9712 * reference inherent device capabilities as opposed to current NVRAM config. 9713 */ 9714#define MC_CMD_GET_CAPABILITIES 0xbe 9715#undef MC_CMD_0xbe_PRIVILEGE_CTG 9716 9717#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9718 9719/* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 9720#define MC_CMD_GET_CAPABILITIES_IN_LEN 0 9721 9722/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 9723#define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 9724/* First word of flags. */ 9725#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 9726#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4 9727#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 9728#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 9729#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 9730#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 9731#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 9732#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 9733#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9734#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9735#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 9736#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9737#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9738#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9739#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 9740#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 9741#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9742#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9743#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9744#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9745#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9746#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9747#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 9748#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9749#define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 9750#define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 9751#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9752#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9753#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 9754#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 9755#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 9756#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 9757#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 9758#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 9759#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 9760#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 9761#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 9762#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 9763#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 9764#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 9765#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 9766#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 9767#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 9768#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 9769#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 9770#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 9771#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 9772#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 9773#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 9774#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9775#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9776#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9777#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 9778#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 9779#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9780#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9781#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 9782#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 9783#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 9784#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 9785/* RxDPCPU firmware id. */ 9786#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 9787#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 9788/* enum: Standard RXDP firmware */ 9789#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 9790/* enum: Low latency RXDP firmware */ 9791#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 9792/* enum: Packed stream RXDP firmware */ 9793#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 9794/* enum: Rules engine RXDP firmware */ 9795#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5 9796/* enum: DPDK RXDP firmware */ 9797#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6 9798/* enum: BIST RXDP firmware */ 9799#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 9800/* enum: RXDP Test firmware image 1 */ 9801#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9802/* enum: RXDP Test firmware image 2 */ 9803#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9804/* enum: RXDP Test firmware image 3 */ 9805#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9806/* enum: RXDP Test firmware image 4 */ 9807#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9808/* enum: RXDP Test firmware image 5 */ 9809#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 9810/* enum: RXDP Test firmware image 6 */ 9811#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9812/* enum: RXDP Test firmware image 7 */ 9813#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9814/* enum: RXDP Test firmware image 8 */ 9815#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9816/* enum: RXDP Test firmware image 9 */ 9817#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9818/* enum: RXDP Test firmware image 10 */ 9819#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c 9820/* TxDPCPU firmware id. */ 9821#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 9822#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 9823/* enum: Standard TXDP firmware */ 9824#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 9825/* enum: Low latency TXDP firmware */ 9826#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 9827/* enum: High packet rate TXDP firmware */ 9828#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 9829/* enum: Rules engine TXDP firmware */ 9830#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5 9831/* enum: DPDK TXDP firmware */ 9832#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6 9833/* enum: BIST TXDP firmware */ 9834#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 9835/* enum: TXDP Test firmware image 1 */ 9836#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9837/* enum: TXDP Test firmware image 2 */ 9838#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9839/* enum: TXDP CSR bus test firmware */ 9840#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 9841#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 9842#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 9843#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 9844#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9845#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9846#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9847/* enum: reserved value - do not use (may indicate alternative interpretation 9848 * of REV field in future) 9849 */ 9850#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 9851/* enum: Trivial RX PD firmware for early Huntington development (Huntington 9852 * development only) 9853 */ 9854#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9855/* enum: RX PD firmware with approximately Siena-compatible behaviour 9856 * (Huntington development only) 9857 */ 9858#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9859/* enum: Full featured RX PD production firmware */ 9860#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9861/* enum: (deprecated original name for the FULL_FEATURED variant) */ 9862#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9863/* enum: siena_compat variant RX PD firmware using PM rather than MAC 9864 * (Huntington development only) 9865 */ 9866#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9867/* enum: Low latency RX PD production firmware */ 9868#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9869/* enum: Packed stream RX PD production firmware */ 9870#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9871/* enum: RX PD firmware handling layer 2 only for high packet rate performance 9872 * tests (Medford development only) 9873 */ 9874#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9875/* enum: Rules engine RX PD production firmware */ 9876#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9877/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 9878#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9 9879/* enum: DPDK RX PD production firmware */ 9880#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa 9881/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9882#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9883/* enum: RX PD firmware parsing but not filtering network overlay tunnel 9884 * encapsulations (Medford development only) 9885 */ 9886#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9887#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 9888#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 9889#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 9890#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9891#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9892#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9893/* enum: reserved value - do not use (may indicate alternative interpretation 9894 * of REV field in future) 9895 */ 9896#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 9897/* enum: Trivial TX PD firmware for early Huntington development (Huntington 9898 * development only) 9899 */ 9900#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9901/* enum: TX PD firmware with approximately Siena-compatible behaviour 9902 * (Huntington development only) 9903 */ 9904#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9905/* enum: Full featured TX PD production firmware */ 9906#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 9907/* enum: (deprecated original name for the FULL_FEATURED variant) */ 9908#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9909/* enum: siena_compat variant TX PD firmware using PM rather than MAC 9910 * (Huntington development only) 9911 */ 9912#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9913#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9914/* enum: TX PD firmware handling layer 2 only for high packet rate performance 9915 * tests (Medford development only) 9916 */ 9917#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9918/* enum: Rules engine TX PD production firmware */ 9919#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 9920/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 9921#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9 9922/* enum: DPDK TX PD production firmware */ 9923#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa 9924/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9925#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9926/* Hardware capabilities of NIC */ 9927#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 9928#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4 9929/* Licensed capabilities */ 9930#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 9931#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4 9932 9933/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 9934#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 9935 9936/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 9937#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 9938/* First word of flags. */ 9939#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 9940#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4 9941#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 9942#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 9943#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 9944#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 9945#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 9946#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 9947#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9948#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9949#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 9950#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9951#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9952#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9953#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 9954#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 9955#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9956#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9957#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9958#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9959#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9960#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9961#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 9962#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9963#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 9964#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 9965#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9966#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9967#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 9968#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 9969#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 9970#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 9971#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 9972#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 9973#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 9974#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 9975#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 9976#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 9977#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 9978#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 9979#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 9980#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 9981#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 9982#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 9983#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 9984#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 9985#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 9986#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 9987#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 9988#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9989#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9990#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9991#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 9992#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 9993#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9994#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9995#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 9996#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 9997#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 9998#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 9999/* RxDPCPU firmware id. */ 10000#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 10001#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 10002/* enum: Standard RXDP firmware */ 10003#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 10004/* enum: Low latency RXDP firmware */ 10005#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 10006/* enum: Packed stream RXDP firmware */ 10007#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 10008/* enum: Rules engine RXDP firmware */ 10009#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5 10010/* enum: DPDK RXDP firmware */ 10011#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6 10012/* enum: BIST RXDP firmware */ 10013#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 10014/* enum: RXDP Test firmware image 1 */ 10015#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10016/* enum: RXDP Test firmware image 2 */ 10017#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10018/* enum: RXDP Test firmware image 3 */ 10019#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10020/* enum: RXDP Test firmware image 4 */ 10021#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10022/* enum: RXDP Test firmware image 5 */ 10023#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 10024/* enum: RXDP Test firmware image 6 */ 10025#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10026/* enum: RXDP Test firmware image 7 */ 10027#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10028/* enum: RXDP Test firmware image 8 */ 10029#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10030/* enum: RXDP Test firmware image 9 */ 10031#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10032/* enum: RXDP Test firmware image 10 */ 10033#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c 10034/* TxDPCPU firmware id. */ 10035#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 10036#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 10037/* enum: Standard TXDP firmware */ 10038#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 10039/* enum: Low latency TXDP firmware */ 10040#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 10041/* enum: High packet rate TXDP firmware */ 10042#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 10043/* enum: Rules engine TXDP firmware */ 10044#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5 10045/* enum: DPDK TXDP firmware */ 10046#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6 10047/* enum: BIST TXDP firmware */ 10048#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 10049/* enum: TXDP Test firmware image 1 */ 10050#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10051/* enum: TXDP Test firmware image 2 */ 10052#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10053/* enum: TXDP CSR bus test firmware */ 10054#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 10055#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 10056#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 10057#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 10058#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10059#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10060#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10061/* enum: reserved value - do not use (may indicate alternative interpretation 10062 * of REV field in future) 10063 */ 10064#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 10065/* enum: Trivial RX PD firmware for early Huntington development (Huntington 10066 * development only) 10067 */ 10068#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10069/* enum: RX PD firmware with approximately Siena-compatible behaviour 10070 * (Huntington development only) 10071 */ 10072#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10073/* enum: Full featured RX PD production firmware */ 10074#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10075/* enum: (deprecated original name for the FULL_FEATURED variant) */ 10076#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10077/* enum: siena_compat variant RX PD firmware using PM rather than MAC 10078 * (Huntington development only) 10079 */ 10080#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10081/* enum: Low latency RX PD production firmware */ 10082#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10083/* enum: Packed stream RX PD production firmware */ 10084#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10085/* enum: RX PD firmware handling layer 2 only for high packet rate performance 10086 * tests (Medford development only) 10087 */ 10088#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10089/* enum: Rules engine RX PD production firmware */ 10090#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10091/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10092#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9 10093/* enum: DPDK RX PD production firmware */ 10094#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa 10095/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10096#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10097/* enum: RX PD firmware parsing but not filtering network overlay tunnel 10098 * encapsulations (Medford development only) 10099 */ 10100#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10101#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 10102#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 10103#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 10104#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10105#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10106#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10107/* enum: reserved value - do not use (may indicate alternative interpretation 10108 * of REV field in future) 10109 */ 10110#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 10111/* enum: Trivial TX PD firmware for early Huntington development (Huntington 10112 * development only) 10113 */ 10114#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10115/* enum: TX PD firmware with approximately Siena-compatible behaviour 10116 * (Huntington development only) 10117 */ 10118#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10119/* enum: Full featured TX PD production firmware */ 10120#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10121/* enum: (deprecated original name for the FULL_FEATURED variant) */ 10122#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10123/* enum: siena_compat variant TX PD firmware using PM rather than MAC 10124 * (Huntington development only) 10125 */ 10126#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10127#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10128/* enum: TX PD firmware handling layer 2 only for high packet rate performance 10129 * tests (Medford development only) 10130 */ 10131#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10132/* enum: Rules engine TX PD production firmware */ 10133#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10134/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10135#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9 10136/* enum: DPDK TX PD production firmware */ 10137#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa 10138/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10139#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10140/* Hardware capabilities of NIC */ 10141#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 10142#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4 10143/* Licensed capabilities */ 10144#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 10145#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4 10146/* Second word of flags. Not present on older firmware (check the length). */ 10147#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 10148#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4 10149#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 10150#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 10151#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 10152#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10153#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 10154#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 10155#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 10156#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 10157#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 10158#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 10159#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 10160#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10161#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10162#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10163#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 10164#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 10165#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 10166#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10167#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 10168#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 10169#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 10170#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 10171#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 10172#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 10173#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10174#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10175#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13 10176#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1 10177#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14 10178#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1 10179#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15 10180#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1 10181#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16 10182#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1 10183#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17 10184#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1 10185#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 10186#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 10187#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19 10188#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1 10189#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20 10190#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1 10191#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 10192#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 10193#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 10194#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 10195#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22 10196#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1 10197#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 10198#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 10199#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24 10200#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1 10201#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25 10202#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1 10203/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10204 * on older firmware (check the length). 10205 */ 10206#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10207#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10208/* One byte per PF containing the number of the external port assigned to this 10209 * PF, indexed by PF number. Special values indicate that a PF is either not 10210 * present or not assigned. 10211 */ 10212#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10213#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10214#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10215/* enum: The caller is not permitted to access information on this PF. */ 10216#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 10217/* enum: PF does not exist. */ 10218#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 10219/* enum: PF does exist but is not assigned to any external port. */ 10220#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 10221/* enum: This value indicates that PF is assigned, but it cannot be expressed 10222 * in this field. It is intended for a possible future situation where a more 10223 * complex scheme of PFs to ports mapping is being used. The future driver 10224 * should look for a new field supporting the new scheme. The current/old 10225 * driver should treat this value as PF_NOT_ASSIGNED. 10226 */ 10227#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10228/* One byte per PF containing the number of its VFs, indexed by PF number. A 10229 * special value indicates that a PF is not present. 10230 */ 10231#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 10232#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 10233#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 10234/* enum: The caller is not permitted to access information on this PF. */ 10235/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 10236/* enum: PF does not exist. */ 10237/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 10238/* Number of VIs available for each external port */ 10239#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 10240#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 10241#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 10242/* Size of RX descriptor cache expressed as binary logarithm The actual size 10243 * equals (2 ^ RX_DESC_CACHE_SIZE) 10244 */ 10245#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 10246#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 10247/* Size of TX descriptor cache expressed as binary logarithm The actual size 10248 * equals (2 ^ TX_DESC_CACHE_SIZE) 10249 */ 10250#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 10251#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 10252/* Total number of available PIO buffers */ 10253#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 10254#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 10255/* Size of a single PIO buffer */ 10256#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 10257#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 10258 10259/* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 10260#define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76 10261/* First word of flags. */ 10262#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 10263#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4 10264#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 10265#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 10266#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 10267#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 10268#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 10269#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 10270#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10271#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10272#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 10273#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10274#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10275#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10276#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 10277#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 10278#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10279#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10280#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10281#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10282#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10283#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10284#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 10285#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10286#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 10287#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 10288#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10289#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10290#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 10291#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 10292#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 10293#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 10294#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 10295#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 10296#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 10297#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 10298#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 10299#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 10300#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 10301#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 10302#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 10303#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 10304#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 10305#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 10306#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 10307#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 10308#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 10309#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 10310#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 10311#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10312#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10313#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10314#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 10315#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 10316#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10317#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10318#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 10319#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 10320#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 10321#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 10322/* RxDPCPU firmware id. */ 10323#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 10324#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 10325/* enum: Standard RXDP firmware */ 10326#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 10327/* enum: Low latency RXDP firmware */ 10328#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 10329/* enum: Packed stream RXDP firmware */ 10330#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 10331/* enum: Rules engine RXDP firmware */ 10332#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5 10333/* enum: DPDK RXDP firmware */ 10334#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6 10335/* enum: BIST RXDP firmware */ 10336#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 10337/* enum: RXDP Test firmware image 1 */ 10338#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10339/* enum: RXDP Test firmware image 2 */ 10340#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10341/* enum: RXDP Test firmware image 3 */ 10342#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10343/* enum: RXDP Test firmware image 4 */ 10344#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10345/* enum: RXDP Test firmware image 5 */ 10346#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 10347/* enum: RXDP Test firmware image 6 */ 10348#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10349/* enum: RXDP Test firmware image 7 */ 10350#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10351/* enum: RXDP Test firmware image 8 */ 10352#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10353/* enum: RXDP Test firmware image 9 */ 10354#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10355/* enum: RXDP Test firmware image 10 */ 10356#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c 10357/* TxDPCPU firmware id. */ 10358#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 10359#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 10360/* enum: Standard TXDP firmware */ 10361#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 10362/* enum: Low latency TXDP firmware */ 10363#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 10364/* enum: High packet rate TXDP firmware */ 10365#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 10366/* enum: Rules engine TXDP firmware */ 10367#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5 10368/* enum: DPDK TXDP firmware */ 10369#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6 10370/* enum: BIST TXDP firmware */ 10371#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 10372/* enum: TXDP Test firmware image 1 */ 10373#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10374/* enum: TXDP Test firmware image 2 */ 10375#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10376/* enum: TXDP CSR bus test firmware */ 10377#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 10378#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 10379#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 10380#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 10381#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10382#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10383#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10384/* enum: reserved value - do not use (may indicate alternative interpretation 10385 * of REV field in future) 10386 */ 10387#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 10388/* enum: Trivial RX PD firmware for early Huntington development (Huntington 10389 * development only) 10390 */ 10391#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10392/* enum: RX PD firmware with approximately Siena-compatible behaviour 10393 * (Huntington development only) 10394 */ 10395#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10396/* enum: Full featured RX PD production firmware */ 10397#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10398/* enum: (deprecated original name for the FULL_FEATURED variant) */ 10399#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10400/* enum: siena_compat variant RX PD firmware using PM rather than MAC 10401 * (Huntington development only) 10402 */ 10403#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10404/* enum: Low latency RX PD production firmware */ 10405#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10406/* enum: Packed stream RX PD production firmware */ 10407#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10408/* enum: RX PD firmware handling layer 2 only for high packet rate performance 10409 * tests (Medford development only) 10410 */ 10411#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10412/* enum: Rules engine RX PD production firmware */ 10413#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10414/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10415#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9 10416/* enum: DPDK RX PD production firmware */ 10417#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa 10418/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10419#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10420/* enum: RX PD firmware parsing but not filtering network overlay tunnel 10421 * encapsulations (Medford development only) 10422 */ 10423#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10424#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 10425#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 10426#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 10427#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10428#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10429#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10430/* enum: reserved value - do not use (may indicate alternative interpretation 10431 * of REV field in future) 10432 */ 10433#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 10434/* enum: Trivial TX PD firmware for early Huntington development (Huntington 10435 * development only) 10436 */ 10437#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10438/* enum: TX PD firmware with approximately Siena-compatible behaviour 10439 * (Huntington development only) 10440 */ 10441#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10442/* enum: Full featured TX PD production firmware */ 10443#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10444/* enum: (deprecated original name for the FULL_FEATURED variant) */ 10445#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10446/* enum: siena_compat variant TX PD firmware using PM rather than MAC 10447 * (Huntington development only) 10448 */ 10449#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10450#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10451/* enum: TX PD firmware handling layer 2 only for high packet rate performance 10452 * tests (Medford development only) 10453 */ 10454#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10455/* enum: Rules engine TX PD production firmware */ 10456#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10457/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10458#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9 10459/* enum: DPDK TX PD production firmware */ 10460#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa 10461/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10462#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10463/* Hardware capabilities of NIC */ 10464#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 10465#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4 10466/* Licensed capabilities */ 10467#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 10468#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4 10469/* Second word of flags. Not present on older firmware (check the length). */ 10470#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 10471#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4 10472#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 10473#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 10474#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 10475#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10476#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 10477#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 10478#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 10479#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 10480#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 10481#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 10482#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 10483#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10484#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10485#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10486#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 10487#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 10488#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 10489#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10490#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 10491#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 10492#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 10493#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 10494#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 10495#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 10496#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10497#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10498#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13 10499#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1 10500#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14 10501#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1 10502#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15 10503#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1 10504#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16 10505#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1 10506#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17 10507#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1 10508#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 10509#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 10510#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19 10511#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1 10512#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20 10513#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1 10514#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 10515#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 10516#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 10517#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 10518#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22 10519#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1 10520#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 10521#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 10522#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24 10523#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1 10524#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25 10525#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1 10526/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10527 * on older firmware (check the length). 10528 */ 10529#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10530#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10531/* One byte per PF containing the number of the external port assigned to this 10532 * PF, indexed by PF number. Special values indicate that a PF is either not 10533 * present or not assigned. 10534 */ 10535#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10536#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10537#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10538/* enum: The caller is not permitted to access information on this PF. */ 10539#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 10540/* enum: PF does not exist. */ 10541#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 10542/* enum: PF does exist but is not assigned to any external port. */ 10543#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 10544/* enum: This value indicates that PF is assigned, but it cannot be expressed 10545 * in this field. It is intended for a possible future situation where a more 10546 * complex scheme of PFs to ports mapping is being used. The future driver 10547 * should look for a new field supporting the new scheme. The current/old 10548 * driver should treat this value as PF_NOT_ASSIGNED. 10549 */ 10550#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10551/* One byte per PF containing the number of its VFs, indexed by PF number. A 10552 * special value indicates that a PF is not present. 10553 */ 10554#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 10555#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 10556#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 10557/* enum: The caller is not permitted to access information on this PF. */ 10558/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 10559/* enum: PF does not exist. */ 10560/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 10561/* Number of VIs available for each external port */ 10562#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 10563#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 10564#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 10565/* Size of RX descriptor cache expressed as binary logarithm The actual size 10566 * equals (2 ^ RX_DESC_CACHE_SIZE) 10567 */ 10568#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 10569#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 10570/* Size of TX descriptor cache expressed as binary logarithm The actual size 10571 * equals (2 ^ TX_DESC_CACHE_SIZE) 10572 */ 10573#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 10574#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 10575/* Total number of available PIO buffers */ 10576#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 10577#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 10578/* Size of a single PIO buffer */ 10579#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 10580#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 10581/* On chips later than Medford the amount of address space assigned to each VI 10582 * is configurable. This is a global setting that the driver must query to 10583 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 10584 * with 8k VI windows. 10585 */ 10586#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 10587#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 10588/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 10589 * CTPIO is not mapped. 10590 */ 10591#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 10592/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10593#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 10594/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10595#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 10596/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 10597 * (SF-115995-SW) in the present configuration of firmware and port mode. 10598 */ 10599#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 10600#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 10601/* Number of buffers per adapter that can be used for VFIFO Stuffing 10602 * (SF-115995-SW) in the present configuration of firmware and port mode. 10603 */ 10604#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 10605#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 10606 10607/* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */ 10608#define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78 10609/* First word of flags. */ 10610#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0 10611#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4 10612#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3 10613#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1 10614#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4 10615#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1 10616#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5 10617#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1 10618#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10619#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10620#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7 10621#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10622#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10623#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10624#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9 10625#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1 10626#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10627#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10628#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10629#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10630#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10631#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10632#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13 10633#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10634#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14 10635#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1 10636#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10637#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10638#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16 10639#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1 10640#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17 10641#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1 10642#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18 10643#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1 10644#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19 10645#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1 10646#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20 10647#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1 10648#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21 10649#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1 10650#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22 10651#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1 10652#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23 10653#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1 10654#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24 10655#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1 10656#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25 10657#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1 10658#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26 10659#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10660#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10661#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10662#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28 10663#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1 10664#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10665#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10666#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30 10667#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1 10668#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31 10669#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1 10670/* RxDPCPU firmware id. */ 10671#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4 10672#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2 10673/* enum: Standard RXDP firmware */ 10674#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0 10675/* enum: Low latency RXDP firmware */ 10676#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1 10677/* enum: Packed stream RXDP firmware */ 10678#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2 10679/* enum: Rules engine RXDP firmware */ 10680#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5 10681/* enum: DPDK RXDP firmware */ 10682#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6 10683/* enum: BIST RXDP firmware */ 10684#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a 10685/* enum: RXDP Test firmware image 1 */ 10686#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10687/* enum: RXDP Test firmware image 2 */ 10688#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10689/* enum: RXDP Test firmware image 3 */ 10690#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10691/* enum: RXDP Test firmware image 4 */ 10692#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10693/* enum: RXDP Test firmware image 5 */ 10694#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105 10695/* enum: RXDP Test firmware image 6 */ 10696#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10697/* enum: RXDP Test firmware image 7 */ 10698#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10699/* enum: RXDP Test firmware image 8 */ 10700#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10701/* enum: RXDP Test firmware image 9 */ 10702#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10703/* enum: RXDP Test firmware image 10 */ 10704#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c 10705/* TxDPCPU firmware id. */ 10706#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6 10707#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2 10708/* enum: Standard TXDP firmware */ 10709#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0 10710/* enum: Low latency TXDP firmware */ 10711#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1 10712/* enum: High packet rate TXDP firmware */ 10713#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3 10714/* enum: Rules engine TXDP firmware */ 10715#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5 10716/* enum: DPDK TXDP firmware */ 10717#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6 10718/* enum: BIST TXDP firmware */ 10719#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d 10720/* enum: TXDP Test firmware image 1 */ 10721#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10722/* enum: TXDP Test firmware image 2 */ 10723#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10724/* enum: TXDP CSR bus test firmware */ 10725#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103 10726#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8 10727#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2 10728#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0 10729#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10730#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10731#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10732/* enum: reserved value - do not use (may indicate alternative interpretation 10733 * of REV field in future) 10734 */ 10735#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0 10736/* enum: Trivial RX PD firmware for early Huntington development (Huntington 10737 * development only) 10738 */ 10739#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10740/* enum: RX PD firmware with approximately Siena-compatible behaviour 10741 * (Huntington development only) 10742 */ 10743#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10744/* enum: Full featured RX PD production firmware */ 10745#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10746/* enum: (deprecated original name for the FULL_FEATURED variant) */ 10747#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10748/* enum: siena_compat variant RX PD firmware using PM rather than MAC 10749 * (Huntington development only) 10750 */ 10751#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10752/* enum: Low latency RX PD production firmware */ 10753#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10754/* enum: Packed stream RX PD production firmware */ 10755#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10756/* enum: RX PD firmware handling layer 2 only for high packet rate performance 10757 * tests (Medford development only) 10758 */ 10759#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10760/* enum: Rules engine RX PD production firmware */ 10761#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10762/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10763#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9 10764/* enum: DPDK RX PD production firmware */ 10765#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa 10766/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10767#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10768/* enum: RX PD firmware parsing but not filtering network overlay tunnel 10769 * encapsulations (Medford development only) 10770 */ 10771#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10772#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10 10773#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2 10774#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0 10775#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10776#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10777#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10778/* enum: reserved value - do not use (may indicate alternative interpretation 10779 * of REV field in future) 10780 */ 10781#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0 10782/* enum: Trivial TX PD firmware for early Huntington development (Huntington 10783 * development only) 10784 */ 10785#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10786/* enum: TX PD firmware with approximately Siena-compatible behaviour 10787 * (Huntington development only) 10788 */ 10789#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10790/* enum: Full featured TX PD production firmware */ 10791#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10792/* enum: (deprecated original name for the FULL_FEATURED variant) */ 10793#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10794/* enum: siena_compat variant TX PD firmware using PM rather than MAC 10795 * (Huntington development only) 10796 */ 10797#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10798#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10799/* enum: TX PD firmware handling layer 2 only for high packet rate performance 10800 * tests (Medford development only) 10801 */ 10802#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10803/* enum: Rules engine TX PD production firmware */ 10804#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10805/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10806#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9 10807/* enum: DPDK TX PD production firmware */ 10808#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa 10809/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10810#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10811/* Hardware capabilities of NIC */ 10812#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12 10813#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4 10814/* Licensed capabilities */ 10815#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16 10816#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4 10817/* Second word of flags. Not present on older firmware (check the length). */ 10818#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20 10819#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4 10820#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0 10821#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1 10822#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1 10823#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10824#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2 10825#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1 10826#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3 10827#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1 10828#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4 10829#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1 10830#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5 10831#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10832#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10833#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10834#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7 10835#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1 10836#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8 10837#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10838#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9 10839#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1 10840#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10 10841#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1 10842#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11 10843#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1 10844#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10845#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10846#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13 10847#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1 10848#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14 10849#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1 10850#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15 10851#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1 10852#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16 10853#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1 10854#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17 10855#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1 10856#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 10857#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 10858#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19 10859#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1 10860#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20 10861#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1 10862#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 10863#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 10864#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 10865#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 10866#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22 10867#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1 10868#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 10869#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 10870#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24 10871#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1 10872#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25 10873#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1 10874/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10875 * on older firmware (check the length). 10876 */ 10877#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10878#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10879/* One byte per PF containing the number of the external port assigned to this 10880 * PF, indexed by PF number. Special values indicate that a PF is either not 10881 * present or not assigned. 10882 */ 10883#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10884#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10885#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10886/* enum: The caller is not permitted to access information on this PF. */ 10887#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff 10888/* enum: PF does not exist. */ 10889#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe 10890/* enum: PF does exist but is not assigned to any external port. */ 10891#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd 10892/* enum: This value indicates that PF is assigned, but it cannot be expressed 10893 * in this field. It is intended for a possible future situation where a more 10894 * complex scheme of PFs to ports mapping is being used. The future driver 10895 * should look for a new field supporting the new scheme. The current/old 10896 * driver should treat this value as PF_NOT_ASSIGNED. 10897 */ 10898#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10899/* One byte per PF containing the number of its VFs, indexed by PF number. A 10900 * special value indicates that a PF is not present. 10901 */ 10902#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42 10903#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1 10904#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16 10905/* enum: The caller is not permitted to access information on this PF. */ 10906/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */ 10907/* enum: PF does not exist. */ 10908/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */ 10909/* Number of VIs available for each external port */ 10910#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58 10911#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2 10912#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4 10913/* Size of RX descriptor cache expressed as binary logarithm The actual size 10914 * equals (2 ^ RX_DESC_CACHE_SIZE) 10915 */ 10916#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66 10917#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1 10918/* Size of TX descriptor cache expressed as binary logarithm The actual size 10919 * equals (2 ^ TX_DESC_CACHE_SIZE) 10920 */ 10921#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67 10922#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1 10923/* Total number of available PIO buffers */ 10924#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68 10925#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2 10926/* Size of a single PIO buffer */ 10927#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70 10928#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2 10929/* On chips later than Medford the amount of address space assigned to each VI 10930 * is configurable. This is a global setting that the driver must query to 10931 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 10932 * with 8k VI windows. 10933 */ 10934#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72 10935#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1 10936/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 10937 * CTPIO is not mapped. 10938 */ 10939#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0 10940/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10941#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1 10942/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10943#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2 10944/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 10945 * (SF-115995-SW) in the present configuration of firmware and port mode. 10946 */ 10947#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 10948#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 10949/* Number of buffers per adapter that can be used for VFIFO Stuffing 10950 * (SF-115995-SW) in the present configuration of firmware and port mode. 10951 */ 10952#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 10953#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 10954/* Entry count in the MAC stats array, including the final GENERATION_END 10955 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 10956 * hold at least this many 64-bit stats values, if they wish to receive all 10957 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 10958 * stats array returned will be truncated. 10959 */ 10960#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76 10961#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2 10962 10963/* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */ 10964#define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 84 10965/* First word of flags. */ 10966#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0 10967#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4 10968#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3 10969#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1 10970#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4 10971#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1 10972#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5 10973#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1 10974#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10975#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10976#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7 10977#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10978#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10979#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10980#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9 10981#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1 10982#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10983#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10984#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10985#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10986#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10987#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10988#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13 10989#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10990#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14 10991#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1 10992#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10993#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10994#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16 10995#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1 10996#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17 10997#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1 10998#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18 10999#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1 11000#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19 11001#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1 11002#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20 11003#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1 11004#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21 11005#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1 11006#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22 11007#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1 11008#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23 11009#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1 11010#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24 11011#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1 11012#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25 11013#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1 11014#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26 11015#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1 11016#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27 11017#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 11018#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28 11019#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1 11020#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 11021#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 11022#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30 11023#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1 11024#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31 11025#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1 11026/* RxDPCPU firmware id. */ 11027#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4 11028#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 2 11029/* enum: Standard RXDP firmware */ 11030#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0 11031/* enum: Low latency RXDP firmware */ 11032#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1 11033/* enum: Packed stream RXDP firmware */ 11034#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2 11035/* enum: Rules engine RXDP firmware */ 11036#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5 11037/* enum: DPDK RXDP firmware */ 11038#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6 11039/* enum: BIST RXDP firmware */ 11040#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a 11041/* enum: RXDP Test firmware image 1 */ 11042#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 11043/* enum: RXDP Test firmware image 2 */ 11044#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 11045/* enum: RXDP Test firmware image 3 */ 11046#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 11047/* enum: RXDP Test firmware image 4 */ 11048#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 11049/* enum: RXDP Test firmware image 5 */ 11050#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105 11051/* enum: RXDP Test firmware image 6 */ 11052#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 11053/* enum: RXDP Test firmware image 7 */ 11054#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 11055/* enum: RXDP Test firmware image 8 */ 11056#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 11057/* enum: RXDP Test firmware image 9 */ 11058#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 11059/* enum: RXDP Test firmware image 10 */ 11060#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c 11061/* TxDPCPU firmware id. */ 11062#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 6 11063#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 2 11064/* enum: Standard TXDP firmware */ 11065#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0 11066/* enum: Low latency TXDP firmware */ 11067#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1 11068/* enum: High packet rate TXDP firmware */ 11069#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3 11070/* enum: Rules engine TXDP firmware */ 11071#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5 11072/* enum: DPDK TXDP firmware */ 11073#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6 11074/* enum: BIST TXDP firmware */ 11075#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d 11076/* enum: TXDP Test firmware image 1 */ 11077#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 11078/* enum: TXDP Test firmware image 2 */ 11079#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 11080/* enum: TXDP CSR bus test firmware */ 11081#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103 11082#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8 11083#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2 11084#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0 11085#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12 11086#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12 11087#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 11088/* enum: reserved value - do not use (may indicate alternative interpretation 11089 * of REV field in future) 11090 */ 11091#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0 11092/* enum: Trivial RX PD firmware for early Huntington development (Huntington 11093 * development only) 11094 */ 11095#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 11096/* enum: RX PD firmware with approximately Siena-compatible behaviour 11097 * (Huntington development only) 11098 */ 11099#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 11100/* enum: Full featured RX PD production firmware */ 11101#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 11102/* enum: (deprecated original name for the FULL_FEATURED variant) */ 11103#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3 11104/* enum: siena_compat variant RX PD firmware using PM rather than MAC 11105 * (Huntington development only) 11106 */ 11107#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11108/* enum: Low latency RX PD production firmware */ 11109#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 11110/* enum: Packed stream RX PD production firmware */ 11111#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 11112/* enum: RX PD firmware handling layer 2 only for high packet rate performance 11113 * tests (Medford development only) 11114 */ 11115#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 11116/* enum: Rules engine RX PD production firmware */ 11117#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 11118/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 11119#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9 11120/* enum: DPDK RX PD production firmware */ 11121#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa 11122/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11123#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11124/* enum: RX PD firmware parsing but not filtering network overlay tunnel 11125 * encapsulations (Medford development only) 11126 */ 11127#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 11128#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10 11129#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2 11130#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0 11131#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12 11132#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12 11133#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 11134/* enum: reserved value - do not use (may indicate alternative interpretation 11135 * of REV field in future) 11136 */ 11137#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0 11138/* enum: Trivial TX PD firmware for early Huntington development (Huntington 11139 * development only) 11140 */ 11141#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 11142/* enum: TX PD firmware with approximately Siena-compatible behaviour 11143 * (Huntington development only) 11144 */ 11145#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 11146/* enum: Full featured TX PD production firmware */ 11147#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 11148/* enum: (deprecated original name for the FULL_FEATURED variant) */ 11149#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3 11150/* enum: siena_compat variant TX PD firmware using PM rather than MAC 11151 * (Huntington development only) 11152 */ 11153#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11154#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 11155/* enum: TX PD firmware handling layer 2 only for high packet rate performance 11156 * tests (Medford development only) 11157 */ 11158#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 11159/* enum: Rules engine TX PD production firmware */ 11160#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 11161/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 11162#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9 11163/* enum: DPDK TX PD production firmware */ 11164#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa 11165/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11166#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11167/* Hardware capabilities of NIC */ 11168#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 12 11169#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4 11170/* Licensed capabilities */ 11171#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 16 11172#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4 11173/* Second word of flags. Not present on older firmware (check the length). */ 11174#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20 11175#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4 11176#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0 11177#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1 11178#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1 11179#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1 11180#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2 11181#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1 11182#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3 11183#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1 11184#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4 11185#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1 11186#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5 11187#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 11188#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 11189#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 11190#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7 11191#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1 11192#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8 11193#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 11194#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9 11195#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1 11196#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10 11197#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1 11198#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11 11199#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1 11200#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 11201#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 11202#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13 11203#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1 11204#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14 11205#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1 11206#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15 11207#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1 11208#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16 11209#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1 11210#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17 11211#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1 11212#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 11213#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 11214#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19 11215#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1 11216#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20 11217#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1 11218#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 11219#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 11220#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 11221#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 11222#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22 11223#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1 11224#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 11225#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 11226#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24 11227#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1 11228#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25 11229#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1 11230/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 11231 * on older firmware (check the length). 11232 */ 11233#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 11234#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 11235/* One byte per PF containing the number of the external port assigned to this 11236 * PF, indexed by PF number. Special values indicate that a PF is either not 11237 * present or not assigned. 11238 */ 11239#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 11240#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 11241#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 11242/* enum: The caller is not permitted to access information on this PF. */ 11243#define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff 11244/* enum: PF does not exist. */ 11245#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe 11246/* enum: PF does exist but is not assigned to any external port. */ 11247#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd 11248/* enum: This value indicates that PF is assigned, but it cannot be expressed 11249 * in this field. It is intended for a possible future situation where a more 11250 * complex scheme of PFs to ports mapping is being used. The future driver 11251 * should look for a new field supporting the new scheme. The current/old 11252 * driver should treat this value as PF_NOT_ASSIGNED. 11253 */ 11254#define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 11255/* One byte per PF containing the number of its VFs, indexed by PF number. A 11256 * special value indicates that a PF is not present. 11257 */ 11258#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 42 11259#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1 11260#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 16 11261/* enum: The caller is not permitted to access information on this PF. */ 11262/* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */ 11263/* enum: PF does not exist. */ 11264/* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */ 11265/* Number of VIs available for each external port */ 11266#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58 11267#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2 11268#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4 11269/* Size of RX descriptor cache expressed as binary logarithm The actual size 11270 * equals (2 ^ RX_DESC_CACHE_SIZE) 11271 */ 11272#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 66 11273#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1 11274/* Size of TX descriptor cache expressed as binary logarithm The actual size 11275 * equals (2 ^ TX_DESC_CACHE_SIZE) 11276 */ 11277#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 67 11278#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1 11279/* Total number of available PIO buffers */ 11280#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 68 11281#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 2 11282/* Size of a single PIO buffer */ 11283#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 70 11284#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 2 11285/* On chips later than Medford the amount of address space assigned to each VI 11286 * is configurable. This is a global setting that the driver must query to 11287 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 11288 * with 8k VI windows. 11289 */ 11290#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 72 11291#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1 11292/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 11293 * CTPIO is not mapped. 11294 */ 11295#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0 11296/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11297#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1 11298/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11299#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2 11300/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 11301 * (SF-115995-SW) in the present configuration of firmware and port mode. 11302 */ 11303#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 11304#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 11305/* Number of buffers per adapter that can be used for VFIFO Stuffing 11306 * (SF-115995-SW) in the present configuration of firmware and port mode. 11307 */ 11308#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 11309#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 11310/* Entry count in the MAC stats array, including the final GENERATION_END 11311 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 11312 * hold at least this many 64-bit stats values, if they wish to receive all 11313 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 11314 * stats array returned will be truncated. 11315 */ 11316#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 76 11317#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 2 11318/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 11319 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 11320 */ 11321#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80 11322#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4 11323 11324/***********************************/ 11325/* MC_CMD_V2_EXTN 11326 * Encapsulation for a v2 extended command 11327 */ 11328#define MC_CMD_V2_EXTN 0x7f 11329 11330/* MC_CMD_V2_EXTN_IN msgrequest */ 11331#define MC_CMD_V2_EXTN_IN_LEN 4 11332/* the extended command number */ 11333#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 11334#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 11335#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 11336#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 11337/* the actual length of the encapsulated command (which is not in the v1 11338 * header) 11339 */ 11340#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 11341#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 11342#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 11343#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2 11344/* Type of command/response */ 11345#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28 11346#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4 11347/* enum: MCDI command directed to or response originating from the MC. */ 11348#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0 11349/* enum: MCDI command directed to a TSA controller. MCDI responses of this type 11350 * are not defined. 11351 */ 11352#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1 11353 11354/***********************************/ 11355/* MC_CMD_TCM_BUCKET_ALLOC 11356 * Allocate a pacer bucket (for qau rp or a snapper test) 11357 */ 11358#define MC_CMD_TCM_BUCKET_ALLOC 0xb2 11359#undef MC_CMD_0xb2_PRIVILEGE_CTG 11360 11361#define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11362 11363/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 11364#define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 11365 11366/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 11367#define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 11368/* the bucket id */ 11369#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 11370#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4 11371 11372/***********************************/ 11373/* MC_CMD_TCM_BUCKET_FREE 11374 * Free a pacer bucket 11375 */ 11376#define MC_CMD_TCM_BUCKET_FREE 0xb3 11377#undef MC_CMD_0xb3_PRIVILEGE_CTG 11378 11379#define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11380 11381/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 11382#define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 11383/* the bucket id */ 11384#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 11385#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4 11386 11387/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 11388#define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 11389 11390/***********************************/ 11391/* MC_CMD_TCM_BUCKET_INIT 11392 * Initialise pacer bucket with a given rate 11393 */ 11394#define MC_CMD_TCM_BUCKET_INIT 0xb4 11395#undef MC_CMD_0xb4_PRIVILEGE_CTG 11396 11397#define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11398 11399/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 11400#define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 11401/* the bucket id */ 11402#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 11403#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4 11404/* the rate in mbps */ 11405#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 11406#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4 11407 11408/* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 11409#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 11410/* the bucket id */ 11411#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 11412#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4 11413/* the rate in mbps */ 11414#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 11415#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4 11416/* the desired maximum fill level */ 11417#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 11418#define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4 11419 11420/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 11421#define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 11422 11423/***********************************/ 11424/* MC_CMD_TCM_TXQ_INIT 11425 * Initialise txq in pacer with given options or set options 11426 */ 11427#define MC_CMD_TCM_TXQ_INIT 0xb5 11428#undef MC_CMD_0xb5_PRIVILEGE_CTG 11429 11430#define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11431 11432/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 11433#define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 11434/* the txq id */ 11435#define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 11436#define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4 11437/* the static priority associated with the txq */ 11438#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 11439#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4 11440/* bitmask of the priority queues this txq is inserted into when inserted. */ 11441#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 11442#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4 11443#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 11444#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11445#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 11446#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 11447#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 11448#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 11449/* the reaction point (RP) bucket */ 11450#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 11451#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4 11452/* an already reserved bucket (typically set to bucket associated with outer 11453 * vswitch) 11454 */ 11455#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 11456#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4 11457/* an already reserved bucket (typically set to bucket associated with inner 11458 * vswitch) 11459 */ 11460#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 11461#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4 11462/* the min bucket (typically for ETS/minimum bandwidth) */ 11463#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 11464#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4 11465 11466/* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 11467#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 11468/* the txq id */ 11469#define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 11470#define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4 11471/* the static priority associated with the txq */ 11472#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 11473#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4 11474/* bitmask of the priority queues this txq is inserted into when inserted. */ 11475#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 11476#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4 11477#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 11478#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11479#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 11480#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 11481#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 11482#define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 11483/* the reaction point (RP) bucket */ 11484#define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 11485#define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4 11486/* an already reserved bucket (typically set to bucket associated with outer 11487 * vswitch) 11488 */ 11489#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 11490#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4 11491/* an already reserved bucket (typically set to bucket associated with inner 11492 * vswitch) 11493 */ 11494#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 11495#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4 11496/* the min bucket (typically for ETS/minimum bandwidth) */ 11497#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 11498#define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4 11499/* the static priority associated with the txq */ 11500#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 11501#define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4 11502 11503/* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 11504#define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 11505 11506/***********************************/ 11507/* MC_CMD_LINK_PIOBUF 11508 * Link a push I/O buffer to a TxQ 11509 */ 11510#define MC_CMD_LINK_PIOBUF 0x92 11511#undef MC_CMD_0x92_PRIVILEGE_CTG 11512 11513#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11514 11515/* MC_CMD_LINK_PIOBUF_IN msgrequest */ 11516#define MC_CMD_LINK_PIOBUF_IN_LEN 8 11517/* Handle for allocated push I/O buffer. */ 11518#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 11519#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 11520/* Function Local Instance (VI) number. */ 11521#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 11522#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 11523 11524/* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 11525#define MC_CMD_LINK_PIOBUF_OUT_LEN 0 11526 11527/***********************************/ 11528/* MC_CMD_UNLINK_PIOBUF 11529 * Unlink a push I/O buffer from a TxQ 11530 */ 11531#define MC_CMD_UNLINK_PIOBUF 0x93 11532#undef MC_CMD_0x93_PRIVILEGE_CTG 11533 11534#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11535 11536/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 11537#define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 11538/* Function Local Instance (VI) number. */ 11539#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 11540#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 11541 11542/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 11543#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 11544 11545/***********************************/ 11546/* MC_CMD_VSWITCH_ALLOC 11547 * allocate and initialise a v-switch. 11548 */ 11549#define MC_CMD_VSWITCH_ALLOC 0x94 11550#undef MC_CMD_0x94_PRIVILEGE_CTG 11551 11552#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11553 11554/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 11555#define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 11556/* The port to connect to the v-switch's upstream port. */ 11557#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11558#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11559/* The type of v-switch to create. */ 11560#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 11561#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4 11562/* enum: VLAN */ 11563#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 11564/* enum: VEB */ 11565#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 11566/* enum: VEPA (obsolete) */ 11567#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 11568/* enum: MUX */ 11569#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 11570/* enum: Snapper specific; semantics TBD */ 11571#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 11572/* Flags controlling v-port creation */ 11573#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 11574#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4 11575#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11576#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11577/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 11578 * this must be one or greated, and the attached v-ports must have exactly this 11579 * number of tags. For other v-switch types, this must be zero of greater, and 11580 * is an upper limit on the number of VLAN tags for attached v-ports. An error 11581 * will be returned if existing configuration means we can't support attached 11582 * v-ports with this number of tags. 11583 */ 11584#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11585#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 11586 11587/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 11588#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 11589 11590/***********************************/ 11591/* MC_CMD_VSWITCH_FREE 11592 * de-allocate a v-switch. 11593 */ 11594#define MC_CMD_VSWITCH_FREE 0x95 11595#undef MC_CMD_0x95_PRIVILEGE_CTG 11596 11597#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11598 11599/* MC_CMD_VSWITCH_FREE_IN msgrequest */ 11600#define MC_CMD_VSWITCH_FREE_IN_LEN 4 11601/* The port to which the v-switch is connected. */ 11602#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11603#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4 11604 11605/* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 11606#define MC_CMD_VSWITCH_FREE_OUT_LEN 0 11607 11608/***********************************/ 11609/* MC_CMD_VSWITCH_QUERY 11610 * read some config of v-switch. For now this command is an empty placeholder. 11611 * It may be used to check if a v-switch is connected to a given EVB port (if 11612 * not, then the command returns ENOENT). 11613 */ 11614#define MC_CMD_VSWITCH_QUERY 0x63 11615#undef MC_CMD_0x63_PRIVILEGE_CTG 11616 11617#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11618 11619/* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 11620#define MC_CMD_VSWITCH_QUERY_IN_LEN 4 11621/* The port to which the v-switch is connected. */ 11622#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11623#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 11624 11625/* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 11626#define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 11627 11628/***********************************/ 11629/* MC_CMD_VPORT_ALLOC 11630 * allocate a v-port. 11631 */ 11632#define MC_CMD_VPORT_ALLOC 0x96 11633#undef MC_CMD_0x96_PRIVILEGE_CTG 11634 11635#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11636 11637/* MC_CMD_VPORT_ALLOC_IN msgrequest */ 11638#define MC_CMD_VPORT_ALLOC_IN_LEN 20 11639/* The port to which the v-switch is connected. */ 11640#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11641#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11642/* The type of the new v-port. */ 11643#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 11644#define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4 11645/* enum: VLAN (obsolete) */ 11646#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 11647/* enum: VEB (obsolete) */ 11648#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 11649/* enum: VEPA (obsolete) */ 11650#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 11651/* enum: A normal v-port receives packets which match a specified MAC and/or 11652 * VLAN. 11653 */ 11654#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 11655/* enum: An expansion v-port packets traffic which don't match any other 11656 * v-port. 11657 */ 11658#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 11659/* enum: An test v-port receives packets which match any filters installed by 11660 * its downstream components. 11661 */ 11662#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 11663/* Flags controlling v-port creation */ 11664#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 11665#define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4 11666#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11667#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11668#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 11669#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 11670/* The number of VLAN tags to insert/remove. An error will be returned if 11671 * incompatible with the number of VLAN tags specified for the upstream 11672 * v-switch. 11673 */ 11674#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11675#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 11676/* The actual VLAN tags to insert/remove */ 11677#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 11678#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4 11679#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 11680#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11681#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 11682#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11683 11684/* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 11685#define MC_CMD_VPORT_ALLOC_OUT_LEN 4 11686/* The handle of the new v-port */ 11687#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 11688#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4 11689 11690/***********************************/ 11691/* MC_CMD_VPORT_FREE 11692 * de-allocate a v-port. 11693 */ 11694#define MC_CMD_VPORT_FREE 0x97 11695#undef MC_CMD_0x97_PRIVILEGE_CTG 11696 11697#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11698 11699/* MC_CMD_VPORT_FREE_IN msgrequest */ 11700#define MC_CMD_VPORT_FREE_IN_LEN 4 11701/* The handle of the v-port */ 11702#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 11703#define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4 11704 11705/* MC_CMD_VPORT_FREE_OUT msgresponse */ 11706#define MC_CMD_VPORT_FREE_OUT_LEN 0 11707 11708/***********************************/ 11709/* MC_CMD_VADAPTOR_ALLOC 11710 * allocate a v-adaptor. 11711 */ 11712#define MC_CMD_VADAPTOR_ALLOC 0x98 11713#undef MC_CMD_0x98_PRIVILEGE_CTG 11714 11715#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11716 11717/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 11718#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 11719/* The port to connect to the v-adaptor's port. */ 11720#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11721#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11722/* Flags controlling v-adaptor creation */ 11723#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 11724#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4 11725#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 11726#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 11727#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 11728#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 11729/* The number of VLAN tags to strip on receive */ 11730#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 11731#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4 11732/* The number of VLAN tags to transparently insert/remove. */ 11733#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 11734#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 11735/* The actual VLAN tags to insert/remove */ 11736#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 11737#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4 11738#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 11739#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11740#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 11741#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11742/* The MAC address to assign to this v-adaptor */ 11743#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 11744#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 11745/* enum: Derive the MAC address from the upstream port */ 11746#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 11747 11748/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 11749#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 11750 11751/***********************************/ 11752/* MC_CMD_VADAPTOR_FREE 11753 * de-allocate a v-adaptor. 11754 */ 11755#define MC_CMD_VADAPTOR_FREE 0x99 11756#undef MC_CMD_0x99_PRIVILEGE_CTG 11757 11758#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11759 11760/* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 11761#define MC_CMD_VADAPTOR_FREE_IN_LEN 4 11762/* The port to which the v-adaptor is connected. */ 11763#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11764#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4 11765 11766/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 11767#define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 11768 11769/***********************************/ 11770/* MC_CMD_VADAPTOR_SET_MAC 11771 * assign a new MAC address to a v-adaptor. 11772 */ 11773#define MC_CMD_VADAPTOR_SET_MAC 0x5d 11774#undef MC_CMD_0x5d_PRIVILEGE_CTG 11775 11776#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11777 11778/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 11779#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 11780/* The port to which the v-adaptor is connected. */ 11781#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11782#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 11783/* The new MAC address to assign to this v-adaptor */ 11784#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 11785#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 11786 11787/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 11788#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 11789 11790/***********************************/ 11791/* MC_CMD_VADAPTOR_GET_MAC 11792 * read the MAC address assigned to a v-adaptor. 11793 */ 11794#define MC_CMD_VADAPTOR_GET_MAC 0x5e 11795#undef MC_CMD_0x5e_PRIVILEGE_CTG 11796 11797#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11798 11799/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 11800#define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 11801/* The port to which the v-adaptor is connected. */ 11802#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11803#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 11804 11805/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 11806#define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 11807/* The MAC address assigned to this v-adaptor */ 11808#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 11809#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 11810 11811/***********************************/ 11812/* MC_CMD_VADAPTOR_QUERY 11813 * read some config of v-adaptor. 11814 */ 11815#define MC_CMD_VADAPTOR_QUERY 0x61 11816#undef MC_CMD_0x61_PRIVILEGE_CTG 11817 11818#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11819 11820/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 11821#define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 11822/* The port to which the v-adaptor is connected. */ 11823#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11824#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 11825 11826/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 11827#define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 11828/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11829#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 11830#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4 11831/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 11832#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 11833#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4 11834/* The number of VLAN tags that may still be added */ 11835#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 11836#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 11837 11838/***********************************/ 11839/* MC_CMD_EVB_PORT_ASSIGN 11840 * assign a port to a PCI function. 11841 */ 11842#define MC_CMD_EVB_PORT_ASSIGN 0x9a 11843#undef MC_CMD_0x9a_PRIVILEGE_CTG 11844 11845#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11846 11847/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 11848#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 11849/* The port to assign. */ 11850#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 11851#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4 11852/* The target function to modify. */ 11853#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 11854#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4 11855#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 11856#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 11857#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 11858#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 11859 11860/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 11861#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 11862 11863/***********************************/ 11864/* MC_CMD_RDWR_A64_REGIONS 11865 * Assign the 64 bit region addresses. 11866 */ 11867#define MC_CMD_RDWR_A64_REGIONS 0x9b 11868#undef MC_CMD_0x9b_PRIVILEGE_CTG 11869 11870#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11871 11872/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 11873#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 11874#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 11875#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4 11876#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 11877#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4 11878#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 11879#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4 11880#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 11881#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4 11882/* Write enable bits 0-3, set to write, clear to read. */ 11883#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 11884#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 11885#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 11886#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 11887 11888/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 11889 * regardless of state of write bits in the request. 11890 */ 11891#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 11892#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 11893#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4 11894#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 11895#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4 11896#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 11897#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4 11898#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 11899#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4 11900 11901/***********************************/ 11902/* MC_CMD_ONLOAD_STACK_ALLOC 11903 * Allocate an Onload stack ID. 11904 */ 11905#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 11906#undef MC_CMD_0x9c_PRIVILEGE_CTG 11907 11908#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11909 11910/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 11911#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 11912/* The handle of the owning upstream port */ 11913#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11914#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11915 11916/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 11917#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 11918/* The handle of the new Onload stack */ 11919#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 11920#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4 11921 11922/***********************************/ 11923/* MC_CMD_ONLOAD_STACK_FREE 11924 * Free an Onload stack ID. 11925 */ 11926#define MC_CMD_ONLOAD_STACK_FREE 0x9d 11927#undef MC_CMD_0x9d_PRIVILEGE_CTG 11928 11929#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11930 11931/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 11932#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 11933/* The handle of the Onload stack */ 11934#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 11935#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4 11936 11937/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 11938#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 11939 11940/***********************************/ 11941/* MC_CMD_RSS_CONTEXT_ALLOC 11942 * Allocate an RSS context. 11943 */ 11944#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 11945#undef MC_CMD_0x9e_PRIVILEGE_CTG 11946 11947#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11948 11949/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 11950#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 11951/* The handle of the owning upstream port */ 11952#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11953#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11954/* The type of context to allocate */ 11955#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 11956#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4 11957/* enum: Allocate a context for exclusive use. The key and indirection table 11958 * must be explicitly configured. 11959 */ 11960#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 11961/* enum: Allocate a context for shared use; this will spread across a range of 11962 * queues, but the key and indirection table are pre-configured and may not be 11963 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 11964 */ 11965#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 11966/* Number of queues spanned by this context, in the range 1-64; valid offsets 11967 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 11968 */ 11969#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 11970#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4 11971 11972/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 11973#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 11974/* The handle of the new RSS context. This should be considered opaque to the 11975 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11976 * handle. 11977 */ 11978#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 11979#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4 11980/* enum: guaranteed invalid RSS context handle value */ 11981#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 11982 11983/***********************************/ 11984/* MC_CMD_RSS_CONTEXT_FREE 11985 * Free an RSS context. 11986 */ 11987#define MC_CMD_RSS_CONTEXT_FREE 0x9f 11988#undef MC_CMD_0x9f_PRIVILEGE_CTG 11989 11990#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11991 11992/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 11993#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 11994/* The handle of the RSS context */ 11995#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 11996#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4 11997 11998/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 11999#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 12000 12001/***********************************/ 12002/* MC_CMD_RSS_CONTEXT_SET_KEY 12003 * Set the Toeplitz hash key for an RSS context. 12004 */ 12005#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 12006#undef MC_CMD_0xa0_PRIVILEGE_CTG 12007 12008#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12009 12010/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 12011#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 12012/* The handle of the RSS context */ 12013#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 12014#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4 12015/* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 12016#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 12017#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 12018 12019/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 12020#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 12021 12022/***********************************/ 12023/* MC_CMD_RSS_CONTEXT_GET_KEY 12024 * Get the Toeplitz hash key for an RSS context. 12025 */ 12026#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 12027#undef MC_CMD_0xa1_PRIVILEGE_CTG 12028 12029#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12030 12031/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 12032#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 12033/* The handle of the RSS context */ 12034#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 12035#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4 12036 12037/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 12038#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 12039/* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 12040#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 12041#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 12042 12043/***********************************/ 12044/* MC_CMD_RSS_CONTEXT_SET_TABLE 12045 * Set the indirection table for an RSS context. 12046 */ 12047#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 12048#undef MC_CMD_0xa2_PRIVILEGE_CTG 12049 12050#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12051 12052/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 12053#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 12054/* The handle of the RSS context */ 12055#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 12056#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 12057/* The 128-byte indirection table (1 byte per entry) */ 12058#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 12059#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 12060 12061/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 12062#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 12063 12064/***********************************/ 12065/* MC_CMD_RSS_CONTEXT_GET_TABLE 12066 * Get the indirection table for an RSS context. 12067 */ 12068#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 12069#undef MC_CMD_0xa3_PRIVILEGE_CTG 12070 12071#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12072 12073/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 12074#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 12075/* The handle of the RSS context */ 12076#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 12077#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 12078 12079/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 12080#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 12081/* The 128-byte indirection table (1 byte per entry) */ 12082#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 12083#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 12084 12085/***********************************/ 12086/* MC_CMD_RSS_CONTEXT_SET_FLAGS 12087 * Set various control flags for an RSS context. 12088 */ 12089#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 12090#undef MC_CMD_0xe1_PRIVILEGE_CTG 12091 12092#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12093 12094/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 12095#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 12096/* The handle of the RSS context */ 12097#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 12098#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 12099/* Hash control flags. The _EN bits are always supported, but new modes are 12100 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 12101 * in this case, the MODE fields may be set to non-zero values, and will take 12102 * effect regardless of the settings of the _EN flags. See the RSS_MODE 12103 * structure for the meaning of the mode bits. Drivers must check the 12104 * capability before trying to set any _MODE fields, as older firmware will 12105 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 12106 * the case where all the _MODE flags are zero, the _EN flags take effect, 12107 * providing backward compatibility for existing drivers. (Setting all _MODE 12108 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 12109 * particular packet type.) 12110 */ 12111#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 12112#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4 12113#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 12114#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 12115#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 12116#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 12117#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 12118#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 12119#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 12120#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 12121#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 12122#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 12123#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 12124#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 12125#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 12126#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 12127#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 12128#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 12129#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 12130#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 12131#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 12132#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 12133#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 12134#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 12135 12136/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 12137#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 12138 12139/***********************************/ 12140/* MC_CMD_RSS_CONTEXT_GET_FLAGS 12141 * Get various control flags for an RSS context. 12142 */ 12143#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 12144#undef MC_CMD_0xe2_PRIVILEGE_CTG 12145 12146#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12147 12148/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 12149#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 12150/* The handle of the RSS context */ 12151#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 12152#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 12153 12154/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 12155#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 12156/* Hash control flags. If all _MODE bits are zero (which will always be true 12157 * for older firmware which does not report the ADDITIONAL_RSS_MODES 12158 * capability), the _EN bits report the state. If any _MODE bits are non-zero 12159 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 12160 * then the _EN bits should be disregarded, although the _MODE flags are 12161 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 12162 * context and in the case where the _EN flags were used in the SET. This 12163 * provides backward compatibility: old drivers will not be attempting to 12164 * derive any meaning from the _MODE bits (and can never set them to any value 12165 * not representable by the _EN bits); new drivers can always determine the 12166 * mode by looking only at the _MODE bits; the value returned by a GET can 12167 * always be used for a SET regardless of old/new driver vs. old/new firmware. 12168 */ 12169#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 12170#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4 12171#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 12172#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 12173#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 12174#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 12175#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 12176#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 12177#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 12178#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 12179#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 12180#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 12181#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 12182#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 12183#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 12184#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 12185#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 12186#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 12187#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 12188#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 12189#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 12190#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 12191#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 12192#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 12193 12194/***********************************/ 12195/* MC_CMD_DOT1P_MAPPING_ALLOC 12196 * Allocate a .1p mapping. 12197 */ 12198#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 12199#undef MC_CMD_0xa4_PRIVILEGE_CTG 12200 12201#define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12202 12203/* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 12204#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 12205/* The handle of the owning upstream port */ 12206#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 12207#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 12208/* Number of queues spanned by this mapping, in the range 1-64; valid fixed 12209 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 12210 * referenced RSS contexts must span no more than this number. 12211 */ 12212#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 12213#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4 12214 12215/* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 12216#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 12217/* The handle of the new .1p mapping. This should be considered opaque to the 12218 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 12219 * handle. 12220 */ 12221#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 12222#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4 12223/* enum: guaranteed invalid .1p mapping handle value */ 12224#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 12225 12226/***********************************/ 12227/* MC_CMD_DOT1P_MAPPING_FREE 12228 * Free a .1p mapping. 12229 */ 12230#define MC_CMD_DOT1P_MAPPING_FREE 0xa5 12231#undef MC_CMD_0xa5_PRIVILEGE_CTG 12232 12233#define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12234 12235/* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 12236#define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 12237/* The handle of the .1p mapping */ 12238#define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 12239#define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4 12240 12241/* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 12242#define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 12243 12244/***********************************/ 12245/* MC_CMD_DOT1P_MAPPING_SET_TABLE 12246 * Set the mapping table for a .1p mapping. 12247 */ 12248#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 12249#undef MC_CMD_0xa6_PRIVILEGE_CTG 12250 12251#define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12252 12253/* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 12254#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 12255/* The handle of the .1p mapping */ 12256#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12257#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 12258/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12259 * handle) 12260 */ 12261#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 12262#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 12263 12264/* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 12265#define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 12266 12267/***********************************/ 12268/* MC_CMD_DOT1P_MAPPING_GET_TABLE 12269 * Get the mapping table for a .1p mapping. 12270 */ 12271#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 12272#undef MC_CMD_0xa7_PRIVILEGE_CTG 12273 12274#define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12275 12276/* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 12277#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 12278/* The handle of the .1p mapping */ 12279#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12280#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 12281 12282/* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 12283#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 12284/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12285 * handle) 12286 */ 12287#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 12288#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 12289 12290/***********************************/ 12291/* MC_CMD_GET_VECTOR_CFG 12292 * Get Interrupt Vector config for this PF. 12293 */ 12294#define MC_CMD_GET_VECTOR_CFG 0xbf 12295#undef MC_CMD_0xbf_PRIVILEGE_CTG 12296 12297#define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12298 12299/* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 12300#define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 12301 12302/* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 12303#define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 12304/* Base absolute interrupt vector number. */ 12305#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 12306#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4 12307/* Number of interrupt vectors allocate to this PF. */ 12308#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 12309#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4 12310/* Number of interrupt vectors to allocate per VF. */ 12311#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 12312#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4 12313 12314/***********************************/ 12315/* MC_CMD_SET_VECTOR_CFG 12316 * Set Interrupt Vector config for this PF. 12317 */ 12318#define MC_CMD_SET_VECTOR_CFG 0xc0 12319#undef MC_CMD_0xc0_PRIVILEGE_CTG 12320 12321#define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12322 12323/* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 12324#define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 12325/* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 12326 * let the system find a suitable base. 12327 */ 12328#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 12329#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4 12330/* Number of interrupt vectors allocate to this PF. */ 12331#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 12332#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4 12333/* Number of interrupt vectors to allocate per VF. */ 12334#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 12335#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4 12336 12337/* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 12338#define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 12339 12340/***********************************/ 12341/* MC_CMD_VPORT_ADD_MAC_ADDRESS 12342 * Add a MAC address to a v-port 12343 */ 12344#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 12345#undef MC_CMD_0xa8_PRIVILEGE_CTG 12346 12347#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12348 12349/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 12350#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 12351/* The handle of the v-port */ 12352#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12353#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4 12354/* MAC address to add */ 12355#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 12356#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 12357 12358/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 12359#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 12360 12361/***********************************/ 12362/* MC_CMD_VPORT_DEL_MAC_ADDRESS 12363 * Delete a MAC address from a v-port 12364 */ 12365#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 12366#undef MC_CMD_0xa9_PRIVILEGE_CTG 12367 12368#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12369 12370/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 12371#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 12372/* The handle of the v-port */ 12373#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12374#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4 12375/* MAC address to add */ 12376#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 12377#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 12378 12379/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 12380#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 12381 12382/***********************************/ 12383/* MC_CMD_VPORT_GET_MAC_ADDRESSES 12384 * Delete a MAC address from a v-port 12385 */ 12386#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 12387#undef MC_CMD_0xaa_PRIVILEGE_CTG 12388 12389#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12390 12391/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 12392#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 12393/* The handle of the v-port */ 12394#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 12395#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4 12396 12397/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 12398#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 12399#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 12400#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 12401/* The number of MAC addresses returned */ 12402#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 12403#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4 12404/* Array of MAC addresses */ 12405#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 12406#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 12407#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 12408#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 12409 12410/***********************************/ 12411/* MC_CMD_VPORT_RECONFIGURE 12412 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 12413 * has already been passed to another function (v-port's user), then that 12414 * function will be reset before applying the changes. 12415 */ 12416#define MC_CMD_VPORT_RECONFIGURE 0xeb 12417#undef MC_CMD_0xeb_PRIVILEGE_CTG 12418 12419#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12420 12421/* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 12422#define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 12423/* The handle of the v-port */ 12424#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 12425#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4 12426/* Flags requesting what should be changed. */ 12427#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 12428#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4 12429#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 12430#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 12431#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 12432#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 12433/* The number of VLAN tags to insert/remove. An error will be returned if 12434 * incompatible with the number of VLAN tags specified for the upstream 12435 * v-switch. 12436 */ 12437#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 12438#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4 12439/* The actual VLAN tags to insert/remove */ 12440#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 12441#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4 12442#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 12443#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 12444#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 12445#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 12446/* The number of MAC addresses to add */ 12447#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 12448#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4 12449/* MAC addresses to add */ 12450#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 12451#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 12452#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 12453 12454/* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 12455#define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 12456#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 12457#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4 12458#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 12459#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 12460 12461/***********************************/ 12462/* MC_CMD_EVB_PORT_QUERY 12463 * read some config of v-port. 12464 */ 12465#define MC_CMD_EVB_PORT_QUERY 0x62 12466#undef MC_CMD_0x62_PRIVILEGE_CTG 12467 12468#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12469 12470/* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 12471#define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 12472/* The handle of the v-port */ 12473#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 12474#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4 12475 12476/* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 12477#define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 12478/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 12479#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 12480#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4 12481/* The number of VLAN tags that may be used on a v-adaptor connected to this 12482 * EVB port. 12483 */ 12484#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 12485#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 12486 12487/***********************************/ 12488/* MC_CMD_DUMP_BUFTBL_ENTRIES 12489 * Dump buffer table entries, mainly for command client debug use. Dumps 12490 * absolute entries, and does not use chunk handles. All entries must be in 12491 * range, and used for q page mapping, Although the latter restriction may be 12492 * lifted in future. 12493 */ 12494#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 12495#undef MC_CMD_0xab_PRIVILEGE_CTG 12496 12497#define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12498 12499/* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 12500#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 12501/* Index of the first buffer table entry. */ 12502#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 12503#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 12504/* Number of buffer table entries to dump. */ 12505#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 12506#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 12507 12508/* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 12509#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 12510#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 12511#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 12512/* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 12513#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 12514#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 12515#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 12516#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 12517 12518/***********************************/ 12519/* MC_CMD_SET_RXDP_CONFIG 12520 * Set global RXDP configuration settings 12521 */ 12522#define MC_CMD_SET_RXDP_CONFIG 0xc1 12523#undef MC_CMD_0xc1_PRIVILEGE_CTG 12524 12525#define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12526 12527/* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 12528#define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 12529#define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 12530#define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4 12531#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 12532#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 12533#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 12534#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 12535/* enum: pad to 64 bytes */ 12536#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 12537/* enum: pad to 128 bytes (Medford only) */ 12538#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 12539/* enum: pad to 256 bytes (Medford only) */ 12540#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 12541 12542/* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 12543#define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 12544 12545/***********************************/ 12546/* MC_CMD_GET_RXDP_CONFIG 12547 * Get global RXDP configuration settings 12548 */ 12549#define MC_CMD_GET_RXDP_CONFIG 0xc2 12550#undef MC_CMD_0xc2_PRIVILEGE_CTG 12551 12552#define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12553 12554/* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 12555#define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 12556 12557/* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 12558#define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 12559#define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 12560#define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4 12561#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 12562#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 12563#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 12564#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 12565/* Enum values, see field(s): */ 12566/* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 12567 12568/***********************************/ 12569/* MC_CMD_GET_CLOCK 12570 * Return the system and PDCPU clock frequencies. 12571 */ 12572#define MC_CMD_GET_CLOCK 0xac 12573#undef MC_CMD_0xac_PRIVILEGE_CTG 12574 12575#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12576 12577/* MC_CMD_GET_CLOCK_IN msgrequest */ 12578#define MC_CMD_GET_CLOCK_IN_LEN 0 12579 12580/* MC_CMD_GET_CLOCK_OUT msgresponse */ 12581#define MC_CMD_GET_CLOCK_OUT_LEN 8 12582/* System frequency, MHz */ 12583#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 12584#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4 12585/* DPCPU frequency, MHz */ 12586#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 12587#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4 12588 12589/***********************************/ 12590/* MC_CMD_SET_CLOCK 12591 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 12592 */ 12593#define MC_CMD_SET_CLOCK 0xad 12594#undef MC_CMD_0xad_PRIVILEGE_CTG 12595 12596#define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12597 12598/* MC_CMD_SET_CLOCK_IN msgrequest */ 12599#define MC_CMD_SET_CLOCK_IN_LEN 28 12600/* Requested frequency in MHz for system clock domain */ 12601#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 12602#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4 12603/* enum: Leave the system clock domain frequency unchanged */ 12604#define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 12605/* Requested frequency in MHz for inter-core clock domain */ 12606#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 12607#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4 12608/* enum: Leave the inter-core clock domain frequency unchanged */ 12609#define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 12610/* Requested frequency in MHz for DPCPU clock domain */ 12611#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 12612#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4 12613/* enum: Leave the DPCPU clock domain frequency unchanged */ 12614#define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 12615/* Requested frequency in MHz for PCS clock domain */ 12616#define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 12617#define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4 12618/* enum: Leave the PCS clock domain frequency unchanged */ 12619#define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 12620/* Requested frequency in MHz for MC clock domain */ 12621#define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 12622#define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4 12623/* enum: Leave the MC clock domain frequency unchanged */ 12624#define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 12625/* Requested frequency in MHz for rmon clock domain */ 12626#define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 12627#define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4 12628/* enum: Leave the rmon clock domain frequency unchanged */ 12629#define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 12630/* Requested frequency in MHz for vswitch clock domain */ 12631#define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 12632#define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4 12633/* enum: Leave the vswitch clock domain frequency unchanged */ 12634#define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 12635 12636/* MC_CMD_SET_CLOCK_OUT msgresponse */ 12637#define MC_CMD_SET_CLOCK_OUT_LEN 28 12638/* Resulting system frequency in MHz */ 12639#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 12640#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4 12641/* enum: The system clock domain doesn't exist */ 12642#define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 12643/* Resulting inter-core frequency in MHz */ 12644#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 12645#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4 12646/* enum: The inter-core clock domain doesn't exist / isn't used */ 12647#define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 12648/* Resulting DPCPU frequency in MHz */ 12649#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 12650#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4 12651/* enum: The dpcpu clock domain doesn't exist */ 12652#define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 12653/* Resulting PCS frequency in MHz */ 12654#define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 12655#define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4 12656/* enum: The PCS clock domain doesn't exist / isn't controlled */ 12657#define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 12658/* Resulting MC frequency in MHz */ 12659#define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 12660#define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4 12661/* enum: The MC clock domain doesn't exist / isn't controlled */ 12662#define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 12663/* Resulting rmon frequency in MHz */ 12664#define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 12665#define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4 12666/* enum: The rmon clock domain doesn't exist / isn't controlled */ 12667#define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 12668/* Resulting vswitch frequency in MHz */ 12669#define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 12670#define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4 12671/* enum: The vswitch clock domain doesn't exist / isn't controlled */ 12672#define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 12673 12674/***********************************/ 12675/* MC_CMD_DPCPU_RPC 12676 * Send an arbitrary DPCPU message. 12677 */ 12678#define MC_CMD_DPCPU_RPC 0xae 12679#undef MC_CMD_0xae_PRIVILEGE_CTG 12680 12681#define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12682 12683/* MC_CMD_DPCPU_RPC_IN msgrequest */ 12684#define MC_CMD_DPCPU_RPC_IN_LEN 36 12685#define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 12686#define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4 12687/* enum: RxDPCPU0 */ 12688#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 12689/* enum: TxDPCPU0 */ 12690#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 12691/* enum: TxDPCPU1 */ 12692#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 12693/* enum: RxDPCPU1 (Medford only) */ 12694#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 12695/* enum: RxDPCPU (will be for the calling function; for now, just an alias of 12696 * DPCPU_RX0) 12697 */ 12698#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 12699/* enum: TxDPCPU (will be for the calling function; for now, just an alias of 12700 * DPCPU_TX0) 12701 */ 12702#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 12703/* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 12704 * initialised to zero 12705 */ 12706#define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 12707#define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 12708#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 12709#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 12710#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 12711#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 12712#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 12713#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 12714#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 12715#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 12716#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 12717#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 12718#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 12719#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 12720#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 12721#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 12722#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 12723#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 12724#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 12725#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 12726#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 12727#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 12728#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 12729#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 12730#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 12731#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 12732#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 12733#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 12734#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 12735#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 12736#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 12737#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 12738#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 12739#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 12740#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 12741#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 12742#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 12743#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 12744#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 12745#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 12746#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 12747#define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 12748#define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 12749/* Register data to write. Only valid in write/write-read. */ 12750#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 12751#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4 12752/* Register address. */ 12753#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 12754#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4 12755 12756/* MC_CMD_DPCPU_RPC_OUT msgresponse */ 12757#define MC_CMD_DPCPU_RPC_OUT_LEN 36 12758#define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 12759#define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4 12760/* DATA */ 12761#define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 12762#define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 12763#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 12764#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 12765#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 12766#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 12767#define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 12768#define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 12769#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 12770#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4 12771#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 12772#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4 12773#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 12774#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4 12775#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 12776#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4 12777 12778/***********************************/ 12779/* MC_CMD_TRIGGER_INTERRUPT 12780 * Trigger an interrupt by prodding the BIU. 12781 */ 12782#define MC_CMD_TRIGGER_INTERRUPT 0xe3 12783#undef MC_CMD_0xe3_PRIVILEGE_CTG 12784 12785#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12786 12787/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 12788#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 12789/* Interrupt level relative to base for function. */ 12790#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 12791#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4 12792 12793/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 12794#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 12795 12796/***********************************/ 12797/* MC_CMD_SHMBOOT_OP 12798 * Special operations to support (for now) shmboot. 12799 */ 12800#define MC_CMD_SHMBOOT_OP 0xe6 12801#undef MC_CMD_0xe6_PRIVILEGE_CTG 12802 12803#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 12804 12805/* MC_CMD_SHMBOOT_OP_IN msgrequest */ 12806#define MC_CMD_SHMBOOT_OP_IN_LEN 4 12807/* Identifies the operation to perform */ 12808#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 12809#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4 12810/* enum: Copy slave_data section to the slave core. (Greenport only) */ 12811#define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 12812 12813/* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 12814#define MC_CMD_SHMBOOT_OP_OUT_LEN 0 12815 12816/***********************************/ 12817/* MC_CMD_CAP_BLK_READ 12818 * Read multiple 64bit words from capture block memory 12819 */ 12820#define MC_CMD_CAP_BLK_READ 0xe7 12821#undef MC_CMD_0xe7_PRIVILEGE_CTG 12822 12823#define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12824 12825/* MC_CMD_CAP_BLK_READ_IN msgrequest */ 12826#define MC_CMD_CAP_BLK_READ_IN_LEN 12 12827#define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 12828#define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4 12829#define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 12830#define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4 12831#define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 12832#define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4 12833 12834/* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 12835#define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 12836#define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 12837#define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 12838#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 12839#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 12840#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 12841#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 12842#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 12843#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 12844 12845/***********************************/ 12846/* MC_CMD_DUMP_DO 12847 * Take a dump of the DUT state 12848 */ 12849#define MC_CMD_DUMP_DO 0xe8 12850#undef MC_CMD_0xe8_PRIVILEGE_CTG 12851 12852#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12853 12854/* MC_CMD_DUMP_DO_IN msgrequest */ 12855#define MC_CMD_DUMP_DO_IN_LEN 52 12856#define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 12857#define MC_CMD_DUMP_DO_IN_PADDING_LEN 4 12858#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 12859#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4 12860#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 12861#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 12862#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 12863#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 12864#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 12865#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 12866#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 12867#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 12868#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 12869#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 12870#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 12871#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 12872#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 12873#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 12874#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 12875#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 12876#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 12877#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 12878#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 12879#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 12880#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 12881#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 12882#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 12883#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 12884#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 12885#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 12886/* enum: The uart port this command was received over (if using a uart 12887 * transport) 12888 */ 12889#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 12890#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 12891#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 12892#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 12893#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4 12894#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 12895#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 12896#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 12897#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 12898/* Enum values, see field(s): */ 12899/* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12900#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 12901#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 12902#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 12903#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 12904#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 12905#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 12906#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 12907#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 12908#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 12909#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 12910#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 12911#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 12912#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 12913#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 12914#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 12915#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 12916#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 12917#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 12918 12919/* MC_CMD_DUMP_DO_OUT msgresponse */ 12920#define MC_CMD_DUMP_DO_OUT_LEN 4 12921#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 12922#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4 12923 12924/***********************************/ 12925/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 12926 * Configure unsolicited dumps 12927 */ 12928#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 12929#undef MC_CMD_0xe9_PRIVILEGE_CTG 12930 12931#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12932 12933/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 12934#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 12935#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 12936#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4 12937#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 12938#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4 12939/* Enum values, see field(s): */ 12940/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 12941#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 12942#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 12943/* Enum values, see field(s): */ 12944/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12945#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 12946#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 12947#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 12948#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 12949#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 12950#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 12951#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 12952#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 12953#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 12954#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 12955#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 12956#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 12957#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 12958#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 12959#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 12960#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 12961#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 12962#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 12963#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 12964#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4 12965/* Enum values, see field(s): */ 12966/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 12967#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 12968#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 12969/* Enum values, see field(s): */ 12970/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12971#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 12972#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 12973#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 12974#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 12975#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 12976#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 12977#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 12978#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 12979#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 12980#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 12981#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 12982#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 12983#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 12984#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 12985#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 12986#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 12987#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 12988#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 12989 12990/***********************************/ 12991/* MC_CMD_SET_PSU 12992 * Adjusts power supply parameters. This is a warranty-voiding operation. 12993 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 12994 * the parameter is out of range. 12995 */ 12996#define MC_CMD_SET_PSU 0xea 12997#undef MC_CMD_0xea_PRIVILEGE_CTG 12998 12999#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13000 13001/* MC_CMD_SET_PSU_IN msgrequest */ 13002#define MC_CMD_SET_PSU_IN_LEN 12 13003#define MC_CMD_SET_PSU_IN_PARAM_OFST 0 13004#define MC_CMD_SET_PSU_IN_PARAM_LEN 4 13005#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 13006#define MC_CMD_SET_PSU_IN_RAIL_OFST 4 13007#define MC_CMD_SET_PSU_IN_RAIL_LEN 4 13008#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 13009#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 13010/* desired value, eg voltage in mV */ 13011#define MC_CMD_SET_PSU_IN_VALUE_OFST 8 13012#define MC_CMD_SET_PSU_IN_VALUE_LEN 4 13013 13014/* MC_CMD_SET_PSU_OUT msgresponse */ 13015#define MC_CMD_SET_PSU_OUT_LEN 0 13016 13017/***********************************/ 13018/* MC_CMD_GET_FUNCTION_INFO 13019 * Get function information. PF and VF number. 13020 */ 13021#define MC_CMD_GET_FUNCTION_INFO 0xec 13022#undef MC_CMD_0xec_PRIVILEGE_CTG 13023 13024#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13025 13026/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 13027#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 13028 13029/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 13030#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 13031#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 13032#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4 13033#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 13034#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4 13035 13036/***********************************/ 13037/* MC_CMD_ENABLE_OFFLINE_BIST 13038 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 13039 * mode, calling function gets exclusive MCDI ownership. The only way out is 13040 * reboot. 13041 */ 13042#define MC_CMD_ENABLE_OFFLINE_BIST 0xed 13043#undef MC_CMD_0xed_PRIVILEGE_CTG 13044 13045#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 13046 13047/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 13048#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 13049 13050/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 13051#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 13052 13053/***********************************/ 13054/* MC_CMD_UART_SEND_DATA 13055 * Send checksummed[sic] block of data over the uart. Response is a placeholder 13056 * should we wish to make this reliable; currently requests are fire-and- 13057 * forget. 13058 */ 13059#define MC_CMD_UART_SEND_DATA 0xee 13060#undef MC_CMD_0xee_PRIVILEGE_CTG 13061 13062#define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13063 13064/* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 13065#define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 13066#define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 13067#define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 13068/* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 13069#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 13070#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4 13071/* Offset at which to write the data */ 13072#define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 13073#define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4 13074/* Length of data */ 13075#define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 13076#define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4 13077/* Reserved for future use */ 13078#define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 13079#define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4 13080#define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 13081#define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 13082#define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 13083#define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 13084 13085/* MC_CMD_UART_SEND_DATA_IN msgresponse */ 13086#define MC_CMD_UART_SEND_DATA_IN_LEN 0 13087 13088/***********************************/ 13089/* MC_CMD_UART_RECV_DATA 13090 * Request checksummed[sic] block of data over the uart. Only a placeholder, 13091 * subject to change and not currently implemented. 13092 */ 13093#define MC_CMD_UART_RECV_DATA 0xef 13094#undef MC_CMD_0xef_PRIVILEGE_CTG 13095 13096#define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13097 13098/* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 13099#define MC_CMD_UART_RECV_DATA_OUT_LEN 16 13100/* CRC32 over OFFSET, LENGTH, RESERVED */ 13101#define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 13102#define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4 13103/* Offset from which to read the data */ 13104#define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 13105#define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4 13106/* Length of data */ 13107#define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 13108#define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4 13109/* Reserved for future use */ 13110#define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 13111#define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4 13112 13113/* MC_CMD_UART_RECV_DATA_IN msgresponse */ 13114#define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 13115#define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 13116#define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 13117/* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 13118#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 13119#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4 13120/* Offset at which to write the data */ 13121#define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 13122#define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4 13123/* Length of data */ 13124#define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 13125#define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4 13126/* Reserved for future use */ 13127#define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 13128#define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4 13129#define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 13130#define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 13131#define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 13132#define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 13133 13134/***********************************/ 13135/* MC_CMD_READ_FUSES 13136 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 13137 */ 13138#define MC_CMD_READ_FUSES 0xf0 13139#undef MC_CMD_0xf0_PRIVILEGE_CTG 13140 13141#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13142 13143/* MC_CMD_READ_FUSES_IN msgrequest */ 13144#define MC_CMD_READ_FUSES_IN_LEN 8 13145/* Offset in OTP to read */ 13146#define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 13147#define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4 13148/* Length of data to read in bytes */ 13149#define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 13150#define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4 13151 13152/* MC_CMD_READ_FUSES_OUT msgresponse */ 13153#define MC_CMD_READ_FUSES_OUT_LENMIN 4 13154#define MC_CMD_READ_FUSES_OUT_LENMAX 252 13155#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 13156/* Length of returned OTP data in bytes */ 13157#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 13158#define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4 13159/* Returned data */ 13160#define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 13161#define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 13162#define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 13163#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 13164 13165/***********************************/ 13166/* MC_CMD_KR_TUNE 13167 * Get or set KR Serdes RXEQ and TX Driver settings 13168 */ 13169#define MC_CMD_KR_TUNE 0xf1 13170#undef MC_CMD_0xf1_PRIVILEGE_CTG 13171 13172#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 13173 13174/* MC_CMD_KR_TUNE_IN msgrequest */ 13175#define MC_CMD_KR_TUNE_IN_LENMIN 4 13176#define MC_CMD_KR_TUNE_IN_LENMAX 252 13177#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 13178/* Requested operation */ 13179#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 13180#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 13181/* enum: Get current RXEQ settings */ 13182#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 13183/* enum: Override RXEQ settings */ 13184#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 13185/* enum: Get current TX Driver settings */ 13186#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 13187/* enum: Override TX Driver settings */ 13188#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 13189/* enum: Force KR Serdes reset / recalibration */ 13190#define MC_CMD_KR_TUNE_IN_RECAL 0x4 13191/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 13192 * signal. 13193 */ 13194#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 13195/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 13196 * caller should call this command repeatedly after starting eye plot, until no 13197 * more data is returned. 13198 */ 13199#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 13200/* enum: Read Figure Of Merit (eye quality, higher is better). */ 13201#define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 13202/* enum: Start/stop link training frames */ 13203#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8 13204/* enum: Issue KR link training command (control training coefficients) */ 13205#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9 13206/* Align the arguments to 32 bits */ 13207#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 13208#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 13209/* Arguments specific to the operation */ 13210#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 13211#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 13212#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 13213#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 13214 13215/* MC_CMD_KR_TUNE_OUT msgresponse */ 13216#define MC_CMD_KR_TUNE_OUT_LEN 0 13217 13218/* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 13219#define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 13220/* Requested operation */ 13221#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 13222#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 13223/* Align the arguments to 32 bits */ 13224#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 13225#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 13226 13227/* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 13228#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 13229#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 13230#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 13231/* RXEQ Parameter */ 13232#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 13233#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 13234#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 13235#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 13236#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 13237#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 13238/* enum: Attenuation (0-15, Huntington) */ 13239#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 13240/* enum: CTLE Boost (0-15, Huntington) */ 13241#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 13242/* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 13243 * positive, Medford - 0-31) 13244 */ 13245#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 13246/* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 13247 * positive, Medford - 0-31) 13248 */ 13249#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 13250/* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 13251 * positive, Medford - 0-16) 13252 */ 13253#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 13254/* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 13255 * positive, Medford - 0-16) 13256 */ 13257#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 13258/* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 13259 * positive, Medford - 0-16) 13260 */ 13261#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 13262/* enum: Edge DFE DLEV (0-128 for Medford) */ 13263#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 13264/* enum: Variable Gain Amplifier (0-15, Medford) */ 13265#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 13266/* enum: CTLE EQ Capacitor (0-15, Medford) */ 13267#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 13268/* enum: CTLE EQ Resistor (0-7, Medford) */ 13269#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 13270/* enum: CTLE gain (0-31, Medford2) */ 13271#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb 13272/* enum: CTLE pole (0-31, Medford2) */ 13273#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc 13274/* enum: CTLE peaking (0-31, Medford2) */ 13275#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd 13276/* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */ 13277#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe 13278/* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */ 13279#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf 13280/* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */ 13281#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10 13282/* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */ 13283#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11 13284/* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */ 13285#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12 13286/* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */ 13287#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13 13288/* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */ 13289#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14 13290/* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */ 13291#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15 13292/* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */ 13293#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16 13294/* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */ 13295#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17 13296/* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */ 13297#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18 13298/* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */ 13299#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19 13300/* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */ 13301#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a 13302/* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */ 13303#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b 13304/* enum: Negative h1 polarity data sampler offset calibration code, even path 13305 * (Medford2 - 6 bit signed (-29 - +29))) 13306 */ 13307#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c 13308/* enum: Negative h1 polarity data sampler offset calibration code, odd path 13309 * (Medford2 - 6 bit signed (-29 - +29))) 13310 */ 13311#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d 13312/* enum: Positive h1 polarity data sampler offset calibration code, even path 13313 * (Medford2 - 6 bit signed (-29 - +29))) 13314 */ 13315#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e 13316/* enum: Positive h1 polarity data sampler offset calibration code, odd path 13317 * (Medford2 - 6 bit signed (-29 - +29))) 13318 */ 13319#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f 13320/* enum: CDR calibration loop code (Medford2) */ 13321#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20 13322/* enum: CDR integral loop code (Medford2) */ 13323#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21 13324#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 13325#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 13326#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13327#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13328#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13329#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13330#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 13331#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 13332#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 13333#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 13334#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 13335#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 13336#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 13337#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13338#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13339 13340/* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 13341#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 13342#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 13343#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 13344/* Requested operation */ 13345#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 13346#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 13347/* Align the arguments to 32 bits */ 13348#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 13349#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 13350/* RXEQ Parameter */ 13351#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 13352#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 13353#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 13354#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 13355#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 13356#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 13357/* Enum values, see field(s): */ 13358/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 13359#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 13360#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 13361/* Enum values, see field(s): */ 13362/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13363#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 13364#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 13365#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 13366#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 13367#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 13368#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13369#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 13370#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 13371 13372/* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 13373#define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 13374 13375/* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 13376#define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 13377/* Requested operation */ 13378#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 13379#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 13380/* Align the arguments to 32 bits */ 13381#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 13382#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 13383 13384/* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 13385#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 13386#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 13387#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13388/* TXEQ Parameter */ 13389#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13390#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13391#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13392#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13393#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13394#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13395/* enum: TX Amplitude (Huntington, Medford, Medford2) */ 13396#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 13397/* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 13398#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 13399/* enum: De-Emphasis Tap1 Fine */ 13400#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 13401/* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 13402#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 13403/* enum: De-Emphasis Tap2 Fine (Huntington) */ 13404#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 13405/* enum: Pre-Emphasis Magnitude (Huntington) */ 13406#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 13407/* enum: Pre-Emphasis Fine (Huntington) */ 13408#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 13409/* enum: TX Slew Rate Coarse control (Huntington) */ 13410#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 13411/* enum: TX Slew Rate Fine control (Huntington) */ 13412#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 13413/* enum: TX Termination Impedance control (Huntington) */ 13414#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 13415/* enum: TX Amplitude Fine control (Medford) */ 13416#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 13417/* enum: Pre-shoot Tap (Medford, Medford2) */ 13418#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 13419/* enum: De-emphasis Tap (Medford, Medford2) */ 13420#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 13421#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13422#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 13423#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13424#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13425#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13426#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13427#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 13428#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 13429#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 13430#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 13431#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 13432#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 13433#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 13434 13435/* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 13436#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 13437#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 13438#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 13439/* Requested operation */ 13440#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 13441#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 13442/* Align the arguments to 32 bits */ 13443#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 13444#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 13445/* TXEQ Parameter */ 13446#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 13447#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 13448#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 13449#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 13450#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 13451#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 13452/* Enum values, see field(s): */ 13453/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 13454#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 13455#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 13456/* Enum values, see field(s): */ 13457/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 13458#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 13459#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 13460#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 13461#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13462#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 13463#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 13464 13465/* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 13466#define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 13467 13468/* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 13469#define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 13470/* Requested operation */ 13471#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 13472#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 13473/* Align the arguments to 32 bits */ 13474#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 13475#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 13476 13477/* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 13478#define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 13479 13480/* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 13481#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 13482/* Requested operation */ 13483#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13484#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13485/* Align the arguments to 32 bits */ 13486#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13487#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13488/* Port-relative lane to scan eye on */ 13489#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13490#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 13491 13492/* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */ 13493#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12 13494/* Requested operation */ 13495#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0 13496#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1 13497/* Align the arguments to 32 bits */ 13498#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1 13499#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3 13500#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4 13501#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4 13502#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0 13503#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8 13504#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31 13505#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1 13506/* Scan duration / cycle count */ 13507#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8 13508#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4 13509 13510/* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 13511#define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 13512 13513/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 13514#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 13515/* Requested operation */ 13516#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13517#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13518/* Align the arguments to 32 bits */ 13519#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13520#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13521 13522/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 13523#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 13524#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 13525#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 13526#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 13527#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 13528#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 13529#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 13530 13531/* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 13532#define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 13533/* Requested operation */ 13534#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 13535#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 13536/* Align the arguments to 32 bits */ 13537#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 13538#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 13539#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 13540#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4 13541#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0 13542#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8 13543#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31 13544#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1 13545 13546/* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 13547#define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 13548#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 13549#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4 13550 13551/* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */ 13552#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8 13553/* Requested operation */ 13554#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0 13555#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1 13556/* Align the arguments to 32 bits */ 13557#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1 13558#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3 13559#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4 13560#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4 13561#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */ 13562#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */ 13563 13564/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */ 13565#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28 13566/* Requested operation */ 13567#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0 13568#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1 13569/* Align the arguments to 32 bits */ 13570#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1 13571#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3 13572#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4 13573#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4 13574/* Set INITIALIZE state */ 13575#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8 13576#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4 13577/* Set PRESET state */ 13578#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12 13579#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4 13580/* C(-1) request */ 13581#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16 13582#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4 13583#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */ 13584#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */ 13585#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */ 13586/* C(0) request */ 13587#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20 13588#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4 13589/* Enum values, see field(s): */ 13590/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13591/* C(+1) request */ 13592#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24 13593#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4 13594/* Enum values, see field(s): */ 13595/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13596 13597/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */ 13598#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24 13599/* C(-1) status */ 13600#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0 13601#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4 13602#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */ 13603#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */ 13604#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */ 13605#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */ 13606/* C(0) status */ 13607#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4 13608#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4 13609/* Enum values, see field(s): */ 13610/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13611/* C(+1) status */ 13612#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8 13613#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4 13614/* Enum values, see field(s): */ 13615/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13616/* C(-1) value */ 13617#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12 13618#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4 13619/* C(0) value */ 13620#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16 13621#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4 13622/* C(+1) status */ 13623#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20 13624#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4 13625 13626/***********************************/ 13627/* MC_CMD_PCIE_TUNE 13628 * Get or set PCIE Serdes RXEQ and TX Driver settings 13629 */ 13630#define MC_CMD_PCIE_TUNE 0xf2 13631#undef MC_CMD_0xf2_PRIVILEGE_CTG 13632 13633#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 13634 13635/* MC_CMD_PCIE_TUNE_IN msgrequest */ 13636#define MC_CMD_PCIE_TUNE_IN_LENMIN 4 13637#define MC_CMD_PCIE_TUNE_IN_LENMAX 252 13638#define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 13639/* Requested operation */ 13640#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 13641#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 13642/* enum: Get current RXEQ settings */ 13643#define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 13644/* enum: Override RXEQ settings */ 13645#define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 13646/* enum: Get current TX Driver settings */ 13647#define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 13648/* enum: Override TX Driver settings */ 13649#define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 13650/* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 13651#define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 13652/* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 13653 * caller should call this command repeatedly after starting eye plot, until no 13654 * more data is returned. 13655 */ 13656#define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 13657/* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 13658#define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 13659/* Align the arguments to 32 bits */ 13660#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 13661#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 13662/* Arguments specific to the operation */ 13663#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 13664#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 13665#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 13666#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 13667 13668/* MC_CMD_PCIE_TUNE_OUT msgresponse */ 13669#define MC_CMD_PCIE_TUNE_OUT_LEN 0 13670 13671/* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 13672#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 13673/* Requested operation */ 13674#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13675#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13676/* Align the arguments to 32 bits */ 13677#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13678#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13679 13680/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 13681#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 13682#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 13683#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 13684/* RXEQ Parameter */ 13685#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 13686#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 13687#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 13688#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 13689#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 13690#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 13691/* enum: Attenuation (0-15) */ 13692#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 13693/* enum: CTLE Boost (0-15) */ 13694#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 13695/* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 13696#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 13697/* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 13698#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 13699/* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 13700#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 13701/* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 13702#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 13703/* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 13704#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 13705/* enum: DFE DLev */ 13706#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 13707/* enum: Figure of Merit */ 13708#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 13709/* enum: CTLE EQ Capacitor (HF Gain) */ 13710#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 13711/* enum: CTLE EQ Resistor (DC Gain) */ 13712#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 13713#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 13714#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 13715#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13716#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13717#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13718#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13719#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 13720#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 13721#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 13722#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 13723#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 13724#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 13725#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 13726#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 13727#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 13728#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 13729#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 13730#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 13731#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 13732#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 13733#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 13734#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 13735#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 13736#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13737#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13738 13739/* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 13740#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 13741#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 13742#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 13743/* Requested operation */ 13744#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 13745#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 13746/* Align the arguments to 32 bits */ 13747#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 13748#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 13749/* RXEQ Parameter */ 13750#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 13751#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 13752#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 13753#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 13754#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 13755#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 13756/* Enum values, see field(s): */ 13757/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 13758#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 13759#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 13760/* Enum values, see field(s): */ 13761/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13762#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 13763#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 13764#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 13765#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 13766#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 13767#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13768#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 13769#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 13770 13771/* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 13772#define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 13773 13774/* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 13775#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 13776/* Requested operation */ 13777#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13778#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13779/* Align the arguments to 32 bits */ 13780#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13781#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13782 13783/* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 13784#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 13785#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 13786#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13787/* RXEQ Parameter */ 13788#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13789#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13790#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13791#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13792#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13793#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13794/* enum: TxMargin (PIPE) */ 13795#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 13796/* enum: TxSwing (PIPE) */ 13797#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 13798/* enum: De-emphasis coefficient C(-1) (PIPE) */ 13799#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 13800/* enum: De-emphasis coefficient C(0) (PIPE) */ 13801#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 13802/* enum: De-emphasis coefficient C(+1) (PIPE) */ 13803#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 13804#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13805#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 13806/* Enum values, see field(s): */ 13807/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13808#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 13809#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 13810#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13811#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13812 13813/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 13814#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 13815/* Requested operation */ 13816#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 13817#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 13818/* Align the arguments to 32 bits */ 13819#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 13820#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 13821#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13822#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 13823 13824/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 13825#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 13826 13827/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 13828#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 13829/* Requested operation */ 13830#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 13831#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 13832/* Align the arguments to 32 bits */ 13833#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 13834#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 13835 13836/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 13837#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 13838#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 13839#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 13840#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 13841#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 13842#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 13843#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 13844 13845/* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 13846#define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 13847 13848/* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 13849#define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 13850 13851/***********************************/ 13852/* MC_CMD_LICENSING 13853 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 13854 * - not used for V3 licensing 13855 */ 13856#define MC_CMD_LICENSING 0xf3 13857#undef MC_CMD_0xf3_PRIVILEGE_CTG 13858 13859#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13860 13861/* MC_CMD_LICENSING_IN msgrequest */ 13862#define MC_CMD_LICENSING_IN_LEN 4 13863/* identifies the type of operation requested */ 13864#define MC_CMD_LICENSING_IN_OP_OFST 0 13865#define MC_CMD_LICENSING_IN_OP_LEN 4 13866/* enum: re-read and apply licenses after a license key partition update; note 13867 * that this operation returns a zero-length response 13868 */ 13869#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 13870/* enum: report counts of installed licenses */ 13871#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 13872 13873/* MC_CMD_LICENSING_OUT msgresponse */ 13874#define MC_CMD_LICENSING_OUT_LEN 28 13875/* count of application keys which are valid */ 13876#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 13877#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4 13878/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 13879 * MC_CMD_FC_OP_LICENSE) 13880 */ 13881#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 13882#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4 13883/* count of application keys which are invalid due to being blacklisted */ 13884#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 13885#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4 13886/* count of application keys which are invalid due to being unverifiable */ 13887#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 13888#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4 13889/* count of application keys which are invalid due to being for the wrong node 13890 */ 13891#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 13892#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4 13893/* licensing state (for diagnostics; the exact meaning of the bits in this 13894 * field are private to the firmware) 13895 */ 13896#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 13897#define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4 13898/* licensing subsystem self-test report (for manftest) */ 13899#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 13900#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4 13901/* enum: licensing subsystem self-test failed */ 13902#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 13903/* enum: licensing subsystem self-test passed */ 13904#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 13905 13906/***********************************/ 13907/* MC_CMD_LICENSING_V3 13908 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 13909 * - V3 licensing (Medford) 13910 */ 13911#define MC_CMD_LICENSING_V3 0xd0 13912#undef MC_CMD_0xd0_PRIVILEGE_CTG 13913 13914#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13915 13916/* MC_CMD_LICENSING_V3_IN msgrequest */ 13917#define MC_CMD_LICENSING_V3_IN_LEN 4 13918/* identifies the type of operation requested */ 13919#define MC_CMD_LICENSING_V3_IN_OP_OFST 0 13920#define MC_CMD_LICENSING_V3_IN_OP_LEN 4 13921/* enum: re-read and apply licenses after a license key partition update; note 13922 * that this operation returns a zero-length response 13923 */ 13924#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 13925/* enum: report counts of installed licenses Returns EAGAIN if license 13926 * processing (updating) has been started but not yet completed. 13927 */ 13928#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 13929 13930/* MC_CMD_LICENSING_V3_OUT msgresponse */ 13931#define MC_CMD_LICENSING_V3_OUT_LEN 88 13932/* count of keys which are valid */ 13933#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 13934#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4 13935/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 13936 * MC_CMD_FC_OP_LICENSE) 13937 */ 13938#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 13939#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4 13940/* count of keys which are invalid due to being unverifiable */ 13941#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 13942#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4 13943/* count of keys which are invalid due to being for the wrong node */ 13944#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 13945#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4 13946/* licensing state (for diagnostics; the exact meaning of the bits in this 13947 * field are private to the firmware) 13948 */ 13949#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 13950#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4 13951/* licensing subsystem self-test report (for manftest) */ 13952#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 13953#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4 13954/* enum: licensing subsystem self-test failed */ 13955#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 13956/* enum: licensing subsystem self-test passed */ 13957#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 13958/* bitmask of licensed applications */ 13959#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 13960#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 13961#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 13962#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 13963/* reserved for future use */ 13964#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 13965#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 13966/* bitmask of licensed features */ 13967#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 13968#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 13969#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 13970#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 13971/* reserved for future use */ 13972#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 13973#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 13974 13975/***********************************/ 13976/* MC_CMD_LICENSING_GET_ID_V3 13977 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 13978 * partition - V3 licensing (Medford) 13979 */ 13980#define MC_CMD_LICENSING_GET_ID_V3 0xd1 13981#undef MC_CMD_0xd1_PRIVILEGE_CTG 13982 13983#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13984 13985/* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 13986#define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 13987 13988/* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 13989#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 13990#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 13991#define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 13992/* type of license (eg 3) */ 13993#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 13994#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4 13995/* length of the license ID (in bytes) */ 13996#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 13997#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4 13998/* the unique license ID of the adapter */ 13999#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 14000#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 14001#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 14002#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 14003 14004/***********************************/ 14005/* MC_CMD_MC2MC_PROXY 14006 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 14007 * This will fail on a single-core system. 14008 */ 14009#define MC_CMD_MC2MC_PROXY 0xf4 14010#undef MC_CMD_0xf4_PRIVILEGE_CTG 14011 14012#define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14013 14014/* MC_CMD_MC2MC_PROXY_IN msgrequest */ 14015#define MC_CMD_MC2MC_PROXY_IN_LEN 0 14016 14017/* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 14018#define MC_CMD_MC2MC_PROXY_OUT_LEN 0 14019 14020/***********************************/ 14021/* MC_CMD_GET_LICENSED_APP_STATE 14022 * Query the state of an individual licensed application. (Note that the actual 14023 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 14024 * or a reboot of the MC.) Not used for V3 licensing 14025 */ 14026#define MC_CMD_GET_LICENSED_APP_STATE 0xf5 14027#undef MC_CMD_0xf5_PRIVILEGE_CTG 14028 14029#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14030 14031/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 14032#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 14033/* application ID to query (LICENSED_APP_ID_xxx) */ 14034#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 14035#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4 14036 14037/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 14038#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 14039/* state of this application */ 14040#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 14041#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4 14042/* enum: no (or invalid) license is present for the application */ 14043#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 14044/* enum: a valid license is present for the application */ 14045#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 14046 14047/***********************************/ 14048/* MC_CMD_GET_LICENSED_V3_APP_STATE 14049 * Query the state of an individual licensed application. (Note that the actual 14050 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 14051 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 14052 */ 14053#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 14054#undef MC_CMD_0xd2_PRIVILEGE_CTG 14055 14056#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14057 14058/* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 14059#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 14060/* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 14061 * mask 14062 */ 14063#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 14064#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 14065#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 14066#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 14067 14068/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 14069#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 14070/* state of this application */ 14071#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 14072#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4 14073/* enum: no (or invalid) license is present for the application */ 14074#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 14075/* enum: a valid license is present for the application */ 14076#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 14077 14078/***********************************/ 14079/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 14080 * Query the state of an one or more licensed features. (Note that the actual 14081 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 14082 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 14083 */ 14084#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 14085#undef MC_CMD_0xd3_PRIVILEGE_CTG 14086 14087#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14088 14089/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 14090#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 14091/* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 14092 * more bits set 14093 */ 14094#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 14095#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 14096#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 14097#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 14098 14099/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 14100#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 14101/* states of these features - bit set for licensed, clear for not licensed */ 14102#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 14103#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 14104#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 14105#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 14106 14107/***********************************/ 14108/* MC_CMD_LICENSED_APP_OP 14109 * Perform an action for an individual licensed application - not used for V3 14110 * licensing. 14111 */ 14112#define MC_CMD_LICENSED_APP_OP 0xf6 14113#undef MC_CMD_0xf6_PRIVILEGE_CTG 14114 14115#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14116 14117/* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 14118#define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 14119#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 14120#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 14121/* application ID */ 14122#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 14123#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4 14124/* the type of operation requested */ 14125#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 14126#define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4 14127/* enum: validate application */ 14128#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 14129/* enum: mask application */ 14130#define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 14131/* arguments specific to this particular operation */ 14132#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 14133#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 14134#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 14135#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 14136 14137/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 14138#define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 14139#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 14140#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 14141/* result specific to this particular operation */ 14142#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 14143#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 14144#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 14145#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 14146 14147/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 14148#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 14149/* application ID */ 14150#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 14151#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4 14152/* the type of operation requested */ 14153#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 14154#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4 14155/* validation challenge */ 14156#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 14157#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 14158 14159/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 14160#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 14161/* feature expiry (time_t) */ 14162#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 14163#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4 14164/* validation response */ 14165#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 14166#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 14167 14168/* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 14169#define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 14170/* application ID */ 14171#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 14172#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4 14173/* the type of operation requested */ 14174#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 14175#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4 14176/* flag */ 14177#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 14178#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4 14179 14180/* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 14181#define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 14182 14183/***********************************/ 14184/* MC_CMD_LICENSED_V3_VALIDATE_APP 14185 * Perform validation for an individual licensed application - V3 licensing 14186 * (Medford) 14187 */ 14188#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 14189#undef MC_CMD_0xd4_PRIVILEGE_CTG 14190 14191#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14192 14193/* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 14194#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 14195/* challenge for validation (384 bits) */ 14196#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 14197#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 14198/* application ID expressed as a single bit mask */ 14199#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 14200#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 14201#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 14202#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 14203 14204/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 14205#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 14206/* validation response to challenge in the form of ECDSA signature consisting 14207 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 14208 * SHA-384 digest of a message constructed from the concatenation of the input 14209 * message and the remaining fields of this output message, e.g. challenge[48 14210 * bytes] ... expiry_time[4 bytes] ... 14211 */ 14212#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 14213#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 14214/* application expiry time */ 14215#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 14216#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4 14217/* application expiry units */ 14218#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 14219#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4 14220/* enum: expiry units are accounting units */ 14221#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 14222/* enum: expiry units are calendar days */ 14223#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 14224/* base MAC address of the NIC stored in NVRAM (note that this is a constant 14225 * value for a given NIC regardless which function is calling, effectively this 14226 * is PF0 base MAC address) 14227 */ 14228#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 14229#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 14230/* MAC address of v-adaptor associated with the client. If no such v-adapator 14231 * exists, then the field is filled with 0xFF. 14232 */ 14233#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 14234#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 14235 14236/***********************************/ 14237/* MC_CMD_LICENSED_V3_MASK_FEATURES 14238 * Mask features - V3 licensing (Medford) 14239 */ 14240#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 14241#undef MC_CMD_0xd5_PRIVILEGE_CTG 14242 14243#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14244 14245/* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 14246#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 14247/* mask to be applied to features to be changed */ 14248#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 14249#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 14250#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 14251#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 14252/* whether to turn on or turn off the masked features */ 14253#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 14254#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4 14255/* enum: turn the features off */ 14256#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 14257/* enum: turn the features back on */ 14258#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 14259 14260/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 14261#define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 14262 14263/***********************************/ 14264/* MC_CMD_LICENSING_V3_TEMPORARY 14265 * Perform operations to support installation of a single temporary license in 14266 * the adapter, in addition to those found in the licensing partition. See 14267 * SF-116124-SW for an overview of how this could be used. The license is 14268 * stored in MC persistent data and so will survive a MC reboot, but will be 14269 * erased when the adapter is power cycled 14270 */ 14271#define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 14272#undef MC_CMD_0xd6_PRIVILEGE_CTG 14273 14274#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 14275 14276/* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 14277#define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 14278/* operation code */ 14279#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 14280#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4 14281/* enum: install a new license, overwriting any existing temporary license. 14282 * This is an asynchronous operation owing to the time taken to validate an 14283 * ECDSA license 14284 */ 14285#define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 14286/* enum: clear the license immediately rather than waiting for the next power 14287 * cycle 14288 */ 14289#define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 14290/* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 14291 * operation 14292 */ 14293#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 14294 14295/* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 14296#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 14297#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 14298#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4 14299/* ECDSA license and signature */ 14300#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 14301#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 14302 14303/* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 14304#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 14305#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 14306#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4 14307 14308/* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 14309#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 14310#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 14311#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4 14312 14313/* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 14314#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 14315/* status code */ 14316#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 14317#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4 14318/* enum: finished validating and installing license */ 14319#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 14320/* enum: license validation and installation in progress */ 14321#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 14322/* enum: licensing error. More specific error messages are not provided to 14323 * avoid exposing details of the licensing system to the client 14324 */ 14325#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 14326/* bitmask of licensed features */ 14327#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 14328#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 14329#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 14330#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 14331 14332/***********************************/ 14333/* MC_CMD_SET_PORT_SNIFF_CONFIG 14334 * Configure RX port sniffing for the physical port associated with the calling 14335 * function. Only a privileged function may change the port sniffing 14336 * configuration. A copy of all traffic delivered to the host (non-promiscuous 14337 * mode) or all traffic arriving at the port (promiscuous mode) may be 14338 * delivered to a specific queue, or a set of queues with RSS. 14339 */ 14340#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 14341#undef MC_CMD_0xf7_PRIVILEGE_CTG 14342 14343#define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14344 14345/* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 14346#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 14347/* configuration flags */ 14348#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 14349#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 14350#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 14351#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 14352#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 14353#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 14354/* receive queue handle (for RSS mode, this is the base queue) */ 14355#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 14356#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 14357/* receive mode */ 14358#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 14359#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 14360/* enum: receive to just the specified queue */ 14361#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 14362/* enum: receive to multiple queues using RSS context */ 14363#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 14364/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 14365 * that these handles should be considered opaque to the host, although a value 14366 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 14367 */ 14368#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 14369#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 14370 14371/* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 14372#define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 14373 14374/***********************************/ 14375/* MC_CMD_GET_PORT_SNIFF_CONFIG 14376 * Obtain the current RX port sniffing configuration for the physical port 14377 * associated with the calling function. Only a privileged function may read 14378 * the configuration. 14379 */ 14380#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 14381#undef MC_CMD_0xf8_PRIVILEGE_CTG 14382 14383#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14384 14385/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 14386#define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 14387 14388/* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 14389#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 14390/* configuration flags */ 14391#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 14392#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 14393#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 14394#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 14395#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 14396#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 14397/* receiving queue handle (for RSS mode, this is the base queue) */ 14398#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 14399#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 14400/* receive mode */ 14401#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 14402#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 14403/* enum: receiving to just the specified queue */ 14404#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 14405/* enum: receiving to multiple queues using RSS context */ 14406#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 14407/* RSS context (for RX_MODE_RSS) */ 14408#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 14409#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 14410 14411/***********************************/ 14412/* MC_CMD_SET_PARSER_DISP_CONFIG 14413 * Change configuration related to the parser-dispatcher subsystem. 14414 */ 14415#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 14416#undef MC_CMD_0xf9_PRIVILEGE_CTG 14417 14418#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14419 14420/* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 14421#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 14422#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 14423#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 14424/* the type of configuration setting to change */ 14425#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 14426#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 14427/* enum: Per-TXQ enable for multicast UDP destination lookup for possible 14428 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 14429 */ 14430#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 14431/* enum: Per-v-adaptor enable for suppression of self-transmissions on the 14432 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 14433 * boolean.) 14434 */ 14435#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 14436/* handle for the entity to update: queue handle, EVB port ID, etc. depending 14437 * on the type of configuration setting being changed 14438 */ 14439#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 14440#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 14441/* new value: the details depend on the type of configuration setting being 14442 * changed 14443 */ 14444#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 14445#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 14446#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 14447#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 14448 14449/* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 14450#define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 14451 14452/***********************************/ 14453/* MC_CMD_GET_PARSER_DISP_CONFIG 14454 * Read configuration related to the parser-dispatcher subsystem. 14455 */ 14456#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 14457#undef MC_CMD_0xfa_PRIVILEGE_CTG 14458 14459#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14460 14461/* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 14462#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 14463/* the type of configuration setting to read */ 14464#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 14465#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 14466/* Enum values, see field(s): */ 14467/* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 14468/* handle for the entity to query: queue handle, EVB port ID, etc. depending on 14469 * the type of configuration setting being read 14470 */ 14471#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 14472#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 14473 14474/* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 14475#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 14476#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 14477#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 14478/* current value: the details depend on the type of configuration setting being 14479 * read 14480 */ 14481#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 14482#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 14483#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 14484#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 14485 14486/***********************************/ 14487/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 14488 * Configure TX port sniffing for the physical port associated with the calling 14489 * function. Only a privileged function may change the port sniffing 14490 * configuration. A copy of all traffic transmitted through the port may be 14491 * delivered to a specific queue, or a set of queues with RSS. Note that these 14492 * packets are delivered with transmit timestamps in the packet prefix, not 14493 * receive timestamps, so it is likely that the queue(s) will need to be 14494 * dedicated as TX sniff receivers. 14495 */ 14496#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 14497#undef MC_CMD_0xfb_PRIVILEGE_CTG 14498 14499#define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14500 14501/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 14502#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 14503/* configuration flags */ 14504#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 14505#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 14506#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 14507#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 14508/* receive queue handle (for RSS mode, this is the base queue) */ 14509#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 14510#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 14511/* receive mode */ 14512#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 14513#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 14514/* enum: receive to just the specified queue */ 14515#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 14516/* enum: receive to multiple queues using RSS context */ 14517#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 14518/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 14519 * that these handles should be considered opaque to the host, although a value 14520 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 14521 */ 14522#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 14523#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 14524 14525/* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14526#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 14527 14528/***********************************/ 14529/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 14530 * Obtain the current TX port sniffing configuration for the physical port 14531 * associated with the calling function. Only a privileged function may read 14532 * the configuration. 14533 */ 14534#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 14535#undef MC_CMD_0xfc_PRIVILEGE_CTG 14536 14537#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14538 14539/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 14540#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 14541 14542/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14543#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 14544/* configuration flags */ 14545#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 14546#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 14547#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 14548#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 14549/* receiving queue handle (for RSS mode, this is the base queue) */ 14550#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 14551#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 14552/* receive mode */ 14553#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 14554#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 14555/* enum: receiving to just the specified queue */ 14556#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 14557/* enum: receiving to multiple queues using RSS context */ 14558#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 14559/* RSS context (for RX_MODE_RSS) */ 14560#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 14561#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 14562 14563/***********************************/ 14564/* MC_CMD_RMON_STATS_RX_ERRORS 14565 * Per queue rx error stats. 14566 */ 14567#define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 14568#undef MC_CMD_0xfe_PRIVILEGE_CTG 14569 14570#define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14571 14572/* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 14573#define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 14574/* The rx queue to get stats for. */ 14575#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 14576#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4 14577#define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 14578#define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4 14579#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 14580#define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 14581 14582/* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 14583#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 14584#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 14585#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4 14586#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 14587#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4 14588#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 14589#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4 14590#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 14591#define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4 14592 14593/***********************************/ 14594/* MC_CMD_GET_PCIE_RESOURCE_INFO 14595 * Find out about available PCIE resources 14596 */ 14597#define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 14598#undef MC_CMD_0xfd_PRIVILEGE_CTG 14599 14600#define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14601 14602/* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 14603#define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 14604 14605/* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 14606#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 14607/* The maximum number of PFs the device can expose */ 14608#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 14609#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4 14610/* The maximum number of VFs the device can expose in total */ 14611#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 14612#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4 14613/* The maximum number of MSI-X vectors the device can provide in total */ 14614#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 14615#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4 14616/* the number of MSI-X vectors the device will allocate by default to each PF 14617 */ 14618#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 14619#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4 14620/* the number of MSI-X vectors the device will allocate by default to each VF 14621 */ 14622#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 14623#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4 14624/* the maximum number of MSI-X vectors the device can allocate to any one PF */ 14625#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 14626#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4 14627/* the maximum number of MSI-X vectors the device can allocate to any one VF */ 14628#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 14629#define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4 14630 14631/***********************************/ 14632/* MC_CMD_GET_PORT_MODES 14633 * Find out about available port modes 14634 */ 14635#define MC_CMD_GET_PORT_MODES 0xff 14636#undef MC_CMD_0xff_PRIVILEGE_CTG 14637 14638#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14639 14640/* MC_CMD_GET_PORT_MODES_IN msgrequest */ 14641#define MC_CMD_GET_PORT_MODES_IN_LEN 0 14642 14643/* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 14644#define MC_CMD_GET_PORT_MODES_OUT_LEN 12 14645/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 14646#define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 14647#define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4 14648/* Default (canonical) board mode */ 14649#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 14650#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4 14651/* Current board mode */ 14652#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 14653#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4 14654 14655/***********************************/ 14656/* MC_CMD_READ_ATB 14657 * Sample voltages on the ATB 14658 */ 14659#define MC_CMD_READ_ATB 0x100 14660#undef MC_CMD_0x100_PRIVILEGE_CTG 14661 14662#define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE 14663 14664/* MC_CMD_READ_ATB_IN msgrequest */ 14665#define MC_CMD_READ_ATB_IN_LEN 16 14666#define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 14667#define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4 14668#define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 14669#define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 14670#define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 14671#define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 14672#define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4 14673#define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 14674#define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4 14675#define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 14676#define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4 14677 14678/* MC_CMD_READ_ATB_OUT msgresponse */ 14679#define MC_CMD_READ_ATB_OUT_LEN 4 14680#define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 14681#define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4 14682 14683/***********************************/ 14684/* MC_CMD_GET_WORKAROUNDS 14685 * Read the list of all implemented and all currently enabled workarounds. The 14686 * enums here must correspond with those in MC_CMD_WORKAROUND. 14687 */ 14688#define MC_CMD_GET_WORKAROUNDS 0x59 14689#undef MC_CMD_0x59_PRIVILEGE_CTG 14690 14691#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14692 14693/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 14694#define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 14695/* Each workaround is represented by a single bit according to the enums below. 14696 */ 14697#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 14698#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4 14699#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 14700#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4 14701/* enum: Bug 17230 work around. */ 14702#define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 14703/* enum: Bug 35388 work around (unsafe EVQ writes). */ 14704#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 14705/* enum: Bug35017 workaround (A64 tables must be identity map) */ 14706#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 14707/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 14708#define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 14709/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 14710 * - before adding code that queries this workaround, remember that there's 14711 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 14712 * and will hence (incorrectly) report that the bug doesn't exist. 14713 */ 14714#define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 14715/* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 14716#define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 14717/* enum: Bug 61265 work around (broken EVQ TMR writes). */ 14718#define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 14719 14720/***********************************/ 14721/* MC_CMD_PRIVILEGE_MASK 14722 * Read/set privileges of an arbitrary PCIe function 14723 */ 14724#define MC_CMD_PRIVILEGE_MASK 0x5a 14725#undef MC_CMD_0x5a_PRIVILEGE_CTG 14726 14727#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14728 14729/* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 14730#define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 14731/* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 14732 * 1,3 = 0x00030001 14733 */ 14734#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 14735#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4 14736#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 14737#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 14738#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 14739#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 14740#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 14741/* New privilege mask to be set. The mask will only be changed if the MSB is 14742 * set to 1. 14743 */ 14744#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 14745#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4 14746#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 14747#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 14748#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 14749#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 14750#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 14751/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 14752#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 14753#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 14754#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 14755#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 14756#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 14757#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 14758/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 14759 * adress. 14760 */ 14761#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 14762/* enum: Privilege that allows a Function to change the MAC address configured 14763 * in its associated vAdapter/vPort. 14764 */ 14765#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 14766/* enum: Privilege that allows a Function to install filters that specify VLANs 14767 * that are not in the permit list for the associated vPort. This privilege is 14768 * primarily to support ESX where vPorts are created that restrict traffic to 14769 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 14770 */ 14771#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 14772/* enum: Privilege for insecure commands. Commands that belong to this group 14773 * are not permitted on secure adapters regardless of the privilege mask. 14774 */ 14775#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000 14776/* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for 14777 * administrator-level operations that are not allowed from the local host once 14778 * an adapter has Bound to a remote ServerLock Controller (see doxbox 14779 * SF-117064-DG for background). 14780 */ 14781#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000 14782/* enum: Set this bit to indicate that a new privilege mask is to be set, 14783 * otherwise the command will only read the existing mask. 14784 */ 14785#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 14786 14787/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 14788#define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 14789/* For an admin function, always all the privileges are reported. */ 14790#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 14791#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4 14792 14793/***********************************/ 14794/* MC_CMD_LINK_STATE_MODE 14795 * Read/set link state mode of a VF 14796 */ 14797#define MC_CMD_LINK_STATE_MODE 0x5c 14798#undef MC_CMD_0x5c_PRIVILEGE_CTG 14799 14800#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14801 14802/* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 14803#define MC_CMD_LINK_STATE_MODE_IN_LEN 8 14804/* The target function to have its link state mode read or set, must be a VF 14805 * e.g. VF 1,3 = 0x00030001 14806 */ 14807#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 14808#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4 14809#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 14810#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 14811#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 14812#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 14813/* New link state mode to be set */ 14814#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 14815#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4 14816#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 14817#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 14818#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 14819/* enum: Use this value to just read the existing setting without modifying it. 14820 */ 14821#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 14822 14823/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 14824#define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 14825#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 14826#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4 14827 14828/***********************************/ 14829/* MC_CMD_GET_SNAPSHOT_LENGTH 14830 * Obtain the current range of allowable values for the SNAPSHOT_LENGTH 14831 * parameter to MC_CMD_INIT_RXQ. 14832 */ 14833#define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 14834#undef MC_CMD_0x101_PRIVILEGE_CTG 14835 14836#define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14837 14838/* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 14839#define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 14840 14841/* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 14842#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 14843/* Minimum acceptable snapshot length. */ 14844#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 14845#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4 14846/* Maximum acceptable snapshot length. */ 14847#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 14848#define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4 14849 14850/***********************************/ 14851/* MC_CMD_FUSE_DIAGS 14852 * Additional fuse diagnostics 14853 */ 14854#define MC_CMD_FUSE_DIAGS 0x102 14855#undef MC_CMD_0x102_PRIVILEGE_CTG 14856 14857#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE 14858 14859/* MC_CMD_FUSE_DIAGS_IN msgrequest */ 14860#define MC_CMD_FUSE_DIAGS_IN_LEN 0 14861 14862/* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 14863#define MC_CMD_FUSE_DIAGS_OUT_LEN 48 14864/* Total number of mismatched bits between pairs in area 0 */ 14865#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 14866#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4 14867/* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 14868#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 14869#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4 14870/* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 14871#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 14872#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4 14873/* Checksum of data after logical OR of pairs in area 0 */ 14874#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 14875#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4 14876/* Total number of mismatched bits between pairs in area 1 */ 14877#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 14878#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4 14879/* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 14880#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 14881#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4 14882/* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 14883#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 14884#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4 14885/* Checksum of data after logical OR of pairs in area 1 */ 14886#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 14887#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4 14888/* Total number of mismatched bits between pairs in area 2 */ 14889#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 14890#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4 14891/* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 14892#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 14893#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4 14894/* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 14895#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 14896#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4 14897/* Checksum of data after logical OR of pairs in area 2 */ 14898#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 14899#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4 14900 14901/***********************************/ 14902/* MC_CMD_PRIVILEGE_MODIFY 14903 * Modify the privileges of a set of PCIe functions. Note that this operation 14904 * only effects non-admin functions unless the admin privilege itself is 14905 * included in one of the masks provided. 14906 */ 14907#define MC_CMD_PRIVILEGE_MODIFY 0x60 14908#undef MC_CMD_0x60_PRIVILEGE_CTG 14909 14910#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14911 14912/* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 14913#define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 14914/* The groups of functions to have their privilege masks modified. */ 14915#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 14916#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4 14917#define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 14918#define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 14919#define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 14920#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 14921#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 14922#define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 14923/* For VFS_OF_PF specify the PF, for ONE specify the target function */ 14924#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 14925#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4 14926#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 14927#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 14928#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 14929#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 14930/* Privileges to be added to the target functions. For privilege definitions 14931 * refer to the command MC_CMD_PRIVILEGE_MASK 14932 */ 14933#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 14934#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4 14935/* Privileges to be removed from the target functions. For privilege 14936 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 14937 */ 14938#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 14939#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4 14940 14941/* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 14942#define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 14943 14944/***********************************/ 14945/* MC_CMD_XPM_READ_BYTES 14946 * Read XPM memory 14947 */ 14948#define MC_CMD_XPM_READ_BYTES 0x103 14949#undef MC_CMD_0x103_PRIVILEGE_CTG 14950 14951#define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14952 14953/* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 14954#define MC_CMD_XPM_READ_BYTES_IN_LEN 8 14955/* Start address (byte) */ 14956#define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 14957#define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4 14958/* Count (bytes) */ 14959#define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 14960#define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4 14961 14962/* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 14963#define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 14964#define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 14965#define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 14966/* Data */ 14967#define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 14968#define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 14969#define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 14970#define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 14971 14972/***********************************/ 14973/* MC_CMD_XPM_WRITE_BYTES 14974 * Write XPM memory 14975 */ 14976#define MC_CMD_XPM_WRITE_BYTES 0x104 14977#undef MC_CMD_0x104_PRIVILEGE_CTG 14978 14979#define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE 14980 14981/* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 14982#define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 14983#define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 14984#define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 14985/* Start address (byte) */ 14986#define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 14987#define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4 14988/* Count (bytes) */ 14989#define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 14990#define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4 14991/* Data */ 14992#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 14993#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 14994#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 14995#define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 14996 14997/* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 14998#define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 14999 15000/***********************************/ 15001/* MC_CMD_XPM_READ_SECTOR 15002 * Read XPM sector 15003 */ 15004#define MC_CMD_XPM_READ_SECTOR 0x105 15005#undef MC_CMD_0x105_PRIVILEGE_CTG 15006 15007#define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15008 15009/* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 15010#define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 15011/* Sector index */ 15012#define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 15013#define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4 15014/* Sector size */ 15015#define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 15016#define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4 15017 15018/* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 15019#define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 15020#define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 15021#define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 15022/* Sector type */ 15023#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 15024#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4 15025#define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 15026#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 15027#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 15028#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */ 15029#define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 15030/* Sector data */ 15031#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 15032#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 15033#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 15034#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 15035 15036/***********************************/ 15037/* MC_CMD_XPM_WRITE_SECTOR 15038 * Write XPM sector 15039 */ 15040#define MC_CMD_XPM_WRITE_SECTOR 0x106 15041#undef MC_CMD_0x106_PRIVILEGE_CTG 15042 15043#define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15044 15045/* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 15046#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 15047#define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 15048#define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 15049/* If writing fails due to an uncorrectable error, try up to RETRIES following 15050 * sectors (or until no more space available). If 0, only one write attempt is 15051 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 15052 * mechanism. 15053 */ 15054#define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 15055#define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 15056#define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 15057#define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 15058/* Sector type */ 15059#define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 15060#define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4 15061/* Enum values, see field(s): */ 15062/* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 15063/* Sector size */ 15064#define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 15065#define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4 15066/* Sector data */ 15067#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 15068#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 15069#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 15070#define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 15071 15072/* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 15073#define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 15074/* New sector index */ 15075#define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 15076#define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4 15077 15078/***********************************/ 15079/* MC_CMD_XPM_INVALIDATE_SECTOR 15080 * Invalidate XPM sector 15081 */ 15082#define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 15083#undef MC_CMD_0x107_PRIVILEGE_CTG 15084 15085#define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15086 15087/* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 15088#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 15089/* Sector index */ 15090#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 15091#define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4 15092 15093/* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 15094#define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 15095 15096/***********************************/ 15097/* MC_CMD_XPM_BLANK_CHECK 15098 * Blank-check XPM memory and report bad locations 15099 */ 15100#define MC_CMD_XPM_BLANK_CHECK 0x108 15101#undef MC_CMD_0x108_PRIVILEGE_CTG 15102 15103#define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15104 15105/* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 15106#define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 15107/* Start address (byte) */ 15108#define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 15109#define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4 15110/* Count (bytes) */ 15111#define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 15112#define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4 15113 15114/* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 15115#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 15116#define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 15117#define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 15118/* Total number of bad (non-blank) locations */ 15119#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 15120#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4 15121/* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 15122 * into MCDI response) 15123 */ 15124#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 15125#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 15126#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 15127#define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 15128 15129/***********************************/ 15130/* MC_CMD_XPM_REPAIR 15131 * Blank-check and repair XPM memory 15132 */ 15133#define MC_CMD_XPM_REPAIR 0x109 15134#undef MC_CMD_0x109_PRIVILEGE_CTG 15135 15136#define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15137 15138/* MC_CMD_XPM_REPAIR_IN msgrequest */ 15139#define MC_CMD_XPM_REPAIR_IN_LEN 8 15140/* Start address (byte) */ 15141#define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 15142#define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4 15143/* Count (bytes) */ 15144#define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 15145#define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4 15146 15147/* MC_CMD_XPM_REPAIR_OUT msgresponse */ 15148#define MC_CMD_XPM_REPAIR_OUT_LEN 0 15149 15150/***********************************/ 15151/* MC_CMD_XPM_DECODER_TEST 15152 * Test XPM memory address decoders for gross manufacturing defects. Can only 15153 * be performed on an unprogrammed part. 15154 */ 15155#define MC_CMD_XPM_DECODER_TEST 0x10a 15156#undef MC_CMD_0x10a_PRIVILEGE_CTG 15157 15158#define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15159 15160/* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 15161#define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 15162 15163/* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 15164#define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 15165 15166/***********************************/ 15167/* MC_CMD_XPM_WRITE_TEST 15168 * XPM memory write test. Test XPM write logic for gross manufacturing defects 15169 * by writing to a dedicated test row. There are 16 locations in the test row 15170 * and the test can only be performed on locations that have not been 15171 * previously used (i.e. can be run at most 16 times). The test will pick the 15172 * first available location to use, or fail with ENOSPC if none left. 15173 */ 15174#define MC_CMD_XPM_WRITE_TEST 0x10b 15175#undef MC_CMD_0x10b_PRIVILEGE_CTG 15176 15177#define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15178 15179/* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 15180#define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 15181 15182/* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 15183#define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 15184 15185/***********************************/ 15186/* MC_CMD_EXEC_SIGNED 15187 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 15188 * and if correct begin execution from the start of IMEM. The caller supplies a 15189 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 15190 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 15191 * to match flash booting. The command will respond with EINVAL if the CMAC 15192 * does match, otherwise it will respond with success before it jumps to IMEM. 15193 */ 15194#define MC_CMD_EXEC_SIGNED 0x10c 15195#undef MC_CMD_0x10c_PRIVILEGE_CTG 15196 15197#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15198 15199/* MC_CMD_EXEC_SIGNED_IN msgrequest */ 15200#define MC_CMD_EXEC_SIGNED_IN_LEN 28 15201/* the length of code to include in the CMAC */ 15202#define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 15203#define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4 15204/* the length of date to include in the CMAC */ 15205#define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 15206#define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4 15207/* the XPM sector containing the key to use */ 15208#define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 15209#define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4 15210/* the expected CMAC value */ 15211#define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 15212#define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 15213 15214/* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 15215#define MC_CMD_EXEC_SIGNED_OUT_LEN 0 15216 15217/***********************************/ 15218/* MC_CMD_PREPARE_SIGNED 15219 * Prepare to upload a signed image. This will scrub the specified length of 15220 * the data region, which must be at least as large as the DATALEN supplied to 15221 * MC_CMD_EXEC_SIGNED. 15222 */ 15223#define MC_CMD_PREPARE_SIGNED 0x10d 15224#undef MC_CMD_0x10d_PRIVILEGE_CTG 15225 15226#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15227 15228/* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 15229#define MC_CMD_PREPARE_SIGNED_IN_LEN 4 15230/* the length of data area to clear */ 15231#define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 15232#define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4 15233 15234/* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 15235#define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 15236 15237/***********************************/ 15238/* MC_CMD_SET_SECURITY_RULE 15239 * Set blacklist and/or whitelist action for a particular match criteria. 15240 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15241 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15242 * been used in any released code and may change during development. This note 15243 * will be removed once it is regarded as stable. 15244 */ 15245#define MC_CMD_SET_SECURITY_RULE 0x10f 15246#undef MC_CMD_0x10f_PRIVILEGE_CTG 15247 15248#define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15249 15250/* MC_CMD_SET_SECURITY_RULE_IN msgrequest */ 15251#define MC_CMD_SET_SECURITY_RULE_IN_LEN 92 15252/* fields to include in match criteria */ 15253#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0 15254#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_LEN 4 15255#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0 15256#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1 15257#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1 15258#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1 15259#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2 15260#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1 15261#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3 15262#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1 15263#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4 15264#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1 15265#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5 15266#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1 15267#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6 15268#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1 15269#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7 15270#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1 15271#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8 15272#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1 15273#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9 15274#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1 15275#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10 15276#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1 15277#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11 15278#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1 15279#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12 15280#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1 15281#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13 15282#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1 15283#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14 15284#define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1 15285/* remote MAC address to match (as bytes in network order) */ 15286#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4 15287#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6 15288/* remote port to match (as bytes in network order) */ 15289#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10 15290#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2 15291/* local MAC address to match (as bytes in network order) */ 15292#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12 15293#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6 15294/* local port to match (as bytes in network order) */ 15295#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18 15296#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2 15297/* Ethernet type to match (as bytes in network order) */ 15298#define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20 15299#define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2 15300/* Inner VLAN tag to match (as bytes in network order) */ 15301#define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22 15302#define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2 15303/* Outer VLAN tag to match (as bytes in network order) */ 15304#define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24 15305#define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2 15306/* IP protocol to match (in low byte; set high byte to 0) */ 15307#define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26 15308#define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2 15309/* Physical port to match (as little-endian 32-bit value) */ 15310#define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28 15311#define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_LEN 4 15312/* Reserved; set to 0 */ 15313#define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32 15314#define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_LEN 4 15315/* remote IP address to match (as bytes in network order; set last 12 bytes to 15316 * 0 for IPv4 address) 15317 */ 15318#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36 15319#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16 15320/* local IP address to match (as bytes in network order; set last 12 bytes to 0 15321 * for IPv4 address) 15322 */ 15323#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52 15324#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16 15325/* remote subnet ID to match (as little-endian 32-bit value); note that remote 15326 * subnets are matched by mapping the remote IP address to a "subnet ID" via a 15327 * data structure which must already have been configured using 15328 * MC_CMD_SUBNET_MAP_SET_NODE appropriately 15329 */ 15330#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68 15331#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_LEN 4 15332/* remote portrange ID to match (as little-endian 32-bit value); note that 15333 * remote port ranges are matched by mapping the remote port to a "portrange 15334 * ID" via a data structure which must already have been configured using 15335 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 15336 */ 15337#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72 15338#define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_LEN 4 15339/* local portrange ID to match (as little-endian 32-bit value); note that local 15340 * port ranges are matched by mapping the local port to a "portrange ID" via a 15341 * data structure which must already have been configured using 15342 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 15343 */ 15344#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76 15345#define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_LEN 4 15346/* set the action for transmitted packets matching this rule */ 15347#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80 15348#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_LEN 4 15349/* enum: make no decision */ 15350#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0 15351/* enum: decide to accept the packet */ 15352#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1 15353/* enum: decide to drop the packet */ 15354#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2 15355/* enum: inform the TSA controller about some sample of packets matching this 15356 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with 15357 * either the WHITELIST or BLACKLIST action 15358 */ 15359#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE 0x4 15360/* enum: do not change the current TX action */ 15361#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff 15362/* set the action for received packets matching this rule */ 15363#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84 15364#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_LEN 4 15365/* enum: make no decision */ 15366#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0 15367/* enum: decide to accept the packet */ 15368#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1 15369/* enum: decide to drop the packet */ 15370#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2 15371/* enum: inform the TSA controller about some sample of packets matching this 15372 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with 15373 * either the WHITELIST or BLACKLIST action 15374 */ 15375#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE 0x4 15376/* enum: do not change the current RX action */ 15377#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff 15378/* counter ID to associate with this rule; IDs are allocated using 15379 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC 15380 */ 15381#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88 15382#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_LEN 4 15383/* enum: special value for the null counter ID */ 15384#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0 15385/* enum: special value to tell the MC to allocate an available counter */ 15386#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO 0xeeeeeeee 15387/* enum: special value to request use of hardware counter (Medford2 only) */ 15388#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW 0xffffffff 15389 15390/* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */ 15391#define MC_CMD_SET_SECURITY_RULE_OUT_LEN 32 15392/* new reference count for uses of counter ID */ 15393#define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0 15394#define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_LEN 4 15395/* constructed match bits for this rule (as a tracing aid only) */ 15396#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4 15397#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12 15398/* constructed discriminator bits for this rule (as a tracing aid only) */ 15399#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16 15400#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_LEN 4 15401/* base location for probes for this rule (as a tracing aid only) */ 15402#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20 15403#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_LEN 4 15404/* step for probes for this rule (as a tracing aid only) */ 15405#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24 15406#define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_LEN 4 15407/* ID for reading back the counter */ 15408#define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_OFST 28 15409#define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_LEN 4 15410 15411/***********************************/ 15412/* MC_CMD_RESET_SECURITY_RULES 15413 * Reset all blacklist and whitelist actions for a particular physical port, or 15414 * all ports. (Medford-only; for use by SolarSecure apps, not directly by 15415 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional. 15416 * It has not yet been used in any released code and may change during 15417 * development. This note will be removed once it is regarded as stable. 15418 */ 15419#define MC_CMD_RESET_SECURITY_RULES 0x110 15420#undef MC_CMD_0x110_PRIVILEGE_CTG 15421 15422#define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15423 15424/* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */ 15425#define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4 15426/* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */ 15427#define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0 15428#define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_LEN 4 15429/* enum: special value to reset all physical ports */ 15430#define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff 15431 15432/* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */ 15433#define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0 15434 15435/***********************************/ 15436/* MC_CMD_GET_SECURITY_RULESET_VERSION 15437 * Return a large hash value representing a "version" of the complete set of 15438 * currently active blacklist / whitelist rules and associated data structures. 15439 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15440 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15441 * been used in any released code and may change during development. This note 15442 * will be removed once it is regarded as stable. 15443 */ 15444#define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111 15445#undef MC_CMD_0x111_PRIVILEGE_CTG 15446 15447#define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15448 15449/* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */ 15450#define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0 15451 15452/* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */ 15453#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1 15454#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252 15455#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num)) 15456/* Opaque hash value; length may vary depending on the hash scheme used */ 15457#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0 15458#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1 15459#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1 15460#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252 15461 15462/***********************************/ 15463/* MC_CMD_SECURITY_RULE_COUNTER_ALLOC 15464 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 15465 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 15466 * NOTE - this message definition is provisional. It has not yet been used in 15467 * any released code and may change during development. This note will be 15468 * removed once it is regarded as stable. 15469 */ 15470#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112 15471#undef MC_CMD_0x112_PRIVILEGE_CTG 15472 15473#define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15474 15475/* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */ 15476#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4 15477/* the number of new counter IDs to request */ 15478#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0 15479#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_LEN 4 15480 15481/* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */ 15482#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4 15483#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252 15484#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num)) 15485/* the number of new counter IDs allocated (may be less than the number 15486 * requested if resources are unavailable) 15487 */ 15488#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0 15489#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_LEN 4 15490/* new counter ID(s) */ 15491#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4 15492#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4 15493#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0 15494#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62 15495 15496/***********************************/ 15497/* MC_CMD_SECURITY_RULE_COUNTER_FREE 15498 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 15499 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 15500 * NOTE - this message definition is provisional. It has not yet been used in 15501 * any released code and may change during development. This note will be 15502 * removed once it is regarded as stable. 15503 */ 15504#define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113 15505#undef MC_CMD_0x113_PRIVILEGE_CTG 15506 15507#define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15508 15509/* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */ 15510#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4 15511#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252 15512#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num)) 15513/* the number of counter IDs to free */ 15514#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0 15515#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_LEN 4 15516/* the counter ID(s) to free */ 15517#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4 15518#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4 15519#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0 15520#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62 15521 15522/* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */ 15523#define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0 15524 15525/***********************************/ 15526/* MC_CMD_SUBNET_MAP_SET_NODE 15527 * Atomically update a trie node in the map of subnets to subnet IDs. The 15528 * constants in the descriptions of the fields of this message may be retrieved 15529 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford- 15530 * only; for use by SolarSecure apps, not directly by drivers. See 15531 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15532 * been used in any released code and may change during development. This note 15533 * will be removed once it is regarded as stable. 15534 */ 15535#define MC_CMD_SUBNET_MAP_SET_NODE 0x114 15536#undef MC_CMD_0x114_PRIVILEGE_CTG 15537 15538#define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15539 15540/* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */ 15541#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6 15542#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252 15543#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num)) 15544/* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */ 15545#define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0 15546#define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_LEN 4 15547/* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer 15548 * to the next node, expressed as an offset in the trie memory (i.e. node ID 15549 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range 15550 * SUBNET_ID_MIN .. SUBNET_ID_MAX 15551 */ 15552#define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4 15553#define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2 15554#define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1 15555#define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124 15556 15557/* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */ 15558#define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0 15559 15560/* PORTRANGE_TREE_ENTRY structuredef */ 15561#define PORTRANGE_TREE_ENTRY_LEN 4 15562/* key for branch nodes (<= key takes left branch, > key takes right branch), 15563 * or magic value for leaf nodes 15564 */ 15565#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0 15566#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2 15567#define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */ 15568#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0 15569#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16 15570/* final portrange ID for leaf nodes (don't care for branch nodes) */ 15571#define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2 15572#define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2 15573#define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16 15574#define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16 15575 15576/***********************************/ 15577/* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 15578 * Atomically update the entire tree mapping remote port ranges to portrange 15579 * IDs. The constants in the descriptions of the fields of this message may be 15580 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 15581 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15582 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15583 * been used in any released code and may change during development. This note 15584 * will be removed once it is regarded as stable. 15585 */ 15586#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115 15587#undef MC_CMD_0x115_PRIVILEGE_CTG 15588 15589#define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15590 15591/* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 15592#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 15593#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 15594#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 15595/* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 15596 * PORTRANGE_TREE_ENTRY 15597 */ 15598#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 15599#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 15600#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 15601#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 15602 15603/* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 15604#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 15605 15606/***********************************/ 15607/* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 15608 * Atomically update the entire tree mapping remote port ranges to portrange 15609 * IDs. The constants in the descriptions of the fields of this message may be 15610 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 15611 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15612 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15613 * been used in any released code and may change during development. This note 15614 * will be removed once it is regarded as stable. 15615 */ 15616#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116 15617#undef MC_CMD_0x116_PRIVILEGE_CTG 15618 15619#define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15620 15621/* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 15622#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 15623#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 15624#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 15625/* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 15626 * PORTRANGE_TREE_ENTRY 15627 */ 15628#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 15629#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 15630#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 15631#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 15632 15633/* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 15634#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 15635 15636/* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 15637#define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 15638/* UDP port (the standard ports are named below but any port may be used) */ 15639#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 15640#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 15641/* enum: the IANA allocated UDP port for VXLAN */ 15642#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 15643/* enum: the IANA allocated UDP port for Geneve */ 15644#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 15645#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 15646#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 15647/* tunnel encapsulation protocol (only those named below are supported) */ 15648#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 15649#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 15650/* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 15651#define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 15652/* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 15653#define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 15654#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 15655#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 15656 15657/***********************************/ 15658/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 15659 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 15660 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 15661 * encapsulation PDUs and filter them using the tunnel encapsulation filter 15662 * chain rather than the standard filter chain. Note that this command can 15663 * cause all functions to see a reset. (Available on Medford only.) 15664 */ 15665#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 15666#undef MC_CMD_0x117_PRIVILEGE_CTG 15667 15668#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15669 15670/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 15671#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 15672#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 15673#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 15674/* Flags */ 15675#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 15676#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 15677#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 15678#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 15679/* The number of entries in the ENTRIES array */ 15680#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 15681#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 15682/* Entries defining the UDP port to protocol mapping, each laid out as a 15683 * TUNNEL_ENCAP_UDP_PORT_ENTRY 15684 */ 15685#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 15686#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 15687#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 15688#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 15689 15690/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 15691#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 15692/* Flags */ 15693#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 15694#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 15695#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 15696#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 15697 15698/***********************************/ 15699/* MC_CMD_RX_BALANCING 15700 * Configure a port upconverter to distribute the packets on both RX engines. 15701 * Packets are distributed based on a table with the destination vFIFO. The 15702 * index of the table is a hash of source and destination of IPV4 and VLAN 15703 * priority. 15704 */ 15705#define MC_CMD_RX_BALANCING 0x118 15706#undef MC_CMD_0x118_PRIVILEGE_CTG 15707 15708#define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15709 15710/* MC_CMD_RX_BALANCING_IN msgrequest */ 15711#define MC_CMD_RX_BALANCING_IN_LEN 16 15712/* The RX port whose upconverter table will be modified */ 15713#define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 15714#define MC_CMD_RX_BALANCING_IN_PORT_LEN 4 15715/* The VLAN priority associated to the table index and vFIFO */ 15716#define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 15717#define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4 15718/* The resulting bit of SRC^DST for indexing the table */ 15719#define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 15720#define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4 15721/* The RX engine to which the vFIFO in the table entry will point to */ 15722#define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 15723#define MC_CMD_RX_BALANCING_IN_ENG_LEN 4 15724 15725/* MC_CMD_RX_BALANCING_OUT msgresponse */ 15726#define MC_CMD_RX_BALANCING_OUT_LEN 0 15727 15728/***********************************/ 15729/* MC_CMD_TSA_BIND 15730 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more 15731 * info in respect to the binding protocol. 15732 */ 15733#define MC_CMD_TSA_BIND 0x119 15734#undef MC_CMD_0x119_PRIVILEGE_CTG 15735 15736#define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15737 15738/* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */ 15739#define MC_CMD_TSA_BIND_IN_LEN 4 15740#define MC_CMD_TSA_BIND_IN_OP_OFST 0 15741#define MC_CMD_TSA_BIND_IN_OP_LEN 4 15742/* enum: Obsolete. Use MC_CMD_SECURE_NIC_INFO_IN_STATUS. */ 15743#define MC_CMD_TSA_BIND_OP_GET_ID 0x1 15744/* enum: Get a binding ticket from the TSAN. The binding ticket is used as part 15745 * of the binding procedure to authorize the binding of an adapter to a TSAID. 15746 * Refer to SF-114946-SW for more information. This sub-command is only 15747 * available over a TLS secure connection between the TSAN and TSAC. 15748 */ 15749#define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2 15750/* enum: Opcode associated with the propagation of a private key that TSAN uses 15751 * as part of post-binding authentication procedure. More specifically, TSAN 15752 * uses this key for a signing operation. TSAC uses the counterpart public key 15753 * to verify the signature. Note - The post-binding authentication occurs when 15754 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to 15755 * SF-114946-SW for more information. This sub-command is only available over a 15756 * TLS secure connection between the TSAN and TSAC. 15757 */ 15758#define MC_CMD_TSA_BIND_OP_SET_KEY 0x3 15759/* enum: Request an insecure unbinding operation. This sub-command is available 15760 * for any privileged client. 15761 */ 15762#define MC_CMD_TSA_BIND_OP_UNBIND 0x4 15763/* enum: Obsolete. Use MC_CMD_TSA_BIND_OP_SECURE_UNBIND. */ 15764#define MC_CMD_TSA_BIND_OP_UNBIND_EXT 0x5 15765/* enum: Opcode associated with the propagation of the unbinding secret token. 15766 * TSAN persists the unbinding secret token. Refer to SF-115479-TC for more 15767 * information. This sub-command is only available over a TLS secure connection 15768 * between the TSAN and TSAC. 15769 */ 15770#define MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN 0x6 15771/* enum: Obsolete. Use MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION. */ 15772#define MC_CMD_TSA_BIND_OP_DECOMMISSION 0x7 15773/* enum: Obsolete. Use MC_CMD_GET_CERTIFICATE. */ 15774#define MC_CMD_TSA_BIND_OP_GET_CERTIFICATE 0x8 15775/* enum: Request a secure unbinding operation using unbinding token. This sub- 15776 * command is available for any privileged client. 15777 */ 15778#define MC_CMD_TSA_BIND_OP_SECURE_UNBIND 0x9 15779/* enum: Request a secure decommissioning operation. This sub-command is 15780 * available for any privileged client. 15781 */ 15782#define MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION 0xa 15783/* enum: Test facility that allows an adapter to be configured to behave as if 15784 * Bound to a TSA controller with restricted MCDI administrator operations. 15785 * This operation is primarily intended to aid host driver development. 15786 */ 15787#define MC_CMD_TSA_BIND_OP_TEST_MCDI 0xb 15788 15789/* MC_CMD_TSA_BIND_IN_GET_ID msgrequest: Obsolete. Use 15790 * MC_CMD_SECURE_NIC_INFO_IN_STATUS. 15791 */ 15792#define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20 15793/* The operation requested. */ 15794#define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0 15795#define MC_CMD_TSA_BIND_IN_GET_ID_OP_LEN 4 15796/* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates 15797 * the nonce every time as part of the TSAN post-binding authentication 15798 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re- 15799 * connect to the TSAC. Refer to SF-114946-SW for more information. 15800 */ 15801#define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4 15802#define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16 15803 15804/* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */ 15805#define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4 15806/* The operation requested. */ 15807#define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0 15808#define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_LEN 4 15809 15810/* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */ 15811#define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5 15812#define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252 15813#define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num)) 15814/* The operation requested. */ 15815#define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0 15816#define MC_CMD_TSA_BIND_IN_SET_KEY_OP_LEN 4 15817/* This data blob contains the private key generated by the TSAC. TSAN uses 15818 * this key for a signing operation. Note- This private key is used in 15819 * conjunction with the post-binding TSAN authentication procedure that occurs 15820 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer 15821 * to SF-114946-SW for more information. 15822 */ 15823#define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4 15824#define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1 15825#define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1 15826#define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248 15827 15828/* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Request an insecure unbinding 15829 * operation. 15830 */ 15831#define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10 15832/* The operation requested. */ 15833#define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0 15834#define MC_CMD_TSA_BIND_IN_UNBIND_OP_LEN 4 15835/* TSAN unique identifier for the network adapter */ 15836#define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4 15837#define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6 15838 15839/* MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest: Obsolete. Use 15840 * MC_CMD_TSA_BIND_IN_SECURE_UNBIND. 15841 */ 15842#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMIN 93 15843#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX 252 15844#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LEN(num) (92+1*(num)) 15845/* The operation requested. */ 15846#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_OFST 0 15847#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_LEN 4 15848/* TSAN unique identifier for the network adapter */ 15849#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_OFST 4 15850#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_LEN 6 15851/* Align the arguments to 32 bits */ 15852#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_OFST 10 15853#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_LEN 2 15854/* This attribute identifies the TSA infrastructure domain. The length of the 15855 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max 15856 * length. Note- The TSAID is the Organizational Unit Name filed as part of the 15857 * root and server certificates. 15858 */ 15859#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_OFST 12 15860#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_LEN 1 15861#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_NUM 64 15862/* Unbinding secret token. The adapter validates this unbinding token by 15863 * comparing it against the one stored on the adapter as part of the 15864 * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for 15865 * more information. 15866 */ 15867#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_OFST 76 15868#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_LEN 16 15869/* This is the signature of the above mentioned fields- TSANID, TSAID and 15870 * UNBINDTOKEN. As per current requirements, the SIG opaque data blob contains 15871 * ECDSA ECC-384 based signature. The ECC curve is secp384r1. The signature is 15872 * also ASN-1 encoded. Note- The signature is verified based on the public key 15873 * stored into the root certificate that is provisioned on the adapter side. 15874 * This key is known as the PUKtsaid. Refer to SF-115479-TC for more 15875 * information. 15876 */ 15877#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_OFST 92 15878#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_LEN 1 15879#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MINNUM 1 15880#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MAXNUM 160 15881 15882/* MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest */ 15883#define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_LEN 20 15884/* The operation requested. */ 15885#define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_OFST 0 15886#define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_LEN 4 15887/* Unbinding secret token. TSAN persists the unbinding secret token. Refer to 15888 * SF-115479-TC for more information. 15889 */ 15890#define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_OFST 4 15891#define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_LEN 16 15892/* enum: There are situations when the binding process does not complete 15893 * successfully due to key, other attributes corruption at the database level 15894 * (Controller). Adapter can't connect to the controller anymore. To recover, 15895 * make usage of the decommission command that forces the adapter into 15896 * unbinding state. 15897 */ 15898#define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_ADAPTER_BINDING_FAILURE 0x1 15899 15900/* MC_CMD_TSA_BIND_IN_DECOMMISSION msgrequest: Obsolete. Use 15901 * MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION. 15902 */ 15903#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMIN 109 15904#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX 252 15905#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LEN(num) (108+1*(num)) 15906/* This is the signature of the above mentioned fields- TSAID, USER and REASON. 15907 * As per current requirements, the SIG opaque data blob contains ECDSA ECC-384 15908 * based signature. The ECC curve is secp384r1. The signature is also ASN-1 15909 * encoded . Note- The signature is verified based on the public key stored 15910 * into the root certificate that is provisioned on the adapter side. This key 15911 * is known as the PUKtsaid. Refer to SF-115479-TC for more information. 15912 */ 15913#define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_OFST 108 15914#define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_LEN 1 15915#define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MINNUM 1 15916#define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MAXNUM 144 15917/* The operation requested. */ 15918#define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_OFST 0 15919#define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_LEN 4 15920/* This attribute identifies the TSA infrastructure domain. The length of the 15921 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max 15922 * length. Note- The TSAID is the Organizational Unit Name filed as part of the 15923 * root and server certificates. 15924 */ 15925#define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_OFST 4 15926#define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_LEN 1 15927#define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_NUM 64 15928/* User ID that comes, as an example, from the Controller. Note- The 33 byte 15929 * length of this attribute is max length of the linux user name plus null 15930 * character. 15931 */ 15932#define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_OFST 68 15933#define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_LEN 1 15934#define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_NUM 33 15935/* Align the arguments to 32 bits */ 15936#define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_OFST 101 15937#define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_LEN 3 15938/* Reason of why decommissioning happens Note- The list of reasons, defined as 15939 * part of the enumeration below, can be extended. 15940 */ 15941#define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_OFST 104 15942#define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_LEN 4 15943 15944/* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE msgrequest: Obsolete. Use 15945 * MC_CMD_GET_CERTIFICATE. 15946 */ 15947#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_LEN 8 15948/* The operation requested, must be MC_CMD_TSA_BIND_OP_GET_CERTIFICATE. */ 15949#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_OFST 0 15950#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_LEN 4 15951/* Type of the certificate to be retrieved. */ 15952#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_OFST 4 15953#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_LEN 4 15954#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED 0x0 /* enum */ 15955/* enum: Adapter Authentication Certificate (AAC). The AAC is used by the 15956 * controller to verify the authenticity of the adapter. 15957 */ 15958#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC 0x1 15959/* enum: Adapter Authentication Signing Certificate (AASC). The AASC is used by 15960 * the controller to verify the validity of AAC. 15961 */ 15962#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC 0x2 15963 15964/* MC_CMD_TSA_BIND_IN_SECURE_UNBIND msgrequest: Request a secure unbinding 15965 * operation using unbinding token. 15966 */ 15967#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMIN 97 15968#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMAX 200 15969#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LEN(num) (96+1*(num)) 15970/* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_UNBIND. */ 15971#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_OFST 0 15972#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_LEN 4 15973/* Type of the message. (MESSAGE_TYPE_xxx) Must be 15974 * MESSAGE_TYPE_TSA_SECURE_UNBIND. 15975 */ 15976#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_MESSAGE_TYPE_OFST 4 15977#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_MESSAGE_TYPE_LEN 4 15978/* TSAN unique identifier for the network adapter */ 15979#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_OFST 8 15980#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_LEN 6 15981/* Align the arguments to 32 bits */ 15982#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_RSVD_OFST 14 15983#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_RSVD_LEN 2 15984/* A NUL padded US-ASCII string identifying the TSA infrastructure domain. This 15985 * field is for information only, and not used by the firmware. Note- The TSAID 15986 * is the Organizational Unit Name field as part of the root and server 15987 * certificates. 15988 */ 15989#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_OFST 16 15990#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_LEN 1 15991#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_NUM 64 15992/* Unbinding secret token. The adapter validates this unbinding token by 15993 * comparing it against the one stored on the adapter as part of the 15994 * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for 15995 * more information. 15996 */ 15997#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_UNBINDTOKEN_OFST 80 15998#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_UNBINDTOKEN_LEN 16 15999/* The signature computed and encoded as specified by MESSAGE_TYPE. */ 16000#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_OFST 96 16001#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_LEN 1 16002#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_MINNUM 1 16003#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_MAXNUM 104 16004 16005/* MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION msgrequest: Request a secure 16006 * decommissioning operation. 16007 */ 16008#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMIN 113 16009#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMAX 216 16010#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LEN(num) (112+1*(num)) 16011/* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION. */ 16012#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_OFST 0 16013#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_LEN 4 16014/* Type of the message. (MESSAGE_TYPE_xxx) Must be 16015 * MESSAGE_TYPE_SECURE_DECOMMISSION. 16016 */ 16017#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_MESSAGE_TYPE_OFST 4 16018#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_MESSAGE_TYPE_LEN 4 16019/* A NUL padded US-ASCII string identifying the TSA infrastructure domain. This 16020 * field is for information only, and not used by the firmware. Note- The TSAID 16021 * is the Organizational Unit Name field as part of the root and server 16022 * certificates. 16023 */ 16024#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_OFST 8 16025#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_LEN 1 16026#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_NUM 64 16027/* A NUL padded US-ASCII string containing user name of the creator of the 16028 * decommissioning ticket. This field is for information only, and not used by 16029 * the firmware. 16030 */ 16031#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_OFST 72 16032#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_LEN 1 16033#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_NUM 36 16034/* Reason of why decommissioning happens */ 16035#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_REASON_OFST 108 16036#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_REASON_LEN 4 16037/* enum: There are situations when the binding process does not complete 16038 * successfully due to key, other attributes corruption at the database level 16039 * (Controller). Adapter can't connect to the controller anymore. To recover, 16040 * use the decommission command to force the adapter into unbound state. 16041 */ 16042#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_ADAPTER_BINDING_FAILURE 0x1 16043/* The signature computed and encoded as specified by MESSAGE_TYPE. */ 16044#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_OFST 112 16045#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_LEN 1 16046#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_MINNUM 1 16047#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_MAXNUM 104 16048 16049/* MC_CMD_TSA_BIND_IN_TEST_MCDI msgrequest: Test mode that emulates MCDI 16050 * interface restrictions of a bound adapter. This operation is intended for 16051 * test use on adapters that are not deployed and bound to a TSA Controller. 16052 * Using it on a Bound adapter will succeed but will not alter the MCDI 16053 * privileges as MCDI operations will already be restricted. 16054 */ 16055#define MC_CMD_TSA_BIND_IN_TEST_MCDI_LEN 8 16056/* The operation requested must be MC_CMD_TSA_BIND_OP_TEST_MCDI. */ 16057#define MC_CMD_TSA_BIND_IN_TEST_MCDI_OP_OFST 0 16058#define MC_CMD_TSA_BIND_IN_TEST_MCDI_OP_LEN 4 16059/* Enable or disable emulation of bound adapter */ 16060#define MC_CMD_TSA_BIND_IN_TEST_MCDI_CTRL_OFST 4 16061#define MC_CMD_TSA_BIND_IN_TEST_MCDI_CTRL_LEN 4 16062#define MC_CMD_TSA_BIND_IN_TEST_MCDI_DISABLE 0x0 /* enum */ 16063#define MC_CMD_TSA_BIND_IN_TEST_MCDI_ENABLE 0x1 /* enum */ 16064 16065/* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse: Obsolete. Use 16066 * MC_CMD_SECURE_NIC_INFO_OUT_STATUS. 16067 */ 16068#define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15 16069#define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252 16070#define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num)) 16071/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_ID that is sent back to 16072 * the caller. 16073 */ 16074#define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0 16075#define MC_CMD_TSA_BIND_OUT_GET_ID_OP_LEN 4 16076/* Rules engine type. Note- The rules engine type allows TSAC to further 16077 * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the 16078 * proper action accordingly. As an example, TSAC uses the rules engine type to 16079 * select the SF key that differs in the case of TSAN vs. NIC Emulator. 16080 */ 16081#define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4 16082#define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_LEN 4 16083/* enum: Hardware rules engine. */ 16084#define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1 16085/* enum: Nic emulator rules engine. */ 16086#define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2 16087/* enum: SSFE. */ 16088#define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3 16089/* TSAN unique identifier for the network adapter */ 16090#define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 8 16091#define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6 16092/* The signature data blob. The signature is computed against the message 16093 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC 16094 * for more information also in respect to the private keys that are used to 16095 * sign the message based on TSAN pre/post-binding authentication procedure. 16096 */ 16097#define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 14 16098#define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1 16099#define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1 16100#define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 238 16101 16102/* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */ 16103#define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5 16104#define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252 16105#define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num)) 16106/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_TICKET that is sent back 16107 * to the caller. 16108 */ 16109#define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0 16110#define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_LEN 4 16111/* The ticket represents the data blob construct that TSAN sends to TSAC as 16112 * part of the binding protocol. From the TSAN perspective the ticket is an 16113 * opaque construct. For more info refer to SF-115479-TC. 16114 */ 16115#define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4 16116#define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1 16117#define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1 16118#define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248 16119 16120/* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */ 16121#define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4 16122/* The protocol operation code MC_CMD_TSA_BIND_OP_SET_KEY that is sent back to 16123 * the caller. 16124 */ 16125#define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0 16126#define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_LEN 4 16127 16128/* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse: Response to insecure unbind request. 16129 */ 16130#define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8 16131/* Same as MC_CMD_ERR field, but included as 0 in success cases */ 16132#define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0 16133#define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_LEN 4 16134/* Extra status information */ 16135#define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4 16136#define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_LEN 4 16137/* enum: Unbind successful. */ 16138#define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0 16139/* enum: TSANID mismatch */ 16140#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1 16141/* enum: Unable to remove the binding ticket from persistent storage. */ 16142#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2 16143/* enum: TSAN is not bound to a binding ticket. */ 16144#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3 16145 16146/* MC_CMD_TSA_BIND_OUT_UNBIND_EXT msgresponse: Obsolete. Use 16147 * MC_CMD_TSA_BIND_OUT_SECURE_UNBIND. 16148 */ 16149#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_LEN 8 16150/* Same as MC_CMD_ERR field, but included as 0 in success cases */ 16151#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_OFST 0 16152#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_LEN 4 16153/* Extra status information */ 16154#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_OFST 4 16155#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_LEN 4 16156/* enum: Unbind successful. */ 16157#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND 0x0 16158/* enum: TSANID mismatch */ 16159#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID 0x1 16160/* enum: Unable to remove the binding ticket from persistent storage. */ 16161#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET 0x2 16162/* enum: TSAN is not bound to a binding ticket. */ 16163#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND 0x3 16164/* enum: Invalid unbind token */ 16165#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN 0x4 16166/* enum: Invalid signature */ 16167#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE 0x5 16168 16169/* MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN msgresponse */ 16170#define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_LEN 4 16171/* The protocol operation code MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN that is sent 16172 * back to the caller. 16173 */ 16174#define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_OFST 0 16175#define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_LEN 4 16176 16177/* MC_CMD_TSA_BIND_OUT_DECOMMISSION msgresponse: Obsolete. Use 16178 * MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION. 16179 */ 16180#define MC_CMD_TSA_BIND_OUT_DECOMMISSION_LEN 4 16181/* The protocol operation code MC_CMD_TSA_BIND_OP_DECOMMISSION that is sent 16182 * back to the caller. 16183 */ 16184#define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_OFST 0 16185#define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_LEN 4 16186 16187/* MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE msgresponse */ 16188#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMIN 9 16189#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMAX 252 16190#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LEN(num) (8+1*(num)) 16191/* The protocol operation code MC_CMD_TSA_BIND_OP_GET_CERTIFICATE that is sent 16192 * back to the caller. 16193 */ 16194#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_OFST 0 16195#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_LEN 4 16196/* Type of the certificate. */ 16197#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_OFST 4 16198#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_LEN 4 16199/* Enum values, see field(s): */ 16200/* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE/TYPE */ 16201/* The certificate data. */ 16202#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_OFST 8 16203#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_LEN 1 16204#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MINNUM 1 16205#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MAXNUM 244 16206 16207/* MC_CMD_TSA_BIND_OUT_SECURE_UNBIND msgresponse: Response to secure unbind 16208 * request. 16209 */ 16210#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_LEN 8 16211/* The protocol operation code that is sent back to the caller. */ 16212#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OP_OFST 0 16213#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OP_LEN 4 16214#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_RESULT_OFST 4 16215#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_RESULT_LEN 4 16216/* enum: Unbind successful. */ 16217#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OK_UNBOUND 0x0 16218/* enum: TSANID mismatch */ 16219#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TSANID 0x1 16220/* enum: Unable to remove the binding ticket from persistent storage. */ 16221#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_REMOVE_TICKET 0x2 16222/* enum: TSAN is not bound to a domain. */ 16223#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_NOT_BOUND 0x3 16224/* enum: Invalid unbind token */ 16225#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TOKEN 0x4 16226/* enum: Invalid signature */ 16227#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_SIGNATURE 0x5 16228 16229/* MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION msgresponse: Response to secure 16230 * decommission request. 16231 */ 16232#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_LEN 8 16233/* The protocol operation code that is sent back to the caller. */ 16234#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OP_OFST 0 16235#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OP_LEN 4 16236#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_RESULT_OFST 4 16237#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_RESULT_LEN 4 16238/* enum: Unbind successful. */ 16239#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OK_UNBOUND 0x0 16240/* enum: TSANID mismatch */ 16241#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TSANID 0x1 16242/* enum: Unable to remove the binding ticket from persistent storage. */ 16243#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_REMOVE_TICKET 0x2 16244/* enum: TSAN is not bound to a domain. */ 16245#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_NOT_BOUND 0x3 16246/* enum: Invalid unbind token */ 16247#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TOKEN 0x4 16248/* enum: Invalid signature */ 16249#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_SIGNATURE 0x5 16250 16251/* MC_CMD_TSA_BIND_OUT_TEST_MCDI msgrequest */ 16252#define MC_CMD_TSA_BIND_OUT_TEST_MCDI_LEN 4 16253/* The protocol operation code MC_CMD_TSA_BIND_OP_TEST_MCDI that is sent back 16254 * to the caller. 16255 */ 16256#define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_OFST 0 16257#define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_LEN 4 16258 16259/***********************************/ 16260/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE 16261 * Manage the persistent NVRAM cache of security rules created with 16262 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated 16263 * as rules are added or removed; the active ruleset must be explicitly 16264 * committed to the cache. The cache may also be explicitly invalidated, 16265 * without affecting the currently active ruleset. When the cache is valid, it 16266 * will be loaded at power on or MC reboot, instead of the default ruleset. 16267 * Rollback of the currently active ruleset to the cached version (when it is 16268 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not 16269 * directly by drivers. See SF-114946-SW.) NOTE - The only sub-operation 16270 * allowed in an adapter bound to a TSA controller from the local host is 16271 * OP_GET_CACHED_VERSION. All other sub-operations are prohibited. 16272 */ 16273#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a 16274#undef MC_CMD_0x11a_PRIVILEGE_CTG 16275 16276#define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16277 16278/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */ 16279#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4 16280/* the operation to perform */ 16281#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0 16282#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_LEN 4 16283/* enum: reports the ruleset version that is cached in persistent storage but 16284 * performs no other action 16285 */ 16286#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0 16287/* enum: rolls back the active state to the cached version. (May fail with 16288 * ENOENT if there is no valid cached version.) 16289 */ 16290#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1 16291/* enum: commits the active state to the persistent cache */ 16292#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2 16293/* enum: invalidates the persistent cache without affecting the active state */ 16294#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3 16295 16296/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */ 16297#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5 16298#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252 16299#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num)) 16300/* indicates whether the persistent cache is valid (after completion of the 16301 * requested operation in the case of rollback, commit, or invalidate) 16302 */ 16303#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0 16304#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_LEN 4 16305/* enum: persistent cache is invalid (the VERSION field will be empty in this 16306 * case) 16307 */ 16308#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0 16309/* enum: persistent cache is valid */ 16310#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1 16311/* cached ruleset version (after completion of the requested operation, in the 16312 * case of rollback, commit, or invalidate) as an opaque hash value in the same 16313 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION 16314 */ 16315#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4 16316#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1 16317#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1 16318#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248 16319 16320/***********************************/ 16321/* MC_CMD_NVRAM_PRIVATE_APPEND 16322 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 16323 * if the tag is already present. 16324 */ 16325#define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 16326#undef MC_CMD_0x11c_PRIVILEGE_CTG 16327 16328#define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16329 16330/* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 16331#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 16332#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 16333#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 16334/* The tag to be appended */ 16335#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 16336#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4 16337/* The length of the data */ 16338#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 16339#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4 16340/* The data to be contained in the TLV structure */ 16341#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 16342#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 16343#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 16344#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 16345 16346/* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 16347#define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 16348 16349/***********************************/ 16350/* MC_CMD_XPM_VERIFY_CONTENTS 16351 * Verify that the contents of the XPM memory is correct (Medford only). This 16352 * is used during manufacture to check that the XPM memory has been programmed 16353 * correctly at ATE. 16354 */ 16355#define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 16356#undef MC_CMD_0x11b_PRIVILEGE_CTG 16357 16358#define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16359 16360/* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 16361#define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 16362/* Data type to be checked */ 16363#define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 16364#define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4 16365 16366/* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 16367#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 16368#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 16369#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 16370/* Number of sectors found (test builds only) */ 16371#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 16372#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4 16373/* Number of bytes found (test builds only) */ 16374#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 16375#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4 16376/* Length of signature */ 16377#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 16378#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4 16379/* Signature */ 16380#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 16381#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 16382#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 16383#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 16384 16385/***********************************/ 16386/* MC_CMD_SET_EVQ_TMR 16387 * Update the timer load, timer reload and timer mode values for a given EVQ. 16388 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 16389 * be rounded up to the granularity supported by the hardware, then truncated 16390 * to the range supported by the hardware. The resulting value after the 16391 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 16392 * and TMR_RELOAD_ACT_NS). 16393 */ 16394#define MC_CMD_SET_EVQ_TMR 0x120 16395#undef MC_CMD_0x120_PRIVILEGE_CTG 16396 16397#define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16398 16399/* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 16400#define MC_CMD_SET_EVQ_TMR_IN_LEN 16 16401/* Function-relative queue instance */ 16402#define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 16403#define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4 16404/* Requested value for timer load (in nanoseconds) */ 16405#define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 16406#define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4 16407/* Requested value for timer reload (in nanoseconds) */ 16408#define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 16409#define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4 16410/* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 16411#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 16412#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4 16413#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 16414#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 16415#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 16416#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 16417 16418/* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 16419#define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 16420/* Actual value for timer load (in nanoseconds) */ 16421#define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 16422#define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4 16423/* Actual value for timer reload (in nanoseconds) */ 16424#define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 16425#define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4 16426 16427/***********************************/ 16428/* MC_CMD_GET_EVQ_TMR_PROPERTIES 16429 * Query properties about the event queue timers. 16430 */ 16431#define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 16432#undef MC_CMD_0x122_PRIVILEGE_CTG 16433 16434#define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16435 16436/* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 16437#define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 16438 16439/* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 16440#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 16441/* Reserved for future use. */ 16442#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 16443#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4 16444/* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 16445 * nanoseconds) for each increment of the timer load/reload count. The 16446 * requested duration of a timer is this value multiplied by the timer 16447 * load/reload count. 16448 */ 16449#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 16450#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4 16451/* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 16452 * allowed for timer load/reload counts. 16453 */ 16454#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 16455#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4 16456/* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 16457 * multiple of this step size will be rounded in an implementation defined 16458 * manner. 16459 */ 16460#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 16461#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4 16462/* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 16463 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 16464 */ 16465#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 16466#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4 16467/* Timer durations requested via MCDI that are not a multiple of this step size 16468 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 16469 */ 16470#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 16471#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4 16472/* For timers updated using the bug35388 workaround, this is the time interval 16473 * (in nanoseconds) for each increment of the timer load/reload count. The 16474 * requested duration of a timer is this value multiplied by the timer 16475 * load/reload count. This field is only meaningful if the bug35388 workaround 16476 * is enabled. 16477 */ 16478#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 16479#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4 16480/* For timers updated using the bug35388 workaround, this is the maximum value 16481 * allowed for timer load/reload counts. This field is only meaningful if the 16482 * bug35388 workaround is enabled. 16483 */ 16484#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 16485#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4 16486/* For timers updated using the bug35388 workaround, timer load/reload counts 16487 * not a multiple of this step size will be rounded in an implementation 16488 * defined manner. This field is only meaningful if the bug35388 workaround is 16489 * enabled. 16490 */ 16491#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 16492#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4 16493 16494/***********************************/ 16495/* MC_CMD_ALLOCATE_TX_VFIFO_CP 16496 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 16497 * non used switch buffers. 16498 */ 16499#define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 16500#undef MC_CMD_0x11d_PRIVILEGE_CTG 16501 16502#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16503 16504/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 16505#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 16506/* Desired instance. Must be set to a specific instance, which is a function 16507 * local queue index. 16508 */ 16509#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 16510#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4 16511/* Will the common pool be used as TX_vFIFO_ULL (1) */ 16512#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 16513#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4 16514#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 16515/* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 16516#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 16517/* Number of buffers to reserve for the common pool */ 16518#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 16519#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4 16520/* TX datapath to which the Common Pool is connected to. */ 16521#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 16522#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4 16523/* enum: Extracts information from function */ 16524#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 16525/* Network port or RX Engine to which the common pool connects. */ 16526#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 16527#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4 16528/* enum: Extracts information from function */ 16529/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 16530#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 16531#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 16532#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 16533#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 16534/* enum: To enable Switch loopback with Rx engine 0 */ 16535#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 16536/* enum: To enable Switch loopback with Rx engine 1 */ 16537#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 16538 16539/* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 16540#define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 16541/* ID of the common pool allocated */ 16542#define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 16543#define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4 16544 16545/***********************************/ 16546/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 16547 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 16548 * previously allocated common pools. 16549 */ 16550#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 16551#undef MC_CMD_0x11e_PRIVILEGE_CTG 16552 16553#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16554 16555/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 16556#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 16557/* Common pool previously allocated to which the new vFIFO will be associated 16558 */ 16559#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 16560#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4 16561/* Port or RX engine to associate the vFIFO egress */ 16562#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 16563#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4 16564/* enum: Extracts information from common pool */ 16565#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 16566#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 16567#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 16568#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 16569#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 16570/* enum: To enable Switch loopback with Rx engine 0 */ 16571#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 16572/* enum: To enable Switch loopback with Rx engine 1 */ 16573#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 16574/* Minimum number of buffers that the pool must have */ 16575#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 16576#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4 16577/* enum: Do not check the space available */ 16578#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 16579/* Will the vFIFO be used as TX_vFIFO_ULL */ 16580#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 16581#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4 16582/* Network priority of the vFIFO,if applicable */ 16583#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 16584#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4 16585/* enum: Search for the lowest unused priority */ 16586#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 16587 16588/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 16589#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 16590/* Short vFIFO ID */ 16591#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 16592#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4 16593/* Network priority of the vFIFO */ 16594#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 16595#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4 16596 16597/***********************************/ 16598/* MC_CMD_TEARDOWN_TX_VFIFO_VF 16599 * This interface clears the configuration of the given vFIFO and leaves it 16600 * ready to be re-used. 16601 */ 16602#define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 16603#undef MC_CMD_0x11f_PRIVILEGE_CTG 16604 16605#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16606 16607/* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 16608#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 16609/* Short vFIFO ID */ 16610#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 16611#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4 16612 16613/* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 16614#define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 16615 16616/***********************************/ 16617/* MC_CMD_DEALLOCATE_TX_VFIFO_CP 16618 * This interface clears the configuration of the given common pool and leaves 16619 * it ready to be re-used. 16620 */ 16621#define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 16622#undef MC_CMD_0x121_PRIVILEGE_CTG 16623 16624#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16625 16626/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 16627#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 16628/* Common pool ID given when pool allocated */ 16629#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 16630#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4 16631 16632/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 16633#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 16634 16635/***********************************/ 16636/* MC_CMD_REKEY 16637 * This request causes the NIC to generate a new per-NIC key and program it 16638 * into the write-once memory. During the process all flash partitions that are 16639 * protected with a CMAC are verified with the old per-NIC key and then signed 16640 * with the new per-NIC key. If the NIC has already reached its rekey limit the 16641 * REKEY op will return MC_CMD_ERR_ERANGE. The REKEY op may block until 16642 * completion or it may return 0 and continue processing, therefore the caller 16643 * must poll at least once to confirm that the rekeying has completed. The POLL 16644 * operation returns MC_CMD_ERR_EBUSY if the rekey process is still running 16645 * otherwise it will return the result of the last completed rekey operation, 16646 * or 0 if there has not been a previous rekey. 16647 */ 16648#define MC_CMD_REKEY 0x123 16649#undef MC_CMD_0x123_PRIVILEGE_CTG 16650 16651#define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16652 16653/* MC_CMD_REKEY_IN msgrequest */ 16654#define MC_CMD_REKEY_IN_LEN 4 16655/* the type of operation requested */ 16656#define MC_CMD_REKEY_IN_OP_OFST 0 16657#define MC_CMD_REKEY_IN_OP_LEN 4 16658/* enum: Start the rekeying operation */ 16659#define MC_CMD_REKEY_IN_OP_REKEY 0x0 16660/* enum: Poll for completion of the rekeying operation */ 16661#define MC_CMD_REKEY_IN_OP_POLL 0x1 16662 16663/* MC_CMD_REKEY_OUT msgresponse */ 16664#define MC_CMD_REKEY_OUT_LEN 0 16665 16666/***********************************/ 16667/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 16668 * This interface allows the host to find out how many common pool buffers are 16669 * not yet assigned. 16670 */ 16671#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 16672#undef MC_CMD_0x124_PRIVILEGE_CTG 16673 16674#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16675 16676/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 16677#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 16678 16679/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 16680#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 16681/* Available buffers for the ENG to NET vFIFOs. */ 16682#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 16683#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4 16684/* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 16685#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 16686#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4 16687 16688/***********************************/ 16689/* MC_CMD_SET_SECURITY_FUSES 16690 * Change the security level of the adapter by setting bits in the write-once 16691 * memory. The firmware maps each flag in the message to a set of one or more 16692 * hardware-defined or software-defined bits and sets these bits in the write- 16693 * once memory. For Medford the hardware-defined bits are defined in 16694 * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0 16695 * if all of the required bits were set and returns MC_CMD_ERR_EIO if any of 16696 * the required bits were not set. 16697 */ 16698#define MC_CMD_SET_SECURITY_FUSES 0x126 16699#undef MC_CMD_0x126_PRIVILEGE_CTG 16700 16701#define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16702 16703/* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */ 16704#define MC_CMD_SET_SECURITY_FUSES_IN_LEN 4 16705/* Flags specifying what type of security features are being set */ 16706#define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0 16707#define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_LEN 4 16708#define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0 16709#define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1 16710#define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1 16711#define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1 16712#define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_LBN 31 16713#define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_WIDTH 1 16714 16715/* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */ 16716#define MC_CMD_SET_SECURITY_FUSES_OUT_LEN 0 16717 16718/* MC_CMD_SET_SECURITY_FUSES_V2_OUT msgresponse */ 16719#define MC_CMD_SET_SECURITY_FUSES_V2_OUT_LEN 4 16720/* Flags specifying which security features are enforced on the NIC after the 16721 * flags in the request have been applied. See 16722 * MC_CMD_SET_SECURITY_FUSES_IN/FLAGS for flag definitions. 16723 */ 16724#define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_OFST 0 16725#define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_LEN 4 16726 16727/***********************************/ 16728/* MC_CMD_TSA_INFO 16729 * Messages sent from TSA adapter to TSA controller. This command is only valid 16730 * when the MCDI header has MESSAGE_TYPE set to MCDI_MESSAGE_TYPE_TSA. This 16731 * command is not sent by the driver to the MC; it is sent from the MC to a TSA 16732 * controller, being treated more like an alert message rather than a command; 16733 * hence the MC does not expect a response in return. Doxbox reference 16734 * SF-117371-SW 16735 */ 16736#define MC_CMD_TSA_INFO 0x127 16737#undef MC_CMD_0x127_PRIVILEGE_CTG 16738 16739#define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16740 16741/* MC_CMD_TSA_INFO_IN msgrequest */ 16742#define MC_CMD_TSA_INFO_IN_LEN 4 16743#define MC_CMD_TSA_INFO_IN_OP_HDR_OFST 0 16744#define MC_CMD_TSA_INFO_IN_OP_HDR_LEN 4 16745#define MC_CMD_TSA_INFO_IN_OP_LBN 0 16746#define MC_CMD_TSA_INFO_IN_OP_WIDTH 16 16747/* enum: Information about recently discovered local IP address of the adapter 16748 */ 16749#define MC_CMD_TSA_INFO_OP_LOCAL_IP 0x1 16750/* enum: Information about a sampled packet that either - did not match any 16751 * black/white-list filters and was allowed by the default filter or - did not 16752 * match any black/white-list filters and was denied by the default filter 16753 */ 16754#define MC_CMD_TSA_INFO_OP_PKT_SAMPLE 0x2 16755 16756/* MC_CMD_TSA_INFO_IN_LOCAL_IP msgrequest: 16757 * 16758 * The TSA controller maintains a list of IP addresses valid for each port of a 16759 * TSA adapter. The TSA controller requires information from the adapter 16760 * inorder to learn new IP addresses assigned to a physical port and to 16761 * identify those that are no longer assigned to the physical port. For this 16762 * purpose, the TSA adapter snoops ARP replies, gratuitous ARP requests and ARP 16763 * probe packets seen on each physical port. This definition describes the 16764 * format of the notification message sent from a TSA adapter to a TSA 16765 * controller related to any information related to a change in IP address 16766 * assignment for a port. Doxbox reference SF-117371. 16767 * 16768 * There may be a possibility of combining multiple notifications in a single 16769 * message in future. When that happens, a new flag can be defined using the 16770 * reserved bits to describe the extended format of this notification. 16771 */ 16772#define MC_CMD_TSA_INFO_IN_LOCAL_IP_LEN 18 16773#define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_OFST 0 16774#define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_LEN 4 16775/* Additional metadata describing the IP address information such as source of 16776 * information retrieval, type of IP address, physical port number. 16777 */ 16778#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_OFST 4 16779#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_LEN 4 16780#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_LBN 0 16781#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_WIDTH 8 16782#define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_LBN 8 16783#define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_WIDTH 8 16784#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_LBN 16 16785#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_WIDTH 8 16786/* enum: ARP reply sent out of the physical port */ 16787#define MC_CMD_TSA_INFO_IP_REASON_TX_ARP 0x0 16788/* enum: ARP probe packet received on the physical port */ 16789#define MC_CMD_TSA_INFO_IP_REASON_RX_ARP_PROBE 0x1 16790/* enum: Gratuitous ARP packet received on the physical port */ 16791#define MC_CMD_TSA_INFO_IP_REASON_RX_GRATUITOUS_ARP 0x2 16792/* enum: DHCP ACK packet received on the physical port */ 16793#define MC_CMD_TSA_INFO_IP_REASON_RX_DHCP_ACK 0x3 16794#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_LBN 24 16795#define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_WIDTH 1 16796#define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_LBN 25 16797#define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_WIDTH 7 16798/* IPV4 address retrieved from the sampled packets. This field is relevant only 16799 * when META_IPV4 is set to 1. 16800 */ 16801#define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_OFST 8 16802#define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_LEN 4 16803/* Target MAC address retrieved from the sampled packet. */ 16804#define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_OFST 12 16805#define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_LEN 1 16806#define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_NUM 6 16807 16808/* MC_CMD_TSA_INFO_IN_PKT_SAMPLE msgrequest: 16809 * 16810 * It is desireable for the TSA controller to learn the traffic pattern of 16811 * packets seen at the network port being monitored. In order to learn about 16812 * the traffic pattern, the TSA controller may want to sample packets seen at 16813 * the network port. Based on the packet samples that the TSA controller 16814 * receives from the adapter, the controller may choose to configure additional 16815 * black-list or white-list rules to allow or block packets as required. 16816 * 16817 * Although the entire sampled packet as seen on the network port is available 16818 * to the MC the length of sampled packet sent to controller is restricted by 16819 * MCDI payload size. Besides, the TSA controller does not require the entire 16820 * packet to make decisions about filter updates. Hence the packet sample being 16821 * passed to the controller is truncated to 128 bytes. This length is large 16822 * enough to hold the ethernet header, IP header and maximum length of 16823 * supported L4 protocol headers (IPv4 only, but can hold IPv6 header too, if 16824 * required in future). 16825 * 16826 * The intention is that any future changes to this message format that are not 16827 * backwards compatible will be defined with a new operation code. 16828 */ 16829#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_LEN 136 16830#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_OFST 0 16831#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_LEN 4 16832/* Additional metadata describing the sampled packet */ 16833#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_OFST 4 16834#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_LEN 4 16835#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_LBN 0 16836#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_WIDTH 8 16837#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_LBN 8 16838#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_WIDTH 1 16839#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_LBN 9 16840#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_WIDTH 7 16841#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_LBN 16 16842#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_WIDTH 4 16843#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_LBN 16 16844#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_WIDTH 1 16845#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_LBN 17 16846#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_WIDTH 1 16847#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_LBN 18 16848#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_WIDTH 1 16849/* 128-byte raw prefix of the sampled packet which includes the ethernet 16850 * header, IP header and L4 protocol header (only IPv4 supported initially). 16851 * This provides the controller enough information about the packet sample to 16852 * report traffic patterns seen on a network port and to make decisions 16853 * concerning rule-set updates. 16854 */ 16855#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_OFST 8 16856#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_LEN 1 16857#define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_NUM 128 16858 16859/* MC_CMD_TSA_INFO_OUT msgresponse */ 16860#define MC_CMD_TSA_INFO_OUT_LEN 0 16861 16862/***********************************/ 16863/* MC_CMD_HOST_INFO 16864 * Commands to appply or retrieve host-related information from an adapter. 16865 * Doxbox reference SF-117371-SW 16866 */ 16867#define MC_CMD_HOST_INFO 0x128 16868#undef MC_CMD_0x128_PRIVILEGE_CTG 16869 16870#define MC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16871 16872/* MC_CMD_HOST_INFO_IN msgrequest */ 16873#define MC_CMD_HOST_INFO_IN_LEN 4 16874/* sub-operation code info */ 16875#define MC_CMD_HOST_INFO_IN_OP_HDR_OFST 0 16876#define MC_CMD_HOST_INFO_IN_OP_HDR_LEN 4 16877#define MC_CMD_HOST_INFO_IN_OP_LBN 0 16878#define MC_CMD_HOST_INFO_IN_OP_WIDTH 16 16879/* enum: Read a 16-byte unique host identifier from the adapter. This UUID 16880 * helps to identify the host that an adapter is plugged into. This identifier 16881 * is ideally the system UUID retrieved and set by the UEFI driver. If the UEFI 16882 * driver is unable to extract the system UUID, it would still set a random 16883 * 16-byte value into each supported SF adapter plugged into it. Host UUIDs may 16884 * change if the system is power-cycled, however, they persist across adapter 16885 * resets. If the host UUID was not set on an adapter, due to an unsupported 16886 * version of UEFI driver, then this command returns an error. Doxbox reference 16887 * - SF-117371-SW section 'Host UUID'. 16888 */ 16889#define MC_CMD_HOST_INFO_OP_GET_UUID 0x0 16890/* enum: Set a 16-byte unique host identifier on the adapter to identify the 16891 * host that the adapter is plugged into. See MC_CMD_HOST_INFO_OP_GET_UUID for 16892 * further details. 16893 */ 16894#define MC_CMD_HOST_INFO_OP_SET_UUID 0x1 16895 16896/* MC_CMD_HOST_INFO_IN_GET_UUID msgrequest */ 16897#define MC_CMD_HOST_INFO_IN_GET_UUID_LEN 4 16898/* sub-operation code info */ 16899#define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_OFST 0 16900#define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_LEN 4 16901 16902/* MC_CMD_HOST_INFO_OUT_GET_UUID msgresponse */ 16903#define MC_CMD_HOST_INFO_OUT_GET_UUID_LEN 16 16904/* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 16905 * for further details. 16906 */ 16907#define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_OFST 0 16908#define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_LEN 1 16909#define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_NUM 16 16910 16911/* MC_CMD_HOST_INFO_IN_SET_UUID msgrequest */ 16912#define MC_CMD_HOST_INFO_IN_SET_UUID_LEN 20 16913/* sub-operation code info */ 16914#define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_OFST 0 16915#define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_LEN 4 16916/* 16-byte host UUID set on the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID for 16917 * further details. 16918 */ 16919#define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_OFST 4 16920#define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_LEN 1 16921#define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_NUM 16 16922 16923/* MC_CMD_HOST_INFO_OUT_SET_UUID msgresponse */ 16924#define MC_CMD_HOST_INFO_OUT_SET_UUID_LEN 0 16925 16926/***********************************/ 16927/* MC_CMD_TSAN_INFO 16928 * Get TSA adapter information. TSA controllers query each TSA adapter to learn 16929 * some configuration parameters of each adapter. Doxbox reference SF-117371-SW 16930 * section 'Adapter Information' 16931 */ 16932#define MC_CMD_TSAN_INFO 0x129 16933#undef MC_CMD_0x129_PRIVILEGE_CTG 16934 16935#define MC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16936 16937/* MC_CMD_TSAN_INFO_IN msgrequest */ 16938#define MC_CMD_TSAN_INFO_IN_LEN 4 16939/* sub-operation code info */ 16940#define MC_CMD_TSAN_INFO_IN_OP_HDR_OFST 0 16941#define MC_CMD_TSAN_INFO_IN_OP_HDR_LEN 4 16942#define MC_CMD_TSAN_INFO_IN_OP_LBN 0 16943#define MC_CMD_TSAN_INFO_IN_OP_WIDTH 16 16944/* enum: Read configuration parameters and IDs that uniquely identify an 16945 * adapter. The parameters include - host identification, adapter 16946 * identification string and number of physical ports on the adapter. 16947 */ 16948#define MC_CMD_TSAN_INFO_OP_GET_CFG 0x0 16949 16950/* MC_CMD_TSAN_INFO_IN_GET_CFG msgrequest */ 16951#define MC_CMD_TSAN_INFO_IN_GET_CFG_LEN 4 16952/* sub-operation code info */ 16953#define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_OFST 0 16954#define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_LEN 4 16955 16956/* MC_CMD_TSAN_INFO_OUT_GET_CFG msgresponse */ 16957#define MC_CMD_TSAN_INFO_OUT_GET_CFG_LEN 26 16958/* Information about the configuration parameters returned in this response. */ 16959#define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_OFST 0 16960#define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_LEN 4 16961#define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_LBN 0 16962#define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_WIDTH 16 16963#define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_LBN 0 16964#define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_WIDTH 1 16965#define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_LBN 16 16966#define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_WIDTH 8 16967/* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 16968 * for further details. 16969 */ 16970#define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_OFST 4 16971#define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_LEN 1 16972#define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_NUM 16 16973/* A unique identifier per adapter. The base MAC address of the card is used 16974 * for this purpose. 16975 */ 16976#define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_OFST 20 16977#define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_LEN 1 16978#define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_NUM 6 16979 16980/* MC_CMD_TSAN_INFO_OUT_GET_CFG_V2 msgresponse */ 16981#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_LEN 36 16982/* Information about the configuration parameters returned in this response. */ 16983#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_OFST 0 16984#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_LEN 4 16985#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_LBN 0 16986#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_WIDTH 16 16987#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_LBN 0 16988#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_WIDTH 1 16989#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_LBN 16 16990#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_WIDTH 8 16991/* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 16992 * for further details. 16993 */ 16994#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_OFST 4 16995#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_LEN 1 16996#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_NUM 16 16997/* A unique identifier per adapter. The base MAC address of the card is used 16998 * for this purpose. 16999 */ 17000#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_OFST 20 17001#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_LEN 1 17002#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_NUM 6 17003/* Unused bytes, defined for 32-bit alignment of new fields. */ 17004#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_UNUSED_OFST 26 17005#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_UNUSED_LEN 2 17006/* Maximum number of TSA statistics counters in each direction of dataflow 17007 * supported on the card. Note that the statistics counters are always 17008 * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx 17009 * counter. 17010 */ 17011#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_MAX_STATS_OFST 28 17012#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_MAX_STATS_LEN 4 17013/* Width of each statistics counter (represented in bits). This gives an 17014 * indication of wrap point to the user. 17015 */ 17016#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_OFST 32 17017#define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_LEN 4 17018 17019/***********************************/ 17020/* MC_CMD_TSA_STATISTICS 17021 * TSA adapter statistics operations. 17022 */ 17023#define MC_CMD_TSA_STATISTICS 0x130 17024#undef MC_CMD_0x130_PRIVILEGE_CTG 17025 17026#define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17027 17028/* MC_CMD_TSA_STATISTICS_IN msgrequest */ 17029#define MC_CMD_TSA_STATISTICS_IN_LEN 4 17030/* TSA statistics sub-operation code */ 17031#define MC_CMD_TSA_STATISTICS_IN_OP_CODE_OFST 0 17032#define MC_CMD_TSA_STATISTICS_IN_OP_CODE_LEN 4 17033/* enum: Get the configuration parameters that describe the TSA statistics 17034 * layout on the adapter. 17035 */ 17036#define MC_CMD_TSA_STATISTICS_OP_GET_CONFIG 0x0 17037/* enum: Read and/or clear TSA statistics counters. */ 17038#define MC_CMD_TSA_STATISTICS_OP_READ_CLEAR 0x1 17039 17040/* MC_CMD_TSA_STATISTICS_IN_GET_CONFIG msgrequest */ 17041#define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_LEN 4 17042/* TSA statistics sub-operation code */ 17043#define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_OFST 0 17044#define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_LEN 4 17045 17046/* MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG msgresponse */ 17047#define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_LEN 8 17048/* Maximum number of TSA statistics counters in each direction of dataflow 17049 * supported on the card. Note that the statistics counters are always 17050 * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx 17051 * counter. 17052 */ 17053#define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_OFST 0 17054#define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_LEN 4 17055/* Width of each statistics counter (represented in bits). This gives an 17056 * indication of wrap point to the user. 17057 */ 17058#define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_OFST 4 17059#define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_LEN 4 17060 17061/* MC_CMD_TSA_STATISTICS_IN_READ_CLEAR msgrequest */ 17062#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMIN 20 17063#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMAX 252 17064#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LEN(num) (16+4*(num)) 17065/* TSA statistics sub-operation code */ 17066#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_OFST 0 17067#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_LEN 4 17068/* Parameters describing the statistics operation */ 17069#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_OFST 4 17070#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_LEN 4 17071#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_LBN 0 17072#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_WIDTH 1 17073#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_LBN 1 17074#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_WIDTH 1 17075/* Counter ID list specification type */ 17076#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_OFST 8 17077#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_LEN 4 17078/* enum: The statistics counters are specified as an unordered list of 17079 * individual counter ID. 17080 */ 17081#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST 0x0 17082/* enum: The statistics counters are specified as a range of consecutive 17083 * counter IDs. 17084 */ 17085#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE 0x1 17086/* Number of statistics counters */ 17087#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_OFST 12 17088#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_LEN 4 17089/* Counter IDs to be read/cleared. When mode is set to LIST, this entry holds a 17090 * list of counter IDs to be operated on. When mode is set to RANGE, this entry 17091 * holds a single counter ID representing the start of the range of counter IDs 17092 * to be operated on. 17093 */ 17094#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_OFST 16 17095#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_LEN 4 17096#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MINNUM 1 17097#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MAXNUM 59 17098 17099/* MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR msgresponse */ 17100#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMIN 24 17101#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMAX 248 17102#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LEN(num) (8+16*(num)) 17103/* Number of statistics counters returned in this response */ 17104#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_OFST 0 17105#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_LEN 4 17106/* MC_TSA_STATISTICS_ENTRY Note that this field is expected to start at a 17107 * 64-bit aligned offset 17108 */ 17109#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_OFST 8 17110#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_LEN 16 17111#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MINNUM 1 17112#define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MAXNUM 15 17113 17114/* MC_TSA_STATISTICS_ENTRY structuredef */ 17115#define MC_TSA_STATISTICS_ENTRY_LEN 16 17116/* Tx statistics counter */ 17117#define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0 17118#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8 17119#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0 17120#define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4 17121#define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0 17122#define MC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64 17123/* Rx statistics counter */ 17124#define MC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8 17125#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8 17126#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8 17127#define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12 17128#define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64 17129#define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64 17130 17131/***********************************/ 17132/* MC_CMD_ERASE_INITIAL_NIC_SECRET 17133 * This request causes the NIC to find the initial NIC secret (programmed 17134 * during ATE) in XPM memory and if and only if the NIC has already been 17135 * rekeyed with MC_CMD_REKEY, erase it. This is used by manftest after 17136 * installing TSA binding certificates. See SF-117631-TC. 17137 */ 17138#define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131 17139#undef MC_CMD_0x131_PRIVILEGE_CTG 17140 17141#define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17142 17143/* MC_CMD_ERASE_INITIAL_NIC_SECRET_IN msgrequest */ 17144#define MC_CMD_ERASE_INITIAL_NIC_SECRET_IN_LEN 0 17145 17146/* MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT msgresponse */ 17147#define MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT_LEN 0 17148 17149/***********************************/ 17150/* MC_CMD_TSA_CONFIG 17151 * TSA adapter configuration operations. This command is used to prepare the 17152 * NIC for TSA binding. 17153 */ 17154#define MC_CMD_TSA_CONFIG 0x64 17155#undef MC_CMD_0x64_PRIVILEGE_CTG 17156 17157#define MC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17158 17159/* MC_CMD_TSA_CONFIG_IN msgrequest */ 17160#define MC_CMD_TSA_CONFIG_IN_LEN 4 17161/* TSA configuration sub-operation code */ 17162#define MC_CMD_TSA_CONFIG_IN_OP_OFST 0 17163#define MC_CMD_TSA_CONFIG_IN_OP_LEN 4 17164/* enum: Append a single item to the tsa_config partition. Items will be 17165 * encrypted unless they are declared as non-sensitive. Returns 17166 * MC_CMD_ERR_EEXIST if the tag is already present. 17167 */ 17168#define MC_CMD_TSA_CONFIG_OP_APPEND 0x1 17169/* enum: Reset the tsa_config partition to a clean state. */ 17170#define MC_CMD_TSA_CONFIG_OP_RESET 0x2 17171/* enum: Read back a configured item from tsa_config partition. Returns 17172 * MC_CMD_ERR_ENOENT if the item doesn't exist, or MC_CMD_ERR_EPERM if the item 17173 * is declared as sensitive (i.e. is encrypted). 17174 */ 17175#define MC_CMD_TSA_CONFIG_OP_READ 0x3 17176 17177/* MC_CMD_TSA_CONFIG_IN_APPEND msgrequest */ 17178#define MC_CMD_TSA_CONFIG_IN_APPEND_LENMIN 12 17179#define MC_CMD_TSA_CONFIG_IN_APPEND_LENMAX 252 17180#define MC_CMD_TSA_CONFIG_IN_APPEND_LEN(num) (12+1*(num)) 17181/* TSA configuration sub-operation code. The value shall be 17182 * MC_CMD_TSA_CONFIG_OP_APPEND. 17183 */ 17184#define MC_CMD_TSA_CONFIG_IN_APPEND_OP_OFST 0 17185#define MC_CMD_TSA_CONFIG_IN_APPEND_OP_LEN 4 17186/* The tag to be appended */ 17187#define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_OFST 4 17188#define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_LEN 4 17189/* The length of the data in bytes */ 17190#define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_OFST 8 17191#define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_LEN 4 17192/* The item data */ 17193#define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_OFST 12 17194#define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_LEN 1 17195#define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MINNUM 0 17196#define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MAXNUM 240 17197 17198/* MC_CMD_TSA_CONFIG_OUT_APPEND msgresponse */ 17199#define MC_CMD_TSA_CONFIG_OUT_APPEND_LEN 0 17200 17201/* MC_CMD_TSA_CONFIG_IN_RESET msgrequest */ 17202#define MC_CMD_TSA_CONFIG_IN_RESET_LEN 4 17203/* TSA configuration sub-operation code. The value shall be 17204 * MC_CMD_TSA_CONFIG_OP_RESET. 17205 */ 17206#define MC_CMD_TSA_CONFIG_IN_RESET_OP_OFST 0 17207#define MC_CMD_TSA_CONFIG_IN_RESET_OP_LEN 4 17208 17209/* MC_CMD_TSA_CONFIG_OUT_RESET msgresponse */ 17210#define MC_CMD_TSA_CONFIG_OUT_RESET_LEN 0 17211 17212/* MC_CMD_TSA_CONFIG_IN_READ msgrequest */ 17213#define MC_CMD_TSA_CONFIG_IN_READ_LEN 8 17214/* TSA configuration sub-operation code. The value shall be 17215 * MC_CMD_TSA_CONFIG_OP_READ. 17216 */ 17217#define MC_CMD_TSA_CONFIG_IN_READ_OP_OFST 0 17218#define MC_CMD_TSA_CONFIG_IN_READ_OP_LEN 4 17219/* The tag to be read */ 17220#define MC_CMD_TSA_CONFIG_IN_READ_TAG_OFST 4 17221#define MC_CMD_TSA_CONFIG_IN_READ_TAG_LEN 4 17222 17223/* MC_CMD_TSA_CONFIG_OUT_READ msgresponse */ 17224#define MC_CMD_TSA_CONFIG_OUT_READ_LENMIN 8 17225#define MC_CMD_TSA_CONFIG_OUT_READ_LENMAX 252 17226#define MC_CMD_TSA_CONFIG_OUT_READ_LEN(num) (8+1*(num)) 17227/* The tag that was read */ 17228#define MC_CMD_TSA_CONFIG_OUT_READ_TAG_OFST 0 17229#define MC_CMD_TSA_CONFIG_OUT_READ_TAG_LEN 4 17230/* The length of the data in bytes */ 17231#define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_OFST 4 17232#define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_LEN 4 17233/* The data of the item. */ 17234#define MC_CMD_TSA_CONFIG_OUT_READ_DATA_OFST 8 17235#define MC_CMD_TSA_CONFIG_OUT_READ_DATA_LEN 1 17236#define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MINNUM 0 17237#define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MAXNUM 244 17238 17239/* MC_TSA_IPV4_ITEM structuredef */ 17240#define MC_TSA_IPV4_ITEM_LEN 8 17241/* Additional metadata describing the IP address information such as the 17242 * physical port number the address is being used on. Unused space in this 17243 * field is reserved for future expansion. 17244 */ 17245#define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_OFST 0 17246#define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LEN 4 17247#define MC_TSA_IPV4_ITEM_PORT_IDX_LBN 0 17248#define MC_TSA_IPV4_ITEM_PORT_IDX_WIDTH 8 17249#define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LBN 0 17250#define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_WIDTH 32 17251/* The IPv4 address in little endian byte order. */ 17252#define MC_TSA_IPV4_ITEM_IPV4_ADDR_OFST 4 17253#define MC_TSA_IPV4_ITEM_IPV4_ADDR_LEN 4 17254#define MC_TSA_IPV4_ITEM_IPV4_ADDR_LBN 32 17255#define MC_TSA_IPV4_ITEM_IPV4_ADDR_WIDTH 32 17256 17257/***********************************/ 17258/* MC_CMD_TSA_IPADDR 17259 * TSA operations relating to the monitoring and expiry of local IP addresses 17260 * discovered by the controller. These commands are sent from a TSA controller 17261 * to a TSA adapter. 17262 */ 17263#define MC_CMD_TSA_IPADDR 0x65 17264#undef MC_CMD_0x65_PRIVILEGE_CTG 17265 17266#define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17267 17268/* MC_CMD_TSA_IPADDR_IN msgrequest */ 17269#define MC_CMD_TSA_IPADDR_IN_LEN 4 17270/* Header containing information to identify which sub-operation of this 17271 * command to perform. The header contains a 16-bit op-code. Unused space in 17272 * this field is reserved for future expansion. 17273 */ 17274#define MC_CMD_TSA_IPADDR_IN_OP_HDR_OFST 0 17275#define MC_CMD_TSA_IPADDR_IN_OP_HDR_LEN 4 17276#define MC_CMD_TSA_IPADDR_IN_OP_LBN 0 17277#define MC_CMD_TSA_IPADDR_IN_OP_WIDTH 16 17278/* enum: Request that the adapter verifies that the IPv4 addresses supplied are 17279 * still in use by the host by sending ARP probes to the host. The MC does not 17280 * wait for a response to the probes and sends an MCDI response to the 17281 * controller once the probes have been sent to the host. The response to the 17282 * probes (if there are any) will be forwarded to the controller using 17283 * MC_CMD_TSA_INFO alerts. 17284 */ 17285#define MC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4 0x1 17286/* enum: Notify the adapter that one or more IPv4 addresses are no longer valid 17287 * for the host of the adapter. The adapter should remove the IPv4 addresses 17288 * from its local cache. 17289 */ 17290#define MC_CMD_TSA_IPADDR_OP_REMOVE_IPV4 0x2 17291 17292/* MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4 msgrequest */ 17293#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMIN 16 17294#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMAX 248 17295#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LEN(num) (8+8*(num)) 17296/* Header containing information to identify which sub-operation of this 17297 * command to perform. The header contains a 16-bit op-code. Unused space in 17298 * this field is reserved for future expansion. 17299 */ 17300#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_OFST 0 17301#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_LEN 4 17302#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_LBN 0 17303#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_WIDTH 16 17304/* Number of IPv4 addresses to validate. */ 17305#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_OFST 4 17306#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_LEN 4 17307/* The IPv4 addresses to validate, in struct MC_TSA_IPV4_ITEM format. */ 17308#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8 17309#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8 17310#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8 17311#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12 17312#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1 17313#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30 17314 17315/* MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4 msgresponse */ 17316#define MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4_LEN 0 17317 17318/* MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4 msgrequest */ 17319#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMIN 16 17320#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMAX 248 17321#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LEN(num) (8+8*(num)) 17322/* Header containing information to identify which sub-operation of this 17323 * command to perform. The header contains a 16-bit op-code. Unused space in 17324 * this field is reserved for future expansion. 17325 */ 17326#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_OFST 0 17327#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_LEN 4 17328#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_LBN 0 17329#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_WIDTH 16 17330/* Number of IPv4 addresses to remove. */ 17331#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_OFST 4 17332#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_LEN 4 17333/* The IPv4 addresses that have expired, in struct MC_TSA_IPV4_ITEM format. */ 17334#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8 17335#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8 17336#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8 17337#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12 17338#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1 17339#define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30 17340 17341/* MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4 msgresponse */ 17342#define MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4_LEN 0 17343 17344/***********************************/ 17345/* MC_CMD_SECURE_NIC_INFO 17346 * Get secure NIC information. While many of the features reported by these 17347 * commands are related to TSA, they must be supported in firmware where TSA is 17348 * disabled. 17349 */ 17350#define MC_CMD_SECURE_NIC_INFO 0x132 17351#undef MC_CMD_0x132_PRIVILEGE_CTG 17352 17353#define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17354 17355/* MC_CMD_SECURE_NIC_INFO_IN msgrequest */ 17356#define MC_CMD_SECURE_NIC_INFO_IN_LEN 4 17357/* sub-operation code info */ 17358#define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_OFST 0 17359#define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_LEN 4 17360#define MC_CMD_SECURE_NIC_INFO_IN_OP_LBN 0 17361#define MC_CMD_SECURE_NIC_INFO_IN_OP_WIDTH 16 17362/* enum: Get the status of various security settings, all signed along with a 17363 * challenge chosen by the host. 17364 */ 17365#define MC_CMD_SECURE_NIC_INFO_OP_STATUS 0x0 17366 17367/* MC_CMD_SECURE_NIC_INFO_IN_STATUS msgrequest */ 17368#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_LEN 24 17369/* sub-operation code, must be MC_CMD_SECURE_NIC_INFO_OP_STATUS */ 17370#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_OFST 0 17371#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_LEN 4 17372/* Type of key to be used to sign response. */ 17373#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_OFST 4 17374#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_LEN 4 17375#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED 0x0 /* enum */ 17376/* enum: Solarflare adapter authentication key, installed by Manftest. */ 17377#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH 0x1 17378/* enum: TSA binding key, installed after adapter is bound to a TSA controller. 17379 * This is not supported in firmware which does not support TSA. 17380 */ 17381#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING 0x2 17382/* enum: Customer adapter authentication key. Installed by the customer in the 17383 * field, but otherwise similar to the Solarflare adapter authentication key. 17384 */ 17385#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH 0x3 17386/* Random challenge generated by the host. */ 17387#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_OFST 8 17388#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_LEN 16 17389 17390/* MC_CMD_SECURE_NIC_INFO_OUT_STATUS msgresponse */ 17391#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_LEN 420 17392/* Length of the signature in MSG_SIGNATURE. */ 17393#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_OFST 0 17394#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_LEN 4 17395/* Signature over the message, starting at MESSAGE_TYPE and continuing to the 17396 * end of the MCDI response, allowing the message format to be extended. The 17397 * signature uses ECDSA 384 encoding in ASN.1 format. It has variable length, 17398 * with a maximum of 384 bytes. 17399 */ 17400#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_OFST 4 17401#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN 384 17402/* Enum value indicating the type of response. This protects against chosen 17403 * message attacks. The enum values are random rather than sequential to make 17404 * it unlikely that values will be reused should other commands in a different 17405 * namespace need to create signed messages. 17406 */ 17407#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_OFST 388 17408#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_LEN 4 17409/* enum: Message type value for the response to a 17410 * MC_CMD_SECURE_NIC_INFO_IN_STATUS message. 17411 */ 17412#define MC_CMD_SECURE_NIC_INFO_STATUS 0xdb4 17413/* The challenge provided by the host in the MC_CMD_SECURE_NIC_INFO_IN_STATUS 17414 * message 17415 */ 17416#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_OFST 392 17417#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_LEN 16 17418/* The first 32 bits of XPM memory, which include security and flag bits, die 17419 * ID and chip ID revision. The meaning of these bits is defined in 17420 * mc/include/mc/xpm.h in the firmwaresrc repository. 17421 */ 17422#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_OFST 408 17423#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_LEN 4 17424#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_OFST 412 17425#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_LEN 2 17426#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_OFST 414 17427#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_LEN 2 17428#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_OFST 416 17429#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_LEN 2 17430#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_OFST 418 17431#define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_LEN 2 17432 17433/***********************************/ 17434/* MC_CMD_TSA_TEST 17435 * A simple ping-pong command just to test the adapter<>controller MCDI 17436 * communication channel. This command makes not changes to the TSA adapter's 17437 * internal state. It is used by the controller just to verify that the MCDI 17438 * communication channel is working fine. This command takes no additonal 17439 * parameters in request or response. 17440 */ 17441#define MC_CMD_TSA_TEST 0x125 17442#undef MC_CMD_0x125_PRIVILEGE_CTG 17443 17444#define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17445 17446/* MC_CMD_TSA_TEST_IN msgrequest */ 17447#define MC_CMD_TSA_TEST_IN_LEN 0 17448 17449/* MC_CMD_TSA_TEST_OUT msgresponse */ 17450#define MC_CMD_TSA_TEST_OUT_LEN 0 17451 17452/***********************************/ 17453/* MC_CMD_TSA_RULESET_OVERRIDE 17454 * Override TSA ruleset that is currently active on the adapter. This operation 17455 * does not modify the ruleset itself. This operation provides a mechanism to 17456 * apply an allow-all or deny-all operation on all packets, thereby completely 17457 * ignoring the rule-set configured on the adapter. The main purpose of this 17458 * operation is to provide a deterministic state to the TSA firewall during 17459 * rule-set transitions. 17460 */ 17461#define MC_CMD_TSA_RULESET_OVERRIDE 0x12a 17462#undef MC_CMD_0x12a_PRIVILEGE_CTG 17463 17464#define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17465 17466/* MC_CMD_TSA_RULESET_OVERRIDE_IN msgrequest */ 17467#define MC_CMD_TSA_RULESET_OVERRIDE_IN_LEN 4 17468/* The override state to apply. */ 17469#define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_OFST 0 17470#define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_LEN 4 17471/* enum: No override in place - the existing ruleset is in operation. */ 17472#define MC_CMD_TSA_RULESET_OVERRIDE_NONE 0x0 17473/* enum: Block all packets seen on all datapath channel except those packets 17474 * required for basic configuration of the TSA NIC such as ARPs and TSA- 17475 * communication traffic. Such exceptional traffic is handled differently 17476 * compared to TSA rulesets. 17477 */ 17478#define MC_CMD_TSA_RULESET_OVERRIDE_BLOCK 0x1 17479/* enum: Allow all packets through all datapath channel. The TSA adapter 17480 * behaves like a normal NIC without any firewalls. 17481 */ 17482#define MC_CMD_TSA_RULESET_OVERRIDE_ALLOW 0x2 17483 17484/* MC_CMD_TSA_RULESET_OVERRIDE_OUT msgresponse */ 17485#define MC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0 17486 17487/***********************************/ 17488/* MC_CMD_TSAC_REQUEST 17489 * Generic command to send requests from a TSA controller to a TSA adapter. 17490 * Specific usage is determined by the TYPE field. 17491 */ 17492#define MC_CMD_TSAC_REQUEST 0x12b 17493#undef MC_CMD_0x12b_PRIVILEGE_CTG 17494 17495#define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17496 17497/* MC_CMD_TSAC_REQUEST_IN msgrequest */ 17498#define MC_CMD_TSAC_REQUEST_IN_LEN 4 17499/* The type of request from the controller. */ 17500#define MC_CMD_TSAC_REQUEST_IN_TYPE_OFST 0 17501#define MC_CMD_TSAC_REQUEST_IN_TYPE_LEN 4 17502/* enum: Request the adapter to resend localIP information from it's cache. The 17503 * command does not return any IP address information; IP addresses are sent as 17504 * TSA notifications as descibed in MC_CMD_TSA_INFO_IN_LOCAL_IP. 17505 */ 17506#define MC_CMD_TSAC_REQUEST_LOCALIP 0x0 17507 17508/* MC_CMD_TSAC_REQUEST_OUT msgresponse */ 17509#define MC_CMD_TSAC_REQUEST_OUT_LEN 0 17510 17511/***********************************/ 17512/* MC_CMD_SUC_VERSION 17513 * Get the version of the SUC 17514 */ 17515#define MC_CMD_SUC_VERSION 0x134 17516#undef MC_CMD_0x134_PRIVILEGE_CTG 17517 17518#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17519 17520/* MC_CMD_SUC_VERSION_IN msgrequest */ 17521#define MC_CMD_SUC_VERSION_IN_LEN 0 17522 17523/* MC_CMD_SUC_VERSION_OUT msgresponse */ 17524#define MC_CMD_SUC_VERSION_OUT_LEN 24 17525/* The SUC firmware version as four numbers - a.b.c.d */ 17526#define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0 17527#define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4 17528#define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4 17529/* The date, in seconds since the Unix epoch, when the firmware image was 17530 * built. 17531 */ 17532#define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16 17533#define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4 17534/* The ID of the SUC chip. This is specific to the platform but typically 17535 * indicates family, memory sizes etc. See SF-116728-SW for further details. 17536 */ 17537#define MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20 17538#define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4 17539 17540/* MC_CMD_SUC_BOOT_VERSION_IN msgrequest: Get the version of the SUC boot 17541 * loader. 17542 */ 17543#define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4 17544#define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0 17545#define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4 17546/* enum: Requests the SUC boot version. */ 17547#define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b 17548 17549/* MC_CMD_SUC_BOOT_VERSION_OUT msgresponse */ 17550#define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4 17551/* The SUC boot version */ 17552#define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0 17553#define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4 17554 17555/***********************************/ 17556/* MC_CMD_SUC_MANFTEST 17557 * Operations to support manftest on SUC based systems. 17558 */ 17559#define MC_CMD_SUC_MANFTEST 0x135 17560#undef MC_CMD_0x135_PRIVILEGE_CTG 17561 17562#define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17563 17564/* MC_CMD_SUC_MANFTEST_IN msgrequest */ 17565#define MC_CMD_SUC_MANFTEST_IN_LEN 4 17566/* The manftest operation to be performed. */ 17567#define MC_CMD_SUC_MANFTEST_IN_OP_OFST 0 17568#define MC_CMD_SUC_MANFTEST_IN_OP_LEN 4 17569/* enum: Read serial number and use count. */ 17570#define MC_CMD_SUC_MANFTEST_WEAROUT_READ 0x0 17571/* enum: Update use count on wearout adapter. */ 17572#define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE 0x1 17573/* enum: Start an ADC calibration. */ 17574#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START 0x2 17575/* enum: Read the status of an ADC calibration. */ 17576#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS 0x3 17577/* enum: Read the results of an ADC calibration. */ 17578#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT 0x4 17579/* enum: Read the PCIe configuration. */ 17580#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ 0x5 17581/* enum: Write the PCIe configuration. */ 17582#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE 0x6 17583/* enum: Write FRU information to SUC. The FRU information is taken from the 17584 * FRU_INFORMATION partition. Attempts to write to read-only FRUs are rejected. 17585 */ 17586#define MC_CMD_SUC_MANFTEST_FRU_WRITE 0x7 17587 17588/* MC_CMD_SUC_MANFTEST_OUT msgresponse */ 17589#define MC_CMD_SUC_MANFTEST_OUT_LEN 0 17590 17591/* MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN msgrequest */ 17592#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_LEN 4 17593/* The manftest operation to be performed. This must be 17594 * MC_CMD_SUC_MANFTEST_WEAROUT_READ. 17595 */ 17596#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_OFST 0 17597#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_LEN 4 17598 17599/* MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT msgresponse */ 17600#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_LEN 20 17601/* The serial number of the wearout adapter, see SF-112717-PR for format. */ 17602#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_OFST 0 17603#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_LEN 16 17604/* The use count of the wearout adapter. */ 17605#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_OFST 16 17606#define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_LEN 4 17607 17608/* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN msgrequest */ 17609#define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_LEN 4 17610/* The manftest operation to be performed. This must be 17611 * MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE. 17612 */ 17613#define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_OFST 0 17614#define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_LEN 4 17615 17616/* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT msgresponse */ 17617#define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT_LEN 0 17618 17619/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN msgrequest */ 17620#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_LEN 4 17621/* The manftest operation to be performed. This must be 17622 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START. 17623 */ 17624#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_OFST 0 17625#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_LEN 4 17626 17627/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT msgresponse */ 17628#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT_LEN 0 17629 17630/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN msgrequest */ 17631#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_LEN 4 17632/* The manftest operation to be performed. This must be 17633 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS. 17634 */ 17635#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_OFST 0 17636#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_LEN 4 17637 17638/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT msgresponse */ 17639#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_LEN 4 17640/* The combined status of the calibration operation. */ 17641#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_OFST 0 17642#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_LEN 4 17643#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_LBN 0 17644#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_WIDTH 1 17645#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_LBN 1 17646#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_WIDTH 1 17647#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_LBN 2 17648#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_WIDTH 4 17649#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_LBN 6 17650#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_WIDTH 2 17651 17652/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN msgrequest */ 17653#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_LEN 4 17654/* The manftest operation to be performed. This must be 17655 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT. 17656 */ 17657#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_OFST 0 17658#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_LEN 4 17659 17660/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT msgresponse */ 17661#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_LEN 12 17662/* The set of calibration results. */ 17663#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0 17664#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_LEN 4 17665#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_NUM 3 17666 17667/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN msgrequest */ 17668#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_LEN 4 17669/* The manftest operation to be performed. This must be 17670 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ. 17671 */ 17672#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_OFST 0 17673#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_LEN 4 17674 17675/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT msgresponse */ 17676#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_LEN 4 17677/* The PCIe vendor ID. */ 17678#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0 17679#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_VENDOR_ID_LEN 2 17680/* The PCIe device ID. */ 17681#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_DEVICE_ID_OFST 2 17682#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_DEVICE_ID_LEN 2 17683 17684/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN msgrequest */ 17685#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_LEN 8 17686/* The manftest operation to be performed. This must be 17687 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE. 17688 */ 17689#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_OFST 0 17690#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_LEN 4 17691/* The PCIe vendor ID. */ 17692#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_OFST 4 17693#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_LEN 2 17694/* The PCIe device ID. */ 17695#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_OFST 6 17696#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_LEN 2 17697 17698/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT msgresponse */ 17699#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT_LEN 0 17700 17701/* MC_CMD_SUC_MANFTEST_FRU_WRITE_IN msgrequest */ 17702#define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_LEN 4 17703/* The manftest operation to be performed. This must be 17704 * MC_CMD_SUC_MANFTEST_FRU_WRITE 17705 */ 17706#define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_OP_OFST 0 17707#define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_OP_LEN 4 17708 17709/* MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT msgresponse */ 17710#define MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT_LEN 0 17711 17712/***********************************/ 17713/* MC_CMD_GET_CERTIFICATE 17714 * Request a certificate. 17715 */ 17716#define MC_CMD_GET_CERTIFICATE 0x12c 17717#undef MC_CMD_0x12c_PRIVILEGE_CTG 17718 17719#define MC_CMD_0x12c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17720 17721/* MC_CMD_GET_CERTIFICATE_IN msgrequest */ 17722#define MC_CMD_GET_CERTIFICATE_IN_LEN 8 17723/* Type of the certificate to be retrieved. */ 17724#define MC_CMD_GET_CERTIFICATE_IN_TYPE_OFST 0 17725#define MC_CMD_GET_CERTIFICATE_IN_TYPE_LEN 4 17726#define MC_CMD_GET_CERTIFICATE_IN_UNUSED 0x0 /* enum */ 17727#define MC_CMD_GET_CERTIFICATE_IN_AAC 0x1 /* enum */ 17728/* enum: Adapter Authentication Certificate (AAC). The AAC is unique to each 17729 * adapter and is used to verify its authenticity. It is installed by Manftest. 17730 */ 17731#define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH 0x1 17732#define MC_CMD_GET_CERTIFICATE_IN_AASC 0x2 /* enum */ 17733/* enum: Adapter Authentication Signing Certificate (AASC). The AASC is shared 17734 * by a group of adapters (typically a purchase order) and is used to verify 17735 * the validity of AAC along with the SF root certificate. It is installed by 17736 * Manftest. 17737 */ 17738#define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH_SIGNING 0x2 17739#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AAC 0x3 /* enum */ 17740/* enum: Customer Adapter Authentication Certificate. The Customer AAC is 17741 * unique to each adapter and is used to verify its authenticity in cases where 17742 * either the AAC is not installed or a customer desires to use their own 17743 * certificate chain. It is installed by the customer. 17744 */ 17745#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH 0x3 17746#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AASC 0x4 /* enum */ 17747/* enum: Customer Adapter Authentication Certificate. The Customer AASC is 17748 * shared by a group of adapters and is used to verify the validity of the 17749 * Customer AAC along with the customers root certificate. It is installed by 17750 * the customer. 17751 */ 17752#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH_SIGNING 0x4 17753/* Offset, measured in bytes, relative to the start of the certificate data 17754 * from which the certificate is to be retrieved. 17755 */ 17756#define MC_CMD_GET_CERTIFICATE_IN_OFFSET_OFST 4 17757#define MC_CMD_GET_CERTIFICATE_IN_OFFSET_LEN 4 17758 17759/* MC_CMD_GET_CERTIFICATE_OUT msgresponse */ 17760#define MC_CMD_GET_CERTIFICATE_OUT_LENMIN 13 17761#define MC_CMD_GET_CERTIFICATE_OUT_LENMAX 252 17762#define MC_CMD_GET_CERTIFICATE_OUT_LEN(num) (12+1*(num)) 17763/* Type of the certificate. */ 17764#define MC_CMD_GET_CERTIFICATE_OUT_TYPE_OFST 0 17765#define MC_CMD_GET_CERTIFICATE_OUT_TYPE_LEN 4 17766/* Enum values, see field(s): */ 17767/* MC_CMD_GET_CERTIFICATE_IN/TYPE */ 17768/* Offset, measured in bytes, relative to the start of the certificate data 17769 * from which data in this message starts. 17770 */ 17771#define MC_CMD_GET_CERTIFICATE_OUT_OFFSET_OFST 4 17772#define MC_CMD_GET_CERTIFICATE_OUT_OFFSET_LEN 4 17773/* Total length of the certificate data. */ 17774#define MC_CMD_GET_CERTIFICATE_OUT_TOTAL_LENGTH_OFST 8 17775#define MC_CMD_GET_CERTIFICATE_OUT_TOTAL_LENGTH_LEN 4 17776/* The certificate data. */ 17777#define MC_CMD_GET_CERTIFICATE_OUT_DATA_OFST 12 17778#define MC_CMD_GET_CERTIFICATE_OUT_DATA_LEN 1 17779#define MC_CMD_GET_CERTIFICATE_OUT_DATA_MINNUM 1 17780#define MC_CMD_GET_CERTIFICATE_OUT_DATA_MAXNUM 240 17781 17782/***********************************/ 17783/* MC_CMD_GET_NIC_GLOBAL 17784 * Get a global value which applies to all PCI functions 17785 */ 17786#define MC_CMD_GET_NIC_GLOBAL 0x12d 17787#undef MC_CMD_0x12d_PRIVILEGE_CTG 17788 17789#define MC_CMD_0x12d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17790 17791/* MC_CMD_GET_NIC_GLOBAL_IN msgrequest */ 17792#define MC_CMD_GET_NIC_GLOBAL_IN_LEN 4 17793/* Key to request value for, see enum values in MC_CMD_SET_NIC_GLOBAL. If the 17794 * given key is unknown to the current firmware, the call will fail with 17795 * ENOENT. 17796 */ 17797#define MC_CMD_GET_NIC_GLOBAL_IN_KEY_OFST 0 17798#define MC_CMD_GET_NIC_GLOBAL_IN_KEY_LEN 4 17799 17800/* MC_CMD_GET_NIC_GLOBAL_OUT msgresponse */ 17801#define MC_CMD_GET_NIC_GLOBAL_OUT_LEN 4 17802/* Value of requested key, see key descriptions below. */ 17803#define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_OFST 0 17804#define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_LEN 4 17805 17806/***********************************/ 17807/* MC_CMD_SET_NIC_GLOBAL 17808 * Set a global value which applies to all PCI functions. Most global values 17809 * can only be changed under specific conditions, and this call will return an 17810 * appropriate error otherwise (see key descriptions). 17811 */ 17812#define MC_CMD_SET_NIC_GLOBAL 0x12e 17813#undef MC_CMD_0x12e_PRIVILEGE_CTG 17814 17815#define MC_CMD_0x12e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17816 17817/* MC_CMD_SET_NIC_GLOBAL_IN msgrequest */ 17818#define MC_CMD_SET_NIC_GLOBAL_IN_LEN 8 17819/* Key to change value of. Firmware will return ENOENT for keys it doesn't know 17820 * about. 17821 */ 17822#define MC_CMD_SET_NIC_GLOBAL_IN_KEY_OFST 0 17823#define MC_CMD_SET_NIC_GLOBAL_IN_KEY_LEN 4 17824/* enum: Request switching the datapath firmware sub-variant. Currently only 17825 * useful when running the DPDK f/w variant. See key values below, and the DPDK 17826 * section of the EF10 Driver Writers Guide. Note that any driver attaching 17827 * with the SUBVARIANT_AWARE flag cleared is implicitly considered as a request 17828 * to switch back to the default sub-variant, and will thus reset this value. 17829 * If a sub-variant switch happens, all other PCI functions will get their 17830 * resources reset (they will see an MC reboot). 17831 */ 17832#define MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT 0x1 17833/* New value to set, see key descriptions above. */ 17834#define MC_CMD_SET_NIC_GLOBAL_IN_VALUE_OFST 4 17835#define MC_CMD_SET_NIC_GLOBAL_IN_VALUE_LEN 4 17836/* enum: Only if KEY = FIRMWARE_SUBVARIANT. Default sub-variant with support 17837 * for maximum features for the current f/w variant. A request from a 17838 * privileged function to set this particular value will always succeed. 17839 */ 17840#define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT 0x0 17841/* enum: Only if KEY = FIRMWARE_SUBVARIANT. Increases packet rate at the cost 17842 * of not supporting any TX checksum offloads. Only supported when running some 17843 * f/w variants, others will return ENOTSUP (as reported by the homonymous bit 17844 * in MC_CMD_GET_CAPABILITIES_V2). Can only be set when no other drivers are 17845 * attached, and the calling driver must have no resources allocated. See the 17846 * DPDK section of the EF10 Driver Writers Guide for a more detailed 17847 * description with possible error codes. 17848 */ 17849#define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM 0x1 17850 17851/***********************************/ 17852/* MC_CMD_LTSSM_TRACE_POLL 17853 * Medford2 hardware has support for logging all LTSSM state transitions to a 17854 * hardware buffer. When built with WITH_LTSSM_TRACE=1, the firmware will 17855 * periodially dump the contents of this hardware buffer to an internal 17856 * firmware buffer for later extraction. 17857 */ 17858#define MC_CMD_LTSSM_TRACE_POLL 0x12f 17859#undef MC_CMD_0x12f_PRIVILEGE_CTG 17860 17861#define MC_CMD_0x12f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17862 17863/* MC_CMD_LTSSM_TRACE_POLL_IN msgrequest: Read transitions from the firmware 17864 * internal buffer. 17865 */ 17866#define MC_CMD_LTSSM_TRACE_POLL_IN_LEN 4 17867/* The maximum number of row that the caller can accept. The format of each row 17868 * is defined in MC_CMD_LTSSM_TRACE_POLL_OUT. 17869 */ 17870#define MC_CMD_LTSSM_TRACE_POLL_IN_MAX_ROW_COUNT_OFST 0 17871#define MC_CMD_LTSSM_TRACE_POLL_IN_MAX_ROW_COUNT_LEN 4 17872 17873/* MC_CMD_LTSSM_TRACE_POLL_OUT msgresponse */ 17874#define MC_CMD_LTSSM_TRACE_POLL_OUT_LENMIN 16 17875#define MC_CMD_LTSSM_TRACE_POLL_OUT_LENMAX 248 17876#define MC_CMD_LTSSM_TRACE_POLL_OUT_LEN(num) (8+8*(num)) 17877#define MC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_OFST 0 17878#define MC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_LEN 4 17879#define MC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_LBN 0 17880#define MC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_WIDTH 1 17881#define MC_CMD_LTSSM_TRACE_POLL_OUT_FW_BUFFER_OVERFLOW_LBN 1 17882#define MC_CMD_LTSSM_TRACE_POLL_OUT_FW_BUFFER_OVERFLOW_WIDTH 1 17883#define MC_CMD_LTSSM_TRACE_POLL_OUT_CONTINUES_LBN 31 17884#define MC_CMD_LTSSM_TRACE_POLL_OUT_CONTINUES_WIDTH 1 17885/* The number of rows present in this response. */ 17886#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROW_COUNT_OFST 4 17887#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROW_COUNT_LEN 4 17888#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_OFST 8 17889#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LEN 8 17890#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_OFST 8 17891#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_OFST 12 17892#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0 17893#define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM 30 17894#define MC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_LBN 0 17895#define MC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_WIDTH 6 17896#define MC_CMD_LTSSM_TRACE_POLL_OUT_RDLH_LINK_UP_LBN 6 17897#define MC_CMD_LTSSM_TRACE_POLL_OUT_RDLH_LINK_UP_WIDTH 1 17898#define MC_CMD_LTSSM_TRACE_POLL_OUT_WAKE_N_LBN 7 17899#define MC_CMD_LTSSM_TRACE_POLL_OUT_WAKE_N_WIDTH 1 17900#define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_PS_LBN 8 17901#define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_PS_WIDTH 24 17902/* The time of the LTSSM transition. Times are reported as fractional 17903 * microseconds since MC boot (wrapping at 2^32us). The fractional part is 17904 * reported in picoseconds. 0 <= TIMESTAMP_PS < 1000000 timestamp in seconds = 17905 * ((TIMESTAMP_US + TIMESTAMP_PS / 1000000) / 1000000) 17906 */ 17907#define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_US_OFST 12 17908#define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_US_LEN 4 17909 17910#endif /* _SIENA_MC_DRIVER_PCOL_H */ 17911