1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35#ifndef _SYS_EFX_EF10_REGS_H 36#define _SYS_EFX_EF10_REGS_H 37 38#ifdef __cplusplus 39extern "C" { 40#endif 41 42/************************************************************************** 43 * NOTE: the line below marks the start of the autogenerated section 44 * EF10 registers and descriptors 45 * 46 ************************************************************************** 47 */ 48 49/* 50 * BIU_HW_REV_ID_REG(32bit): 51 * 52 */ 53 54#define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 55/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 56#define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face 57 58#define ERF_DZ_HW_REV_ID_LBN 0 59#define ERF_DZ_HW_REV_ID_WIDTH 32 60 61/* 62 * BIU_MC_SFT_STATUS_REG(32bit): 63 * 64 */ 65 66#define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 67/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 68#define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 69#define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 70#define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face 71 72#define ERF_DZ_MC_SFT_STATUS_LBN 0 73#define ERF_DZ_MC_SFT_STATUS_WIDTH 32 74 75/* 76 * BIU_INT_ISR_REG(32bit): 77 * 78 */ 79 80#define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 81/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 82#define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 83 84#define ERF_DZ_ISR_REG_LBN 0 85#define ERF_DZ_ISR_REG_WIDTH 32 86 87/* 88 * MC_DB_LWRD_REG(32bit): 89 * 90 */ 91 92#define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 93/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 94#define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 95 96#define ERF_DZ_MC_DOORBELL_L_LBN 0 97#define ERF_DZ_MC_DOORBELL_L_WIDTH 32 98 99/* 100 * MC_DB_HWRD_REG(32bit): 101 * 102 */ 103 104#define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 105/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 106#define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 107 108#define ERF_DZ_MC_DOORBELL_H_LBN 0 109#define ERF_DZ_MC_DOORBELL_H_WIDTH 32 110 111/* 112 * EVQ_RPTR_REG(32bit): 113 * 114 */ 115 116#define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 117/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 118#define ER_DZ_EVQ_RPTR_REG_STEP 8192 119#define ER_DZ_EVQ_RPTR_REG_ROWS 2048 120#define ER_DZ_EVQ_RPTR_REG_RESET 0x0 121 122#define ERF_DZ_EVQ_RPTR_VLD_LBN 15 123#define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 124#define ERF_DZ_EVQ_RPTR_LBN 0 125#define ERF_DZ_EVQ_RPTR_WIDTH 15 126 127/* 128 * EVQ_RPTR_REG_64K(32bit): 129 * 130 */ 131 132#define ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400 133/* medford2a0=pf_dbell_bar */ 134#define ER_FZ_EVQ_RPTR_REG_64K_STEP 65536 135#define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048 136#define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0 137 138#define ERF_FZ_EVQ_RPTR_VLD_LBN 15 139#define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 140#define ERF_FZ_EVQ_RPTR_LBN 0 141#define ERF_FZ_EVQ_RPTR_WIDTH 15 142 143/* 144 * EVQ_RPTR_REG_16K(32bit): 145 * 146 */ 147 148#define ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400 149/* medford2a0=pf_dbell_bar */ 150#define ER_FZ_EVQ_RPTR_REG_16K_STEP 16384 151#define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048 152#define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0 153 154/* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */ 155/* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */ 156/* defined as ERF_FZ_EVQ_RPTR_LBN 0; */ 157/* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */ 158 159/* 160 * EVQ_TMR_REG_64K(32bit): 161 * 162 */ 163 164#define ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420 165/* medford2a0=pf_dbell_bar */ 166#define ER_FZ_EVQ_TMR_REG_64K_STEP 65536 167#define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048 168#define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0 169 170#define ERF_FZ_TC_TMR_REL_VAL_LBN 16 171#define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 172#define ERF_FZ_TC_TIMER_MODE_LBN 14 173#define ERF_FZ_TC_TIMER_MODE_WIDTH 2 174#define ERF_FZ_TC_TIMER_VAL_LBN 0 175#define ERF_FZ_TC_TIMER_VAL_WIDTH 14 176 177/* 178 * EVQ_TMR_REG_16K(32bit): 179 * 180 */ 181 182#define ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420 183/* medford2a0=pf_dbell_bar */ 184#define ER_FZ_EVQ_TMR_REG_16K_STEP 16384 185#define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048 186#define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0 187 188/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ 189/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ 190/* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */ 191/* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */ 192/* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */ 193/* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */ 194 195/* 196 * EVQ_TMR_REG(32bit): 197 * 198 */ 199 200#define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 201/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 202#define ER_DZ_EVQ_TMR_REG_STEP 8192 203#define ER_DZ_EVQ_TMR_REG_ROWS 2048 204#define ER_DZ_EVQ_TMR_REG_RESET 0x0 205 206/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ 207/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ 208#define ERF_DZ_TC_TIMER_MODE_LBN 14 209#define ERF_DZ_TC_TIMER_MODE_WIDTH 2 210#define ERF_DZ_TC_TIMER_VAL_LBN 0 211#define ERF_DZ_TC_TIMER_VAL_WIDTH 14 212 213/* 214 * RX_DESC_UPD_REG_16K(32bit): 215 * 216 */ 217 218#define ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830 219/* medford2a0=pf_dbell_bar */ 220#define ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384 221#define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048 222#define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0 223 224#define ERF_FZ_RX_DESC_WPTR_LBN 0 225#define ERF_FZ_RX_DESC_WPTR_WIDTH 12 226 227/* 228 * RX_DESC_UPD_REG(32bit): 229 * 230 */ 231 232#define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 233/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 234#define ER_DZ_RX_DESC_UPD_REG_STEP 8192 235#define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 236#define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 237 238#define ERF_DZ_RX_DESC_WPTR_LBN 0 239#define ERF_DZ_RX_DESC_WPTR_WIDTH 12 240 241/* 242 * RX_DESC_UPD_REG_64K(32bit): 243 * 244 */ 245 246#define ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830 247/* medford2a0=pf_dbell_bar */ 248#define ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536 249#define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048 250#define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0 251 252/* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */ 253/* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */ 254 255/* 256 * TX_DESC_UPD_REG_64K(96bit): 257 * 258 */ 259 260#define ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10 261/* medford2a0=pf_dbell_bar */ 262#define ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536 263#define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048 264#define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0 265 266#define ERF_FZ_RSVD_LBN 76 267#define ERF_FZ_RSVD_WIDTH 20 268#define ERF_FZ_TX_DESC_WPTR_LBN 64 269#define ERF_FZ_TX_DESC_WPTR_WIDTH 12 270#define ERF_FZ_TX_DESC_HWORD_LBN 32 271#define ERF_FZ_TX_DESC_HWORD_WIDTH 32 272#define ERF_FZ_TX_DESC_LWORD_LBN 0 273#define ERF_FZ_TX_DESC_LWORD_WIDTH 32 274 275/* 276 * TX_DESC_UPD_REG_16K(96bit): 277 * 278 */ 279 280#define ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10 281/* medford2a0=pf_dbell_bar */ 282#define ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384 283#define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048 284#define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0 285 286/* defined as ERF_FZ_RSVD_LBN 76; */ 287/* defined as ERF_FZ_RSVD_WIDTH 20 */ 288/* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */ 289/* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */ 290/* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */ 291/* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */ 292/* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */ 293/* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */ 294 295/* 296 * TX_DESC_UPD_REG(96bit): 297 * 298 */ 299 300#define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 301/* hunta0,medforda0,medford2a0=pf_dbell_bar */ 302#define ER_DZ_TX_DESC_UPD_REG_STEP 8192 303#define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 304#define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 305 306#define ERF_DZ_RSVD_LBN 76 307#define ERF_DZ_RSVD_WIDTH 20 308#define ERF_DZ_TX_DESC_WPTR_LBN 64 309#define ERF_DZ_TX_DESC_WPTR_WIDTH 12 310#define ERF_DZ_TX_DESC_HWORD_LBN 32 311#define ERF_DZ_TX_DESC_HWORD_WIDTH 32 312#define ERF_DZ_TX_DESC_LWORD_LBN 0 313#define ERF_DZ_TX_DESC_LWORD_WIDTH 32 314 315/* ES_DRIVER_EV */ 316#define ESF_DZ_DRV_CODE_LBN 60 317#define ESF_DZ_DRV_CODE_WIDTH 4 318#define ESF_DZ_DRV_SUB_CODE_LBN 56 319#define ESF_DZ_DRV_SUB_CODE_WIDTH 4 320#define ESE_DZ_DRV_TIMER_EV 3 321#define ESE_DZ_DRV_START_UP_EV 2 322#define ESE_DZ_DRV_WAKE_UP_EV 1 323#define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 324#define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 325#define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 326#define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 327#define ESF_DZ_DRV_SUB_DATA_LBN 0 328#define ESF_DZ_DRV_SUB_DATA_WIDTH 56 329#define ESF_DZ_DRV_EVQ_ID_LBN 0 330#define ESF_DZ_DRV_EVQ_ID_WIDTH 14 331#define ESF_DZ_DRV_TMR_ID_LBN 0 332#define ESF_DZ_DRV_TMR_ID_WIDTH 14 333 334/* ES_EVENT_ENTRY */ 335#define ESF_DZ_EV_CODE_LBN 60 336#define ESF_DZ_EV_CODE_WIDTH 4 337#define ESE_DZ_EV_CODE_MCDI_EV 12 338#define ESE_DZ_EV_CODE_DRIVER_EV 5 339#define ESE_DZ_EV_CODE_TX_EV 2 340#define ESE_DZ_EV_CODE_RX_EV 0 341#define ESE_DZ_OTHER other 342#define ESF_DZ_EV_DATA_DW0_LBN 0 343#define ESF_DZ_EV_DATA_DW0_WIDTH 32 344#define ESF_DZ_EV_DATA_DW1_LBN 32 345#define ESF_DZ_EV_DATA_DW1_WIDTH 28 346#define ESF_DZ_EV_DATA_LBN 0 347#define ESF_DZ_EV_DATA_WIDTH 60 348 349/* ES_MC_EVENT */ 350#define ESF_DZ_MC_CODE_LBN 60 351#define ESF_DZ_MC_CODE_WIDTH 4 352#define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 353#define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 354#define ESF_DZ_MC_DROP_EVENT_LBN 58 355#define ESF_DZ_MC_DROP_EVENT_WIDTH 1 356#define ESF_DZ_MC_SOFT_DW0_LBN 0 357#define ESF_DZ_MC_SOFT_DW0_WIDTH 32 358#define ESF_DZ_MC_SOFT_DW1_LBN 32 359#define ESF_DZ_MC_SOFT_DW1_WIDTH 26 360#define ESF_DZ_MC_SOFT_LBN 0 361#define ESF_DZ_MC_SOFT_WIDTH 58 362 363/* ES_RX_EVENT */ 364#define ESF_DZ_RX_CODE_LBN 60 365#define ESF_DZ_RX_CODE_WIDTH 4 366#define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 367#define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 368#define ESF_DZ_RX_DROP_EVENT_LBN 58 369#define ESF_DZ_RX_DROP_EVENT_WIDTH 1 370#define ESF_DD_RX_EV_RSVD2_LBN 54 371#define ESF_DD_RX_EV_RSVD2_WIDTH 4 372#define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 373#define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 374#define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 375#define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 376#define ESF_EZ_RX_EV_RSVD2_LBN 54 377#define ESF_EZ_RX_EV_RSVD2_WIDTH 2 378#define ESF_DZ_RX_EV_SOFT2_LBN 52 379#define ESF_DZ_RX_EV_SOFT2_WIDTH 2 380#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 381#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 382#define ESF_DE_RX_L4_CLASS_LBN 45 383#define ESF_DE_RX_L4_CLASS_WIDTH 3 384#define ESE_DE_L4_CLASS_RSVD7 7 385#define ESE_DE_L4_CLASS_RSVD6 6 386#define ESE_DE_L4_CLASS_RSVD5 5 387#define ESE_DE_L4_CLASS_RSVD4 4 388#define ESE_DE_L4_CLASS_RSVD3 3 389#define ESE_DE_L4_CLASS_UDP 2 390#define ESE_DE_L4_CLASS_TCP 1 391#define ESE_DE_L4_CLASS_UNKNOWN 0 392#define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 393#define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 394#define ESF_FZ_RX_L4_CLASS_LBN 45 395#define ESF_FZ_RX_L4_CLASS_WIDTH 2 396#define ESE_FZ_L4_CLASS_RSVD3 3 397#define ESE_FZ_L4_CLASS_UDP 2 398#define ESE_FZ_L4_CLASS_TCP 1 399#define ESE_FZ_L4_CLASS_UNKNOWN 0 400#define ESF_DZ_RX_L3_CLASS_LBN 42 401#define ESF_DZ_RX_L3_CLASS_WIDTH 3 402#define ESE_DZ_L3_CLASS_RSVD7 7 403#define ESE_DZ_L3_CLASS_IP6_FRAG 6 404#define ESE_DZ_L3_CLASS_ARP 5 405#define ESE_DZ_L3_CLASS_IP4_FRAG 4 406#define ESE_DZ_L3_CLASS_FCOE 3 407#define ESE_DZ_L3_CLASS_IP6 2 408#define ESE_DZ_L3_CLASS_IP4 1 409#define ESE_DZ_L3_CLASS_UNKNOWN 0 410#define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 411#define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 412#define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 413#define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 414#define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 415#define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 416#define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 417#define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 418#define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 419#define ESE_DZ_ETH_TAG_CLASS_NONE 0 420#define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 421#define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 422#define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 423#define ESE_DZ_ETH_BASE_CLASS_LLC 1 424#define ESE_DZ_ETH_BASE_CLASS_ETH2 0 425#define ESF_DZ_RX_MAC_CLASS_LBN 35 426#define ESF_DZ_RX_MAC_CLASS_WIDTH 1 427#define ESE_DZ_MAC_CLASS_MCAST 1 428#define ESE_DZ_MAC_CLASS_UCAST 0 429#define ESF_DD_RX_EV_SOFT1_LBN 32 430#define ESF_DD_RX_EV_SOFT1_WIDTH 3 431#define ESF_EZ_RX_EV_SOFT1_LBN 34 432#define ESF_EZ_RX_EV_SOFT1_WIDTH 1 433#define ESF_EZ_RX_ENCAP_HDR_LBN 32 434#define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 435#define ESE_EZ_ENCAP_HDR_GRE 2 436#define ESE_EZ_ENCAP_HDR_VXLAN 1 437#define ESE_EZ_ENCAP_HDR_NONE 0 438#define ESF_DD_RX_EV_RSVD1_LBN 30 439#define ESF_DD_RX_EV_RSVD1_WIDTH 2 440#define ESF_EZ_RX_EV_RSVD1_LBN 31 441#define ESF_EZ_RX_EV_RSVD1_WIDTH 1 442#define ESF_EZ_RX_ABORT_LBN 30 443#define ESF_EZ_RX_ABORT_WIDTH 1 444#define ESF_DZ_RX_ECC_ERR_LBN 29 445#define ESF_DZ_RX_ECC_ERR_WIDTH 1 446#define ESF_DZ_RX_TRUNC_ERR_LBN 29 447#define ESF_DZ_RX_TRUNC_ERR_WIDTH 1 448#define ESF_DZ_RX_CRC1_ERR_LBN 28 449#define ESF_DZ_RX_CRC1_ERR_WIDTH 1 450#define ESF_DZ_RX_CRC0_ERR_LBN 27 451#define ESF_DZ_RX_CRC0_ERR_WIDTH 1 452#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 453#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 454#define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 455#define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 456#define ESF_DZ_RX_ECRC_ERR_LBN 24 457#define ESF_DZ_RX_ECRC_ERR_WIDTH 1 458#define ESF_DZ_RX_QLABEL_LBN 16 459#define ESF_DZ_RX_QLABEL_WIDTH 5 460#define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 461#define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 462#define ESF_DZ_RX_CONT_LBN 14 463#define ESF_DZ_RX_CONT_WIDTH 1 464#define ESF_DZ_RX_BYTES_LBN 0 465#define ESF_DZ_RX_BYTES_WIDTH 14 466 467/* ES_RX_KER_DESC */ 468#define ESF_DZ_RX_KER_RESERVED_LBN 62 469#define ESF_DZ_RX_KER_RESERVED_WIDTH 2 470#define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 471#define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 472#define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0 473#define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 474#define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32 475#define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16 476#define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 477#define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 478 479/* ES_TX_CSUM_TSTAMP_DESC */ 480#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 481#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 482#define ESF_DZ_TX_OPTION_TYPE_LBN 60 483#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 484#define ESE_DZ_TX_OPTION_DESC_TSO 7 485#define ESE_DZ_TX_OPTION_DESC_VLAN 6 486#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 487#define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 488#define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 489#define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 490#define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 491#define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 492#define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 493#define ESF_DZ_TX_TIMESTAMP_LBN 5 494#define ESF_DZ_TX_TIMESTAMP_WIDTH 1 495#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 496#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 497#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 498#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 499#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 500#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 501#define ESE_DZ_TX_OPTION_CRC_FCOE 1 502#define ESE_DZ_TX_OPTION_CRC_OFF 0 503#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 504#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 505#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 506#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 507 508/* ES_TX_EVENT */ 509#define ESF_DZ_TX_CODE_LBN 60 510#define ESF_DZ_TX_CODE_WIDTH 4 511#define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 512#define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 513#define ESF_DZ_TX_DROP_EVENT_LBN 58 514#define ESF_DZ_TX_DROP_EVENT_WIDTH 1 515#define ESF_DD_TX_EV_RSVD_LBN 48 516#define ESF_DD_TX_EV_RSVD_WIDTH 10 517#define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 518#define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 519#define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 520#define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 521#define ESF_EZ_TX_EV_RSVD_LBN 48 522#define ESF_EZ_TX_EV_RSVD_WIDTH 8 523#define ESF_DZ_TX_SOFT2_LBN 32 524#define ESF_DZ_TX_SOFT2_WIDTH 16 525#define ESF_DD_TX_SOFT1_LBN 24 526#define ESF_DD_TX_SOFT1_WIDTH 8 527#define ESF_EZ_TX_CAN_MERGE_LBN 31 528#define ESF_EZ_TX_CAN_MERGE_WIDTH 1 529#define ESF_EZ_TX_SOFT1_LBN 24 530#define ESF_EZ_TX_SOFT1_WIDTH 7 531#define ESF_DZ_TX_QLABEL_LBN 16 532#define ESF_DZ_TX_QLABEL_WIDTH 5 533#define ESF_DZ_TX_DESCR_INDX_LBN 0 534#define ESF_DZ_TX_DESCR_INDX_WIDTH 16 535 536/* ES_TX_KER_DESC */ 537#define ESF_DZ_TX_KER_TYPE_LBN 63 538#define ESF_DZ_TX_KER_TYPE_WIDTH 1 539#define ESF_DZ_TX_KER_CONT_LBN 62 540#define ESF_DZ_TX_KER_CONT_WIDTH 1 541#define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 542#define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 543#define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 544#define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 545#define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 546#define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 547#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 548#define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 549 550/* ES_TX_PIO_DESC */ 551#define ESF_DZ_TX_PIO_TYPE_LBN 63 552#define ESF_DZ_TX_PIO_TYPE_WIDTH 1 553#define ESF_DZ_TX_PIO_OPT_LBN 60 554#define ESF_DZ_TX_PIO_OPT_WIDTH 3 555#define ESF_DZ_TX_PIO_CONT_LBN 59 556#define ESF_DZ_TX_PIO_CONT_WIDTH 1 557#define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 558#define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 559#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 560#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 561 562/* ES_TX_TSO_DESC */ 563#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 564#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 565#define ESF_DZ_TX_OPTION_TYPE_LBN 60 566#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 567#define ESE_DZ_TX_OPTION_DESC_TSO 7 568#define ESE_DZ_TX_OPTION_DESC_VLAN 6 569#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 570#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 571#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 572#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 573#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 574#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 575#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 576#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 577#define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 578#define ESF_DZ_TX_TSO_IP_ID_LBN 32 579#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 580#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 581#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 582 583/* ES_TX_TSO_V2_DESC_A */ 584#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 585#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 586#define ESF_DZ_TX_OPTION_TYPE_LBN 60 587#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 588#define ESE_DZ_TX_OPTION_DESC_TSO 7 589#define ESE_DZ_TX_OPTION_DESC_VLAN 6 590#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 591#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 592#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 593#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 594#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 595#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 596#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 597#define ESF_DZ_TX_TSO_IP_ID_LBN 32 598#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 599#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 600#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 601 602/* ES_TX_TSO_V2_DESC_B */ 603#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 604#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 605#define ESF_DZ_TX_OPTION_TYPE_LBN 60 606#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 607#define ESE_DZ_TX_OPTION_DESC_TSO 7 608#define ESE_DZ_TX_OPTION_DESC_VLAN 6 609#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 610#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 611#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 612#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 613#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 614#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 615#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 616#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 617#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 618#define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 619#define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 620 621/* ES_TX_VLAN_DESC */ 622#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 623#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 624#define ESF_DZ_TX_OPTION_TYPE_LBN 60 625#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 626#define ESE_DZ_TX_OPTION_DESC_TSO 7 627#define ESE_DZ_TX_OPTION_DESC_VLAN 6 628#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 629#define ESF_DZ_TX_VLAN_OP_LBN 32 630#define ESF_DZ_TX_VLAN_OP_WIDTH 2 631#define ESF_DZ_TX_VLAN_TAG2_LBN 16 632#define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 633#define ESF_DZ_TX_VLAN_TAG1_LBN 0 634#define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 635 636/************************************************************************* 637 * NOTE: the comment line above marks the end of the autogenerated section 638 */ 639 640/* 641 * The workaround for bug 35388 requires multiplexing writes through 642 * the ERF_DZ_TX_DESC_WPTR address. 643 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 644 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 645 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 646 */ 647#define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) 648#define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP 649#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 650#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 651#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 652#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 653#define ERF_DD_EVQ_IND_RPTR_LBN 0 654#define ERF_DD_EVQ_IND_RPTR_WIDTH 8 655#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 656#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 657#define EFE_DD_EVQ_IND_TIMER_FLAGS 3 658#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 659#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 660#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 661#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 662 663/* Packed stream magic doorbell command */ 664#define ERF_DZ_RX_DESC_MAGIC_DOORBELL_LBN 11 665#define ERF_DZ_RX_DESC_MAGIC_DOORBELL_WIDTH 1 666 667#define ERF_DZ_RX_DESC_MAGIC_CMD_LBN 8 668#define ERF_DZ_RX_DESC_MAGIC_CMD_WIDTH 3 669#define ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS 0 670 671#define ERF_DZ_RX_DESC_MAGIC_DATA_LBN 0 672#define ERF_DZ_RX_DESC_MAGIC_DATA_WIDTH 8 673 674/* Packed stream RX packet prefix */ 675#define ES_DZ_PS_RX_PREFIX_TSTAMP_LBN 0 676#define ES_DZ_PS_RX_PREFIX_TSTAMP_WIDTH 32 677#define ES_DZ_PS_RX_PREFIX_CAP_LEN_LBN 32 678#define ES_DZ_PS_RX_PREFIX_CAP_LEN_WIDTH 16 679#define ES_DZ_PS_RX_PREFIX_ORIG_LEN_LBN 48 680#define ES_DZ_PS_RX_PREFIX_ORIG_LEN_WIDTH 16 681 682/* Equal stride super-buffer RX packet prefix (see SF-119419-TC) */ 683#define ES_EZ_ESSB_RX_PREFIX_LEN 8 684#define ES_EZ_ESSB_RX_PREFIX_DATA_LEN_LBN 0 685#define ES_EZ_ESSB_RX_PREFIX_DATA_LEN_WIDTH 16 686#define ES_EZ_ESSB_RX_PREFIX_MARK_LBN 16 687#define ES_EZ_ESSB_RX_PREFIX_MARK_WIDTH 8 688#define ES_EZ_ESSB_RX_PREFIX_HASH_VALID_LBN 28 689#define ES_EZ_ESSB_RX_PREFIX_HASH_VALID_WIDTH 1 690#define ES_EZ_ESSB_RX_PREFIX_MARK_VALID_LBN 29 691#define ES_EZ_ESSB_RX_PREFIX_MARK_VALID_WIDTH 1 692#define ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_LBN 30 693#define ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_WIDTH 1 694#define ES_EZ_ESSB_RX_PREFIX_HASH_LBN 32 695#define ES_EZ_ESSB_RX_PREFIX_HASH_WIDTH 32 696 697/* 698 * An extra flag for the packed stream mode, 699 * signalling the start of a new buffer 700 */ 701#define ESF_DZ_RX_EV_ROTATE_LBN 53 702#define ESF_DZ_RX_EV_ROTATE_WIDTH 1 703 704#ifdef __cplusplus 705} 706#endif 707 708#endif /* _SYS_EFX_EF10_REGS_H */ 709