1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 *    this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 *    this list of conditions and the following disclaimer in the documentation
14 *    and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD$");
35
36#include "efx.h"
37#include "efx_impl.h"
38
39#if EFSYS_OPT_SIENA
40
41static	__checkReturn	efx_rc_t
42siena_intr_init(
43	__in		efx_nic_t *enp,
44	__in		efx_intr_type_t type,
45	__in		efsys_mem_t *esmp);
46
47static			void
48siena_intr_enable(
49	__in		efx_nic_t *enp);
50
51static			void
52siena_intr_disable(
53	__in		efx_nic_t *enp);
54
55static			void
56siena_intr_disable_unlocked(
57	__in		efx_nic_t *enp);
58
59static	__checkReturn	efx_rc_t
60siena_intr_trigger(
61	__in		efx_nic_t *enp,
62	__in		unsigned int level);
63
64static			void
65siena_intr_fini(
66	__in		efx_nic_t *enp);
67
68static			void
69siena_intr_status_line(
70	__in		efx_nic_t *enp,
71	__out		boolean_t *fatalp,
72	__out		uint32_t *qmaskp);
73
74static			void
75siena_intr_status_message(
76	__in		efx_nic_t *enp,
77	__in		unsigned int message,
78	__out		boolean_t *fatalp);
79
80static			void
81siena_intr_fatal(
82	__in		efx_nic_t *enp);
83
84static	__checkReturn	boolean_t
85siena_intr_check_fatal(
86	__in		efx_nic_t *enp);
87
88#endif /* EFSYS_OPT_SIENA */
89
90#if EFSYS_OPT_SIENA
91static const efx_intr_ops_t	__efx_intr_siena_ops = {
92	siena_intr_init,		/* eio_init */
93	siena_intr_enable,		/* eio_enable */
94	siena_intr_disable,		/* eio_disable */
95	siena_intr_disable_unlocked,	/* eio_disable_unlocked */
96	siena_intr_trigger,		/* eio_trigger */
97	siena_intr_status_line,		/* eio_status_line */
98	siena_intr_status_message,	/* eio_status_message */
99	siena_intr_fatal,		/* eio_fatal */
100	siena_intr_fini,		/* eio_fini */
101};
102#endif	/* EFSYS_OPT_SIENA */
103
104#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
105static const efx_intr_ops_t	__efx_intr_ef10_ops = {
106	ef10_intr_init,			/* eio_init */
107	ef10_intr_enable,		/* eio_enable */
108	ef10_intr_disable,		/* eio_disable */
109	ef10_intr_disable_unlocked,	/* eio_disable_unlocked */
110	ef10_intr_trigger,		/* eio_trigger */
111	ef10_intr_status_line,		/* eio_status_line */
112	ef10_intr_status_message,	/* eio_status_message */
113	ef10_intr_fatal,		/* eio_fatal */
114	ef10_intr_fini,			/* eio_fini */
115};
116#endif	/* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
117
118	__checkReturn	efx_rc_t
119efx_intr_init(
120	__in		efx_nic_t *enp,
121	__in		efx_intr_type_t type,
122	__in_opt	efsys_mem_t *esmp)
123{
124	efx_intr_t *eip = &(enp->en_intr);
125	const efx_intr_ops_t *eiop;
126	efx_rc_t rc;
127
128	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
129	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
130
131	if (enp->en_mod_flags & EFX_MOD_INTR) {
132		rc = EINVAL;
133		goto fail1;
134	}
135
136	eip->ei_esmp = esmp;
137	eip->ei_type = type;
138	eip->ei_level = 0;
139
140	enp->en_mod_flags |= EFX_MOD_INTR;
141
142	switch (enp->en_family) {
143#if EFSYS_OPT_SIENA
144	case EFX_FAMILY_SIENA:
145		eiop = &__efx_intr_siena_ops;
146		break;
147#endif	/* EFSYS_OPT_SIENA */
148
149#if EFSYS_OPT_HUNTINGTON
150	case EFX_FAMILY_HUNTINGTON:
151		eiop = &__efx_intr_ef10_ops;
152		break;
153#endif	/* EFSYS_OPT_HUNTINGTON */
154
155#if EFSYS_OPT_MEDFORD
156	case EFX_FAMILY_MEDFORD:
157		eiop = &__efx_intr_ef10_ops;
158		break;
159#endif	/* EFSYS_OPT_MEDFORD */
160
161#if EFSYS_OPT_MEDFORD2
162	case EFX_FAMILY_MEDFORD2:
163		eiop = &__efx_intr_ef10_ops;
164		break;
165#endif	/* EFSYS_OPT_MEDFORD2 */
166
167	default:
168		EFSYS_ASSERT(B_FALSE);
169		rc = ENOTSUP;
170		goto fail2;
171	}
172
173	if ((rc = eiop->eio_init(enp, type, esmp)) != 0)
174		goto fail3;
175
176	eip->ei_eiop = eiop;
177
178	return (0);
179
180fail3:
181	EFSYS_PROBE(fail3);
182fail2:
183	EFSYS_PROBE(fail2);
184fail1:
185	EFSYS_PROBE1(fail1, efx_rc_t, rc);
186
187	return (rc);
188}
189
190		void
191efx_intr_fini(
192	__in	efx_nic_t *enp)
193{
194	efx_intr_t *eip = &(enp->en_intr);
195	const efx_intr_ops_t *eiop = eip->ei_eiop;
196
197	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
198	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
199	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
200
201	eiop->eio_fini(enp);
202
203	enp->en_mod_flags &= ~EFX_MOD_INTR;
204}
205
206			void
207efx_intr_enable(
208	__in		efx_nic_t *enp)
209{
210	efx_intr_t *eip = &(enp->en_intr);
211	const efx_intr_ops_t *eiop = eip->ei_eiop;
212
213	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
214	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
215
216	eiop->eio_enable(enp);
217}
218
219			void
220efx_intr_disable(
221	__in		efx_nic_t *enp)
222{
223	efx_intr_t *eip = &(enp->en_intr);
224	const efx_intr_ops_t *eiop = eip->ei_eiop;
225
226	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
227	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
228
229	eiop->eio_disable(enp);
230}
231
232			void
233efx_intr_disable_unlocked(
234	__in		efx_nic_t *enp)
235{
236	efx_intr_t *eip = &(enp->en_intr);
237	const efx_intr_ops_t *eiop = eip->ei_eiop;
238
239	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
240	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
241
242	eiop->eio_disable_unlocked(enp);
243}
244
245	__checkReturn	efx_rc_t
246efx_intr_trigger(
247	__in		efx_nic_t *enp,
248	__in		unsigned int level)
249{
250	efx_intr_t *eip = &(enp->en_intr);
251	const efx_intr_ops_t *eiop = eip->ei_eiop;
252
253	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
254	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
255
256	return (eiop->eio_trigger(enp, level));
257}
258
259			void
260efx_intr_status_line(
261	__in		efx_nic_t *enp,
262	__out		boolean_t *fatalp,
263	__out		uint32_t *qmaskp)
264{
265	efx_intr_t *eip = &(enp->en_intr);
266	const efx_intr_ops_t *eiop = eip->ei_eiop;
267
268	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
269	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
270
271	eiop->eio_status_line(enp, fatalp, qmaskp);
272}
273
274			void
275efx_intr_status_message(
276	__in		efx_nic_t *enp,
277	__in		unsigned int message,
278	__out		boolean_t *fatalp)
279{
280	efx_intr_t *eip = &(enp->en_intr);
281	const efx_intr_ops_t *eiop = eip->ei_eiop;
282
283	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
284	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
285
286	eiop->eio_status_message(enp, message, fatalp);
287}
288
289		void
290efx_intr_fatal(
291	__in	efx_nic_t *enp)
292{
293	efx_intr_t *eip = &(enp->en_intr);
294	const efx_intr_ops_t *eiop = eip->ei_eiop;
295
296	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
297	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
298
299	eiop->eio_fatal(enp);
300}
301
302/* ************************************************************************* */
303/* ************************************************************************* */
304/* ************************************************************************* */
305
306#if EFSYS_OPT_SIENA
307
308static	__checkReturn	efx_rc_t
309siena_intr_init(
310	__in		efx_nic_t *enp,
311	__in		efx_intr_type_t type,
312	__in		efsys_mem_t *esmp)
313{
314	efx_intr_t *eip = &(enp->en_intr);
315	efx_oword_t oword;
316	efx_rc_t rc;
317
318	if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_INTR_SIZE)) {
319		rc = EINVAL;
320		goto fail1;
321	}
322
323	/*
324	 * bug17213 workaround.
325	 *
326	 * Under legacy interrupts, don't share a level between fatal
327	 * interrupts and event queue interrupts. Under MSI-X, they
328	 * must share, or we won't get an interrupt.
329	 */
330	if (enp->en_family == EFX_FAMILY_SIENA &&
331	    eip->ei_type == EFX_INTR_LINE)
332		eip->ei_level = 0x1f;
333	else
334		eip->ei_level = 0;
335
336	/* Enable all the genuinely fatal interrupts */
337	EFX_SET_OWORD(oword);
338	EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);
339	EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);
340	EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);
341	if (enp->en_family >= EFX_FAMILY_SIENA)
342		EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);
343	EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);
344
345	/* Set up the interrupt address register */
346	EFX_POPULATE_OWORD_3(oword,
347	    FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,
348	    FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,
349	    FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);
350	EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
351
352	return (0);
353
354fail1:
355	EFSYS_PROBE1(fail1, efx_rc_t, rc);
356
357	return (rc);
358}
359
360static			void
361siena_intr_enable(
362	__in		efx_nic_t *enp)
363{
364	efx_intr_t *eip = &(enp->en_intr);
365	efx_oword_t oword;
366
367	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
368
369	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
370	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);
371	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
372}
373
374static			void
375siena_intr_disable(
376	__in		efx_nic_t *enp)
377{
378	efx_oword_t oword;
379
380	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
381	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
382	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
383
384	EFSYS_SPIN(10);
385}
386
387static			void
388siena_intr_disable_unlocked(
389	__in		efx_nic_t *enp)
390{
391	efx_oword_t oword;
392
393	EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
394			&oword, B_FALSE);
395	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
396	EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
397	    &oword, B_FALSE);
398}
399
400static	__checkReturn	efx_rc_t
401siena_intr_trigger(
402	__in		efx_nic_t *enp,
403	__in		unsigned int level)
404{
405	efx_intr_t *eip = &(enp->en_intr);
406	efx_oword_t oword;
407	unsigned int count;
408	uint32_t sel;
409	efx_rc_t rc;
410
411	/* bug16757: No event queues can be initialized */
412	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
413
414	if (level >= EFX_NINTR_SIENA) {
415		rc = EINVAL;
416		goto fail1;
417	}
418
419	if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))
420		return (ENOTSUP); /* avoid EFSYS_PROBE() */
421
422	sel = level;
423
424	/* Trigger a test interrupt */
425	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
426	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel);
427	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1);
428	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
429
430	/*
431	 * Wait up to 100ms for the interrupt to be raised before restoring
432	 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will
433	 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL
434	 */
435	count = 0;
436	do {
437		EFSYS_SPIN(100);	/* 100us */
438
439		EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
440	} while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000);
441
442	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
443	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
444
445	return (0);
446
447fail1:
448	EFSYS_PROBE1(fail1, efx_rc_t, rc);
449
450	return (rc);
451}
452
453static	__checkReturn	boolean_t
454siena_intr_check_fatal(
455	__in		efx_nic_t *enp)
456{
457	efx_intr_t *eip = &(enp->en_intr);
458	efsys_mem_t *esmp = eip->ei_esmp;
459	efx_oword_t oword;
460
461	/* Read the syndrome */
462	EFSYS_MEM_READO(esmp, 0, &oword);
463
464	if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) {
465		EFSYS_PROBE(fatal);
466
467		/* Clear the fatal interrupt condition */
468		EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0);
469		EFSYS_MEM_WRITEO(esmp, 0, &oword);
470
471		return (B_TRUE);
472	}
473
474	return (B_FALSE);
475}
476
477static			void
478siena_intr_status_line(
479	__in		efx_nic_t *enp,
480	__out		boolean_t *fatalp,
481	__out		uint32_t *qmaskp)
482{
483	efx_intr_t *eip = &(enp->en_intr);
484	efx_dword_t dword;
485
486	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
487	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
488
489	/*
490	 * Read the queue mask and implicitly acknowledge the
491	 * interrupt.
492	 */
493	EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
494	*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
495
496	EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
497
498	if (*qmaskp & (1U << eip->ei_level))
499		*fatalp = siena_intr_check_fatal(enp);
500	else
501		*fatalp = B_FALSE;
502}
503
504static			void
505siena_intr_status_message(
506	__in		efx_nic_t *enp,
507	__in		unsigned int message,
508	__out		boolean_t *fatalp)
509{
510	efx_intr_t *eip = &(enp->en_intr);
511
512	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
513	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
514
515	if (message == eip->ei_level)
516		*fatalp = siena_intr_check_fatal(enp);
517	else
518		*fatalp = B_FALSE;
519}
520
521static		void
522siena_intr_fatal(
523	__in	efx_nic_t *enp)
524{
525#if EFSYS_OPT_DECODE_INTR_FATAL
526	efx_oword_t fatal;
527	efx_oword_t mem_per;
528
529	EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal);
530	EFX_ZERO_OWORD(mem_per);
531
532	if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 ||
533	    EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
534		EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per);
535
536	if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0)
537		EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0);
538
539	if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0)
540		EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0);
541
542	if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
543		EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR,
544		    EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
545		    EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
546
547	if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0)
548		EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0);
549
550	if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0)
551		EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0);
552
553	if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0)
554		EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0);
555
556	if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0)
557		EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0);
558
559	if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0)
560		EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0);
561
562	if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0)
563		EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0);
564
565	if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0)
566		EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0);
567
568	if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0)
569		EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR,
570		    EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
571		    EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
572#else
573	EFSYS_ASSERT(0);
574#endif
575}
576
577static		void
578siena_intr_fini(
579	__in	efx_nic_t *enp)
580{
581	efx_oword_t oword;
582
583	/* Clear the interrupt address register */
584	EFX_ZERO_OWORD(oword);
585	EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
586}
587
588#endif /* EFSYS_OPT_SIENA */
589