1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013-2014 Qlogic Corporation
5 * All rights reserved.
6 *
7 *  Redistribution and use in source and binary forms, with or without
8 *  modification, are permitted provided that the following conditions
9 *  are met:
10 *
11 *  1. Redistributions of source code must retain the above copyright
12 *     notice, this list of conditions and the following disclaimer.
13 *  2. Redistributions in binary form must reproduce the above copyright
14 *     notice, this list of conditions and the following disclaimer in the
15 *     documentation and/or other materials provided with the distribution.
16 *
17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 *  POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32/*
33 * File: qls_def.h
34 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
35 */
36
37#ifndef _QLS_DEF_H_
38#define _QLS_DEF_H_
39
40/*
41 * structure encapsulating a DMA buffer
42 */
43struct qla_dma {
44        bus_size_t              alignment;
45        uint32_t                size;
46        void                    *dma_b;
47        bus_addr_t              dma_addr;
48        bus_dmamap_t            dma_map;
49        bus_dma_tag_t           dma_tag;
50};
51typedef struct qla_dma qla_dma_t;
52
53/*
54 * structure encapsulating interrupt vectors
55 */
56struct qla_ivec {
57	uint32_t		cq_idx;
58	void			*ha;
59	struct resource		*irq;
60	void			*handle;
61	int			irq_rid;
62};
63typedef struct qla_ivec qla_ivec_t;
64
65/*
66 * Transmit Related Definitions
67 */
68
69#define MAX_TX_RINGS		1
70#define NUM_TX_DESCRIPTORS	1024
71
72#define QLA_MAX_SEGMENTS	64	/* maximum # of segs in a sg list */
73#define QLA_OAL_BLK_SIZE	(sizeof (q81_txb_desc_t) * QLA_MAX_SEGMENTS)
74
75#define QLA_TX_OALB_TOTAL_SIZE	(NUM_TX_DESCRIPTORS * QLA_OAL_BLK_SIZE)
76
77#define QLA_TX_PRIVATE_BSIZE	((QLA_TX_OALB_TOTAL_SIZE + \
78					PAGE_SIZE + \
79					(PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
80
81#define QLA_MAX_MTU		9000
82#define QLA_STD_FRAME_SIZE	1514
83#define QLA_MAX_TSO_FRAME_SIZE	((64 * 1024 - 1) + 22)
84
85#define QL_FRAME_HDR_SIZE	(ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
86                sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
87
88struct qla_tx_buf {
89	struct mbuf	*m_head;
90	bus_dmamap_t	map;
91
92	/* The number of entries in the OAL is determined by QLA_MAX_SEGMENTS */
93	bus_addr_t      oal_paddr;
94	void		*oal_vaddr;
95};
96typedef struct qla_tx_buf qla_tx_buf_t;
97
98struct qla_tx_ring {
99	volatile struct {
100		uint32_t	wq_dma:1,
101				privb_dma:1;
102	} flags;
103
104	qla_dma_t		privb_dma;
105	qla_dma_t		wq_dma;
106
107	qla_tx_buf_t		tx_buf[NUM_TX_DESCRIPTORS];
108	uint64_t		count;
109
110	struct resource         *wq_db_addr;
111	uint32_t		wq_db_offset;
112
113	q81_tx_cmd_t		*wq_vaddr;
114	bus_addr_t		wq_paddr;
115
116	void			*wq_icb_vaddr;
117	bus_addr_t		wq_icb_paddr;
118
119	uint32_t		*txr_cons_vaddr;
120	bus_addr_t		txr_cons_paddr;
121
122	volatile uint32_t	txr_free; /* # of free entries in tx ring */
123	volatile uint32_t	txr_next; /* # next available tx ring entry */
124	volatile uint32_t	txr_done;
125
126	uint64_t		tx_frames;
127	uint64_t		tx_tso_frames;
128	uint64_t		tx_vlan_frames;
129};
130typedef struct qla_tx_ring qla_tx_ring_t;
131
132/*
133 * Receive Related Definitions
134 */
135
136#define MAX_RX_RINGS		MAX_TX_RINGS
137
138#define NUM_RX_DESCRIPTORS	1024
139#define NUM_CQ_ENTRIES		NUM_RX_DESCRIPTORS
140
141#define QLA_LGB_SIZE		(12 * 1024)
142#define QLA_NUM_LGB_ENTRIES	32
143
144#define QLA_LBQ_SIZE		(QLA_NUM_LGB_ENTRIES * sizeof(q81_bq_addr_e_t))
145
146#define QLA_LGBQ_AND_TABLE_SIZE	\
147	((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
148
149/* Please note that Small Buffer size is determined by max mtu size */
150#define QLA_NUM_SMB_ENTRIES	NUM_RX_DESCRIPTORS
151
152#define QLA_SBQ_SIZE		(QLA_NUM_SMB_ENTRIES * sizeof(q81_bq_addr_e_t))
153
154#define QLA_SMBQ_AND_TABLE_SIZE	\
155	((QLA_SBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
156
157struct qla_rx_buf {
158	struct mbuf	*m_head;
159	bus_dmamap_t	map;
160	bus_addr_t      paddr;
161	void		*next;
162};
163typedef struct qla_rx_buf qla_rx_buf_t;
164
165struct qla_rx_ring {
166	volatile struct {
167		uint32_t	cq_dma:1,
168				lbq_dma:1,
169				sbq_dma:1,
170				lb_dma:1;
171	} flags;
172
173	qla_dma_t		cq_dma;
174	qla_dma_t		lbq_dma;
175	qla_dma_t		sbq_dma;
176	qla_dma_t		lb_dma;
177
178	struct lro_ctrl		lro;
179
180	qla_rx_buf_t		rx_buf[NUM_RX_DESCRIPTORS];
181	qla_rx_buf_t		*rxb_free;
182	uint32_t		rx_free;
183	uint32_t		rx_next;
184
185	uint32_t		cq_db_offset;
186
187	void			*cq_icb_vaddr;
188	bus_addr_t		cq_icb_paddr;
189
190	uint32_t		*cqi_vaddr;
191	bus_addr_t		cqi_paddr;
192
193	void			*cq_base_vaddr;
194	bus_addr_t		cq_base_paddr;
195	uint32_t		cq_next; /* next cq entry to process */
196
197	void			*lbq_addr_tbl_vaddr;
198	bus_addr_t		lbq_addr_tbl_paddr;
199
200	void			*lbq_vaddr;
201	bus_addr_t		lbq_paddr;
202	uint32_t		lbq_next; /* next entry in LBQ to process */
203	uint32_t		lbq_free;/* # of entries in LBQ to arm */
204	uint32_t		lbq_in; /* next entry in LBQ to arm */
205
206	void			*lb_vaddr;
207	bus_addr_t		lb_paddr;
208
209	void			*sbq_addr_tbl_vaddr;
210	bus_addr_t		sbq_addr_tbl_paddr;
211
212	void			*sbq_vaddr;
213	bus_addr_t		sbq_paddr;
214	uint32_t		sbq_next; /* next entry in SBQ to process */
215	uint32_t		sbq_free;/* # of entries in SBQ to arm */
216	uint32_t		sbq_in; /* next entry in SBQ to arm */
217
218	uint64_t		rx_int;
219	uint64_t		rss_int;
220};
221typedef struct qla_rx_ring qla_rx_ring_t;
222
223#define QLA_WATCHDOG_CALLOUT_TICKS	1
224
225/*
226 * Multicast Definitions
227 */
228typedef struct _qla_mcast {
229	uint16_t	rsrvd;
230	uint8_t		addr[6];
231} __packed qla_mcast_t;
232
233/*
234 * Misc. definitions
235 */
236#define QLA_PAGE_SIZE		4096
237
238/*
239 * Adapter structure contains the hardware independent information of the
240 * pci function.
241 */
242struct qla_host {
243        volatile struct {
244                volatile uint32_t
245			mpi_dma			:1,
246			rss_dma			:1,
247			intr_enable		:1,
248			qla_callout_init	:1,
249			qla_watchdog_active	:1,
250			qla_watchdog_exit	:1,
251			qla_watchdog_pause	:1,
252			lro_init		:1,
253			parent_tag		:1,
254			lock_init		:1;
255        } flags;
256
257	volatile uint32_t	hw_init;
258
259	volatile uint32_t	qla_watchdog_exited;
260	volatile uint32_t	qla_watchdog_paused;
261	volatile uint32_t	qla_initiate_recovery;
262
263	device_t		pci_dev;
264
265	uint8_t			pci_func;
266	uint16_t		watchdog_ticks;
267	uint8_t			resvd;
268
269        /* ioctl related */
270        struct cdev             *ioctl_dev;
271
272	/* register mapping */
273	struct resource		*pci_reg;
274	int			reg_rid;
275
276	struct resource		*pci_reg1;
277	int			reg_rid1;
278
279	int			msix_count;
280	qla_ivec_t              irq_vec[MAX_RX_RINGS];
281
282	/* parent dma tag */
283	bus_dma_tag_t           parent_tag;
284
285	/* interface to o.s */
286	struct ifnet		*ifp;
287
288	struct ifmedia		media;
289	uint16_t		max_frame_size;
290	uint16_t		rsrvd0;
291	uint32_t		msize;
292	int			if_flags;
293
294	/* hardware access lock */
295	struct mtx		hw_lock;
296	volatile uint32_t	hw_lock_held;
297
298	uint32_t		vm_pgsize;
299	/* transmit related */
300	uint32_t		num_tx_rings;
301	qla_tx_ring_t		tx_ring[MAX_TX_RINGS];
302
303	bus_dma_tag_t		tx_tag;
304	struct task		tx_task;
305	struct taskqueue	*tx_tq;
306	struct callout		tx_callout;
307	struct mtx		tx_lock;
308
309	/* receive related */
310	uint32_t		num_rx_rings;
311	qla_rx_ring_t		rx_ring[MAX_RX_RINGS];
312	bus_dma_tag_t		rx_tag;
313
314	/* stats */
315	uint32_t		err_m_getcl;
316	uint32_t		err_m_getjcl;
317	uint32_t		err_tx_dmamap_create;
318	uint32_t		err_tx_dmamap_load;
319	uint32_t		err_tx_defrag;
320
321	/* mac address related */
322	uint8_t			mac_rcv_mode;
323	uint8_t			mac_addr[ETHER_ADDR_LEN];
324	uint32_t		nmcast;
325	qla_mcast_t		mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
326
327	/* Link Related */
328        uint8_t			link_up;
329	uint32_t		link_status;
330	uint32_t		link_down_info;
331	uint32_t		link_hw_info;
332	uint32_t		link_dcbx_counters;
333	uint32_t		link_change_counters;
334
335	/* Flash Related */
336	q81_flash_t		flash;
337
338	/* debug stuff */
339	volatile const char 	*qla_lock;
340	volatile const char	*qla_unlock;
341
342	/* Error Recovery Related */
343	uint32_t		err_inject;
344	struct task		err_task;
345	struct taskqueue	*err_tq;
346
347	/* Chip related */
348	uint32_t		rev_id;
349
350	/* mailbox completions */
351	uint32_t		aen[Q81_NUM_AEN_REGISTERS];
352	uint32_t		mbox[Q81_NUM_MBX_REGISTERS];
353	volatile uint32_t       mbx_done;
354
355	/* mpi dump related */
356	qla_dma_t		mpi_dma;
357	qla_dma_t		rss_dma;
358
359};
360typedef struct qla_host qla_host_t;
361
362/* note that align has to be a power of 2 */
363#define QL_ALIGN(size, align) (((size) + ((align) - 1)) & (~((align) - 1)))
364#define QL_MIN(x, y) ((x < y) ? x : y)
365
366#define QL_RUNNING(ifp) \
367		((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
368			IFF_DRV_RUNNING)
369
370/* Return 0, if identical, else 1 */
371
372#define QL_MAC_CMP(mac1, mac2)    \
373	((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
374	(*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
375
376#endif /* #ifndef _QLS_DEF_H_ */
377