1/*
2 * Copyright (c) 2018-2019 Cavium, Inc.
3 * All rights reserved.
4 *
5 *  Redistribution and use in source and binary forms, with or without
6 *  modification, are permitted provided that the following conditions
7 *  are met:
8 *
9 *  1. Redistributions of source code must retain the above copyright
10 *     notice, this list of conditions and the following disclaimer.
11 *  2. Redistributions in binary form must reproduce the above copyright
12 *     notice, this list of conditions and the following disclaimer in the
13 *     documentation and/or other materials provided with the distribution.
14 *
15 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 *  POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30#ifndef __QLNXR_CM_H__
31#define __QLNXR_CM_H__
32
33/* ECORE LL2 has a limit to the number of buffers it can handle.
34 * FYI, OFED used 512 and 128 for recv and send.
35 */
36#define QLNXR_GSI_MAX_RECV_WR	(4096)
37#define QLNXR_GSI_MAX_SEND_WR	(4096)
38
39#define QLNXR_GSI_MAX_RECV_SGE	(1)	/* LL2 FW limitation */
40
41/* future OFED/kernel will have these */
42#define ETH_P_ROCE		(0x8915)
43#define QLNXR_ROCE_V2_UDP_SPORT	(0000)
44
45#if __FreeBSD_version >= 1102000
46
47#define rdma_wr(_wr) rdma_wr(_wr)
48#define ud_wr(_wr) ud_wr(_wr)
49#define atomic_wr(_wr) atomic_wr(_wr)
50
51#else
52
53#define rdma_wr(_wr) (&(_wr->wr.rdma))
54#define ud_wr(_wr) (&(_wr->wr.ud))
55#define atomic_wr(_wr) (&(_wr->wr.atomic))
56
57#endif /* #if __FreeBSD_version >= 1102000 */
58
59static inline u32 qlnxr_get_ipv4_from_gid(u8 *gid)
60{
61	return *(u32 *)(void *)&gid[12];
62}
63
64struct ecore_roce_ll2_header {
65        void *vaddr;
66        dma_addr_t baddr;
67        size_t len;
68};
69
70struct ecore_roce_ll2_buffer {
71        dma_addr_t baddr;
72        size_t len;
73};
74
75struct ecore_roce_ll2_packet {
76        struct ecore_roce_ll2_header header;
77        int n_seg;
78        struct ecore_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
79        int roce_mode;
80        enum ecore_roce_ll2_tx_dest tx_dest;
81};
82
83/* RDMA CM */
84
85extern int qlnxr_gsi_poll_cq(struct ib_cq *ibcq,
86			int num_entries,
87			struct ib_wc *wc);
88
89extern int qlnxr_gsi_post_recv(struct ib_qp *ibqp,
90			struct ib_recv_wr *wr,
91			struct ib_recv_wr **bad_wr);
92
93extern int qlnxr_gsi_post_send(struct ib_qp *ibqp,
94			struct ib_send_wr *wr,
95			struct ib_send_wr **bad_wr);
96
97extern struct ib_qp* qlnxr_create_gsi_qp(struct qlnxr_dev *dev,
98			struct ib_qp_init_attr *attrs,
99			struct qlnxr_qp *qp);
100
101extern void qlnxr_store_gsi_qp_cq(struct qlnxr_dev *dev,
102			struct qlnxr_qp *qp,
103			struct ib_qp_init_attr *attrs);
104
105extern void qlnxr_inc_sw_gsi_cons(struct qlnxr_qp_hwq_info *info);
106
107extern int qlnxr_destroy_gsi_qp(struct qlnxr_dev *dev);
108
109#endif /* #ifndef __QLNXR_CM_H__ */
110