1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31#ifndef _QLNX_IOCTL_H_ 32#define _QLNX_IOCTL_H_ 33 34#include <sys/ioccom.h> 35 36#define QLNX_MAX_HW_FUNCS 2 37 38/* 39 * Read grcdump and grcdump size 40 */ 41 42struct qlnx_grcdump { 43 uint16_t pci_func; 44 uint32_t grcdump_size[QLNX_MAX_HW_FUNCS]; 45 void *grcdump[QLNX_MAX_HW_FUNCS]; 46 uint32_t grcdump_dwords[QLNX_MAX_HW_FUNCS]; 47}; 48typedef struct qlnx_grcdump qlnx_grcdump_t; 49 50/* 51 * Read idle_chk and idle_chk size 52 */ 53struct qlnx_idle_chk { 54 uint16_t pci_func; 55 uint32_t idle_chk_size[QLNX_MAX_HW_FUNCS]; 56 void *idle_chk[QLNX_MAX_HW_FUNCS]; 57 uint32_t idle_chk_dwords[QLNX_MAX_HW_FUNCS]; 58}; 59typedef struct qlnx_idle_chk qlnx_idle_chk_t; 60 61/* 62 * Retrive traces 63 */ 64struct qlnx_trace { 65 uint16_t pci_func; 66 67 uint16_t cmd; 68#define QLNX_MCP_TRACE 0x01 69#define QLNX_REG_FIFO 0x02 70#define QLNX_IGU_FIFO 0x03 71#define QLNX_PROTECTION_OVERRIDE 0x04 72#define QLNX_FW_ASSERTS 0x05 73 74 uint32_t size[QLNX_MAX_HW_FUNCS]; 75 void *buffer[QLNX_MAX_HW_FUNCS]; 76 uint32_t dwords[QLNX_MAX_HW_FUNCS]; 77}; 78typedef struct qlnx_trace qlnx_trace_t; 79 80/* 81 * Read driver info 82 */ 83#define QLNX_DRV_INFO_NAME_LENGTH 32 84#define QLNX_DRV_INFO_VERSION_LENGTH 32 85#define QLNX_DRV_INFO_MFW_VERSION_LENGTH 32 86#define QLNX_DRV_INFO_STORMFW_VERSION_LENGTH 32 87#define QLNX_DRV_INFO_BUS_INFO_LENGTH 32 88 89struct qlnx_drvinfo { 90 char drv_name[QLNX_DRV_INFO_NAME_LENGTH]; 91 char drv_version[QLNX_DRV_INFO_VERSION_LENGTH]; 92 char mfw_version[QLNX_DRV_INFO_MFW_VERSION_LENGTH]; 93 char stormfw_version[QLNX_DRV_INFO_STORMFW_VERSION_LENGTH]; 94 uint32_t eeprom_dump_len; /* in bytes */ 95 uint32_t reg_dump_len; /* in bytes */ 96 char bus_info[QLNX_DRV_INFO_BUS_INFO_LENGTH]; 97}; 98typedef struct qlnx_drvinfo qlnx_drvinfo_t; 99 100/* 101 * Read Device Setting 102 */ 103struct qlnx_dev_setting { 104 uint32_t supported; /* Features this interface supports */ 105 uint32_t advertising; /* Features this interface advertises */ 106 uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 107 uint32_t duplex; /* Duplex, half or full */ 108 uint32_t port; /* Which connector port */ 109 uint32_t phy_address; /* port number*/ 110 uint32_t autoneg; /* Enable or disable autonegotiation */ 111}; 112typedef struct qlnx_dev_setting qlnx_dev_setting_t; 113 114/* 115 * Get Registers 116 */ 117struct qlnx_get_regs { 118 void *reg_buf; 119 uint32_t reg_buf_len; 120}; 121typedef struct qlnx_get_regs qlnx_get_regs_t; 122 123/* 124 * Get/Set NVRAM 125 */ 126struct qlnx_nvram { 127 uint32_t cmd; 128#define QLNX_NVRAM_CMD_WRITE_NVRAM 0x01 129#define QLNX_NVRAM_CMD_READ_NVRAM 0x02 130#define QLNX_NVRAM_CMD_SET_SECURE_MODE 0x03 131#define QLNX_NVRAM_CMD_DEL_FILE 0x04 132#define QLNX_NVRAM_CMD_PUT_FILE_BEGIN 0x05 133#define QLNX_NVRAM_CMD_GET_NVRAM_RESP 0x06 134#define QLNX_NVRAM_CMD_PUT_FILE_DATA 0x07 135 136 void *data; 137 uint32_t offset; 138 uint32_t data_len; 139 uint32_t magic; 140}; 141typedef struct qlnx_nvram qlnx_nvram_t; 142 143/* 144 * Get/Set Device registers 145 */ 146struct qlnx_reg_rd_wr { 147 uint32_t cmd; 148#define QLNX_REG_READ_CMD 0x01 149#define QLNX_REG_WRITE_CMD 0x02 150 151 uint32_t addr; 152 uint32_t val; 153 154 uint32_t access_type; 155#define QLNX_REG_ACCESS_DIRECT 0x01 156#define QLNX_REG_ACCESS_INDIRECT 0x02 157 158 uint32_t hwfn_index; 159}; 160typedef struct qlnx_reg_rd_wr qlnx_reg_rd_wr_t; 161 162/* 163 * Read/Write PCI Configuration 164 */ 165struct qlnx_pcicfg_rd_wr { 166 uint32_t cmd; 167#define QLNX_PCICFG_READ 0x01 168#define QLNX_PCICFG_WRITE 0x02 169 uint32_t reg; 170 uint32_t val; 171 uint32_t width; 172}; 173typedef struct qlnx_pcicfg_rd_wr qlnx_pcicfg_rd_wr_t; 174 175/* 176 * Read MAC address 177 */ 178struct qlnx_perm_mac_addr { 179 char addr[32]; 180}; 181typedef struct qlnx_perm_mac_addr qlnx_perm_mac_addr_t; 182 183/* 184 * Read STORM statistics registers 185 */ 186struct qlnx_storm_stats { 187 /* xstorm */ 188 uint32_t xstorm_active_cycles; 189 uint32_t xstorm_stall_cycles; 190 uint32_t xstorm_sleeping_cycles; 191 uint32_t xstorm_inactive_cycles; 192 193 /* ystorm */ 194 uint32_t ystorm_active_cycles; 195 uint32_t ystorm_stall_cycles; 196 uint32_t ystorm_sleeping_cycles; 197 uint32_t ystorm_inactive_cycles; 198 199 /* pstorm */ 200 uint32_t pstorm_active_cycles; 201 uint32_t pstorm_stall_cycles; 202 uint32_t pstorm_sleeping_cycles; 203 uint32_t pstorm_inactive_cycles; 204 205 /* tstorm */ 206 uint32_t tstorm_active_cycles; 207 uint32_t tstorm_stall_cycles; 208 uint32_t tstorm_sleeping_cycles; 209 uint32_t tstorm_inactive_cycles; 210 211 /* mstorm */ 212 uint32_t mstorm_active_cycles; 213 uint32_t mstorm_stall_cycles; 214 uint32_t mstorm_sleeping_cycles; 215 uint32_t mstorm_inactive_cycles; 216 217 /* ustorm */ 218 uint32_t ustorm_active_cycles; 219 uint32_t ustorm_stall_cycles; 220 uint32_t ustorm_sleeping_cycles; 221 uint32_t ustorm_inactive_cycles; 222}; 223 224typedef struct qlnx_storm_stats qlnx_storm_stats_t; 225 226#define QLNX_STORM_STATS_SAMPLES_PER_HWFN (10000) 227 228#define QLNX_STORM_STATS_BYTES_PER_HWFN (sizeof(qlnx_storm_stats_t) * \ 229 QLNX_STORM_STATS_SAMPLES_PER_HWFN) 230 231struct qlnx_storm_stats_dump { 232 int num_hwfns; 233 int num_samples; 234 void *buffer[QLNX_MAX_HW_FUNCS]; 235}; 236 237typedef struct qlnx_storm_stats_dump qlnx_storm_stats_dump_t; 238 239#define QLNX_LLDP_TYPE_END_OF_LLDPDU 0 240#define QLNX_LLDP_TYPE_CHASSIS_ID 1 241#define QLNX_LLDP_TYPE_PORT_ID 2 242#define QLNX_LLDP_TYPE_TTL 3 243#define QLNX_LLDP_TYPE_PORT_DESC 4 244#define QLNX_LLDP_TYPE_SYS_NAME 5 245#define QLNX_LLDP_TYPE_SYS_DESC 6 246#define QLNX_LLDP_TYPE_SYS_CAPS 7 247#define QLNX_LLDP_TYPE_MGMT_ADDR 8 248#define QLNX_LLDP_TYPE_ORG_SPECIFIC 127 249 250#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 251#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_MAC 0x04 //Mac Address 252#define QLNX_LLDP_CHASSIS_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 253#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_IF_NAME 0x06 //Interface Name 254 255#define QLNX_LLDP_PORT_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 256#define QLNX_LLDP_PORT_ID_SUBTYPE_MAC 0x03 //Mac Address 257#define QLNX_LLDP_PORT_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 258#define QLNX_LLDP_PORT_ID_SUBTYPE_IF_NAME 0x05 //Interface Name 259 260#define QLNX_LLDP_SYS_TLV_SIZE 256 261struct qlnx_lldp_sys_tlvs { 262 int discard_mandatory_tlv; 263 uint8_t buf[QLNX_LLDP_SYS_TLV_SIZE]; 264 uint16_t buf_size; 265}; 266typedef struct qlnx_lldp_sys_tlvs qlnx_lldp_sys_tlvs_t; 267 268/* 269 * Read grcdump size 270 */ 271#define QLNX_GRC_DUMP_SIZE _IOWR('q', 1, qlnx_grcdump_t) 272 273/* 274 * Read grcdump 275 */ 276#define QLNX_GRC_DUMP _IOWR('q', 2, qlnx_grcdump_t) 277 278/* 279 * Read idle_chk size 280 */ 281#define QLNX_IDLE_CHK_SIZE _IOWR('q', 3, qlnx_idle_chk_t) 282 283/* 284 * Read idle_chk 285 */ 286#define QLNX_IDLE_CHK _IOWR('q', 4, qlnx_idle_chk_t) 287 288/* 289 * Read driver info 290 */ 291#define QLNX_DRV_INFO _IOWR('q', 5, qlnx_drvinfo_t) 292 293/* 294 * Read Device Setting 295 */ 296#define QLNX_DEV_SETTING _IOR('q', 6, qlnx_dev_setting_t) 297 298/* 299 * Get Registers 300 */ 301#define QLNX_GET_REGS _IOR('q', 7, qlnx_get_regs_t) 302 303/* 304 * Get/Set NVRAM 305 */ 306#define QLNX_NVRAM _IOWR('q', 8, qlnx_nvram_t) 307 308/* 309 * Get/Set Device registers 310 */ 311#define QLNX_RD_WR_REG _IOWR('q', 9, qlnx_reg_rd_wr_t) 312 313/* 314 * Read/Write PCI Configuration 315 */ 316#define QLNX_RD_WR_PCICFG _IOWR('q', 10, qlnx_pcicfg_rd_wr_t) 317 318/* 319 * Read MAC address 320 */ 321#define QLNX_MAC_ADDR _IOWR('q', 11, qlnx_perm_mac_addr_t) 322 323/* 324 * Read STORM statistics 325 */ 326#define QLNX_STORM_STATS _IOWR('q', 12, qlnx_storm_stats_dump_t) 327 328/* 329 * Read trace size 330 */ 331#define QLNX_TRACE_SIZE _IOWR('q', 13, qlnx_trace_t) 332 333/* 334 * Read trace 335 */ 336#define QLNX_TRACE _IOWR('q', 14, qlnx_trace_t) 337 338/* 339 * Set LLDP TLVS 340 */ 341#define QLNX_SET_LLDP_TLVS _IOWR('q', 15, qlnx_lldp_sys_tlvs_t) 342 343#endif /* #ifndef _QLNX_IOCTL_H_ */ 344