1/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */ 2/* $NetBSD: qat_c2xxxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */ 3 4/* 5 * Copyright (c) 2019 Internet Initiative Japan, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * Copyright(c) 2007-2013 Intel Corporation. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 37 * * Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * * Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in 41 * the documentation and/or other materials provided with the 42 * distribution. 43 * * Neither the name of Intel Corporation nor the names of its 44 * contributors may be used to endorse or promote products derived 45 * from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 48 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 49 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 50 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 51 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 53 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60/* $FreeBSD$ */ 61 62#ifndef _DEV_PCI_QAT_C2XXXREG_H_ 63#define _DEV_PCI_QAT_C2XXXREG_H_ 64 65/* PCI revision IDs */ 66#define QAT_REVID_C2XXX_A0 0x00 67#define QAT_REVID_C2XXX_B0 0x02 68#define QAT_REVID_C2XXX_C0 0x03 69 70/* Max number of accelerators and engines */ 71#define MAX_ACCEL_C2XXX 1 72#define MAX_AE_C2XXX 2 73 74/* PCIe BAR index */ 75#define BAR_SRAM_ID_C2XXX NO_PCI_REG 76#define BAR_PMISC_ID_C2XXX 0 77#define BAR_ETR_ID_C2XXX 1 78 79#define ACCEL_MASK_C2XXX 0x1 80#define AE_MASK_C2XXX 0x3 81 82#define MSIX_AE_VEC_GAP_C2XXX 8 83 84/* PCIe configuration space registers */ 85/* PESRAM: 512K eSRAM */ 86#define BAR_PESRAM_C2XXX NO_PCI_REG 87#define BAR_PESRAM_SIZE_C2XXX 0 88 89/* 90 * PMISC: 16K CAP, 16K Scratch, 32K SSU(QATs), 91 * 32K AE CSRs and transfer registers, 8K CHAP/PMU, 92 * 4K EP CSRs, 4K MSI-X Tables 93 */ 94#define BAR_PMISC_C2XXX 0x18 95#define BAR_PMISC_SIZE_C2XXX 0x20000 /* 128K */ 96 97/* PETRINGCSR: 8K 16 bundles of ET Ring CSRs */ 98#define BAR_PETRINGCSR_C2XXX 0x20 99#define BAR_PETRINGCSR_SIZE_C2XXX 0x4000 /* 16K */ 100 101/* Fuse Control */ 102#define FUSECTL_C2XXX_PKE_DISABLE (1 << 6) 103#define FUSECTL_C2XXX_ATH_DISABLE (1 << 5) 104#define FUSECTL_C2XXX_CPH_DISABLE (1 << 4) 105#define FUSECTL_C2XXX_LOW_SKU (1 << 3) 106#define FUSECTL_C2XXX_MID_SKU (1 << 2) 107#define FUSECTL_C2XXX_AE1_DISABLE (1 << 1) 108 109/* SINT: Signal Target Raw Interrupt Register */ 110#define EP_SINTPF_C2XXX 0x1A024 111 112/* SMIA: Signal Target IA Mask Register */ 113#define EP_SMIA_C2XXX 0x1A028 114#define EP_SMIA_BUNDLES_IRQ_MASK_C2XXX 0xFF 115#define EP_SMIA_AE_IRQ_MASK_C2XXX 0x10000 116#define EP_SMIA_MASK_C2XXX \ 117 (EP_SMIA_BUNDLES_IRQ_MASK_C2XXX | EP_SMIA_AE_IRQ_MASK_C2XXX) 118 119#define EP_RIMISCCTL_C2XXX 0x1A0C4 120#define EP_RIMISCCTL_MASK_C2XXX 0x40000000 121 122#define PFCGCIOSFPRIR_REG_C2XXX 0x2C0 123#define PFCGCIOSFPRIR_MASK_C2XXX 0XFFFF7FFF 124 125/* BAR sub-regions */ 126#define PESRAM_BAR_C2XXX NO_PCI_REG 127#define PESRAM_OFFSET_C2XXX 0x0 128#define PESRAM_SIZE_C2XXX 0x0 129#define CAP_GLOBAL_BAR_C2XXX BAR_PMISC_C2XXX 130#define CAP_GLOBAL_OFFSET_C2XXX 0x00000 131#define CAP_GLOBAL_SIZE_C2XXX 0x04000 132#define CAP_HASH_OFFSET 0x900 133#define SCRATCH_BAR_C2XXX NO_PCI_REG 134#define SCRATCH_OFFSET_C2XXX NO_REG_OFFSET 135#define SCRATCH_SIZE_C2XXX 0x0 136#define SSU_BAR_C2XXX BAR_PMISC_C2XXX 137#define SSU_OFFSET_C2XXX 0x08000 138#define SSU_SIZE_C2XXX 0x08000 139#define AE_BAR_C2XXX BAR_PMISC_C2XXX 140#define AE_OFFSET_C2XXX 0x10000 141#define AE_LOCAL_OFFSET_C2XXX 0x10800 142#define PMU_BAR_C2XXX NO_PCI_REG 143#define PMU_OFFSET_C2XXX NO_REG_OFFSET 144#define PMU_SIZE_C2XXX 0x0 145#define EP_BAR_C2XXX BAR_PMISC_C2XXX 146#define EP_OFFSET_C2XXX 0x1A000 147#define EP_SIZE_C2XXX 0x01000 148#define MSIX_TAB_BAR_C2XXX NO_PCI_REG /* mapped by pci(9) */ 149#define MSIX_TAB_OFFSET_C2XXX 0x1B000 150#define MSIX_TAB_SIZE_C2XXX 0x01000 151#define PETRINGCSR_BAR_C2XXX BAR_PETRINGCSR_C2XXX 152#define PETRINGCSR_OFFSET_C2XXX 0x0 153#define PETRINGCSR_SIZE_C2XXX 0x0 /* use size of BAR */ 154 155/* ETR */ 156#define ETR_MAX_BANKS_C2XXX 8 157#define ETR_MAX_ET_RINGS_C2XXX \ 158 (ETR_MAX_BANKS_C2XXX * ETR_MAX_RINGS_PER_BANK_C2XXX) 159#define ETR_MAX_AP_BANKS_C2XXX 4 160 161#define ETR_TX_RX_GAP_C2XXX 1 162#define ETR_TX_RINGS_MASK_C2XXX 0x51 163 164#define ETR_BUNDLE_SIZE_C2XXX 0x0200 165 166/* Initial bank Interrupt Source mask */ 167#define ETR_INT_SRCSEL_MASK_0_C2XXX 0x4444444CUL 168#define ETR_INT_SRCSEL_MASK_X_C2XXX 0x44444444UL 169 170/* AE firmware */ 171#define AE_FW_PROD_TYPE_C2XXX 0x00800000 172#define AE_FW_MOF_NAME_C2XXX "qat_c2xxxfw" 173#define AE_FW_MMP_NAME_C2XXX "mmp_firmware_c2xxx" 174#define AE_FW_UOF_NAME_C2XXX_A0 "icp_qat_nae.uof" 175#define AE_FW_UOF_NAME_C2XXX_B0 "icp_qat_nae_b0.uof" 176 177#endif 178