1/* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include "opt_platform.h" 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/endian.h> 35#include <sys/mbuf.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/socket.h> 41#include <sys/sysctl.h> 42#include <sys/smp.h> 43#include <sys/taskqueue.h> 44#ifdef MVNETA_KTR 45#include <sys/ktr.h> 46#endif 47 48#include <net/ethernet.h> 49#include <net/bpf.h> 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in_systm.h> 58#include <netinet/in.h> 59#include <netinet/ip.h> 60#include <netinet/tcp_lro.h> 61 62#include <sys/sockio.h> 63#include <sys/bus.h> 64#include <machine/bus.h> 65#include <sys/rman.h> 66#include <machine/resource.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70 71#include <dev/ofw/openfirm.h> 72#include <dev/ofw/ofw_bus.h> 73#include <dev/ofw/ofw_bus_subr.h> 74 75#include <dev/mdio/mdio.h> 76 77#include <arm/mv/mvvar.h> 78 79#if !defined(__aarch64__) 80#include <arm/mv/mvreg.h> 81#include <arm/mv/mvwin.h> 82#endif 83 84#include "if_mvnetareg.h" 85#include "if_mvnetavar.h" 86 87#include "miibus_if.h" 88#include "mdio_if.h" 89 90#ifdef MVNETA_DEBUG 91#define STATIC /* nothing */ 92#else 93#define STATIC static 94#endif 95 96#define DASSERT(x) KASSERT((x), (#x)) 97 98#define A3700_TCLK_250MHZ 250000000 99 100/* Device Register Initialization */ 101STATIC int mvneta_initreg(struct ifnet *); 102 103/* Descriptor Ring Control for each of queues */ 104STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 105STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 106STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 107STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 108STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 109STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 110STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 111STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 112STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113STATIC int mvneta_dma_create(struct mvneta_softc *); 114 115/* Rx/Tx Queue Control */ 116STATIC int mvneta_rx_queue_init(struct ifnet *, int); 117STATIC int mvneta_tx_queue_init(struct ifnet *, int); 118STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 119STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 120STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 121STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 122STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 123STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 124 125/* Interrupt Handlers */ 126STATIC void mvneta_disable_intr(struct mvneta_softc *); 127STATIC void mvneta_enable_intr(struct mvneta_softc *); 128STATIC void mvneta_rxtxth_intr(void *); 129STATIC int mvneta_misc_intr(struct mvneta_softc *); 130STATIC void mvneta_tick(void *); 131/* struct ifnet and mii callbacks*/ 132STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 133STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 134#ifdef MVNETA_MULTIQUEUE 135STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 136#else /* !MVNETA_MULTIQUEUE */ 137STATIC void mvneta_start(struct ifnet *); 138#endif 139STATIC void mvneta_qflush(struct ifnet *); 140STATIC void mvneta_tx_task(void *, int); 141STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 142STATIC void mvneta_init(void *); 143STATIC void mvneta_init_locked(void *); 144STATIC void mvneta_stop(struct mvneta_softc *); 145STATIC void mvneta_stop_locked(struct mvneta_softc *); 146STATIC int mvneta_mediachange(struct ifnet *); 147STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 148STATIC void mvneta_portup(struct mvneta_softc *); 149STATIC void mvneta_portdown(struct mvneta_softc *); 150 151/* Link State Notify */ 152STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 153STATIC int mvneta_update_media(struct mvneta_softc *, int); 154STATIC void mvneta_adjust_link(struct mvneta_softc *); 155STATIC void mvneta_update_eee(struct mvneta_softc *); 156STATIC void mvneta_update_fc(struct mvneta_softc *); 157STATIC void mvneta_link_isr(struct mvneta_softc *); 158STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 159STATIC void mvneta_linkup(struct mvneta_softc *); 160STATIC void mvneta_linkdown(struct mvneta_softc *); 161STATIC void mvneta_linkreset(struct mvneta_softc *); 162 163/* Tx Subroutines */ 164STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 165STATIC void mvneta_tx_set_csumflag(struct ifnet *, 166 struct mvneta_tx_desc *, struct mbuf *); 167STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 168STATIC void mvneta_tx_drain(struct mvneta_softc *); 169 170/* Rx Subroutines */ 171STATIC int mvneta_rx(struct mvneta_softc *, int, int); 172STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 173STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 174STATIC void mvneta_rx_set_csumflag(struct ifnet *, 175 struct mvneta_rx_desc *, struct mbuf *); 176STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 177 178/* MAC address filter */ 179STATIC void mvneta_filter_setup(struct mvneta_softc *); 180 181/* sysctl(9) */ 182STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 183STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 184STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 185STATIC void sysctl_mvneta_init(struct mvneta_softc *); 186 187/* MIB */ 188STATIC void mvneta_clear_mib(struct mvneta_softc *); 189STATIC uint64_t mvneta_read_mib(struct mvneta_softc *, int); 190STATIC void mvneta_update_mib(struct mvneta_softc *); 191 192/* Switch */ 193STATIC boolean_t mvneta_find_ethernet_prop_switch(phandle_t, phandle_t); 194STATIC boolean_t mvneta_has_switch(device_t); 195 196#define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 197#define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 198 199STATIC struct mtx mii_mutex; 200STATIC int mii_init = 0; 201 202/* Device */ 203STATIC int mvneta_detach(device_t); 204/* MII */ 205STATIC int mvneta_miibus_readreg(device_t, int, int); 206STATIC int mvneta_miibus_writereg(device_t, int, int, int); 207 208/* Clock */ 209STATIC uint32_t mvneta_get_clk(void); 210 211static device_method_t mvneta_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_detach, mvneta_detach), 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 216 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 217 /* MDIO interface */ 218 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 219 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 220 221 /* End */ 222 DEVMETHOD_END 223}; 224 225DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 226 227DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 228DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 229MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 230MODULE_DEPEND(mvneta, ether, 1, 1, 1); 231MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 232MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 233 234/* 235 * List of MIB register and names 236 */ 237enum mvneta_mib_idx 238{ 239 MVNETA_MIB_RX_GOOD_OCT_IDX, 240 MVNETA_MIB_RX_BAD_OCT_IDX, 241 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 242 MVNETA_MIB_RX_GOOD_FRAME_IDX, 243 MVNETA_MIB_RX_BAD_FRAME_IDX, 244 MVNETA_MIB_RX_BCAST_FRAME_IDX, 245 MVNETA_MIB_RX_MCAST_FRAME_IDX, 246 MVNETA_MIB_RX_FRAME64_OCT_IDX, 247 MVNETA_MIB_RX_FRAME127_OCT_IDX, 248 MVNETA_MIB_RX_FRAME255_OCT_IDX, 249 MVNETA_MIB_RX_FRAME511_OCT_IDX, 250 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 251 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 252 MVNETA_MIB_TX_GOOD_OCT_IDX, 253 MVNETA_MIB_TX_GOOD_FRAME_IDX, 254 MVNETA_MIB_TX_EXCES_COL_IDX, 255 MVNETA_MIB_TX_MCAST_FRAME_IDX, 256 MVNETA_MIB_TX_BCAST_FRAME_IDX, 257 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 258 MVNETA_MIB_FC_SENT_IDX, 259 MVNETA_MIB_FC_GOOD_IDX, 260 MVNETA_MIB_FC_BAD_IDX, 261 MVNETA_MIB_PKT_UNDERSIZE_IDX, 262 MVNETA_MIB_PKT_FRAGMENT_IDX, 263 MVNETA_MIB_PKT_OVERSIZE_IDX, 264 MVNETA_MIB_PKT_JABBER_IDX, 265 MVNETA_MIB_MAC_RX_ERR_IDX, 266 MVNETA_MIB_MAC_CRC_ERR_IDX, 267 MVNETA_MIB_MAC_COL_IDX, 268 MVNETA_MIB_MAC_LATE_COL_IDX, 269}; 270 271STATIC struct mvneta_mib_def { 272 uint32_t regnum; 273 int reg64; 274 const char *sysctl_name; 275 const char *desc; 276} mvneta_mib_list[] = { 277 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 278 "rx_good_oct", "Good Octets Rx"}, 279 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 280 "rx_bad_oct", "Bad Octets Rx"}, 281 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 282 "tx_mac_err", "MAC Transmit Error"}, 283 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 284 "rx_good_frame", "Good Frames Rx"}, 285 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 286 "rx_bad_frame", "Bad Frames Rx"}, 287 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 288 "rx_bcast_frame", "Broadcast Frames Rx"}, 289 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 290 "rx_mcast_frame", "Multicast Frames Rx"}, 291 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 292 "rx_frame_1_64", "Frame Size 1 - 64"}, 293 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 294 "rx_frame_65_127", "Frame Size 65 - 127"}, 295 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 296 "rx_frame_128_255", "Frame Size 128 - 255"}, 297 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 298 "rx_frame_256_511", "Frame Size 256 - 511"}, 299 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 300 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 301 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 302 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 303 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 304 "tx_good_oct", "Good Octets Tx"}, 305 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 306 "tx_good_frame", "Good Frames Tx"}, 307 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 308 "tx_exces_collision", "Excessive Collision"}, 309 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 310 "tx_mcast_frame", "Multicast Frames Tx"}, 311 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 312 "tx_bcast_frame", "Broadcast Frames Tx"}, 313 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 314 "tx_mac_ctl_err", "Unknown MAC Control"}, 315 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 316 "fc_tx", "Flow Control Tx"}, 317 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 318 "fc_rx_good", "Good Flow Control Rx"}, 319 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 320 "fc_rx_bad", "Bad Flow Control Rx"}, 321 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 322 "pkt_undersize", "Undersized Packets Rx"}, 323 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 324 "pkt_fragment", "Fragmented Packets Rx"}, 325 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 326 "pkt_oversize", "Oversized Packets Rx"}, 327 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 328 "pkt_jabber", "Jabber Packets Rx"}, 329 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 330 "mac_rx_err", "MAC Rx Errors"}, 331 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 332 "mac_crc_err", "MAC CRC Errors"}, 333 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 334 "mac_collision", "MAC Collision"}, 335 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 336 "mac_late_collision", "MAC Late Collision"}, 337}; 338 339static struct resource_spec res_spec[] = { 340 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 341 { SYS_RES_IRQ, 0, RF_ACTIVE }, 342 { -1, 0} 343}; 344 345static struct { 346 driver_intr_t *handler; 347 char * description; 348} mvneta_intrs[] = { 349 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 350}; 351 352STATIC uint32_t 353mvneta_get_clk() 354{ 355#if defined(__aarch64__) 356 return (A3700_TCLK_250MHZ); 357#else 358 return (get_tclk()); 359#endif 360} 361 362static int 363mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 364{ 365 unsigned int mac_h; 366 unsigned int mac_l; 367 368 mac_l = (addr[4] << 8) | (addr[5]); 369 mac_h = (addr[0] << 24) | (addr[1] << 16) | 370 (addr[2] << 8) | (addr[3] << 0); 371 372 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 373 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 374 return (0); 375} 376 377static int 378mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 379{ 380 uint32_t mac_l, mac_h; 381 382#ifdef FDT 383 if (mvneta_fdt_mac_address(sc, addr) == 0) 384 return (0); 385#endif 386 /* 387 * Fall back -- use the currently programmed address. 388 */ 389 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 390 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 391 if (mac_l == 0 && mac_h == 0) { 392 /* 393 * Generate pseudo-random MAC. 394 * Set lower part to random number | unit number. 395 */ 396 mac_l = arc4random() & ~0xff; 397 mac_l |= device_get_unit(sc->dev) & 0xff; 398 mac_h = arc4random(); 399 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 400 if (bootverbose) { 401 device_printf(sc->dev, 402 "Could not acquire MAC address. " 403 "Using randomized one.\n"); 404 } 405 } 406 407 addr[0] = (mac_h & 0xff000000) >> 24; 408 addr[1] = (mac_h & 0x00ff0000) >> 16; 409 addr[2] = (mac_h & 0x0000ff00) >> 8; 410 addr[3] = (mac_h & 0x000000ff); 411 addr[4] = (mac_l & 0x0000ff00) >> 8; 412 addr[5] = (mac_l & 0x000000ff); 413 return (0); 414} 415 416STATIC boolean_t 417mvneta_find_ethernet_prop_switch(phandle_t ethernet, phandle_t node) 418{ 419 boolean_t ret; 420 phandle_t child, switch_eth_handle, switch_eth; 421 422 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 423 if (OF_getencprop(child, "ethernet", (void*)&switch_eth_handle, 424 sizeof(switch_eth_handle)) > 0) { 425 if (switch_eth_handle > 0) { 426 switch_eth = OF_node_from_xref( 427 switch_eth_handle); 428 429 if (switch_eth == ethernet) 430 return (true); 431 } 432 } 433 434 ret = mvneta_find_ethernet_prop_switch(ethernet, child); 435 if (ret != 0) 436 return (ret); 437 } 438 439 return (false); 440} 441 442STATIC boolean_t 443mvneta_has_switch(device_t self) 444{ 445 phandle_t node; 446 447 node = ofw_bus_get_node(self); 448 449 return mvneta_find_ethernet_prop_switch(node, OF_finddevice("/")); 450} 451 452STATIC int 453mvneta_dma_create(struct mvneta_softc *sc) 454{ 455 size_t maxsize, maxsegsz; 456 size_t q; 457 int error; 458 459 /* 460 * Create Tx DMA 461 */ 462 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 463 464 error = bus_dma_tag_create( 465 bus_get_dma_tag(sc->dev), /* parent */ 466 16, 0, /* alignment, boundary */ 467 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 468 BUS_SPACE_MAXADDR, /* highaddr */ 469 NULL, NULL, /* filtfunc, filtfuncarg */ 470 maxsize, /* maxsize */ 471 1, /* nsegments */ 472 maxsegsz, /* maxsegsz */ 473 0, /* flags */ 474 NULL, NULL, /* lockfunc, lockfuncarg */ 475 &sc->tx_dtag); /* dmat */ 476 if (error != 0) { 477 device_printf(sc->dev, 478 "Failed to create DMA tag for Tx descriptors.\n"); 479 goto fail; 480 } 481 error = bus_dma_tag_create( 482 bus_get_dma_tag(sc->dev), /* parent */ 483 1, 0, /* alignment, boundary */ 484 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 485 BUS_SPACE_MAXADDR, /* highaddr */ 486 NULL, NULL, /* filtfunc, filtfuncarg */ 487 MVNETA_MAX_FRAME, /* maxsize */ 488 MVNETA_TX_SEGLIMIT, /* nsegments */ 489 MVNETA_MAX_FRAME, /* maxsegsz */ 490 BUS_DMA_ALLOCNOW, /* flags */ 491 NULL, NULL, /* lockfunc, lockfuncarg */ 492 &sc->txmbuf_dtag); 493 if (error != 0) { 494 device_printf(sc->dev, 495 "Failed to create DMA tag for Tx mbufs.\n"); 496 goto fail; 497 } 498 499 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 500 error = mvneta_ring_alloc_tx_queue(sc, q); 501 if (error != 0) { 502 device_printf(sc->dev, 503 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 504 goto fail; 505 } 506 } 507 508 /* 509 * Create Rx DMA. 510 */ 511 /* Create tag for Rx descripors */ 512 error = bus_dma_tag_create( 513 bus_get_dma_tag(sc->dev), /* parent */ 514 32, 0, /* alignment, boundary */ 515 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 516 BUS_SPACE_MAXADDR, /* highaddr */ 517 NULL, NULL, /* filtfunc, filtfuncarg */ 518 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 519 1, /* nsegments */ 520 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 521 0, /* flags */ 522 NULL, NULL, /* lockfunc, lockfuncarg */ 523 &sc->rx_dtag); /* dmat */ 524 if (error != 0) { 525 device_printf(sc->dev, 526 "Failed to create DMA tag for Rx descriptors.\n"); 527 goto fail; 528 } 529 530 /* Create tag for Rx buffers */ 531 error = bus_dma_tag_create( 532 bus_get_dma_tag(sc->dev), /* parent */ 533 32, 0, /* alignment, boundary */ 534 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 535 BUS_SPACE_MAXADDR, /* highaddr */ 536 NULL, NULL, /* filtfunc, filtfuncarg */ 537 MVNETA_MAX_FRAME, 1, /* maxsize, nsegments */ 538 MVNETA_MAX_FRAME, /* maxsegsz */ 539 0, /* flags */ 540 NULL, NULL, /* lockfunc, lockfuncarg */ 541 &sc->rxbuf_dtag); /* dmat */ 542 if (error != 0) { 543 device_printf(sc->dev, 544 "Failed to create DMA tag for Rx buffers.\n"); 545 goto fail; 546 } 547 548 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 549 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 550 device_printf(sc->dev, 551 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 552 goto fail; 553 } 554 } 555 556 return (0); 557fail: 558 mvneta_detach(sc->dev); 559 560 return (error); 561} 562 563/* ARGSUSED */ 564int 565mvneta_attach(device_t self) 566{ 567 struct mvneta_softc *sc; 568 struct ifnet *ifp; 569 device_t child; 570 int ifm_target; 571 int q, error; 572#if !defined(__aarch64__) 573 uint32_t reg; 574#endif 575 576 sc = device_get_softc(self); 577 sc->dev = self; 578 579 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 580 581 error = bus_alloc_resources(self, res_spec, sc->res); 582 if (error) { 583 device_printf(self, "could not allocate resources\n"); 584 return (ENXIO); 585 } 586 587 sc->version = MVNETA_READ(sc, MVNETA_PV); 588 device_printf(self, "version is %x\n", sc->version); 589 callout_init(&sc->tick_ch, 0); 590 591 /* 592 * make sure DMA engines are in reset state 593 */ 594 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 595 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 596 597#if !defined(__aarch64__) 598 /* 599 * Disable port snoop for buffers and descriptors 600 * to avoid L2 caching of both without DRAM copy. 601 * Obtain coherency settings from the first MBUS 602 * window attribute. 603 */ 604 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 605 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 606 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 607 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 608 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 609 } 610#endif 611 612 /* 613 * MAC address 614 */ 615 if (mvneta_get_mac_address(sc, sc->enaddr)) { 616 device_printf(self, "no mac address.\n"); 617 return (ENXIO); 618 } 619 mvneta_set_mac_address(sc, sc->enaddr); 620 621 mvneta_disable_intr(sc); 622 623 /* Allocate network interface */ 624 ifp = sc->ifp = if_alloc(IFT_ETHER); 625 if (ifp == NULL) { 626 device_printf(self, "if_alloc() failed\n"); 627 mvneta_detach(self); 628 return (ENOMEM); 629 } 630 if_initname(ifp, device_get_name(self), device_get_unit(self)); 631 632 /* 633 * We can support 802.1Q VLAN-sized frames and jumbo 634 * Ethernet frames. 635 */ 636 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 637 638 ifp->if_softc = sc; 639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 640#ifdef MVNETA_MULTIQUEUE 641 ifp->if_transmit = mvneta_transmit; 642 ifp->if_qflush = mvneta_qflush; 643#else /* !MVNETA_MULTIQUEUE */ 644 ifp->if_start = mvneta_start; 645 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 646 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 647 IFQ_SET_READY(&ifp->if_snd); 648#endif 649 ifp->if_init = mvneta_init; 650 ifp->if_ioctl = mvneta_ioctl; 651 652 /* 653 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 654 */ 655 ifp->if_capabilities |= IFCAP_HWCSUM; 656 657 /* 658 * As VLAN hardware tagging is not supported 659 * but is necessary to perform VLAN hardware checksums, 660 * it is done in the driver 661 */ 662 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 663 664 /* 665 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 666 */ 667 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 668 ifp->if_capenable = ifp->if_capabilities; 669 670 /* 671 * Disabled option(s): 672 * - Support for Large Receive Offload 673 */ 674 ifp->if_capabilities |= IFCAP_LRO; 675 676 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 677 678 sc->rx_frame_size = MCLBYTES; /* ether_ifattach() always sets normal mtu */ 679 680 /* 681 * Device DMA Buffer allocation. 682 * Handles resource deallocation in case of failure. 683 */ 684 error = mvneta_dma_create(sc); 685 if (error != 0) { 686 mvneta_detach(self); 687 return (error); 688 } 689 690 /* Initialize queues */ 691 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 692 error = mvneta_ring_init_tx_queue(sc, q); 693 if (error != 0) { 694 mvneta_detach(self); 695 return (error); 696 } 697 } 698 699 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 700 error = mvneta_ring_init_rx_queue(sc, q); 701 if (error != 0) { 702 mvneta_detach(self); 703 return (error); 704 } 705 } 706 707 ether_ifattach(ifp, sc->enaddr); 708 709 /* 710 * Enable DMA engines and Initialize Device Registers. 711 */ 712 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 713 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 714 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 715 mvneta_sc_lock(sc); 716 mvneta_filter_setup(sc); 717 mvneta_sc_unlock(sc); 718 mvneta_initreg(ifp); 719 720 /* 721 * Now MAC is working, setup MII. 722 */ 723 if (mii_init == 0) { 724 /* 725 * MII bus is shared by all MACs and all PHYs in SoC. 726 * serializing the bus access should be safe. 727 */ 728 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 729 mii_init = 1; 730 } 731 732 /* Attach PHY(s) */ 733 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 734 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 735 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 736 MII_OFFSET_ANY, 0); 737 if (error != 0) { 738 if (bootverbose) { 739 device_printf(self, 740 "MII attach failed, error: %d\n", error); 741 } 742 ether_ifdetach(sc->ifp); 743 mvneta_detach(self); 744 return (error); 745 } 746 sc->mii = device_get_softc(sc->miibus); 747 sc->phy_attached = 1; 748 749 /* Disable auto-negotiation in MAC - rely on PHY layer */ 750 mvneta_update_autoneg(sc, FALSE); 751 } else if (sc->use_inband_status == TRUE) { 752 /* In-band link status */ 753 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 754 mvneta_mediastatus); 755 756 /* Configure media */ 757 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 758 0, NULL); 759 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 760 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 761 0, NULL); 762 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 763 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 764 0, NULL); 765 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 766 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 767 768 /* Enable auto-negotiation */ 769 mvneta_update_autoneg(sc, TRUE); 770 771 mvneta_sc_lock(sc); 772 if (MVNETA_IS_LINKUP(sc)) 773 mvneta_linkup(sc); 774 else 775 mvneta_linkdown(sc); 776 mvneta_sc_unlock(sc); 777 778 } else { 779 /* Fixed-link, use predefined values */ 780 mvneta_update_autoneg(sc, FALSE); 781 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 782 mvneta_mediastatus); 783 784 ifm_target = IFM_ETHER; 785 switch (sc->phy_speed) { 786 case 2500: 787 if (sc->phy_mode != MVNETA_PHY_SGMII && 788 sc->phy_mode != MVNETA_PHY_QSGMII) { 789 device_printf(self, 790 "2.5G speed can work only in (Q)SGMII mode\n"); 791 ether_ifdetach(sc->ifp); 792 mvneta_detach(self); 793 return (ENXIO); 794 } 795 ifm_target |= IFM_2500_T; 796 break; 797 case 1000: 798 ifm_target |= IFM_1000_T; 799 break; 800 case 100: 801 ifm_target |= IFM_100_TX; 802 break; 803 case 10: 804 ifm_target |= IFM_10_T; 805 break; 806 default: 807 ether_ifdetach(sc->ifp); 808 mvneta_detach(self); 809 return (ENXIO); 810 } 811 812 if (sc->phy_fdx) 813 ifm_target |= IFM_FDX; 814 else 815 ifm_target |= IFM_HDX; 816 817 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 818 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 819 if_link_state_change(sc->ifp, LINK_STATE_UP); 820 821 if (mvneta_has_switch(self)) { 822 if (bootverbose) 823 device_printf(self, "This device is attached to a switch\n"); 824 child = device_add_child(sc->dev, "mdio", -1); 825 if (child == NULL) { 826 ether_ifdetach(sc->ifp); 827 mvneta_detach(self); 828 return (ENXIO); 829 } 830 bus_generic_attach(sc->dev); 831 bus_generic_attach(child); 832 } 833 834 /* Configure MAC media */ 835 mvneta_update_media(sc, ifm_target); 836 } 837 838 sysctl_mvneta_init(sc); 839 840 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 841 842 error = bus_setup_intr(self, sc->res[1], 843 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 844 &sc->ih_cookie[0]); 845 if (error) { 846 device_printf(self, "could not setup %s\n", 847 mvneta_intrs[0].description); 848 ether_ifdetach(sc->ifp); 849 mvneta_detach(self); 850 return (error); 851 } 852 853 return (0); 854} 855 856STATIC int 857mvneta_detach(device_t dev) 858{ 859 struct mvneta_softc *sc; 860 int q; 861 862 sc = device_get_softc(dev); 863 864 mvneta_stop(sc); 865 /* Detach network interface */ 866 if (sc->ifp) 867 if_free(sc->ifp); 868 869 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 870 mvneta_ring_dealloc_rx_queue(sc, q); 871 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 872 mvneta_ring_dealloc_tx_queue(sc, q); 873 874 if (sc->tx_dtag != NULL) 875 bus_dma_tag_destroy(sc->tx_dtag); 876 if (sc->rx_dtag != NULL) 877 bus_dma_tag_destroy(sc->rx_dtag); 878 if (sc->txmbuf_dtag != NULL) 879 bus_dma_tag_destroy(sc->txmbuf_dtag); 880 if (sc->rxbuf_dtag != NULL) 881 bus_dma_tag_destroy(sc->rxbuf_dtag); 882 883 bus_release_resources(dev, res_spec, sc->res); 884 return (0); 885} 886 887/* 888 * MII 889 */ 890STATIC int 891mvneta_miibus_readreg(device_t dev, int phy, int reg) 892{ 893 struct mvneta_softc *sc; 894 struct ifnet *ifp; 895 uint32_t smi, val; 896 int i; 897 898 sc = device_get_softc(dev); 899 ifp = sc->ifp; 900 901 mtx_lock(&mii_mutex); 902 903 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 904 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 905 break; 906 DELAY(1); 907 } 908 if (i == MVNETA_PHY_TIMEOUT) { 909 if_printf(ifp, "SMI busy timeout\n"); 910 mtx_unlock(&mii_mutex); 911 return (-1); 912 } 913 914 smi = MVNETA_SMI_PHYAD(phy) | 915 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 916 MVNETA_WRITE(sc, MVNETA_SMI, smi); 917 918 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 919 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 920 break; 921 DELAY(1); 922 } 923 924 if (i == MVNETA_PHY_TIMEOUT) { 925 if_printf(ifp, "SMI busy timeout\n"); 926 mtx_unlock(&mii_mutex); 927 return (-1); 928 } 929 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 930 smi = MVNETA_READ(sc, MVNETA_SMI); 931 if (smi & MVNETA_SMI_READVALID) 932 break; 933 DELAY(1); 934 } 935 936 if (i == MVNETA_PHY_TIMEOUT) { 937 if_printf(ifp, "SMI busy timeout\n"); 938 mtx_unlock(&mii_mutex); 939 return (-1); 940 } 941 942 mtx_unlock(&mii_mutex); 943 944#ifdef MVNETA_KTR 945 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 946 MVNETA_PHY_TIMEOUT); 947#endif 948 949 val = smi & MVNETA_SMI_DATA_MASK; 950 951#ifdef MVNETA_KTR 952 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 953 reg, val); 954#endif 955 return (val); 956} 957 958STATIC int 959mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 960{ 961 struct mvneta_softc *sc; 962 struct ifnet *ifp; 963 uint32_t smi; 964 int i; 965 966 sc = device_get_softc(dev); 967 ifp = sc->ifp; 968#ifdef MVNETA_KTR 969 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 970 phy, reg, val); 971#endif 972 973 mtx_lock(&mii_mutex); 974 975 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 976 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 977 break; 978 DELAY(1); 979 } 980 if (i == MVNETA_PHY_TIMEOUT) { 981 if_printf(ifp, "SMI busy timeout\n"); 982 mtx_unlock(&mii_mutex); 983 return (0); 984 } 985 986 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 987 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 988 MVNETA_WRITE(sc, MVNETA_SMI, smi); 989 990 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 991 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 992 break; 993 DELAY(1); 994 } 995 996 mtx_unlock(&mii_mutex); 997 998 if (i == MVNETA_PHY_TIMEOUT) 999 if_printf(ifp, "phy write timed out\n"); 1000 1001 return (0); 1002} 1003 1004STATIC void 1005mvneta_portup(struct mvneta_softc *sc) 1006{ 1007 int q; 1008 1009 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1010 mvneta_rx_lockq(sc, q); 1011 mvneta_rx_queue_enable(sc->ifp, q); 1012 mvneta_rx_unlockq(sc, q); 1013 } 1014 1015 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1016 mvneta_tx_lockq(sc, q); 1017 mvneta_tx_queue_enable(sc->ifp, q); 1018 mvneta_tx_unlockq(sc, q); 1019 } 1020 1021} 1022 1023STATIC void 1024mvneta_portdown(struct mvneta_softc *sc) 1025{ 1026 struct mvneta_rx_ring *rx; 1027 struct mvneta_tx_ring *tx; 1028 int q, cnt; 1029 uint32_t reg; 1030 1031 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1032 rx = MVNETA_RX_RING(sc, q); 1033 mvneta_rx_lockq(sc, q); 1034 rx->queue_status = MVNETA_QUEUE_DISABLED; 1035 mvneta_rx_unlockq(sc, q); 1036 } 1037 1038 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1039 tx = MVNETA_TX_RING(sc, q); 1040 mvneta_tx_lockq(sc, q); 1041 tx->queue_status = MVNETA_QUEUE_DISABLED; 1042 mvneta_tx_unlockq(sc, q); 1043 } 1044 1045 /* Wait for all Rx activity to terminate. */ 1046 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1047 reg = MVNETA_RQC_DIS(reg); 1048 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1049 cnt = 0; 1050 do { 1051 if (cnt >= RX_DISABLE_TIMEOUT) { 1052 if_printf(sc->ifp, 1053 "timeout for RX stopped. rqc 0x%x\n", reg); 1054 break; 1055 } 1056 cnt++; 1057 reg = MVNETA_READ(sc, MVNETA_RQC); 1058 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1059 1060 /* Wait for all Tx activity to terminate. */ 1061 reg = MVNETA_READ(sc, MVNETA_PIE); 1062 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1063 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1064 1065 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1066 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1067 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1068 1069 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1070 reg = MVNETA_TQC_DIS(reg); 1071 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1072 cnt = 0; 1073 do { 1074 if (cnt >= TX_DISABLE_TIMEOUT) { 1075 if_printf(sc->ifp, 1076 "timeout for TX stopped. tqc 0x%x\n", reg); 1077 break; 1078 } 1079 cnt++; 1080 reg = MVNETA_READ(sc, MVNETA_TQC); 1081 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1082 1083 /* Wait for all Tx FIFO is empty */ 1084 cnt = 0; 1085 do { 1086 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1087 if_printf(sc->ifp, 1088 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1089 break; 1090 } 1091 cnt++; 1092 reg = MVNETA_READ(sc, MVNETA_PS0); 1093 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1094 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1095} 1096 1097/* 1098 * Device Register Initialization 1099 * reset device registers to device driver default value. 1100 * the device is not enabled here. 1101 */ 1102STATIC int 1103mvneta_initreg(struct ifnet *ifp) 1104{ 1105 struct mvneta_softc *sc; 1106 int q; 1107 uint32_t reg; 1108 1109 sc = ifp->if_softc; 1110#ifdef MVNETA_KTR 1111 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1112#endif 1113 1114 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1115 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1116 /* Enable mbus retry. */ 1117 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1118 1119 /* Init TX/RX Queue Registers */ 1120 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1121 mvneta_rx_lockq(sc, q); 1122 if (mvneta_rx_queue_init(ifp, q) != 0) { 1123 device_printf(sc->dev, 1124 "initialization failed: cannot initialize queue\n"); 1125 mvneta_rx_unlockq(sc, q); 1126 return (ENOBUFS); 1127 } 1128 mvneta_rx_unlockq(sc, q); 1129 } 1130 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1131 mvneta_tx_lockq(sc, q); 1132 if (mvneta_tx_queue_init(ifp, q) != 0) { 1133 device_printf(sc->dev, 1134 "initialization failed: cannot initialize queue\n"); 1135 mvneta_tx_unlockq(sc, q); 1136 return (ENOBUFS); 1137 } 1138 mvneta_tx_unlockq(sc, q); 1139 } 1140 1141 /* 1142 * Ethernet Unit Control - disable automatic PHY management by HW. 1143 * In case the port uses SMI-controlled PHY, poll its status with 1144 * mii_tick() and update MAC settings accordingly. 1145 */ 1146 reg = MVNETA_READ(sc, MVNETA_EUC); 1147 reg &= ~MVNETA_EUC_POLLING; 1148 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1149 1150 /* EEE: Low Power Idle */ 1151 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1152 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1153 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1154 1155 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1156 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1157 1158 reg = MVNETA_LPIC2_MUSTSET; 1159 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1160 1161 /* Port MAC Control set 0 */ 1162 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1163 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1164 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 1165 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1166 1167 /* Port MAC Control set 2 */ 1168 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1169 switch (sc->phy_mode) { 1170 case MVNETA_PHY_QSGMII: 1171 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1172 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1173 break; 1174 case MVNETA_PHY_SGMII: 1175 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1176 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1177 break; 1178 case MVNETA_PHY_RGMII: 1179 case MVNETA_PHY_RGMII_ID: 1180 reg |= MVNETA_PMACC2_RGMIIEN; 1181 break; 1182 } 1183 reg |= MVNETA_PMACC2_MUSTSET; 1184 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1185 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1186 1187 /* Port Configuration Extended: enable Tx CRC generation */ 1188 reg = MVNETA_READ(sc, MVNETA_PXCX); 1189 reg &= ~MVNETA_PXCX_TXCRCDIS; 1190 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1191 1192 /* clear MIB counter registers(clear by read) */ 1193 mvneta_sc_lock(sc); 1194 mvneta_clear_mib(sc); 1195 mvneta_sc_unlock(sc); 1196 1197 /* Set SDC register except IPGINT bits */ 1198 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1199 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1200 reg |= MVNETA_SDC_BLMR; 1201 reg |= MVNETA_SDC_BLMT; 1202 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1203 1204 return (0); 1205} 1206 1207STATIC void 1208mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1209{ 1210 1211 if (error != 0) 1212 return; 1213 *(bus_addr_t *)arg = segs->ds_addr; 1214} 1215 1216STATIC int 1217mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1218{ 1219 struct mvneta_rx_ring *rx; 1220 struct mvneta_buf *rxbuf; 1221 bus_dmamap_t dmap; 1222 int i, error; 1223 1224 if (q >= MVNETA_RX_QNUM_MAX) 1225 return (EINVAL); 1226 1227 rx = MVNETA_RX_RING(sc, q); 1228 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1229 /* Allocate DMA memory for Rx descriptors */ 1230 error = bus_dmamem_alloc(sc->rx_dtag, 1231 (void**)&(rx->desc), 1232 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1233 &rx->desc_map); 1234 if (error != 0 || rx->desc == NULL) 1235 goto fail; 1236 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1237 rx->desc, 1238 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1239 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1240 if (error != 0) 1241 goto fail; 1242 1243 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1244 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1245 if (error != 0) { 1246 device_printf(sc->dev, 1247 "Failed to create DMA map for Rx buffer num: %d\n", i); 1248 goto fail; 1249 } 1250 rxbuf = &rx->rxbuf[i]; 1251 rxbuf->dmap = dmap; 1252 rxbuf->m = NULL; 1253 } 1254 1255 return (0); 1256fail: 1257 mvneta_ring_dealloc_rx_queue(sc, q); 1258 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1259 return (error); 1260} 1261 1262STATIC int 1263mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1264{ 1265 struct mvneta_tx_ring *tx; 1266 int error; 1267 1268 if (q >= MVNETA_TX_QNUM_MAX) 1269 return (EINVAL); 1270 tx = MVNETA_TX_RING(sc, q); 1271 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1272 error = bus_dmamem_alloc(sc->tx_dtag, 1273 (void**)&(tx->desc), 1274 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1275 &tx->desc_map); 1276 if (error != 0 || tx->desc == NULL) 1277 goto fail; 1278 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1279 tx->desc, 1280 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1281 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1282 if (error != 0) 1283 goto fail; 1284 1285#ifdef MVNETA_MULTIQUEUE 1286 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1287 &tx->ring_mtx); 1288 if (tx->br == NULL) { 1289 device_printf(sc->dev, 1290 "Could not setup buffer ring for TxQ(%d)\n", q); 1291 error = ENOMEM; 1292 goto fail; 1293 } 1294#endif 1295 1296 return (0); 1297fail: 1298 mvneta_ring_dealloc_tx_queue(sc, q); 1299 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1300 return (error); 1301} 1302 1303STATIC void 1304mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1305{ 1306 struct mvneta_tx_ring *tx; 1307 struct mvneta_buf *txbuf; 1308 void *kva; 1309 int error; 1310 int i; 1311 1312 if (q >= MVNETA_TX_QNUM_MAX) 1313 return; 1314 tx = MVNETA_TX_RING(sc, q); 1315 1316 if (tx->taskq != NULL) { 1317 /* Remove task */ 1318 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1319 taskqueue_drain(tx->taskq, &tx->task); 1320 } 1321#ifdef MVNETA_MULTIQUEUE 1322 if (tx->br != NULL) 1323 drbr_free(tx->br, M_DEVBUF); 1324#endif 1325 1326 if (sc->txmbuf_dtag != NULL) { 1327 if (mtx_name(&tx->ring_mtx) != NULL) { 1328 /* 1329 * It is assumed that maps are being loaded after mutex 1330 * is initialized. Therefore we can skip unloading maps 1331 * when mutex is empty. 1332 */ 1333 mvneta_tx_lockq(sc, q); 1334 mvneta_ring_flush_tx_queue(sc, q); 1335 mvneta_tx_unlockq(sc, q); 1336 } 1337 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1338 txbuf = &tx->txbuf[i]; 1339 if (txbuf->dmap != NULL) { 1340 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1341 txbuf->dmap); 1342 if (error != 0) { 1343 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1344 __func__, q, i); 1345 } 1346 } 1347 } 1348 } 1349 1350 if (tx->desc_pa != 0) 1351 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1352 1353 kva = (void *)tx->desc; 1354 if (kva != NULL) 1355 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1356 1357 if (mtx_name(&tx->ring_mtx) != NULL) 1358 mtx_destroy(&tx->ring_mtx); 1359 1360 memset(tx, 0, sizeof(*tx)); 1361} 1362 1363STATIC void 1364mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1365{ 1366 struct mvneta_rx_ring *rx; 1367 struct lro_ctrl *lro; 1368 void *kva; 1369 1370 if (q >= MVNETA_RX_QNUM_MAX) 1371 return; 1372 1373 rx = MVNETA_RX_RING(sc, q); 1374 1375 mvneta_ring_flush_rx_queue(sc, q); 1376 1377 if (rx->desc_pa != 0) 1378 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1379 1380 kva = (void *)rx->desc; 1381 if (kva != NULL) 1382 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1383 1384 lro = &rx->lro; 1385 tcp_lro_free(lro); 1386 1387 if (mtx_name(&rx->ring_mtx) != NULL) 1388 mtx_destroy(&rx->ring_mtx); 1389 1390 memset(rx, 0, sizeof(*rx)); 1391} 1392 1393STATIC int 1394mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1395{ 1396 struct mvneta_rx_ring *rx; 1397 struct lro_ctrl *lro; 1398 int error; 1399 1400 if (q >= MVNETA_RX_QNUM_MAX) 1401 return (0); 1402 1403 rx = MVNETA_RX_RING(sc, q); 1404 rx->dma = rx->cpu = 0; 1405 rx->queue_th_received = MVNETA_RXTH_COUNT; 1406 rx->queue_th_time = (mvneta_get_clk() / 1000) / 10; /* 0.1 [ms] */ 1407 1408 /* Initialize LRO */ 1409 rx->lro_enabled = FALSE; 1410 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1411 lro = &rx->lro; 1412 error = tcp_lro_init(lro); 1413 if (error != 0) 1414 device_printf(sc->dev, "LRO Initialization failed!\n"); 1415 else { 1416 rx->lro_enabled = TRUE; 1417 lro->ifp = sc->ifp; 1418 } 1419 } 1420 1421 return (0); 1422} 1423 1424STATIC int 1425mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1426{ 1427 struct mvneta_tx_ring *tx; 1428 struct mvneta_buf *txbuf; 1429 int i, error; 1430 1431 if (q >= MVNETA_TX_QNUM_MAX) 1432 return (0); 1433 1434 tx = MVNETA_TX_RING(sc, q); 1435 1436 /* Tx handle */ 1437 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1438 txbuf = &tx->txbuf[i]; 1439 txbuf->m = NULL; 1440 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1441 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1442 &txbuf->dmap); 1443 if (error != 0) { 1444 device_printf(sc->dev, 1445 "can't create dma map (tx ring %d)\n", i); 1446 return (error); 1447 } 1448 } 1449 tx->dma = tx->cpu = 0; 1450 tx->used = 0; 1451 tx->drv_error = 0; 1452 tx->queue_status = MVNETA_QUEUE_DISABLED; 1453 tx->queue_hung = FALSE; 1454 1455 tx->ifp = sc->ifp; 1456 tx->qidx = q; 1457 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1458 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1459 taskqueue_thread_enqueue, &tx->taskq); 1460 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1461 device_get_nameunit(sc->dev), q); 1462 1463 return (0); 1464} 1465 1466STATIC void 1467mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1468{ 1469 struct mvneta_tx_ring *tx; 1470 struct mvneta_buf *txbuf; 1471 int i; 1472 1473 tx = MVNETA_TX_RING(sc, q); 1474 KASSERT_TX_MTX(sc, q); 1475 1476 /* Tx handle */ 1477 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1478 txbuf = &tx->txbuf[i]; 1479 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1480 if (txbuf->m != NULL) { 1481 m_freem(txbuf->m); 1482 txbuf->m = NULL; 1483 } 1484 } 1485 tx->dma = tx->cpu = 0; 1486 tx->used = 0; 1487} 1488 1489STATIC void 1490mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1491{ 1492 struct mvneta_rx_ring *rx; 1493 struct mvneta_buf *rxbuf; 1494 int i; 1495 1496 rx = MVNETA_RX_RING(sc, q); 1497 KASSERT_RX_MTX(sc, q); 1498 1499 /* Rx handle */ 1500 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1501 rxbuf = &rx->rxbuf[i]; 1502 mvneta_rx_buf_free(sc, rxbuf); 1503 } 1504 rx->dma = rx->cpu = 0; 1505} 1506 1507/* 1508 * Rx/Tx Queue Control 1509 */ 1510STATIC int 1511mvneta_rx_queue_init(struct ifnet *ifp, int q) 1512{ 1513 struct mvneta_softc *sc; 1514 struct mvneta_rx_ring *rx; 1515 uint32_t reg; 1516 1517 sc = ifp->if_softc; 1518 KASSERT_RX_MTX(sc, q); 1519 rx = MVNETA_RX_RING(sc, q); 1520 DASSERT(rx->desc_pa != 0); 1521 1522 /* descriptor address */ 1523 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1524 1525 /* Rx buffer size and descriptor ring size */ 1526 reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3); 1527 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1528 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1529#ifdef MVNETA_KTR 1530 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1531 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1532#endif 1533 /* Rx packet offset address */ 1534 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1535 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1536#ifdef MVNETA_KTR 1537 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1538 MVNETA_READ(sc, MVNETA_PRXC(q))); 1539#endif 1540 1541 /* if DMA is not working, register is not updated */ 1542 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1543 return (0); 1544} 1545 1546STATIC int 1547mvneta_tx_queue_init(struct ifnet *ifp, int q) 1548{ 1549 struct mvneta_softc *sc; 1550 struct mvneta_tx_ring *tx; 1551 uint32_t reg; 1552 1553 sc = ifp->if_softc; 1554 KASSERT_TX_MTX(sc, q); 1555 tx = MVNETA_TX_RING(sc, q); 1556 DASSERT(tx->desc_pa != 0); 1557 1558 /* descriptor address */ 1559 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1560 1561 /* descriptor ring size */ 1562 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1563 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1564 1565 /* if DMA is not working, register is not updated */ 1566 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1567 return (0); 1568} 1569 1570STATIC int 1571mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1572{ 1573 struct mvneta_softc *sc; 1574 struct mvneta_rx_ring *rx; 1575 uint32_t reg; 1576 1577 sc = ifp->if_softc; 1578 rx = MVNETA_RX_RING(sc, q); 1579 KASSERT_RX_MTX(sc, q); 1580 1581 /* Set Rx interrupt threshold */ 1582 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1583 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1584 1585 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1586 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1587 1588 /* Unmask RXTX_TH Intr. */ 1589 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1590 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1591 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1592 1593 /* Enable Rx queue */ 1594 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1595 reg |= MVNETA_RQC_ENQ(q); 1596 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1597 1598 rx->queue_status = MVNETA_QUEUE_WORKING; 1599 return (0); 1600} 1601 1602STATIC int 1603mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1604{ 1605 struct mvneta_softc *sc; 1606 struct mvneta_tx_ring *tx; 1607 1608 sc = ifp->if_softc; 1609 tx = MVNETA_TX_RING(sc, q); 1610 KASSERT_TX_MTX(sc, q); 1611 1612 /* Enable Tx queue */ 1613 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1614 1615 tx->queue_status = MVNETA_QUEUE_IDLE; 1616 tx->queue_hung = FALSE; 1617 return (0); 1618} 1619 1620STATIC __inline void 1621mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1622{ 1623 1624 DASSERT(q >= 0); 1625 DASSERT(q < MVNETA_RX_QNUM_MAX); 1626 mtx_lock(&sc->rx_ring[q].ring_mtx); 1627} 1628 1629STATIC __inline void 1630mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1631{ 1632 1633 DASSERT(q >= 0); 1634 DASSERT(q < MVNETA_RX_QNUM_MAX); 1635 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1636} 1637 1638STATIC __inline int __unused 1639mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1640{ 1641 1642 DASSERT(q >= 0); 1643 DASSERT(q < MVNETA_TX_QNUM_MAX); 1644 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1645} 1646 1647STATIC __inline void 1648mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1649{ 1650 1651 DASSERT(q >= 0); 1652 DASSERT(q < MVNETA_TX_QNUM_MAX); 1653 mtx_lock(&sc->tx_ring[q].ring_mtx); 1654} 1655 1656STATIC __inline void 1657mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1658{ 1659 1660 DASSERT(q >= 0); 1661 DASSERT(q < MVNETA_TX_QNUM_MAX); 1662 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1663} 1664 1665/* 1666 * Interrupt Handlers 1667 */ 1668STATIC void 1669mvneta_disable_intr(struct mvneta_softc *sc) 1670{ 1671 1672 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1673 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1674 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1675 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1676 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1677 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1678 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1679 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1680 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1681} 1682 1683STATIC void 1684mvneta_enable_intr(struct mvneta_softc *sc) 1685{ 1686 uint32_t reg; 1687 1688 /* Enable Summary Bit to check all interrupt cause. */ 1689 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1690 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1691 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1692 1693 if (sc->use_inband_status) { 1694 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1695 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1696 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1697 } 1698 1699 /* Enable All Queue Interrupt */ 1700 reg = MVNETA_READ(sc, MVNETA_PIE); 1701 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1702 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1703 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1704} 1705 1706STATIC void 1707mvneta_rxtxth_intr(void *arg) 1708{ 1709 struct mvneta_softc *sc; 1710 struct ifnet *ifp; 1711 uint32_t ic, queues; 1712 1713 sc = arg; 1714 ifp = sc->ifp; 1715#ifdef MVNETA_KTR 1716 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1717#endif 1718 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1719 if (ic == 0) 1720 return; 1721 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1722 1723 /* Ack maintance interrupt first */ 1724 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1725 sc->use_inband_status)) { 1726 mvneta_sc_lock(sc); 1727 mvneta_misc_intr(sc); 1728 mvneta_sc_unlock(sc); 1729 } 1730 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1731 return; 1732 /* RxTxTH interrupt */ 1733 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1734 if (__predict_true(queues)) { 1735#ifdef MVNETA_KTR 1736 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1737#endif 1738 /* At the moment the driver support only one RX queue. */ 1739 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1740 mvneta_rx(sc, 0, 0); 1741 } 1742} 1743 1744STATIC int 1745mvneta_misc_intr(struct mvneta_softc *sc) 1746{ 1747 uint32_t ic; 1748 int claimed = 0; 1749 1750#ifdef MVNETA_KTR 1751 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1752#endif 1753 KASSERT_SC_MTX(sc); 1754 1755 for (;;) { 1756 ic = MVNETA_READ(sc, MVNETA_PMIC); 1757 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1758 if (ic == 0) 1759 break; 1760 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1761 claimed = 1; 1762 1763 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1764 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1765 mvneta_link_isr(sc); 1766 } 1767 return (claimed); 1768} 1769 1770STATIC void 1771mvneta_tick(void *arg) 1772{ 1773 struct mvneta_softc *sc; 1774 struct mvneta_tx_ring *tx; 1775 struct mvneta_rx_ring *rx; 1776 int q; 1777 uint32_t fc_prev, fc_curr; 1778 1779 sc = arg; 1780 1781 /* 1782 * This is done before mib update to get the right stats 1783 * for this tick. 1784 */ 1785 mvneta_tx_drain(sc); 1786 1787 /* Extract previous flow-control frame received counter. */ 1788 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1789 /* Read mib registers (clear by read). */ 1790 mvneta_update_mib(sc); 1791 /* Extract current flow-control frame received counter. */ 1792 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1793 1794 1795 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1796 mvneta_sc_lock(sc); 1797 mii_tick(sc->mii); 1798 1799 /* Adjust MAC settings */ 1800 mvneta_adjust_link(sc); 1801 mvneta_sc_unlock(sc); 1802 } 1803 1804 /* 1805 * We were unable to refill the rx queue and left the rx func, leaving 1806 * the ring without mbuf and no way to call the refill func. 1807 */ 1808 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1809 rx = MVNETA_RX_RING(sc, q); 1810 if (rx->needs_refill == TRUE) { 1811 mvneta_rx_lockq(sc, q); 1812 mvneta_rx_queue_refill(sc, q); 1813 mvneta_rx_unlockq(sc, q); 1814 } 1815 } 1816 1817 /* 1818 * Watchdog: 1819 * - check if queue is mark as hung. 1820 * - ignore hung status if we received some pause frame 1821 * as hardware may have paused packet transmit. 1822 */ 1823 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1824 /* 1825 * We should take queue lock, but as we only read 1826 * queue status we can do it without lock, we may 1827 * only missdetect queue status for one tick. 1828 */ 1829 tx = MVNETA_TX_RING(sc, q); 1830 1831 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1832 goto timeout; 1833 } 1834 1835 callout_schedule(&sc->tick_ch, hz); 1836 return; 1837 1838timeout: 1839 if_printf(sc->ifp, "watchdog timeout\n"); 1840 1841 mvneta_sc_lock(sc); 1842 sc->counter_watchdog++; 1843 sc->counter_watchdog_mib++; 1844 /* Trigger reinitialize sequence. */ 1845 mvneta_stop_locked(sc); 1846 mvneta_init_locked(sc); 1847 mvneta_sc_unlock(sc); 1848} 1849 1850STATIC void 1851mvneta_qflush(struct ifnet *ifp) 1852{ 1853#ifdef MVNETA_MULTIQUEUE 1854 struct mvneta_softc *sc; 1855 struct mvneta_tx_ring *tx; 1856 struct mbuf *m; 1857 size_t q; 1858 1859 sc = ifp->if_softc; 1860 1861 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1862 tx = MVNETA_TX_RING(sc, q); 1863 mvneta_tx_lockq(sc, q); 1864 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1865 m_freem(m); 1866 mvneta_tx_unlockq(sc, q); 1867 } 1868#endif 1869 if_qflush(ifp); 1870} 1871 1872STATIC void 1873mvneta_tx_task(void *arg, int pending) 1874{ 1875 struct mvneta_softc *sc; 1876 struct mvneta_tx_ring *tx; 1877 struct ifnet *ifp; 1878 int error; 1879 1880 tx = arg; 1881 ifp = tx->ifp; 1882 sc = ifp->if_softc; 1883 1884 mvneta_tx_lockq(sc, tx->qidx); 1885 error = mvneta_xmit_locked(sc, tx->qidx); 1886 mvneta_tx_unlockq(sc, tx->qidx); 1887 1888 /* Try again */ 1889 if (__predict_false(error != 0 && error != ENETDOWN)) { 1890 pause("mvneta_tx_task_sleep", 1); 1891 taskqueue_enqueue(tx->taskq, &tx->task); 1892 } 1893} 1894 1895STATIC int 1896mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1897{ 1898 struct mvneta_tx_ring *tx; 1899 struct ifnet *ifp; 1900 int error; 1901 1902 KASSERT_TX_MTX(sc, q); 1903 tx = MVNETA_TX_RING(sc, q); 1904 error = 0; 1905 1906 ifp = sc->ifp; 1907 1908 /* Dont enqueue packet if the queue is disabled. */ 1909 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1910 m_freem(*m); 1911 *m = NULL; 1912 return (ENETDOWN); 1913 } 1914 1915 /* Reclaim mbuf if above threshold. */ 1916 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1917 mvneta_tx_queue_complete(sc, q); 1918 1919 /* Do not call transmit path if queue is already too full. */ 1920 if (__predict_false(tx->used > 1921 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1922 return (ENOBUFS); 1923 1924 error = mvneta_tx_queue(sc, m, q); 1925 if (__predict_false(error != 0)) 1926 return (error); 1927 1928 /* Send a copy of the frame to the BPF listener */ 1929 ETHER_BPF_MTAP(ifp, *m); 1930 1931 /* Set watchdog on */ 1932 tx->watchdog_time = ticks; 1933 tx->queue_status = MVNETA_QUEUE_WORKING; 1934 1935 return (error); 1936} 1937 1938#ifdef MVNETA_MULTIQUEUE 1939STATIC int 1940mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1941{ 1942 struct mvneta_softc *sc; 1943 struct mvneta_tx_ring *tx; 1944 int error; 1945 int q; 1946 1947 sc = ifp->if_softc; 1948 1949 /* Use default queue if there is no flow id as thread can migrate. */ 1950 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1951 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1952 else 1953 q = 0; 1954 1955 tx = MVNETA_TX_RING(sc, q); 1956 1957 /* If buf_ring is full start transmit immediatly. */ 1958 if (buf_ring_full(tx->br)) { 1959 mvneta_tx_lockq(sc, q); 1960 mvneta_xmit_locked(sc, q); 1961 mvneta_tx_unlockq(sc, q); 1962 } 1963 1964 /* 1965 * If the buf_ring is empty we will not reorder packets. 1966 * If the lock is available transmit without using buf_ring. 1967 */ 1968 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1969 error = mvneta_xmitfast_locked(sc, q, &m); 1970 mvneta_tx_unlockq(sc, q); 1971 if (__predict_true(error == 0)) 1972 return (0); 1973 1974 /* Transmit can fail in fastpath. */ 1975 if (__predict_false(m == NULL)) 1976 return (error); 1977 } 1978 1979 /* Enqueue then schedule taskqueue. */ 1980 error = drbr_enqueue(ifp, tx->br, m); 1981 if (__predict_false(error != 0)) 1982 return (error); 1983 1984 taskqueue_enqueue(tx->taskq, &tx->task); 1985 return (0); 1986} 1987 1988STATIC int 1989mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1990{ 1991 struct ifnet *ifp; 1992 struct mvneta_tx_ring *tx; 1993 struct mbuf *m; 1994 int error; 1995 1996 KASSERT_TX_MTX(sc, q); 1997 ifp = sc->ifp; 1998 tx = MVNETA_TX_RING(sc, q); 1999 error = 0; 2000 2001 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 2002 error = mvneta_xmitfast_locked(sc, q, &m); 2003 if (__predict_false(error != 0)) { 2004 if (m != NULL) 2005 drbr_putback(ifp, tx->br, m); 2006 else 2007 drbr_advance(ifp, tx->br); 2008 break; 2009 } 2010 drbr_advance(ifp, tx->br); 2011 } 2012 2013 return (error); 2014} 2015#else /* !MVNETA_MULTIQUEUE */ 2016STATIC void 2017mvneta_start(struct ifnet *ifp) 2018{ 2019 struct mvneta_softc *sc; 2020 struct mvneta_tx_ring *tx; 2021 int error; 2022 2023 sc = ifp->if_softc; 2024 tx = MVNETA_TX_RING(sc, 0); 2025 2026 mvneta_tx_lockq(sc, 0); 2027 error = mvneta_xmit_locked(sc, 0); 2028 mvneta_tx_unlockq(sc, 0); 2029 /* Handle retransmit in the background taskq. */ 2030 if (__predict_false(error != 0 && error != ENETDOWN)) 2031 taskqueue_enqueue(tx->taskq, &tx->task); 2032} 2033 2034STATIC int 2035mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2036{ 2037 struct ifnet *ifp; 2038 struct mvneta_tx_ring *tx; 2039 struct mbuf *m; 2040 int error; 2041 2042 KASSERT_TX_MTX(sc, q); 2043 ifp = sc->ifp; 2044 tx = MVNETA_TX_RING(sc, 0); 2045 error = 0; 2046 2047 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2048 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2049 if (m == NULL) 2050 break; 2051 2052 error = mvneta_xmitfast_locked(sc, q, &m); 2053 if (__predict_false(error != 0)) { 2054 if (m != NULL) 2055 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2056 break; 2057 } 2058 } 2059 2060 return (error); 2061} 2062#endif 2063 2064STATIC int 2065mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2066{ 2067 struct mvneta_softc *sc; 2068 struct mvneta_rx_ring *rx; 2069 struct ifreq *ifr; 2070 int error, mask; 2071 uint32_t flags; 2072 int q; 2073 2074 error = 0; 2075 sc = ifp->if_softc; 2076 ifr = (struct ifreq *)data; 2077 switch (cmd) { 2078 case SIOCSIFFLAGS: 2079 mvneta_sc_lock(sc); 2080 if (ifp->if_flags & IFF_UP) { 2081 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2082 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2083 2084 if (flags != 0) 2085 sc->mvneta_if_flags = ifp->if_flags; 2086 2087 if ((flags & IFF_PROMISC) != 0) 2088 mvneta_filter_setup(sc); 2089 } else { 2090 mvneta_init_locked(sc); 2091 sc->mvneta_if_flags = ifp->if_flags; 2092 if (sc->phy_attached) 2093 mii_mediachg(sc->mii); 2094 mvneta_sc_unlock(sc); 2095 break; 2096 } 2097 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2098 mvneta_stop_locked(sc); 2099 2100 sc->mvneta_if_flags = ifp->if_flags; 2101 mvneta_sc_unlock(sc); 2102 break; 2103 case SIOCSIFCAP: 2104 if (ifp->if_mtu > sc->tx_csum_limit && 2105 ifr->ifr_reqcap & IFCAP_TXCSUM) 2106 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2107 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2108 if (mask & IFCAP_HWCSUM) { 2109 ifp->if_capenable &= ~IFCAP_HWCSUM; 2110 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2111 if (ifp->if_capenable & IFCAP_TXCSUM) 2112 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2113 CSUM_UDP; 2114 else 2115 ifp->if_hwassist = 0; 2116 } 2117 if (mask & IFCAP_LRO) { 2118 mvneta_sc_lock(sc); 2119 ifp->if_capenable ^= IFCAP_LRO; 2120 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2121 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2122 rx = MVNETA_RX_RING(sc, q); 2123 rx->lro_enabled = !rx->lro_enabled; 2124 } 2125 } 2126 mvneta_sc_unlock(sc); 2127 } 2128 VLAN_CAPABILITIES(ifp); 2129 break; 2130 case SIOCSIFMEDIA: 2131 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2132 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2133 (ifr->ifr_media & IFM_FDX) == 0) { 2134 device_printf(sc->dev, 2135 "%s half-duplex unsupported\n", 2136 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2137 "1000Base-T" : 2138 "2500Base-T"); 2139 error = EINVAL; 2140 break; 2141 } 2142 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2143 case SIOCGIFXMEDIA: 2144 if (!sc->phy_attached) 2145 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2146 cmd); 2147 else 2148 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2149 cmd); 2150 break; 2151 case SIOCSIFMTU: 2152 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2153 MVNETA_ETHER_SIZE) { 2154 error = EINVAL; 2155 } else { 2156 ifp->if_mtu = ifr->ifr_mtu; 2157 mvneta_sc_lock(sc); 2158 if (ifp->if_mtu + MVNETA_ETHER_SIZE <= MCLBYTES) { 2159 sc->rx_frame_size = MCLBYTES; 2160 } else { 2161 sc->rx_frame_size = MJUM9BYTES; 2162 } 2163 if (ifp->if_mtu > sc->tx_csum_limit) { 2164 ifp->if_capenable &= ~IFCAP_TXCSUM; 2165 ifp->if_hwassist = 0; 2166 } else { 2167 ifp->if_capenable |= IFCAP_TXCSUM; 2168 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2169 CSUM_UDP; 2170 } 2171 2172 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2173 /* Stop hardware */ 2174 mvneta_stop_locked(sc); 2175 /* 2176 * Reinitialize RX queues. 2177 * We need to update RX descriptor size. 2178 */ 2179 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2180 mvneta_rx_lockq(sc, q); 2181 if (mvneta_rx_queue_init(ifp, q) != 0) { 2182 device_printf(sc->dev, 2183 "initialization failed:" 2184 " cannot initialize queue\n"); 2185 mvneta_rx_unlockq(sc, q); 2186 error = ENOBUFS; 2187 break; 2188 } 2189 mvneta_rx_unlockq(sc, q); 2190 } 2191 /* Trigger reinitialization */ 2192 mvneta_init_locked(sc); 2193 } 2194 mvneta_sc_unlock(sc); 2195 } 2196 break; 2197 2198 default: 2199 error = ether_ioctl(ifp, cmd, data); 2200 break; 2201 } 2202 2203 return (error); 2204} 2205 2206STATIC void 2207mvneta_init_locked(void *arg) 2208{ 2209 struct mvneta_softc *sc; 2210 struct ifnet *ifp; 2211 uint32_t reg; 2212 int q, cpu; 2213 2214 sc = arg; 2215 ifp = sc->ifp; 2216 2217 if (!device_is_attached(sc->dev) || 2218 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2219 return; 2220 2221 mvneta_disable_intr(sc); 2222 callout_stop(&sc->tick_ch); 2223 2224 /* Get the latest mac address */ 2225 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2226 mvneta_set_mac_address(sc, sc->enaddr); 2227 mvneta_filter_setup(sc); 2228 2229 /* Start DMA Engine */ 2230 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2231 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2232 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2233 2234 /* Enable port */ 2235 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2236 reg |= MVNETA_PMACC0_PORTEN; 2237 reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK; 2238 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 2239 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2240 2241 /* Allow access to each TXQ/RXQ from both CPU's */ 2242 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2243 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2244 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2245 2246 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2247 mvneta_rx_lockq(sc, q); 2248 mvneta_rx_queue_refill(sc, q); 2249 mvneta_rx_unlockq(sc, q); 2250 } 2251 2252 if (!sc->phy_attached) 2253 mvneta_linkup(sc); 2254 2255 /* Enable interrupt */ 2256 mvneta_enable_intr(sc); 2257 2258 /* Set Counter */ 2259 callout_schedule(&sc->tick_ch, hz); 2260 2261 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2262} 2263 2264STATIC void 2265mvneta_init(void *arg) 2266{ 2267 struct mvneta_softc *sc; 2268 2269 sc = arg; 2270 mvneta_sc_lock(sc); 2271 mvneta_init_locked(sc); 2272 if (sc->phy_attached) 2273 mii_mediachg(sc->mii); 2274 mvneta_sc_unlock(sc); 2275} 2276 2277/* ARGSUSED */ 2278STATIC void 2279mvneta_stop_locked(struct mvneta_softc *sc) 2280{ 2281 struct ifnet *ifp; 2282 struct mvneta_rx_ring *rx; 2283 struct mvneta_tx_ring *tx; 2284 uint32_t reg; 2285 int q; 2286 2287 ifp = sc->ifp; 2288 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2289 return; 2290 2291 mvneta_disable_intr(sc); 2292 2293 callout_stop(&sc->tick_ch); 2294 2295 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2296 2297 /* Link down */ 2298 if (sc->linkup == TRUE) 2299 mvneta_linkdown(sc); 2300 2301 /* Reset the MAC Port Enable bit */ 2302 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2303 reg &= ~MVNETA_PMACC0_PORTEN; 2304 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2305 2306 /* Disable each of queue */ 2307 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2308 rx = MVNETA_RX_RING(sc, q); 2309 2310 mvneta_rx_lockq(sc, q); 2311 mvneta_ring_flush_rx_queue(sc, q); 2312 mvneta_rx_unlockq(sc, q); 2313 } 2314 2315 /* 2316 * Hold Reset state of DMA Engine 2317 * (must write 0x0 to restart it) 2318 */ 2319 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2320 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2321 2322 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2323 tx = MVNETA_TX_RING(sc, q); 2324 2325 mvneta_tx_lockq(sc, q); 2326 mvneta_ring_flush_tx_queue(sc, q); 2327 mvneta_tx_unlockq(sc, q); 2328 } 2329} 2330 2331STATIC void 2332mvneta_stop(struct mvneta_softc *sc) 2333{ 2334 2335 mvneta_sc_lock(sc); 2336 mvneta_stop_locked(sc); 2337 mvneta_sc_unlock(sc); 2338} 2339 2340STATIC int 2341mvneta_mediachange(struct ifnet *ifp) 2342{ 2343 struct mvneta_softc *sc; 2344 2345 sc = ifp->if_softc; 2346 2347 if (!sc->phy_attached && !sc->use_inband_status) { 2348 /* We shouldn't be here */ 2349 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2350 return (0); 2351 } 2352 2353 if (sc->use_inband_status) { 2354 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2355 return (0); 2356 } 2357 2358 mvneta_sc_lock(sc); 2359 2360 /* Update PHY */ 2361 mii_mediachg(sc->mii); 2362 2363 mvneta_sc_unlock(sc); 2364 2365 return (0); 2366} 2367 2368STATIC void 2369mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2370{ 2371 uint32_t psr; 2372 2373 psr = MVNETA_READ(sc, MVNETA_PSR); 2374 2375 /* Speed */ 2376 if (psr & MVNETA_PSR_GMIISPEED) 2377 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2378 else if (psr & MVNETA_PSR_MIISPEED) 2379 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2380 else if (psr & MVNETA_PSR_LINKUP) 2381 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2382 2383 /* Duplex */ 2384 if (psr & MVNETA_PSR_FULLDX) 2385 ifmr->ifm_active |= IFM_FDX; 2386 2387 /* Link */ 2388 ifmr->ifm_status = IFM_AVALID; 2389 if (psr & MVNETA_PSR_LINKUP) 2390 ifmr->ifm_status |= IFM_ACTIVE; 2391} 2392 2393STATIC void 2394mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2395{ 2396 struct mvneta_softc *sc; 2397 struct mii_data *mii; 2398 2399 sc = ifp->if_softc; 2400 2401 if (!sc->phy_attached && !sc->use_inband_status) { 2402 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2403 return; 2404 } 2405 2406 mvneta_sc_lock(sc); 2407 2408 if (sc->use_inband_status) { 2409 mvneta_get_media(sc, ifmr); 2410 mvneta_sc_unlock(sc); 2411 return; 2412 } 2413 2414 mii = sc->mii; 2415 mii_pollstat(mii); 2416 2417 ifmr->ifm_active = mii->mii_media_active; 2418 ifmr->ifm_status = mii->mii_media_status; 2419 2420 mvneta_sc_unlock(sc); 2421} 2422 2423/* 2424 * Link State Notify 2425 */ 2426STATIC void 2427mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2428{ 2429 int reg; 2430 2431 if (enable) { 2432 reg = MVNETA_READ(sc, MVNETA_PANC); 2433 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2434 MVNETA_PANC_ANFCEN); 2435 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2436 MVNETA_PANC_INBANDANEN; 2437 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2438 2439 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2440 reg |= MVNETA_PMACC2_INBANDANMODE; 2441 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2442 2443 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2444 reg |= MVNETA_PSOMSCD_ENABLE; 2445 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2446 } else { 2447 reg = MVNETA_READ(sc, MVNETA_PANC); 2448 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2449 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2450 MVNETA_PANC_INBANDANEN); 2451 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2452 2453 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2454 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2455 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2456 2457 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2458 reg &= ~MVNETA_PSOMSCD_ENABLE; 2459 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2460 } 2461} 2462 2463STATIC int 2464mvneta_update_media(struct mvneta_softc *sc, int media) 2465{ 2466 int reg, err; 2467 boolean_t running; 2468 2469 err = 0; 2470 2471 mvneta_sc_lock(sc); 2472 2473 mvneta_linkreset(sc); 2474 2475 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2476 if (running) 2477 mvneta_stop_locked(sc); 2478 2479 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2480 2481 if (sc->use_inband_status) 2482 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2483 2484 mvneta_update_eee(sc); 2485 mvneta_update_fc(sc); 2486 2487 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2488 reg = MVNETA_READ(sc, MVNETA_PANC); 2489 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2490 MVNETA_PANC_SETMIISPEED | 2491 MVNETA_PANC_SETFULLDX); 2492 if (IFM_SUBTYPE(media) == IFM_1000_T || 2493 IFM_SUBTYPE(media) == IFM_2500_T) { 2494 if ((media & IFM_FDX) == 0) { 2495 device_printf(sc->dev, 2496 "%s half-duplex unsupported\n", 2497 IFM_SUBTYPE(media) == IFM_1000_T ? 2498 "1000Base-T" : 2499 "2500Base-T"); 2500 err = EINVAL; 2501 goto out; 2502 } 2503 reg |= MVNETA_PANC_SETGMIISPEED; 2504 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2505 reg |= MVNETA_PANC_SETMIISPEED; 2506 2507 if (media & IFM_FDX) 2508 reg |= MVNETA_PANC_SETFULLDX; 2509 2510 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2511 } 2512out: 2513 if (running) 2514 mvneta_init_locked(sc); 2515 mvneta_sc_unlock(sc); 2516 return (err); 2517} 2518 2519STATIC void 2520mvneta_adjust_link(struct mvneta_softc *sc) 2521{ 2522 boolean_t phy_linkup; 2523 int reg; 2524 2525 /* Update eee/fc */ 2526 mvneta_update_eee(sc); 2527 mvneta_update_fc(sc); 2528 2529 /* Check for link change */ 2530 phy_linkup = (sc->mii->mii_media_status & 2531 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2532 2533 if (sc->linkup != phy_linkup) 2534 mvneta_linkupdate(sc, phy_linkup); 2535 2536 /* Don't update media on disabled link */ 2537 if (!phy_linkup) 2538 return; 2539 2540 /* Check for media type change */ 2541 if (sc->mvneta_media != sc->mii->mii_media_active) { 2542 sc->mvneta_media = sc->mii->mii_media_active; 2543 2544 reg = MVNETA_READ(sc, MVNETA_PANC); 2545 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2546 MVNETA_PANC_SETMIISPEED | 2547 MVNETA_PANC_SETFULLDX); 2548 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2549 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2550 reg |= MVNETA_PANC_SETGMIISPEED; 2551 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2552 reg |= MVNETA_PANC_SETMIISPEED; 2553 2554 if (sc->mvneta_media & IFM_FDX) 2555 reg |= MVNETA_PANC_SETFULLDX; 2556 2557 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2558 } 2559} 2560 2561STATIC void 2562mvneta_link_isr(struct mvneta_softc *sc) 2563{ 2564 int linkup; 2565 2566 KASSERT_SC_MTX(sc); 2567 2568 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2569 if (sc->linkup == linkup) 2570 return; 2571 2572 if (linkup == TRUE) 2573 mvneta_linkup(sc); 2574 else 2575 mvneta_linkdown(sc); 2576 2577#ifdef DEBUG 2578 log(LOG_DEBUG, 2579 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2580#endif 2581} 2582 2583STATIC void 2584mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2585{ 2586 2587 KASSERT_SC_MTX(sc); 2588 2589 if (linkup == TRUE) 2590 mvneta_linkup(sc); 2591 else 2592 mvneta_linkdown(sc); 2593 2594#ifdef DEBUG 2595 log(LOG_DEBUG, 2596 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2597#endif 2598} 2599 2600STATIC void 2601mvneta_update_eee(struct mvneta_softc *sc) 2602{ 2603 uint32_t reg; 2604 2605 KASSERT_SC_MTX(sc); 2606 2607 /* set EEE parameters */ 2608 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2609 if (sc->cf_lpi) 2610 reg |= MVNETA_LPIC1_LPIRE; 2611 else 2612 reg &= ~MVNETA_LPIC1_LPIRE; 2613 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2614} 2615 2616STATIC void 2617mvneta_update_fc(struct mvneta_softc *sc) 2618{ 2619 uint32_t reg; 2620 2621 KASSERT_SC_MTX(sc); 2622 2623 reg = MVNETA_READ(sc, MVNETA_PANC); 2624 if (sc->cf_fc) { 2625 /* Flow control negotiation */ 2626 reg |= MVNETA_PANC_PAUSEADV; 2627 reg |= MVNETA_PANC_ANFCEN; 2628 } else { 2629 /* Disable flow control negotiation */ 2630 reg &= ~MVNETA_PANC_PAUSEADV; 2631 reg &= ~MVNETA_PANC_ANFCEN; 2632 } 2633 2634 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2635} 2636 2637STATIC void 2638mvneta_linkup(struct mvneta_softc *sc) 2639{ 2640 uint32_t reg; 2641 2642 KASSERT_SC_MTX(sc); 2643 2644 if (!sc->use_inband_status) { 2645 reg = MVNETA_READ(sc, MVNETA_PANC); 2646 reg |= MVNETA_PANC_FORCELINKPASS; 2647 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2648 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2649 } 2650 2651 mvneta_qflush(sc->ifp); 2652 mvneta_portup(sc); 2653 sc->linkup = TRUE; 2654 if_link_state_change(sc->ifp, LINK_STATE_UP); 2655} 2656 2657STATIC void 2658mvneta_linkdown(struct mvneta_softc *sc) 2659{ 2660 uint32_t reg; 2661 2662 KASSERT_SC_MTX(sc); 2663 2664 if (!sc->use_inband_status) { 2665 reg = MVNETA_READ(sc, MVNETA_PANC); 2666 reg &= ~MVNETA_PANC_FORCELINKPASS; 2667 reg |= MVNETA_PANC_FORCELINKFAIL; 2668 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2669 } 2670 2671 mvneta_portdown(sc); 2672 mvneta_qflush(sc->ifp); 2673 sc->linkup = FALSE; 2674 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2675} 2676 2677STATIC void 2678mvneta_linkreset(struct mvneta_softc *sc) 2679{ 2680 struct mii_softc *mii; 2681 2682 if (sc->phy_attached) { 2683 /* Force reset PHY */ 2684 mii = LIST_FIRST(&sc->mii->mii_phys); 2685 if (mii) 2686 mii_phy_reset(mii); 2687 } 2688} 2689 2690/* 2691 * Tx Subroutines 2692 */ 2693STATIC int 2694mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2695{ 2696 struct ifnet *ifp; 2697 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2698 struct mbuf *mtmp, *mbuf; 2699 struct mvneta_tx_ring *tx; 2700 struct mvneta_buf *txbuf; 2701 struct mvneta_tx_desc *t; 2702 uint32_t ptxsu; 2703 int start, used, error, i, txnsegs; 2704 2705 mbuf = *mbufp; 2706 tx = MVNETA_TX_RING(sc, q); 2707 DASSERT(tx->used >= 0); 2708 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2709 t = NULL; 2710 ifp = sc->ifp; 2711 2712 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2713 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2714 if (mbuf == NULL) { 2715 tx->drv_error++; 2716 *mbufp = NULL; 2717 return (ENOBUFS); 2718 } 2719 mbuf->m_flags &= ~M_VLANTAG; 2720 *mbufp = mbuf; 2721 } 2722 2723 if (__predict_false(mbuf->m_next != NULL && 2724 (mbuf->m_pkthdr.csum_flags & 2725 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2726 if (M_WRITABLE(mbuf) == 0) { 2727 mtmp = m_dup(mbuf, M_NOWAIT); 2728 m_freem(mbuf); 2729 if (mtmp == NULL) { 2730 tx->drv_error++; 2731 *mbufp = NULL; 2732 return (ENOBUFS); 2733 } 2734 *mbufp = mbuf = mtmp; 2735 } 2736 } 2737 2738 /* load mbuf using dmamap of 1st descriptor */ 2739 txbuf = &tx->txbuf[tx->cpu]; 2740 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2741 txbuf->dmap, mbuf, txsegs, &txnsegs, 2742 BUS_DMA_NOWAIT); 2743 if (__predict_false(error != 0)) { 2744#ifdef MVNETA_KTR 2745 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2746#endif 2747 /* This is the only recoverable error (except EFBIG). */ 2748 if (error != ENOMEM) { 2749 tx->drv_error++; 2750 m_freem(mbuf); 2751 *mbufp = NULL; 2752 return (ENOBUFS); 2753 } 2754 return (error); 2755 } 2756 2757 if (__predict_false(txnsegs <= 0 2758 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2759 /* we have no enough descriptors or mbuf is broken */ 2760#ifdef MVNETA_KTR 2761 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2762 ifp->if_xname, q, txnsegs); 2763#endif 2764 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2765 return (ENOBUFS); 2766 } 2767 DASSERT(txbuf->m == NULL); 2768 2769 /* remember mbuf using 1st descriptor */ 2770 txbuf->m = mbuf; 2771 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2772 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2773 2774 /* load to tx descriptors */ 2775 start = tx->cpu; 2776 used = 0; 2777 for (i = 0; i < txnsegs; i++) { 2778 t = &tx->desc[tx->cpu]; 2779 t->command = 0; 2780 t->l4ichk = 0; 2781 t->flags = 0; 2782 if (__predict_true(i == 0)) { 2783 /* 1st descriptor */ 2784 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2785 t->command |= MVNETA_TX_CMD_F; 2786 mvneta_tx_set_csumflag(ifp, t, mbuf); 2787 } 2788 t->bufptr_pa = txsegs[i].ds_addr; 2789 t->bytecnt = txsegs[i].ds_len; 2790 tx->cpu = tx_counter_adv(tx->cpu, 1); 2791 2792 tx->used++; 2793 used++; 2794 } 2795 /* t is last descriptor here */ 2796 DASSERT(t != NULL); 2797 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2798 2799 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2800 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2801 2802 while (__predict_false(used > 255)) { 2803 ptxsu = MVNETA_PTXSU_NOWD(255); 2804 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2805 used -= 255; 2806 } 2807 if (__predict_true(used > 0)) { 2808 ptxsu = MVNETA_PTXSU_NOWD(used); 2809 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2810 } 2811 return (0); 2812} 2813 2814STATIC void 2815mvneta_tx_set_csumflag(struct ifnet *ifp, 2816 struct mvneta_tx_desc *t, struct mbuf *m) 2817{ 2818 struct ether_header *eh; 2819 int csum_flags; 2820 uint32_t iphl, ipoff; 2821 struct ip *ip; 2822 2823 iphl = ipoff = 0; 2824 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2825 eh = mtod(m, struct ether_header *); 2826 2827 switch (ntohs(eh->ether_type)) { 2828 case ETHERTYPE_IP: 2829 ipoff = ETHER_HDR_LEN; 2830 break; 2831 case ETHERTYPE_VLAN: 2832 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2833 break; 2834 default: 2835 csum_flags = 0; 2836 } 2837 2838 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2839 ip = (struct ip *)(m->m_data + ipoff); 2840 iphl = ip->ip_hl<<2; 2841 t->command |= MVNETA_TX_CMD_L3_IP4; 2842 } else { 2843 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2844 return; 2845 } 2846 2847 2848 /* L3 */ 2849 if (csum_flags & CSUM_IP) { 2850 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2851 } 2852 2853 /* L4 */ 2854 if (csum_flags & CSUM_IP_TCP) { 2855 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2856 t->command |= MVNETA_TX_CMD_L4_TCP; 2857 } else if (csum_flags & CSUM_IP_UDP) { 2858 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2859 t->command |= MVNETA_TX_CMD_L4_UDP; 2860 } else 2861 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2862 2863 t->l4ichk = 0; 2864 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2865 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2866} 2867 2868STATIC void 2869mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2870{ 2871 struct mvneta_tx_ring *tx; 2872 struct mvneta_buf *txbuf; 2873 struct mvneta_tx_desc *t; 2874 uint32_t ptxs, ptxsu, ndesc; 2875 int i; 2876 2877 KASSERT_TX_MTX(sc, q); 2878 2879 tx = MVNETA_TX_RING(sc, q); 2880 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2881 return; 2882 2883 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2884 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2885 2886 if (__predict_false(ndesc == 0)) { 2887 if (tx->used == 0) 2888 tx->queue_status = MVNETA_QUEUE_IDLE; 2889 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2890 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2891 tx->queue_hung = TRUE; 2892 return; 2893 } 2894 2895#ifdef MVNETA_KTR 2896 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2897 sc->ifp->if_xname, q, ndesc); 2898#endif 2899 2900 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2901 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2902 2903 for (i = 0; i < ndesc; i++) { 2904 t = &tx->desc[tx->dma]; 2905#ifdef MVNETA_KTR 2906 if (t->flags & MVNETA_TX_F_ES) 2907 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2908 sc->ifp->if_xname, q, tx->dma); 2909#endif 2910 txbuf = &tx->txbuf[tx->dma]; 2911 if (__predict_true(txbuf->m != NULL)) { 2912 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2913 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2914 m_freem(txbuf->m); 2915 txbuf->m = NULL; 2916 } 2917 else 2918 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2919 tx->dma = tx_counter_adv(tx->dma, 1); 2920 tx->used--; 2921 } 2922 DASSERT(tx->used >= 0); 2923 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2924 while (__predict_false(ndesc > 255)) { 2925 ptxsu = MVNETA_PTXSU_NORB(255); 2926 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2927 ndesc -= 255; 2928 } 2929 if (__predict_true(ndesc > 0)) { 2930 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2931 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2932 } 2933#ifdef MVNETA_KTR 2934 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2935 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2936#endif 2937 2938 tx->watchdog_time = ticks; 2939 2940 if (tx->used == 0) 2941 tx->queue_status = MVNETA_QUEUE_IDLE; 2942} 2943 2944/* 2945 * Do a final TX complete when TX is idle. 2946 */ 2947STATIC void 2948mvneta_tx_drain(struct mvneta_softc *sc) 2949{ 2950 struct mvneta_tx_ring *tx; 2951 int q; 2952 2953 /* 2954 * Handle trailing mbuf on TX queue. 2955 * Check is done lockess to avoid TX path contention. 2956 */ 2957 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2958 tx = MVNETA_TX_RING(sc, q); 2959 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2960 tx->used > 0) { 2961 mvneta_tx_lockq(sc, q); 2962 mvneta_tx_queue_complete(sc, q); 2963 mvneta_tx_unlockq(sc, q); 2964 } 2965 } 2966} 2967 2968/* 2969 * Rx Subroutines 2970 */ 2971STATIC int 2972mvneta_rx(struct mvneta_softc *sc, int q, int count) 2973{ 2974 uint32_t prxs, npkt; 2975 int more; 2976 2977 more = 0; 2978 mvneta_rx_lockq(sc, q); 2979 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2980 npkt = MVNETA_PRXS_GET_ODC(prxs); 2981 if (__predict_false(npkt == 0)) 2982 goto out; 2983 2984 if (count > 0 && npkt > count) { 2985 more = 1; 2986 npkt = count; 2987 } 2988 mvneta_rx_queue(sc, q, npkt); 2989out: 2990 mvneta_rx_unlockq(sc, q); 2991 return more; 2992} 2993 2994/* 2995 * Helper routine for updating PRXSU register of a given queue. 2996 * Handles number of processed descriptors bigger than maximum acceptable value. 2997 */ 2998STATIC __inline void 2999mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 3000{ 3001 uint32_t prxsu; 3002 3003 while (__predict_false(processed > 255)) { 3004 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 3005 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3006 processed -= 255; 3007 } 3008 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 3009 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3010} 3011 3012static __inline void 3013mvneta_prefetch(void *p) 3014{ 3015 3016 __builtin_prefetch(p); 3017} 3018 3019STATIC void 3020mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 3021{ 3022 struct ifnet *ifp; 3023 struct mvneta_rx_ring *rx; 3024 struct mvneta_rx_desc *r; 3025 struct mvneta_buf *rxbuf; 3026 struct mbuf *m; 3027 struct lro_ctrl *lro; 3028 struct lro_entry *queued; 3029 void *pktbuf; 3030 int i, pktlen, processed, ndma; 3031 3032 KASSERT_RX_MTX(sc, q); 3033 3034 ifp = sc->ifp; 3035 rx = MVNETA_RX_RING(sc, q); 3036 processed = 0; 3037 3038 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3039 return; 3040 3041 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3042 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3043 3044 for (i = 0; i < npkt; i++) { 3045 /* Prefetch next desc, rxbuf. */ 3046 ndma = rx_counter_adv(rx->dma, 1); 3047 mvneta_prefetch(&rx->desc[ndma]); 3048 mvneta_prefetch(&rx->rxbuf[ndma]); 3049 3050 /* get descriptor and packet */ 3051 r = &rx->desc[rx->dma]; 3052 rxbuf = &rx->rxbuf[rx->dma]; 3053 m = rxbuf->m; 3054 rxbuf->m = NULL; 3055 DASSERT(m != NULL); 3056 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3057 BUS_DMASYNC_POSTREAD); 3058 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3059 /* Prefetch mbuf header. */ 3060 mvneta_prefetch(m); 3061 3062 processed++; 3063 /* Drop desc with error status or not in a single buffer. */ 3064 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3065 (MVNETA_RX_F|MVNETA_RX_L)); 3066 if (__predict_false((r->status & MVNETA_RX_ES) || 3067 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3068 (MVNETA_RX_F|MVNETA_RX_L))) 3069 goto rx_error; 3070 3071 /* 3072 * [ OFF | MH | PKT | CRC ] 3073 * bytecnt cover MH, PKT, CRC 3074 */ 3075 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3076 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3077 MVNETA_HWHEADER_SIZE; 3078 3079 /* Prefetch mbuf data. */ 3080 mvneta_prefetch(pktbuf); 3081 3082 /* Write value to mbuf (avoid read). */ 3083 m->m_data = pktbuf; 3084 m->m_len = m->m_pkthdr.len = pktlen; 3085 m->m_pkthdr.rcvif = ifp; 3086 mvneta_rx_set_csumflag(ifp, r, m); 3087 3088 /* Increase rx_dma before releasing the lock. */ 3089 rx->dma = ndma; 3090 3091 if (__predict_false(rx->lro_enabled && 3092 ((r->status & MVNETA_RX_L3_IP) != 0) && 3093 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3094 (m->m_pkthdr.csum_flags & 3095 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3096 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3097 if (rx->lro.lro_cnt != 0) { 3098 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3099 goto rx_done; 3100 } 3101 } 3102 3103 mvneta_rx_unlockq(sc, q); 3104 (*ifp->if_input)(ifp, m); 3105 mvneta_rx_lockq(sc, q); 3106 /* 3107 * Check whether this queue has been disabled in the 3108 * meantime. If yes, then clear LRO and exit. 3109 */ 3110 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3111 goto rx_lro; 3112rx_done: 3113 /* Refresh receive ring to avoid stall and minimize jitter. */ 3114 if (processed >= MVNETA_RX_REFILL_COUNT) { 3115 mvneta_prxsu_update(sc, q, processed); 3116 mvneta_rx_queue_refill(sc, q); 3117 processed = 0; 3118 } 3119 continue; 3120rx_error: 3121 m_freem(m); 3122 rx->dma = ndma; 3123 /* Refresh receive ring to avoid stall and minimize jitter. */ 3124 if (processed >= MVNETA_RX_REFILL_COUNT) { 3125 mvneta_prxsu_update(sc, q, processed); 3126 mvneta_rx_queue_refill(sc, q); 3127 processed = 0; 3128 } 3129 } 3130#ifdef MVNETA_KTR 3131 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3132#endif 3133 /* DMA status update */ 3134 mvneta_prxsu_update(sc, q, processed); 3135 /* Refill the rest of buffers if there are any to refill */ 3136 mvneta_rx_queue_refill(sc, q); 3137 3138rx_lro: 3139 /* 3140 * Flush any outstanding LRO work 3141 */ 3142 lro = &rx->lro; 3143 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3144 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3145 tcp_lro_flush(lro, queued); 3146 } 3147} 3148 3149STATIC void 3150mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3151{ 3152 3153 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3154 /* This will remove all data at once */ 3155 m_freem(rxbuf->m); 3156} 3157 3158STATIC void 3159mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3160{ 3161 struct mvneta_rx_ring *rx; 3162 struct mvneta_rx_desc *r; 3163 struct mvneta_buf *rxbuf; 3164 bus_dma_segment_t segs; 3165 struct mbuf *m; 3166 uint32_t prxs, prxsu, ndesc; 3167 int npkt, refill, nsegs, error; 3168 3169 KASSERT_RX_MTX(sc, q); 3170 3171 rx = MVNETA_RX_RING(sc, q); 3172 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3173 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3174 refill = MVNETA_RX_RING_CNT - ndesc; 3175#ifdef MVNETA_KTR 3176 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3177 refill); 3178#endif 3179 if (__predict_false(refill <= 0)) 3180 return; 3181 3182 for (npkt = 0; npkt < refill; npkt++) { 3183 rxbuf = &rx->rxbuf[rx->cpu]; 3184 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->rx_frame_size); 3185 if (__predict_false(m == NULL)) { 3186 error = ENOBUFS; 3187 break; 3188 } 3189 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3190 3191 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3192 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3193 if (__predict_false(error != 0 || nsegs != 1)) { 3194 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3195 m_freem(m); 3196 break; 3197 } 3198 3199 /* Add the packet to the ring */ 3200 rxbuf->m = m; 3201 r = &rx->desc[rx->cpu]; 3202 r->bufptr_pa = segs.ds_addr; 3203 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3204 3205 rx->cpu = rx_counter_adv(rx->cpu, 1); 3206 } 3207 if (npkt == 0) { 3208 if (refill == MVNETA_RX_RING_CNT) 3209 rx->needs_refill = TRUE; 3210 return; 3211 } 3212 3213 rx->needs_refill = FALSE; 3214 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3215 3216 while (__predict_false(npkt > 255)) { 3217 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3218 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3219 npkt -= 255; 3220 } 3221 if (__predict_true(npkt > 0)) { 3222 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3223 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3224 } 3225} 3226 3227STATIC __inline void 3228mvneta_rx_set_csumflag(struct ifnet *ifp, 3229 struct mvneta_rx_desc *r, struct mbuf *m) 3230{ 3231 uint32_t csum_flags; 3232 3233 csum_flags = 0; 3234 if (__predict_false((r->status & 3235 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3236 return; /* not a IP packet */ 3237 3238 /* L3 */ 3239 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3240 MVNETA_RX_IP_HEADER_OK)) 3241 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3242 3243 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3244 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3245 /* L4 */ 3246 switch (r->status & MVNETA_RX_L4_MASK) { 3247 case MVNETA_RX_L4_TCP: 3248 case MVNETA_RX_L4_UDP: 3249 csum_flags |= CSUM_L4_CALC; 3250 if (__predict_true((r->status & 3251 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3252 csum_flags |= CSUM_L4_VALID; 3253 m->m_pkthdr.csum_data = htons(0xffff); 3254 } 3255 break; 3256 case MVNETA_RX_L4_OTH: 3257 default: 3258 break; 3259 } 3260 } 3261 m->m_pkthdr.csum_flags = csum_flags; 3262} 3263 3264/* 3265 * MAC address filter 3266 */ 3267STATIC void 3268mvneta_filter_setup(struct mvneta_softc *sc) 3269{ 3270 struct ifnet *ifp; 3271 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3272 uint32_t pxc; 3273 int i; 3274 3275 KASSERT_SC_MTX(sc); 3276 3277 memset(dfut, 0, sizeof(dfut)); 3278 memset(dfsmt, 0, sizeof(dfsmt)); 3279 memset(dfomt, 0, sizeof(dfomt)); 3280 3281 ifp = sc->ifp; 3282 ifp->if_flags |= IFF_ALLMULTI; 3283 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3284 for (i = 0; i < MVNETA_NDFSMT; i++) { 3285 dfsmt[i] = dfomt[i] = 3286 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3287 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3288 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3289 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3290 } 3291 } 3292 3293 pxc = MVNETA_READ(sc, MVNETA_PXC); 3294 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3295 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3296 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3297 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3298 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3299 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3300 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3301 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3302 if (ifp->if_flags & IFF_BROADCAST) { 3303 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3304 } 3305 if (ifp->if_flags & IFF_PROMISC) { 3306 pxc |= MVNETA_PXC_UPM; 3307 } 3308 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3309 3310 /* Set Destination Address Filter Unicast Table */ 3311 if (ifp->if_flags & IFF_PROMISC) { 3312 /* pass all unicast addresses */ 3313 for (i = 0; i < MVNETA_NDFUT; i++) { 3314 dfut[i] = 3315 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3316 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3317 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3318 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3319 } 3320 } else { 3321 i = sc->enaddr[5] & 0xf; /* last nibble */ 3322 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3323 } 3324 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3325 3326 /* Set Destination Address Filter Multicast Tables */ 3327 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3328 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3329} 3330 3331/* 3332 * sysctl(9) 3333 */ 3334STATIC int 3335sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3336{ 3337 struct mvneta_sysctl_mib *arg; 3338 struct mvneta_softc *sc; 3339 uint64_t val; 3340 3341 arg = (struct mvneta_sysctl_mib *)arg1; 3342 if (arg == NULL) 3343 return (EINVAL); 3344 3345 sc = arg->sc; 3346 if (sc == NULL) 3347 return (EINVAL); 3348 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3349 return (EINVAL); 3350 3351 mvneta_sc_lock(sc); 3352 val = arg->counter; 3353 mvneta_sc_unlock(sc); 3354 return sysctl_handle_64(oidp, &val, 0, req); 3355} 3356 3357 3358STATIC int 3359sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3360{ 3361 struct mvneta_softc *sc; 3362 int err, val; 3363 3364 val = 0; 3365 sc = (struct mvneta_softc *)arg1; 3366 if (sc == NULL) 3367 return (EINVAL); 3368 3369 err = sysctl_handle_int(oidp, &val, 0, req); 3370 if (err != 0) 3371 return (err); 3372 3373 if (val < 0 || val > 1) 3374 return (EINVAL); 3375 3376 if (val == 1) { 3377 mvneta_sc_lock(sc); 3378 mvneta_clear_mib(sc); 3379 mvneta_sc_unlock(sc); 3380 } 3381 3382 return (0); 3383} 3384 3385STATIC int 3386sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3387{ 3388 struct mvneta_sysctl_queue *arg; 3389 struct mvneta_rx_ring *rx; 3390 struct mvneta_softc *sc; 3391 uint32_t reg, time_mvtclk; 3392 int err, time_us; 3393 3394 rx = NULL; 3395 arg = (struct mvneta_sysctl_queue *)arg1; 3396 if (arg == NULL) 3397 return (EINVAL); 3398 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3399 return (EINVAL); 3400 if (arg->rxtx != MVNETA_SYSCTL_RX) 3401 return (EINVAL); 3402 3403 sc = arg->sc; 3404 if (sc == NULL) 3405 return (EINVAL); 3406 3407 /* read queue length */ 3408 mvneta_sc_lock(sc); 3409 mvneta_rx_lockq(sc, arg->queue); 3410 rx = MVNETA_RX_RING(sc, arg->queue); 3411 time_mvtclk = rx->queue_th_time; 3412 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvneta_get_clk(); 3413 mvneta_rx_unlockq(sc, arg->queue); 3414 mvneta_sc_unlock(sc); 3415 3416 err = sysctl_handle_int(oidp, &time_us, 0, req); 3417 if (err != 0) 3418 return (err); 3419 3420 mvneta_sc_lock(sc); 3421 mvneta_rx_lockq(sc, arg->queue); 3422 3423 /* update queue length (0[sec] - 1[sec]) */ 3424 if (time_us < 0 || time_us > (1000 * 1000)) { 3425 mvneta_rx_unlockq(sc, arg->queue); 3426 mvneta_sc_unlock(sc); 3427 return (EINVAL); 3428 } 3429 time_mvtclk = 3430 (uint64_t)mvneta_get_clk() * (uint64_t)time_us / (1000ULL * 1000ULL); 3431 rx->queue_th_time = time_mvtclk; 3432 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3433 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3434 mvneta_rx_unlockq(sc, arg->queue); 3435 mvneta_sc_unlock(sc); 3436 3437 return (0); 3438} 3439 3440STATIC void 3441sysctl_mvneta_init(struct mvneta_softc *sc) 3442{ 3443 struct sysctl_ctx_list *ctx; 3444 struct sysctl_oid_list *children; 3445 struct sysctl_oid_list *rxchildren; 3446 struct sysctl_oid_list *qchildren, *mchildren; 3447 struct sysctl_oid *tree; 3448 int i, q; 3449 struct mvneta_sysctl_queue *rxarg; 3450#define MVNETA_SYSCTL_NAME(num) "queue" # num 3451 static const char *sysctl_queue_names[] = { 3452 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3453 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3454 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3455 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3456 }; 3457#undef MVNETA_SYSCTL_NAME 3458 3459#ifndef NO_SYSCTL_DESCR 3460#define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3461 static const char *sysctl_queue_descrs[] = { 3462 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3463 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3464 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3465 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3466 }; 3467#undef MVNETA_SYSCTL_DESCR 3468#endif 3469 3470 3471 ctx = device_get_sysctl_ctx(sc->dev); 3472 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3473 3474 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3475 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA RX"); 3476 rxchildren = SYSCTL_CHILDREN(tree); 3477 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3478 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA MIB"); 3479 mchildren = SYSCTL_CHILDREN(tree); 3480 3481 3482 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3483 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3484 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3485 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3486 3487 /* 3488 * MIB access 3489 */ 3490 /* dev.mvneta.[unit].mib.<mibs> */ 3491 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3492 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3493 3494 mib_arg->sc = sc; 3495 mib_arg->index = i; 3496 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3497 mvneta_mib_list[i].sysctl_name, 3498 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3499 (void *)mib_arg, 0, sysctl_read_mib, "I", 3500 mvneta_mib_list[i].desc); 3501 } 3502 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3503 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3504 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3505 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3506 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3507 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3508 3509 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3510 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3511 (void *)sc, 0, sysctl_clear_mib, "I", "Reset MIB counters"); 3512 3513 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3514 rxarg = &sc->sysctl_rx_queue[q]; 3515 3516 rxarg->sc = sc; 3517 rxarg->queue = q; 3518 rxarg->rxtx = MVNETA_SYSCTL_RX; 3519 3520 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3521 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3522 sysctl_queue_names[q], CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 3523 sysctl_queue_descrs[q]); 3524 qchildren = SYSCTL_CHILDREN(tree); 3525 3526 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3527 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3528 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, rxarg, 0, 3529 sysctl_set_queue_rxthtime, "I", 3530 "interrupt coalescing threshold timer [us]"); 3531 } 3532} 3533 3534/* 3535 * MIB 3536 */ 3537STATIC uint64_t 3538mvneta_read_mib(struct mvneta_softc *sc, int index) 3539{ 3540 struct mvneta_mib_def *mib; 3541 uint64_t val; 3542 3543 mib = &mvneta_mib_list[index]; 3544 val = MVNETA_READ_MIB(sc, mib->regnum); 3545 if (mib->reg64) 3546 val |= (uint64_t)MVNETA_READ_MIB(sc, mib->regnum + 4) << 32; 3547 return (val); 3548} 3549 3550STATIC void 3551mvneta_clear_mib(struct mvneta_softc *sc) 3552{ 3553 int i; 3554 3555 KASSERT_SC_MTX(sc); 3556 3557 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3558 (void)mvneta_read_mib(sc, i); 3559 sc->sysctl_mib[i].counter = 0; 3560 } 3561 MVNETA_READ(sc, MVNETA_PDFC); 3562 sc->counter_pdfc = 0; 3563 MVNETA_READ(sc, MVNETA_POFC); 3564 sc->counter_pofc = 0; 3565 sc->counter_watchdog = 0; 3566} 3567 3568STATIC void 3569mvneta_update_mib(struct mvneta_softc *sc) 3570{ 3571 struct mvneta_tx_ring *tx; 3572 int i; 3573 uint64_t val; 3574 uint32_t reg; 3575 3576 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3577 3578 val = mvneta_read_mib(sc, i); 3579 if (val == 0) 3580 continue; 3581 3582 sc->sysctl_mib[i].counter += val; 3583 switch (mvneta_mib_list[i].regnum) { 3584 case MVNETA_MIB_RX_GOOD_OCT: 3585 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3586 break; 3587 case MVNETA_MIB_RX_BAD_FRAME: 3588 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3589 break; 3590 case MVNETA_MIB_RX_GOOD_FRAME: 3591 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3592 break; 3593 case MVNETA_MIB_RX_MCAST_FRAME: 3594 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3595 break; 3596 case MVNETA_MIB_TX_GOOD_OCT: 3597 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3598 break; 3599 case MVNETA_MIB_TX_GOOD_FRAME: 3600 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3601 break; 3602 case MVNETA_MIB_TX_MCAST_FRAME: 3603 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3604 break; 3605 case MVNETA_MIB_MAC_COL: 3606 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3607 break; 3608 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3609 case MVNETA_MIB_TX_EXCES_COL: 3610 case MVNETA_MIB_MAC_LATE_COL: 3611 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3612 break; 3613 } 3614 } 3615 3616 reg = MVNETA_READ(sc, MVNETA_PDFC); 3617 sc->counter_pdfc += reg; 3618 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3619 reg = MVNETA_READ(sc, MVNETA_POFC); 3620 sc->counter_pofc += reg; 3621 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3622 3623 /* TX watchdog. */ 3624 if (sc->counter_watchdog_mib > 0) { 3625 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3626 sc->counter_watchdog_mib = 0; 3627 } 3628 /* 3629 * TX driver errors: 3630 * We do not take queue locks to not disrupt TX path. 3631 * We may only miss one drv error which will be fixed at 3632 * next mib update. We may also clear counter when TX path 3633 * is incrementing it but we only do it if counter was not zero 3634 * thus we may only loose one error. 3635 */ 3636 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3637 tx = MVNETA_TX_RING(sc, i); 3638 3639 if (tx->drv_error > 0) { 3640 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3641 tx->drv_error = 0; 3642 } 3643 } 3644} 3645