1/******************************************************************************* 2SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 4Copyright (c) 2006-2009, Myricom Inc. 5All rights reserved. 6 7Redistribution and use in source and binary forms, with or without 8modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Neither the name of the Myricom Inc, nor the names of its 14 contributors may be used to endorse or promote products derived from 15 this software without specific prior written permission. 16 17THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27POSSIBILITY OF SUCH DAMAGE. 28 29$FreeBSD$ 30***************************************************************************/ 31 32#ifndef _myri10ge_mcp_h 33#define _myri10ge_mcp_h 34 35#define MXGEFW_VERSION_MAJOR 1 36#define MXGEFW_VERSION_MINOR 4 37 38#if defined MXGEFW && !defined _stdint_h_ 39typedef signed char int8_t; 40typedef signed short int16_t; 41typedef signed int int32_t; 42typedef signed long long int64_t; 43typedef unsigned char uint8_t; 44typedef unsigned short uint16_t; 45typedef unsigned int uint32_t; 46typedef unsigned long long uint64_t; 47#endif 48 49/* 8 Bytes */ 50struct mcp_dma_addr { 51 uint32_t high; 52 uint32_t low; 53}; 54typedef struct mcp_dma_addr mcp_dma_addr_t; 55 56/* 4 Bytes */ 57struct mcp_slot { 58 uint16_t checksum; 59 uint16_t length; 60}; 61typedef struct mcp_slot mcp_slot_t; 62 63#ifdef MXGEFW_NDIS 64/* 8-byte descriptor, exclusively used by NDIS drivers. */ 65struct mcp_slot_8 { 66 /* Place hash value at the top so it gets written before length. 67 * The driver polls length. 68 */ 69 uint32_t hash; 70 uint16_t checksum; 71 uint16_t length; 72}; 73typedef struct mcp_slot_8 mcp_slot_8_t; 74 75/* Two bits of length in mcp_slot are used to indicate hash type. */ 76#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 77#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 78#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 79#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 80#endif 81 82/* 64 Bytes */ 83struct mcp_cmd { 84 uint32_t cmd; 85 uint32_t data0; /* will be low portion if data > 32 bits */ 86 /* 8 */ 87 uint32_t data1; /* will be high portion if data > 32 bits */ 88 uint32_t data2; /* currently unused.. */ 89 /* 16 */ 90 struct mcp_dma_addr response_addr; 91 /* 24 */ 92 uint8_t pad[40]; 93}; 94typedef struct mcp_cmd mcp_cmd_t; 95 96/* 8 Bytes */ 97struct mcp_cmd_response { 98 uint32_t data; 99 uint32_t result; 100}; 101typedef struct mcp_cmd_response mcp_cmd_response_t; 102 103/* 104 flags used in mcp_kreq_ether_send_t: 105 106 The SMALL flag is only needed in the first segment. It is raised 107 for packets that are total less or equal 512 bytes. 108 109 The CKSUM flag must be set in all segments. 110 111 The PADDED flags is set if the packet needs to be padded, and it 112 must be set for all segments. 113 114 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 115 length of all previous segments was odd. 116*/ 117 118#define MXGEFW_FLAGS_SMALL 0x1 119#define MXGEFW_FLAGS_TSO_HDR 0x1 120#define MXGEFW_FLAGS_FIRST 0x2 121#define MXGEFW_FLAGS_ALIGN_ODD 0x4 122#define MXGEFW_FLAGS_CKSUM 0x8 123#define MXGEFW_FLAGS_TSO_LAST 0x8 124#define MXGEFW_FLAGS_NO_TSO 0x10 125#define MXGEFW_FLAGS_TSO_CHOP 0x10 126#define MXGEFW_FLAGS_TSO_PLD 0x20 127 128#define MXGEFW_SEND_SMALL_SIZE 1520 129#define MXGEFW_MAX_MTU 9400 130 131union mcp_pso_or_cumlen { 132 uint16_t pseudo_hdr_offset; 133 uint16_t cum_len; 134}; 135typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 136 137#define MXGEFW_MAX_SEND_DESC 12 138#define MXGEFW_PAD 2 139 140/* 16 Bytes */ 141struct mcp_kreq_ether_send { 142 uint32_t addr_high; 143 uint32_t addr_low; 144 uint16_t pseudo_hdr_offset; 145 uint16_t length; 146 uint8_t pad; 147 uint8_t rdma_count; 148 uint8_t cksum_offset; /* where to start computing cksum */ 149 uint8_t flags; /* as defined above */ 150}; 151typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 152 153/* 8 Bytes */ 154struct mcp_kreq_ether_recv { 155 uint32_t addr_high; 156 uint32_t addr_low; 157}; 158typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 159 160/* Commands */ 161 162#define MXGEFW_BOOT_HANDOFF 0xfc0000 163#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 164 165#define MXGEFW_ETH_CMD 0xf80000 166#define MXGEFW_ETH_SEND_4 0x200000 167#define MXGEFW_ETH_SEND_1 0x240000 168#define MXGEFW_ETH_SEND_2 0x280000 169#define MXGEFW_ETH_SEND_3 0x2c0000 170#define MXGEFW_ETH_RECV_SMALL 0x300000 171#define MXGEFW_ETH_RECV_BIG 0x340000 172#define MXGEFW_ETH_SEND_GO 0x380000 173#define MXGEFW_ETH_SEND_STOP 0x3C0000 174 175#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 176#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 177 178enum myri10ge_mcp_cmd_type { 179 MXGEFW_CMD_NONE = 0, 180 /* Reset the mcp, it is left in a safe state, waiting 181 for the driver to set all its parameters */ 182 MXGEFW_CMD_RESET = 1, 183 184 /* get the version number of the current firmware.. 185 (may be available in the eeprom strings..? */ 186 MXGEFW_GET_MCP_VERSION = 2, 187 188 /* Parameters which must be set by the driver before it can 189 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 190 MXGEFW_CMD_RESET is issued */ 191 192 MXGEFW_CMD_SET_INTRQ_DMA = 3, 193 /* data0 = LSW of the host address 194 * data1 = MSW of the host address 195 * data2 = slice number if multiple slices are used 196 */ 197 198 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 199 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 200 201 202 /* Parameters which refer to lanai SRAM addresses where the 203 driver must issue PIO writes for various things */ 204 205 MXGEFW_CMD_GET_SEND_OFFSET = 6, 206 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 207 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 208 /* data0 = slice number if multiple slices are used */ 209 210 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 211 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 212 213 /* Parameters which refer to rings stored on the MCP, 214 and whose size is controlled by the mcp */ 215 216 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 217 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 218 219 /* Parameters which refer to rings stored in the host, 220 and whose size is controlled by the host. Note that 221 all must be physically contiguous and must contain 222 a power of 2 number of entries. */ 223 224 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 225#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) 226 227 /* command to bring ethernet interface up. Above parameters 228 (plus mtu & mac address) must have been exchanged prior 229 to issuing this command */ 230 MXGEFW_CMD_ETHERNET_UP = 14, 231 232 /* command to bring ethernet interface down. No further sends 233 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 234 is issued, and all interrupt queues must be flushed prior 235 to ack'ing this command */ 236 237 MXGEFW_CMD_ETHERNET_DOWN = 15, 238 239 /* commands the driver may issue live, without resetting 240 the nic. Note that increasing the mtu "live" should 241 only be done if the driver has already supplied buffers 242 sufficiently large to handle the new mtu. Decreasing 243 the mtu live is safe */ 244 245 MXGEFW_CMD_SET_MTU = 16, 246 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 247 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 248 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 249 250 MXGEFW_ENABLE_PROMISC = 20, 251 MXGEFW_DISABLE_PROMISC = 21, 252 MXGEFW_SET_MAC_ADDRESS = 22, 253 254 MXGEFW_ENABLE_FLOW_CONTROL = 23, 255 MXGEFW_DISABLE_FLOW_CONTROL = 24, 256 257 /* do a DMA test 258 data0,data1 = DMA address 259 data2 = RDMA length (MSH), WDMA length (LSH) 260 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 261 */ 262 MXGEFW_DMA_TEST = 25, 263 264 MXGEFW_ENABLE_ALLMULTI = 26, 265 MXGEFW_DISABLE_ALLMULTI = 27, 266 267 /* returns MXGEFW_CMD_ERROR_MULTICAST 268 if there is no room in the cache 269 data0,MSH(data1) = multicast group address */ 270 MXGEFW_JOIN_MULTICAST_GROUP = 28, 271 /* returns MXGEFW_CMD_ERROR_MULTICAST 272 if the address is not in the cache, 273 or is equal to FF-FF-FF-FF-FF-FF 274 data0,MSH(data1) = multicast group address */ 275 MXGEFW_LEAVE_MULTICAST_GROUP = 29, 276 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 277 278 MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 279 /* data0, data1 = bus addr, 280 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 281 * adding new stuff to mcp_irq_data without changing the ABI 282 * 283 * If multiple slices are used, data2 contains both the size of the 284 * structure (in the lower 16 bits) and the slice number 285 * (in the upper 16 bits). 286 */ 287 288 MXGEFW_CMD_UNALIGNED_TEST = 32, 289 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 290 chipset */ 291 292 MXGEFW_CMD_UNALIGNED_STATUS = 33, 293 /* return data = boolean, true if the chipset is known to be unaligned */ 294 295 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 296 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 297 * 0 indicates that the NIC consumes as many buffers as they are required 298 * for packet. This is the default behavior. 299 * A power of 2 number indicates that the NIC always uses the specified 300 * number of buffers for each big receive packet. 301 * It is up to the driver to ensure that this value is big enough for 302 * the NIC to be able to receive maximum-sized packets. 303 */ 304 305 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 306 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 307 /* data0 = number of slices n (0, 1, ..., n-1) to enable 308 * data1 = interrupt mode | use of multiple transmit queues. 309 * 0=share one INTx/MSI. 310 * 1=use one MSI-X per queue. 311 * If all queues share one interrupt, the driver must have set 312 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 313 * 2=enable both receive and send queues. 314 * Without this bit set, only one send queue (slice 0's send queue) 315 * is enabled. The receive queues are always enabled. 316 */ 317#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 318#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 319#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 320 321 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 322 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 323 /* data0, data1 = bus address lsw, msw */ 324 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 325 /* get the offset of the indirection table */ 326 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 327 /* set the size of the indirection table */ 328 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 329 /* get the offset of the secret key */ 330 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 331 /* tell nic that the secret key's been updated */ 332 MXGEFW_CMD_SET_RSS_ENABLE = 43, 333 /* data0 = enable/disable rss 334 * 0: disable rss. nic does not distribute receive packets. 335 * 1: enable rss. nic distributes receive packets among queues. 336 * data1 = hash type 337 * 1: IPV4 (required by RSS) 338 * 2: TCP_IPV4 (required by RSS) 339 * 3: IPV4 | TCP_IPV4 (required by RSS) 340 * 4: source port 341 * 5: source port + destination port 342 */ 343#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 344#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 345#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 346#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 347#define MXGEFW_RSS_HASH_TYPE_MAX 0x5 348 349 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 350 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 351 * If the header size of a IPv6 TSO packet is larger than the specified 352 * value, then the driver must not use TSO. 353 * This size restriction only applies to IPv6 TSO. 354 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 355 * always has enough header buffer to store maximum-sized headers. 356 */ 357 358 MXGEFW_CMD_SET_TSO_MODE = 45, 359 /* data0 = TSO mode. 360 * 0: Linux/FreeBSD style (NIC default) 361 * 1: NDIS/NetBSD style 362 */ 363#define MXGEFW_TSO_MODE_LINUX 0 364#define MXGEFW_TSO_MODE_NDIS 1 365 366 MXGEFW_CMD_MDIO_READ = 46, 367 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 368 MXGEFW_CMD_MDIO_WRITE = 47, 369 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 370 371 MXGEFW_CMD_I2C_READ = 48, 372 /* Starts to get a fresh copy of one byte or of the module i2c table, the 373 * obtained data is cached inside the xaui-xfi chip : 374 * data0 : 0 => get one byte, 1=> get 256 bytes 375 * data1 : If data0 == 0: location to refresh 376 * bit 7:0 register location 377 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 378 * bit 23:16 is the i2c bus number (for multi-port NICs) 379 * If data0 == 1: unused 380 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 381 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 382 * will return MXGEFW_CMD_ERROR_BUSY 383 */ 384 MXGEFW_CMD_I2C_BYTE = 49, 385 /* Return the last obtained copy of a given byte in the xfp i2c table 386 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 387 * data0 : index of the desired table entry 388 * Return data = the byte stored at the requested index in the table 389 */ 390 391 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 392 /* Return data = NIC memory offset of mcp_vpump_public_global */ 393 MXGEFW_CMD_RESET_VPUMP = 51, 394 /* Resets the VPUMP state */ 395 396 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 397 /* data0 = mcp_slot type to use. 398 * 0 = the default 4B mcp_slot 399 * 1 = 8B mcp_slot_8 400 */ 401#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 402#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 403 404 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 405 /* set the throttle factor for ethp_z8e 406 data0 = throttle_factor 407 throttle_factor = 256 * pcie-raw-speed / tx_speed 408 tx_speed = 256 * pcie-raw-speed / throttle_factor 409 410 For PCI-E x8: pcie-raw-speed == 16Gb/s 411 For PCI-E x4: pcie-raw-speed == 8Gb/s 412 413 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 414 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 415 416 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 417 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 418 */ 419 420 MXGEFW_CMD_VPUMP_UP = 54, 421 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 422 MXGEFW_CMD_GET_VPUMP_CLK = 55, 423 /* Get the lanai clock */ 424 425 MXGEFW_CMD_GET_DCA_OFFSET = 56, 426 /* offset of dca control for WDMAs */ 427 428 /* VMWare NetQueue commands */ 429 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 430 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 431 /* data0 = filter_id << 16 | queue << 8 | type */ 432 /* data1 = MS4 of MAC Addr */ 433 /* data2 = LS2_MAC << 16 | VLAN_tag */ 434 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 435 /* data0 = filter_id */ 436 MXGEFW_CMD_NETQ_QUERY1 = 60, 437 MXGEFW_CMD_NETQ_QUERY2 = 61, 438 MXGEFW_CMD_NETQ_QUERY3 = 62, 439 MXGEFW_CMD_NETQ_QUERY4 = 63, 440 441 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 442 /* When set, small receive buffers can cross page boundaries. 443 * Both small and big receive buffers may start at any address. 444 * This option has performance implications, so use with caution. 445 */ 446}; 447typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 448 449enum myri10ge_mcp_cmd_status { 450 MXGEFW_CMD_OK = 0, 451 MXGEFW_CMD_UNKNOWN = 1, 452 MXGEFW_CMD_ERROR_RANGE = 2, 453 MXGEFW_CMD_ERROR_BUSY = 3, 454 MXGEFW_CMD_ERROR_EMPTY = 4, 455 MXGEFW_CMD_ERROR_CLOSED = 5, 456 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 457 MXGEFW_CMD_ERROR_BAD_PORT = 7, 458 MXGEFW_CMD_ERROR_RESOURCES = 8, 459 MXGEFW_CMD_ERROR_MULTICAST = 9, 460 MXGEFW_CMD_ERROR_UNALIGNED = 10, 461 MXGEFW_CMD_ERROR_NO_MDIO = 11, 462 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 463 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 464 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 465}; 466typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 467 468#define MXGEFW_OLD_IRQ_DATA_LEN 40 469 470struct mcp_irq_data { 471 /* add new counters at the beginning */ 472 uint32_t future_use[1]; 473 uint32_t dropped_pause; 474 uint32_t dropped_unicast_filtered; 475 uint32_t dropped_bad_crc32; 476 uint32_t dropped_bad_phy; 477 uint32_t dropped_multicast_filtered; 478/* 40 Bytes */ 479 uint32_t send_done_count; 480 481#define MXGEFW_LINK_DOWN 0 482#define MXGEFW_LINK_UP 1 483#define MXGEFW_LINK_MYRINET 2 484#define MXGEFW_LINK_UNKNOWN 3 485 uint32_t link_up; 486 uint32_t dropped_link_overflow; 487 uint32_t dropped_link_error_or_filtered; 488 uint32_t dropped_runt; 489 uint32_t dropped_overrun; 490 uint32_t dropped_no_small_buffer; 491 uint32_t dropped_no_big_buffer; 492 uint32_t rdma_tags_available; 493 494 uint8_t tx_stopped; 495 uint8_t link_down; 496 uint8_t stats_updated; 497 uint8_t valid; 498}; 499typedef struct mcp_irq_data mcp_irq_data_t; 500 501#ifdef MXGEFW_NDIS 502/* Exclusively used by NDIS drivers */ 503struct mcp_rss_shared_interrupt { 504 uint8_t pad[2]; 505 uint8_t queue; 506 uint8_t valid; 507}; 508#endif 509 510/* definitions for NETQ filter type */ 511#define MXGEFW_NETQ_FILTERTYPE_NONE 0 512#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 513#define MXGEFW_NETQ_FILTERTYPE_VLAN 2 514#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 515 516#endif /* _myri10ge_mcp_h */ 517