1/*-
2 * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 * $FreeBSD$
33 */
34
35#ifndef MLX5_IFC_FPGA_H
36#define MLX5_IFC_FPGA_H
37
38enum {
39	MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
40};
41
42enum {
43	MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_EXAMPLE  = 0x1,
44	MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC    = 0x2,
45	MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS      = 0x3,
46};
47
48enum {
49	MLX5_FPGA_SHELL_CAPS_QP_TYPE_SHELL_QP    = 0x1,
50	MLX5_FPGA_SHELL_CAPS_QP_TYPE_SANDBOX_QP  = 0x2,
51};
52
53struct mlx5_ifc_fpga_shell_caps_bits {
54	u8         max_num_qps[0x10];
55	u8         reserved_at_10[0x8];
56	u8         total_rcv_credits[0x8];
57
58	u8         reserved_at_20[0xe];
59	u8         qp_type[0x2];
60	u8         reserved_at_30[0x5];
61	u8         rae[0x1];
62	u8         rwe[0x1];
63	u8         rre[0x1];
64	u8         reserved_at_38[0x4];
65	u8         dc[0x1];
66	u8         ud[0x1];
67	u8         uc[0x1];
68	u8         rc[0x1];
69
70	u8         reserved_at_40[0x1a];
71	u8         log_ddr_size[0x6];
72
73	u8         max_fpga_qp_msg_size[0x20];
74
75	u8         reserved_at_80[0x180];
76};
77
78struct mlx5_ifc_fpga_cap_bits {
79	u8         fpga_id[0x8];
80	u8         fpga_device[0x18];
81
82	u8         register_file_ver[0x20];
83
84	u8         fpga_ctrl_modify[0x1];
85	u8         reserved_at_41[0x5];
86	u8         access_reg_query_mode[0x2];
87	u8         reserved_at_48[0x6];
88	u8         access_reg_modify_mode[0x2];
89	u8         reserved_at_50[0x10];
90
91	u8         reserved_at_60[0x20];
92
93	u8         image_version[0x20];
94
95	u8         image_date[0x20];
96
97	u8         image_time[0x20];
98
99	u8         shell_version[0x20];
100
101	u8         reserved_at_100[0x80];
102
103	struct mlx5_ifc_fpga_shell_caps_bits shell_caps;
104
105	u8         reserved_at_380[0x8];
106	u8         ieee_vendor_id[0x18];
107
108	u8         sandbox_product_version[0x10];
109	u8         sandbox_product_id[0x10];
110
111	u8         sandbox_basic_caps[0x20];
112
113	u8         reserved_at_3e0[0x10];
114	u8         sandbox_extended_caps_len[0x10];
115
116	u8         sandbox_extended_caps_addr[0x40];
117
118	u8         fpga_ddr_start_addr[0x40];
119
120	u8         fpga_cr_space_start_addr[0x40];
121
122	u8         fpga_ddr_size[0x20];
123
124	u8         fpga_cr_space_size[0x20];
125
126	u8         reserved_at_500[0x300];
127};
128
129enum {
130	MLX5_FPGA_CTRL_OPERATION_LOAD                = 0x1,
131	MLX5_FPGA_CTRL_OPERATION_RESET               = 0x2,
132	MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT        = 0x3,
133	MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON   = 0x4,
134	MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF  = 0x5,
135	MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX       = 0x6,
136	MLX5_FPGA_CTRL_OPERATION_DISCONNECT          = 0x9,
137	MLX5_FPGA_CTRL_OPERATION_CONNECT             = 0xA,
138	MLX5_FPGA_CTRL_OPERATION_RELOAD              = 0xB,
139};
140
141struct mlx5_ifc_fpga_ctrl_bits {
142	u8         reserved_at_0[0x8];
143	u8         operation[0x8];
144	u8         reserved_at_10[0x8];
145	u8         status[0x8];
146
147	u8         reserved_at_20[0x8];
148	u8         flash_select_admin[0x8];
149	u8         reserved_at_30[0x8];
150	u8         flash_select_oper[0x8];
151
152	u8         reserved_at_40[0x40];
153};
154
155enum {
156	MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR        = 0x1,
157	MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT        = 0x2,
158	MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR  = 0x3,
159	MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE     = 0x4,
160	MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE          = 0x5,
161	MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED        = 0x6,
162	MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
163};
164
165struct mlx5_ifc_fpga_error_event_bits {
166	u8         reserved_at_0[0x40];
167
168	u8         reserved_at_40[0x18];
169	u8         syndrome[0x8];
170
171	u8         reserved_at_60[0x80];
172};
173
174#define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
175
176struct mlx5_ifc_fpga_access_reg_bits {
177	u8         reserved_at_0[0x20];
178
179	u8         reserved_at_20[0x10];
180	u8         size[0x10];
181
182	u8         address[0x40];
183
184	u8         data[0][0x8];
185};
186
187enum mlx5_ifc_fpga_qp_state {
188	MLX5_FPGA_QPC_STATE_INIT    = 0x0,
189	MLX5_FPGA_QPC_STATE_ACTIVE  = 0x1,
190	MLX5_FPGA_QPC_STATE_ERROR   = 0x2,
191};
192
193enum mlx5_ifc_fpga_qp_type {
194	MLX5_FPGA_QPC_QP_TYPE_SHELL_QP    = 0x0,
195	MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP  = 0x1,
196};
197
198enum mlx5_ifc_fpga_qp_service_type {
199	MLX5_FPGA_QPC_ST_RC  = 0x0,
200};
201
202struct mlx5_ifc_fpga_qpc_bits {
203	u8         state[0x4];
204	u8         reserved_at_4[0x1b];
205	u8         qp_type[0x1];
206
207	u8         reserved_at_20[0x4];
208	u8         st[0x4];
209	u8         reserved_at_28[0x10];
210	u8         traffic_class[0x8];
211
212	u8         ether_type[0x10];
213	u8         prio[0x3];
214	u8         dei[0x1];
215	u8         vid[0xc];
216
217	u8         reserved_at_60[0x20];
218
219	u8         reserved_at_80[0x8];
220	u8         next_rcv_psn[0x18];
221
222	u8         reserved_at_a0[0x8];
223	u8         next_send_psn[0x18];
224
225	u8         reserved_at_c0[0x10];
226	u8         pkey[0x10];
227
228	u8         reserved_at_e0[0x8];
229	u8         remote_qpn[0x18];
230
231	u8         reserved_at_100[0x15];
232	u8         rnr_retry[0x3];
233	u8         reserved_at_118[0x5];
234	u8         retry_count[0x3];
235
236	u8         reserved_at_120[0x20];
237
238	u8         reserved_at_140[0x10];
239	u8         remote_mac_47_32[0x10];
240
241	u8         remote_mac_31_0[0x20];
242
243	u8         remote_ip[16][0x8];
244
245	u8         reserved_at_200[0x40];
246
247	u8         reserved_at_240[0x10];
248	u8         fpga_mac_47_32[0x10];
249
250	u8         fpga_mac_31_0[0x20];
251
252	u8         fpga_ip[16][0x8];
253};
254
255struct mlx5_ifc_fpga_create_qp_in_bits {
256	u8         opcode[0x10];
257	u8         reserved_at_10[0x10];
258
259	u8         reserved_at_20[0x10];
260	u8         op_mod[0x10];
261
262	u8         reserved_at_40[0x40];
263
264	struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
265};
266
267struct mlx5_ifc_fpga_create_qp_out_bits {
268	u8         status[0x8];
269	u8         reserved_at_8[0x18];
270
271	u8         syndrome[0x20];
272
273	u8         reserved_at_40[0x8];
274	u8         fpga_qpn[0x18];
275
276	u8         reserved_at_60[0x20];
277
278	struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
279};
280
281struct mlx5_ifc_fpga_modify_qp_in_bits {
282	u8         opcode[0x10];
283	u8         reserved_at_10[0x10];
284
285	u8         reserved_at_20[0x10];
286	u8         op_mod[0x10];
287
288	u8         reserved_at_40[0x8];
289	u8         fpga_qpn[0x18];
290
291	u8         field_select[0x20];
292
293	struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
294};
295
296struct mlx5_ifc_fpga_modify_qp_out_bits {
297	u8         status[0x8];
298	u8         reserved_at_8[0x18];
299
300	u8         syndrome[0x20];
301
302	u8         reserved_at_40[0x40];
303};
304
305struct mlx5_ifc_fpga_query_qp_in_bits {
306	u8         opcode[0x10];
307	u8         reserved_at_10[0x10];
308
309	u8         reserved_at_20[0x10];
310	u8         op_mod[0x10];
311
312	u8         reserved_at_40[0x8];
313	u8         fpga_qpn[0x18];
314
315	u8         reserved_at_60[0x20];
316};
317
318struct mlx5_ifc_fpga_query_qp_out_bits {
319	u8         status[0x8];
320	u8         reserved_at_8[0x18];
321
322	u8         syndrome[0x20];
323
324	u8         reserved_at_40[0x40];
325
326	struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
327};
328
329struct mlx5_ifc_fpga_query_qp_counters_in_bits {
330	u8         opcode[0x10];
331	u8         reserved_at_10[0x10];
332
333	u8         reserved_at_20[0x10];
334	u8         op_mod[0x10];
335
336	u8         clear[0x1];
337	u8         reserved_at_41[0x7];
338	u8         fpga_qpn[0x18];
339
340	u8         reserved_at_60[0x20];
341};
342
343struct mlx5_ifc_fpga_query_qp_counters_out_bits {
344	u8         status[0x8];
345	u8         reserved_at_8[0x18];
346
347	u8         syndrome[0x20];
348
349	u8         reserved_at_40[0x40];
350
351	u8         rx_ack_packets[0x40];
352
353	u8         rx_send_packets[0x40];
354
355	u8         tx_ack_packets[0x40];
356
357	u8         tx_send_packets[0x40];
358
359	u8         rx_total_drop[0x40];
360
361	u8         reserved_at_1c0[0x1c0];
362};
363
364struct mlx5_ifc_fpga_destroy_qp_in_bits {
365	u8         opcode[0x10];
366	u8         reserved_at_10[0x10];
367
368	u8         reserved_at_20[0x10];
369	u8         op_mod[0x10];
370
371	u8         reserved_at_40[0x8];
372	u8         fpga_qpn[0x18];
373
374	u8         reserved_at_60[0x20];
375};
376
377struct mlx5_ifc_fpga_destroy_qp_out_bits {
378	u8         status[0x8];
379	u8         reserved_at_8[0x18];
380
381	u8         syndrome[0x20];
382
383	u8         reserved_at_40[0x40];
384};
385
386struct mlx5_ifc_ipsec_extended_cap_bits {
387	u8         encapsulation[0x20];
388
389	u8         reserved_0[0x15];
390	u8         ipv4_fragment[0x1];
391	u8         ipv6[0x1];
392	u8         esn[0x1];
393	u8         lso[0x1];
394	u8         transport_and_tunnel_mode[0x1];
395	u8         tunnel_mode[0x1];
396	u8         transport_mode[0x1];
397	u8         ah_esp[0x1];
398	u8         esp[0x1];
399	u8         ah[0x1];
400	u8         ipv4_options[0x1];
401
402	u8         auth_alg[0x20];
403
404	u8         enc_alg[0x20];
405
406	u8         sa_cap[0x20];
407
408	u8         reserved_1[0x10];
409	u8         number_of_ipsec_counters[0x10];
410
411	u8         ipsec_counters_addr_low[0x20];
412	u8         ipsec_counters_addr_high[0x20];
413};
414
415struct mlx5_ifc_ipsec_counters_bits {
416	u8         dec_in_packets[0x40];
417
418	u8         dec_out_packets[0x40];
419
420	u8         dec_bypass_packets[0x40];
421
422	u8         enc_in_packets[0x40];
423
424	u8         enc_out_packets[0x40];
425
426	u8         enc_bypass_packets[0x40];
427
428	u8         drop_dec_packets[0x40];
429
430	u8         failed_auth_dec_packets[0x40];
431
432	u8         drop_enc_packets[0x40];
433
434	u8         success_add_sa[0x40];
435
436	u8         fail_add_sa[0x40];
437
438	u8         success_delete_sa[0x40];
439
440	u8         fail_delete_sa[0x40];
441
442	u8         dropped_cmd[0x40];
443};
444
445struct mlx5_ifc_fpga_shell_counters_bits {
446	u8         reserved_0[0x20];
447
448	u8         clear[0x1];
449	u8         reserved_1[0x1f];
450
451	u8         reserved_2[0x40];
452
453	u8         ddr_read_requests[0x40];
454
455	u8         ddr_write_requests[0x40];
456
457	u8         ddr_read_bytes[0x40];
458
459	u8         ddr_write_bytes[0x40];
460
461	u8         reserved_3[0x200];
462};
463
464enum {
465	MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ            = 0x0,
466	MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE           = 0x1,
467	MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ_RESPONSE   = 0x2,
468	MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE_RESPONSE  = 0x3,
469};
470
471struct mlx5_ifc_fpga_shell_qp_packet_bits {
472	u8         version[0x4];
473	u8         syndrome[0x4];
474	u8         reserved_at_8[0x4];
475	u8         type[0x4];
476	u8         reserved_at_10[0x8];
477	u8         tid[0x8];
478
479	u8         len[0x20];
480
481	u8         address[0x40];
482
483	u8         data[0][0x8];
484};
485
486enum {
487	MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED  = 0x1,
488	MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED            = 0x2,
489};
490
491struct mlx5_ifc_fpga_qp_error_event_bits {
492	u8         reserved_0[0x40];
493
494	u8         reserved_1[0x18];
495	u8         syndrome[0x8];
496
497	u8         reserved_2[0x60];
498
499	u8         reserved_3[0x8];
500	u8         fpga_qpn[0x18];
501};
502
503#endif /* MLX5_IFC_FPGA_H */
504