1/******************************************************************************
2  SPDX-License-Identifier: BSD-3-Clause
3
4  Copyright (c) 2001-2017, Intel Corporation
5  All rights reserved.
6
7  Redistribution and use in source and binary forms, with or without
8  modification, are permitted provided that the following conditions are met:
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10   1. Redistributions of source code must retain the above copyright notice,
11      this list of conditions and the following disclaimer.
12
13   2. Redistributions in binary form must reproduce the above copyright
14      notice, this list of conditions and the following disclaimer in the
15      documentation and/or other materials provided with the distribution.
16
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18      contributors may be used to endorse or promote products derived from
19      this software without specific prior written permission.
20
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32
33******************************************************************************/
34/*$FreeBSD$*/
35
36#ifndef _IXGBE_API_H_
37#define _IXGBE_API_H_
38
39#include "ixgbe_type.h"
40
41void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map);
42
43s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
44
45extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
46extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
47extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
48extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);
49extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);
50extern s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw);
51extern s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw);
52
53s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
54s32 ixgbe_init_hw(struct ixgbe_hw *hw);
55s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
56s32 ixgbe_start_hw(struct ixgbe_hw *hw);
57void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw);
58s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
59enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
60s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
61s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
62u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
63u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
64s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
65s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
66s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
67
68s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
69s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
70s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
71		       u16 *phy_data);
72s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
73			u16 phy_data);
74
75s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
76s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw);
77s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
78			 ixgbe_link_speed *speed,
79			 bool *link_up);
80s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
81			       ixgbe_link_speed speed,
82			       bool autoneg_wait_to_complete);
83s32 ixgbe_set_phy_power(struct ixgbe_hw *, bool on);
84void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
85void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
86void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
87s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
88		     bool autoneg_wait_to_complete);
89s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
90			 bool autoneg_wait_to_complete);
91s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
92		     bool *link_up, bool link_up_wait_to_complete);
93s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
94				bool *autoneg);
95s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
96s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
97s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
98s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
99
100s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
101s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
102s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
103			      u16 words, u16 *data);
104s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
105s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
106			     u16 words, u16 *data);
107
108s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
109s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
110
111s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
112s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
113		  u32 enable_addr);
114s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
115s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
116s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
117s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
118s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
119u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
120s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
121			      u32 addr_count, ixgbe_mc_addr_itr func);
122s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
123			      u32 mc_addr_count, ixgbe_mc_addr_itr func,
124			      bool clear);
125void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
126s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
127s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
128s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
129s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
130		   u32 vind, bool vlan_on, bool vlvf_bypass);
131s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
132		   bool vlan_on, u32 *vfta_delta, u32 vfta,
133		   bool vlvf_bypass);
134s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
135s32 ixgbe_setup_fc(struct ixgbe_hw *hw);
136s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
137			 u8 ver, u16 len, char *driver_ver);
138void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
139s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
140				   u16 *firmware_version);
141s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
142s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
143s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
144s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
145u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
146s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
147s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
148s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
149s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
150s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
151s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
152s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
153					bool cloud_mode);
154void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
155					   union ixgbe_atr_hash_dword input,
156					   union ixgbe_atr_hash_dword common,
157					   u8 queue);
158s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
159				    union ixgbe_atr_input *input_mask, bool cloud_mode);
160s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
161					  union ixgbe_atr_input *input,
162					  u16 soft_id, u8 queue, bool cloud_mode);
163s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
164					  union ixgbe_atr_input *input,
165					  u16 soft_id);
166s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
167					union ixgbe_atr_input *input,
168					union ixgbe_atr_input *mask,
169					u16 soft_id,
170					u8 queue,
171					bool cloud_mode);
172void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
173					  union ixgbe_atr_input *mask);
174u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
175				     union ixgbe_atr_hash_dword common);
176bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
177s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
178			u8 *data);
179s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
180				 u8 dev_addr, u8 *data);
181s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
182s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
183s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
184			 u8 data);
185void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue);
186s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
187				  u8 dev_addr, u8 data);
188s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
189s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
190s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
191s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
192s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
193s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
194s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
195void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
196void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw);
197s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
198			 u16 *wwpn_prefix);
199s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
200s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status);
201s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);
202s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value);
203bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg);
204s32 ixgbe_dmac_config(struct ixgbe_hw *hw);
205s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw);
206s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw);
207s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee);
208void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
209				      unsigned int vf);
210void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable,
211				       int vf);
212s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
213			u32 device_type, u32 *phy_data);
214s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
215			u32 device_type, u32 phy_data);
216void ixgbe_disable_mdd(struct ixgbe_hw *hw);
217void ixgbe_enable_mdd(struct ixgbe_hw *hw);
218void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap);
219void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf);
220s32 ixgbe_enter_lplu(struct ixgbe_hw *hw);
221s32 ixgbe_handle_lasi(struct ixgbe_hw *hw);
222void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed);
223void ixgbe_disable_rx(struct ixgbe_hw *hw);
224void ixgbe_enable_rx(struct ixgbe_hw *hw);
225s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
226			u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
227
228#endif /* _IXGBE_API_H_ */
229