1/*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
3 *
4 * This file is provided under a dual BSD/GPLv2 license.  When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 * The full GNU General Public License is included in this distribution
24 * in the file called LICENSE.GPL.
25 *
26 * BSD LICENSE
27 *
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
29 * All rights reserved.
30 *
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
33 * are met:
34 *
35 *   * Redistributions of source code must retain the above copyright
36 *     notice, this list of conditions and the following disclaimer.
37 *   * Redistributions in binary form must reproduce the above copyright
38 *     notice, this list of conditions and the following disclaimer in
39 *     the documentation and/or other materials provided with the
40 *     distribution.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 *
54 * $FreeBSD$
55 */
56#ifndef _SCIC_SDS_PCI_H_
57#define _SCIC_SDS_PCI_H_
58
59/**
60 * @file
61 *
62 * @brief This file contains the prototypes/macros utilized in writing
63 *        out PCI data for the SCI core.
64 */
65
66#ifdef __cplusplus
67extern "C" {
68#endif // __cplusplus
69
70#include <dev/isci/scil/sci_types.h>
71
72#define PATSBURG_SMU_BAR       0
73#define PATSBURG_SCU_BAR       1
74#define PATSBURG_IO_SPACE_BAR0 2
75#define PATSBURG_IO_SPACE_BAR1 3
76
77#define SCIC_SDS_PCI_REVISION_A0 0
78#define SCIC_SDS_PCI_REVISION_A2 2
79#define SCIC_SDS_PCI_REVISION_B0 4
80#define SCIC_SDS_PCI_REVISION_C0 5
81#define SCIC_SDS_PCI_REVISION_C1 6
82
83enum SCU_CONTROLLER_PCI_REVISION_CODE
84{
85   SCU_PBG_HBA_REV_A0 = SCIC_SDS_PCI_REVISION_A0,
86   SCU_PBG_HBA_REV_A2 = SCIC_SDS_PCI_REVISION_A2,
87   SCU_PBG_HBA_REV_B0 = SCIC_SDS_PCI_REVISION_B0,
88   SCU_PBG_HBA_REV_C0 = SCIC_SDS_PCI_REVISION_C0,
89   SCU_PBG_HBA_REV_C1 = SCIC_SDS_PCI_REVISION_C1
90};
91
92struct SCIC_SDS_CONTROLLER;
93
94void scic_sds_pci_bar_initialization(
95   struct SCIC_SDS_CONTROLLER * this_controller
96);
97
98#if !defined(ENABLE_PCI_IO_SPACE_ACCESS) || defined(ARLINGTON_BUILD)
99
100#define scic_sds_pci_read_smu_dword  scic_cb_pci_read_dword
101#define scic_sds_pci_write_smu_dword scic_cb_pci_write_dword
102#define scic_sds_pci_read_scu_dword  scic_cb_pci_read_dword
103#define scic_sds_pci_write_scu_dword scic_cb_pci_write_dword
104
105#else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
106
107// These two registers form the Data/Index pair equivalent in the
108// SCU. They are only used for access registers in BAR 1, not BAR 0.
109#define SCU_MMR_ADDRESS_WINDOW_OFFSET 0xA0
110#define SCU_MMR_DATA_WINDOW_OFFSET    0xA4
111
112U32 scic_sds_pci_read_smu_dword(
113   SCI_CONTROLLER_HANDLE_T   controller,
114   void                    * address
115);
116
117void scic_sds_pci_write_smu_dword(
118   SCI_CONTROLLER_HANDLE_T   controller,
119   void                    * address,
120   U32                       write_value
121);
122
123U32 scic_sds_pci_read_scu_dword(
124   SCI_CONTROLLER_HANDLE_T   controller,
125   void                    * address
126);
127
128void scic_sds_pci_write_scu_dword(
129   SCI_CONTROLLER_HANDLE_T   controller,
130   void                    * address,
131   U32                       write_value
132);
133
134#endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
135
136#ifdef __cplusplus
137}
138#endif // __cplusplus
139
140#endif // _SCIC_SDS_PCI_H_
141