1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Ian Lepore. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30/* 31 * Driver for ISL12xx family i2c realtime clocks: 32 * - ISL1209 = 2B sram, tamper/event timestamp 33 * - ISL1218 = 8B sram, DS13xx pin compatible (but not software compatible) 34 * - ISL1219 = 2B sram, tamper/event timestamp 35 * - ISL1220 = 8B sram, separate Fout 36 * - ISL1221 = 2B sram, separate Fout, tamper/event timestamp 37 * 38 * This driver supports only the basic RTC functionality in all these chips. 39 */ 40 41#include "opt_platform.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/clock.h> 47#include <sys/kernel.h> 48#include <sys/lock.h> 49#include <sys/module.h> 50#include <sys/sx.h> 51 52#ifdef FDT 53#include <dev/ofw/ofw_bus.h> 54#include <dev/ofw/ofw_bus_subr.h> 55#endif 56 57#include <dev/iicbus/iiconf.h> 58#include <dev/iicbus/iicbus.h> 59 60#include "clock_if.h" 61#include "iicbus_if.h" 62 63/* 64 * All register and bit names as found in the datasheet. When a bit name ends 65 * in 'B' that stands for "bar" and it is an active-low signal; something named 66 * "EVENB" implies 1=event-disable, 0=event-enable. 67 */ 68 69#define ISL12XX_SC_REG 0x00 /* RTC Seconds */ 70 71#define ISL12XX_SR_REG 0x07 /* Status */ 72#define ISL12XX_SR_ARST (1u << 7) /* Auto-reset on status read */ 73#define ISL12XX_SR_XTOSCB (1u << 5) /* Osc disable (use ext osc) */ 74#define ISL12XX_SR_WRTC (1u << 4) /* Write RTC enable */ 75#define ISL12XX_SR_EVT (1u << 3) /* Event occurred (w0c) */ 76#define ISL12XX_SR_ALM (1u << 2) /* Alarm occurred (w0c) */ 77#define ISL12XX_SR_BAT (1u << 1) /* Running on battery (w0c) */ 78#define ISL12XX_SR_RTCF (1u << 0) /* RTC fail (power loss) */ 79#define ISL12XX_SR_W0C_BITS (ISL12XX_SR_BAT | ISL12XX_SR_ALM | ISL12XX_SR_EVT) 80 81#define ISL12XX_INT_REG 0x08 /* Interrupts */ 82#define ISL12XX_INT_IM (1u << 7) /* Alarm interrupt mode */ 83#define ISL12XX_INT_ALME (1u << 6) /* Alarm enable */ 84#define ISL12XX_INT_LPMODE (1u << 5) /* Low Power mode */ 85#define ISL12XX_INT_FOBATB (1u << 4) /* Fout/IRQ disabled on bat */ 86#define ISL12XX_INT_FO_SHIFT 0 /* Frequency output select */ 87#define ISL12XX_INT_FO_MASK 0x0f /* shift and mask. */ 88 89#define ISL12XX_EV_REG 0x09 /* Event */ 90#define ISL12XX_EV_EVIENB (1u << 7) /* Disable internal pullup */ 91#define ISL12XX_EV_EVBATB (1u << 6) /* Disable ev detect on bat */ 92#define ISL12XX_EV_RTCHLT (1u << 5) /* Halt RTC on event */ 93#define ISL12XX_EV_EVEN (1u << 4) /* Event detect enable */ 94#define ISL12XX_EV_EHYS_SHIFT 2 /* Event input hysteresis */ 95#define ISL12XX_EV_EHYS_MASK 0x03 /* selection; see datasheet */ 96#define ISL12XX_EV_ESMP_SHIFT 0 /* Event input sample rate */ 97#define ISL12XX_EV_ESMP_MASK 0x03 /* selection; see datasheet */ 98 99#define ISL12XX_ATR_REG 0x0a /* Analog trim (osc adjust) */ 100 101#define ISL12XX_DTR_REG 0x0b /* Digital trim (osc adjust) */ 102 103#define ISL12XX_SCA_REG 0x0c /* Alarm seconds */ 104 105#define ISL12XX_USR1_REG 0x12 /* User byte 1 */ 106 107#define ISL12XX_USR2_REG 0x13 /* User byte 2 */ 108 109#define ISL12XX_SCT_REG 0x14 /* Timestamp (event) seconds */ 110 111#define ISL12XX_24HR_FLAG (1u << 7) /* Hours register 24-hr mode */ 112#define ISL12XX_PM_FLAG (1u << 5) /* Hours register PM flag */ 113#define ISL12xx_12HR_MASK 0x1f /* Hours mask in AM/PM mode */ 114#define ISL12xx_24HR_MASK 0x3f /* Hours mask in 24-hr mode */ 115 116/* 117 * A struct laid out in the same order as the time registers in the chip. 118 */ 119struct time_regs { 120 uint8_t sec, min, hour, day, month, year; 121}; 122 123struct isl12xx_softc { 124 device_t dev; 125 device_t busdev; 126 struct intr_config_hook 127 init_hook; 128 bool use_ampm; 129}; 130 131#ifdef FDT 132static struct ofw_compat_data compat_data[] = { 133 {"isil,isl1209", 1}, 134 {"isil,isl1218", 1}, 135 {"isil,isl1219", 1}, 136 {"isil,isl1220", 1}, 137 {"isil,isl1221", 1}, 138 {NULL, 0}, 139}; 140#endif 141 142/* 143 * When doing i2c IO, indicate that we need to wait for exclusive bus ownership, 144 * but that we should not wait if we already own the bus. This lets us put 145 * iicbus_acquire_bus() calls with a non-recursive wait at the entry of our API 146 * functions to ensure that only one client at a time accesses the hardware for 147 * the entire series of operations it takes to read or write the clock. 148 */ 149#define WAITFLAGS (IIC_WAIT | IIC_RECURSIVE) 150 151static inline int 152isl12xx_read1(struct isl12xx_softc *sc, uint8_t reg, uint8_t *data) 153{ 154 155 return (iicdev_readfrom(sc->dev, reg, data, 1, WAITFLAGS)); 156} 157 158static inline int 159isl12xx_write1(struct isl12xx_softc *sc, uint8_t reg, uint8_t val) 160{ 161 162 return (iicdev_writeto(sc->dev, reg, &val, 1, WAITFLAGS)); 163} 164 165static void 166isl12xx_init(void *arg) 167{ 168 struct isl12xx_softc *sc = arg; 169 uint8_t sreg; 170 171 config_intrhook_disestablish(&sc->init_hook); 172 173 /* 174 * Check the clock-stopped/power-fail bit, just so we can report it to 175 * the user at boot time. 176 */ 177 isl12xx_read1(sc, ISL12XX_SR_REG, &sreg); 178 if (sreg & ISL12XX_SR_RTCF) { 179 device_printf(sc->dev, 180 "RTC clock stopped; check battery\n"); 181 } 182 183 /* 184 * Register as a system realtime clock. 185 */ 186 clock_register_flags(sc->dev, 1000000, CLOCKF_SETTIME_NO_ADJ); 187 clock_schedule(sc->dev, 1); 188} 189 190static int 191isl12xx_probe(device_t dev) 192{ 193 194#ifdef FDT 195 if (!ofw_bus_status_okay(dev)) 196 return (ENXIO); 197 198 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 199 device_set_desc(dev, "Intersil ISL12xx RTC"); 200 return (BUS_PROBE_DEFAULT); 201 } 202#endif 203 return (ENXIO); 204} 205 206static int 207isl12xx_attach(device_t dev) 208{ 209 struct isl12xx_softc *sc = device_get_softc(dev); 210 211 sc->dev = dev; 212 sc->busdev = device_get_parent(sc->dev); 213 214 /* 215 * Chip init must wait until interrupts are enabled. Often i2c access 216 * works only when the interrupts are available. 217 */ 218 sc->init_hook.ich_func = isl12xx_init; 219 sc->init_hook.ich_arg = sc; 220 if (config_intrhook_establish(&sc->init_hook) != 0) 221 return (ENOMEM); 222 223 return (0); 224} 225 226static int 227isl12xx_detach(device_t dev) 228{ 229 230 clock_unregister(dev); 231 return (0); 232} 233 234static int 235isl12xx_gettime(device_t dev, struct timespec *ts) 236{ 237 struct isl12xx_softc *sc = device_get_softc(dev); 238 struct bcd_clocktime bct; 239 struct time_regs tregs; 240 int err; 241 uint8_t hourmask, sreg; 242 243 /* 244 * Read the status and time registers. 245 */ 246 if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) == 0) { 247 if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) { 248 err = iicdev_readfrom(sc->dev, ISL12XX_SC_REG, &tregs, 249 sizeof(tregs), WAITFLAGS); 250 } 251 iicbus_release_bus(sc->busdev, sc->dev); 252 } 253 if (err != 0) 254 return (err); 255 256 /* If power failed, we can't provide valid time. */ 257 if (sreg & ISL12XX_SR_RTCF) 258 return (EINVAL); 259 260 /* If chip is in AM/PM mode remember that for when we set time. */ 261 if (tregs.hour & ISL12XX_24HR_FLAG) { 262 hourmask = ISL12xx_24HR_MASK; 263 } else { 264 sc->use_ampm = true; 265 hourmask = ISL12xx_12HR_MASK; 266 } 267 268 bct.nsec = 0; 269 bct.sec = tregs.sec; 270 bct.min = tregs.min; 271 bct.hour = tregs.hour & hourmask; 272 bct.day = tregs.day; 273 bct.mon = tregs.month; 274 bct.year = tregs.year; 275 bct.ispm = tregs.hour & ISL12XX_PM_FLAG; 276 277 clock_dbgprint_bcd(sc->dev, CLOCK_DBG_READ, &bct); 278 return (clock_bcd_to_ts(&bct, ts, sc->use_ampm)); 279} 280 281static int 282isl12xx_settime(device_t dev, struct timespec *ts) 283{ 284 struct isl12xx_softc *sc = device_get_softc(dev); 285 struct bcd_clocktime bct; 286 struct time_regs tregs; 287 int err; 288 uint8_t ampmflags, sreg; 289 290 /* 291 * We request a timespec with no resolution-adjustment. That also 292 * disables utc adjustment, so apply that ourselves. 293 */ 294 ts->tv_sec -= utc_offset(); 295 ts->tv_nsec = 0; 296 clock_ts_to_bcd(ts, &bct, sc->use_ampm); 297 clock_dbgprint_bcd(sc->dev, CLOCK_DBG_WRITE, &bct); 298 299 /* If the chip is in AM/PM mode, set flags as needed. */ 300 if (!sc->use_ampm) 301 ampmflags = ISL12XX_24HR_FLAG; 302 else 303 ampmflags = bct.ispm ? ISL12XX_PM_FLAG : 0; 304 305 tregs.sec = bct.sec; 306 tregs.min = bct.min; 307 tregs.hour = bct.hour | ampmflags; 308 tregs.day = bct.day; 309 tregs.month = bct.mon; 310 tregs.year = bct.year % 100; 311 312 /* 313 * To set the time we have to set the WRTC enable bit in the control 314 * register, then write the time regs, then clear the WRTC bit. While 315 * doing so we have to be careful to not write a 0 to any sreg bit which 316 * is "write 0 to clear". One of those bits could get set between 317 * reading and writing the register. All those bits ignore attempts to 318 * write a 1, so just always OR-in all the W0C bits to be sure we never 319 * accidentally clear one. We hold ownership of the i2c bus for the 320 * whole read-modify-write sequence. 321 */ 322 if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) != 0) 323 return (err); 324 if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) { 325 sreg |= ISL12XX_SR_WRTC | ISL12XX_SR_W0C_BITS; 326 if ((err = isl12xx_write1(sc, ISL12XX_SR_REG, sreg)) == 0) { 327 err = iicdev_writeto(sc->dev, ISL12XX_SC_REG, &tregs, 328 sizeof(tregs), WAITFLAGS); 329 sreg &= ~ISL12XX_SR_WRTC; 330 isl12xx_write1(sc, ISL12XX_SR_REG, sreg); 331 } 332 } 333 iicbus_release_bus(sc->busdev, sc->dev); 334 335 return (err); 336} 337 338static device_method_t isl12xx_methods[] = { 339 /* device_if methods */ 340 DEVMETHOD(device_probe, isl12xx_probe), 341 DEVMETHOD(device_attach, isl12xx_attach), 342 DEVMETHOD(device_detach, isl12xx_detach), 343 344 /* clock_if methods */ 345 DEVMETHOD(clock_gettime, isl12xx_gettime), 346 DEVMETHOD(clock_settime, isl12xx_settime), 347 348 DEVMETHOD_END, 349}; 350 351static driver_t isl12xx_driver = { 352 "isl12xx", 353 isl12xx_methods, 354 sizeof(struct isl12xx_softc), 355}; 356static devclass_t isl12xx_devclass; 357 358DRIVER_MODULE(isl12xx, iicbus, isl12xx_driver, isl12xx_devclass, NULL, NULL); 359MODULE_VERSION(isl12xx, 1); 360MODULE_DEPEND(isl12xx, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 361IICBUS_FDT_PNP_INFO(compat_data); 362