1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#ifndef IF_FFECREG_H 31#define IF_FFECREG_H 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36/* 37 * Hardware defines for Freescale Fast Ethernet Controller. 38 */ 39 40/* 41 * MAC registers. 42 */ 43#define FEC_IER_REG 0x0004 44#define FEC_IEM_REG 0x0008 45#define FEC_IER_HBERR (1U << 31) 46#define FEC_IER_BABR (1 << 30) 47#define FEC_IER_BABT (1 << 29) 48#define FEC_IER_GRA (1 << 28) 49#define FEC_IER_TXF (1 << 27) 50#define FEC_IER_TXB (1 << 26) 51#define FEC_IER_RXF (1 << 25) 52#define FEC_IER_RXB (1 << 24) 53#define FEC_IER_MII (1 << 23) 54#define FEC_IER_EBERR (1 << 22) 55#define FEC_IER_LC (1 << 21) 56#define FEC_IER_RL (1 << 20) 57#define FEC_IER_UN (1 << 19) 58#define FEC_IER_PLR (1 << 18) 59#define FEC_IER_WAKEUP (1 << 17) 60#define FEC_IER_AVAIL (1 << 16) 61#define FEC_IER_TIMER (1 << 15) 62 63#define FEC_RDAR_REG 0x0010 64#define FEC_RDAR_RDAR (1 << 24) 65 66#define FEC_TDAR_REG 0x0014 67#define FEC_TDAR_TDAR (1 << 24) 68 69#define FEC_ECR_REG 0x0024 70#define FEC_ECR_DBSWP (1 << 8) 71#define FEC_ECR_STOPEN (1 << 7) 72#define FEC_ECR_DBGEN (1 << 6) 73#define FEC_ECR_SPEED (1 << 5) 74#define FEC_ECR_EN1588 (1 << 4) 75#define FEC_ECR_SLEEP (1 << 3) 76#define FEC_ECR_MAGICEN (1 << 2) 77#define FEC_ECR_ETHEREN (1 << 1) 78#define FEC_ECR_RESET (1 << 0) 79 80#define FEC_MMFR_REG 0x0040 81#define FEC_MMFR_ST_SHIFT 30 82#define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT) 83#define FEC_MMFR_OP_SHIFT 28 84#define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT) 85#define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT) 86#define FEC_MMFR_PA_SHIFT 23 87#define FEC_MMFR_PA_MASK (0x1f << FEC_MMFR_PA_SHIFT) 88#define FEC_MMFR_RA_SHIFT 18 89#define FEC_MMFR_RA_MASK (0x1f << FEC_MMFR_RA_SHIFT) 90#define FEC_MMFR_TA_SHIFT 16 91#define FEC_MMFR_TA_VALUE (0x02 << FEC_MMFR_TA_SHIFT) 92#define FEC_MMFR_DATA_SHIFT 0 93#define FEC_MMFR_DATA_MASK (0xffff << FEC_MMFR_DATA_SHIFT) 94 95#define FEC_MSCR_REG 0x0044 96#define FEC_MSCR_HOLDTIME_SHIFT 8 97#define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT) 98#define FEC_MSCR_DIS_PRE (1 << 7) 99#define FEC_MSCR_MII_SPEED_SHIFT 1 100#define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT) 101 102#define FEC_MIBC_REG 0x0064 103#define FEC_MIBC_DIS (1U << 31) 104#define FEC_MIBC_IDLE (1 << 30) 105#define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */ 106 107#define FEC_RCR_REG 0x0084 108#define FEC_RCR_GRS (1U << 31) 109#define FEC_RCR_NLC (1 << 30) 110#define FEC_RCR_MAX_FL_SHIFT 16 111#define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT) 112#define FEC_RCR_CFEN (1 << 15) 113#define FEC_RCR_CRCFWD (1 << 14) 114#define FEC_RCR_PAUFWD (1 << 13) 115#define FEC_RCR_PADEN (1 << 12) 116#define FEC_RCR_RMII_10T (1 << 9) 117#define FEC_RCR_RMII_MODE (1 << 8) 118#define FEC_RCR_RGMII_EN (1 << 6) 119#define FEC_RCR_FCE (1 << 5) 120#define FEC_RCR_BC_REJ (1 << 4) 121#define FEC_RCR_PROM (1 << 3) 122#define FEC_RCR_MII_MODE (1 << 2) 123#define FEC_RCR_DRT (1 << 1) 124#define FEC_RCR_LOOP (1 << 0) 125 126#define FEC_TCR_REG 0x00c4 127#define FEC_TCR_ADDINS (1 << 9) 128#define FEC_TCR_ADDSEL_SHIFT 5 129#define FEC_TCR_ADDSEL_MASK (0x07 << FEC_TCR_ADDSEL_SHIFT) 130#define FEC_TCR_RFC_PAUSE (1 << 4) 131#define FEC_TCR_TFC_PAUSE (1 << 3) 132#define FEC_TCR_FDEN (1 << 2) 133#define FEC_TCR_GTS (1 << 0) 134 135#define FEC_PALR_REG 0x00e4 136#define FEC_PALR_PADDR1_SHIFT 0 137#define FEC_PALR_PADDR1_MASK (0xffffffff << FEC_PALR_PADDR1_SHIFT) 138 139#define FEC_PAUR_REG 0x00e8 140#define FEC_PAUR_PADDR2_SHIFT 16 141#define FEC_PAUR_PADDR2_MASK (0xffff << FEC_PAUR_PADDR2_SHIFT) 142#define FEC_PAUR_TYPE_VALUE (0x8808) 143 144#define FEC_OPD_REG 0x00ec 145#define FEC_OPD_PAUSE_DUR_SHIFT 0 146#define FEC_OPD_PAUSE_DUR_MASK (0xffff << FEC_OPD_PAUSE_DUR_SHIFT) 147 148#define FEC_IAUR_REG 0x0118 149#define FEC_IALR_REG 0x011c 150 151#define FEC_GAUR_REG 0x0120 152#define FEC_GALR_REG 0x0124 153 154#define FEC_TFWR_REG 0x0144 155#define FEC_TFWR_STRFWD (1 << 8) 156#define FEC_TFWR_TWFR_SHIFT 0 157#define FEC_TFWR_TWFR_MASK (0x3f << FEC_TFWR_TWFR_SHIFT) 158#define FEC_TFWR_TWFR_128BYTE (0x02 << FEC_TFWR_TWFR_SHIFT) 159 160#define FEC_RDSR_REG 0x0180 161 162#define FEC_TDSR_REG 0x0184 163 164#define FEC_MRBR_REG 0x0188 165#define FEC_MRBR_R_BUF_SIZE_SHIFT 0 166#define FEC_MRBR_R_BUF_SIZE_MASK (0x3fff << FEC_MRBR_R_BUF_SIZE_SHIFT) 167 168#define FEC_RSFL_REG 0x0190 169#define FEC_RSEM_REG 0x0194 170#define FEC_RAEM_REG 0x0198 171#define FEC_RAFL_REG 0x019c 172#define FEC_TSEM_REG 0x01a0 173#define FEC_TAEM_REG 0x01a4 174#define FEC_TAFL_REG 0x01a8 175#define FEC_TIPG_REG 0x01ac 176#define FEC_FTRL_REG 0x01b0 177 178#define FEC_TACC_REG 0x01c0 179#define FEC_TACC_PROCHK (1 << 4) 180#define FEC_TACC_IPCHK (1 << 3) 181#define FEC_TACC_SHIFT16 (1 << 0) 182 183#define FEC_RACC_REG 0x01c4 184#define FEC_RACC_SHIFT16 (1 << 7) 185#define FEC_RACC_LINEDIS (1 << 6) 186#define FEC_RACC_PRODIS (1 << 2) 187#define FEC_RACC_IPDIS (1 << 1) 188#define FEC_RACC_PADREM (1 << 0) 189 190/* 191 * IEEE-1588 timer registers 192 */ 193 194#define FEC_ATCR_REG 0x0400 195#define FEC_ATCR_SLAVE (1u << 13) 196#define FEC_ATCR_CAPTURE (1u << 11) 197#define FEC_ATCR_RESTART (1u << 9) 198#define FEC_ATCR_PINPER (1u << 7) 199#define FEC_ATCR_PEREN (1u << 4) 200#define FEC_ATCR_OFFRST (1u << 3) 201#define FEC_ATCR_OFFEN (1u << 2) 202#define FEC_ATCR_EN (1u << 0) 203 204#define FEC_ATVR_REG 0x0404 205#define FEC_ATOFF_REG 0x0408 206#define FEC_ATPER_REG 0x040c 207#define FEC_ATCOR_REG 0x0410 208#define FEC_ATINC_REG 0x0414 209#define FEC_ATSTMP_REG 0x0418 210 211/* 212 * Statistics registers 213 */ 214#define FEC_RMON_T_DROP 0x200 215#define FEC_RMON_T_PACKETS 0x204 216#define FEC_RMON_T_BC_PKT 0x208 217#define FEC_RMON_T_MC_PKT 0x20C 218#define FEC_RMON_T_CRC_ALIGN 0x210 219#define FEC_RMON_T_UNDERSIZE 0x214 220#define FEC_RMON_T_OVERSIZE 0x218 221#define FEC_RMON_T_FRAG 0x21C 222#define FEC_RMON_T_JAB 0x220 223#define FEC_RMON_T_COL 0x224 224#define FEC_RMON_T_P64 0x228 225#define FEC_RMON_T_P65TO127 0x22C 226#define FEC_RMON_T_P128TO255 0x230 227#define FEC_RMON_T_P256TO511 0x234 228#define FEC_RMON_T_P512TO1023 0x238 229#define FEC_RMON_T_P1024TO2047 0x23C 230#define FEC_RMON_T_P_GTE2048 0x240 231#define FEC_RMON_T_OCTECTS 0x240 232#define FEC_IEEE_T_DROP 0x248 233#define FEC_IEEE_T_FRAME_OK 0x24C 234#define FEC_IEEE_T_1COL 0x250 235#define FEC_IEEE_T_MCOL 0x254 236#define FEC_IEEE_T_DEF 0x258 237#define FEC_IEEE_T_LCOL 0x25C 238#define FEC_IEEE_T_EXCOL 0x260 239#define FEC_IEEE_T_MACERR 0x264 240#define FEC_IEEE_T_CSERR 0x268 241#define FEC_IEEE_T_SQE 0x26C 242#define FEC_IEEE_T_FDXFC 0x270 243#define FEC_IEEE_T_OCTETS_OK 0x274 244#define FEC_RMON_R_PACKETS 0x284 245#define FEC_RMON_R_BC_PKT 0x288 246#define FEC_RMON_R_MC_PKT 0x28C 247#define FEC_RMON_R_CRC_ALIGN 0x290 248#define FEC_RMON_R_UNDERSIZE 0x294 249#define FEC_RMON_R_OVERSIZE 0x298 250#define FEC_RMON_R_FRAG 0x29C 251#define FEC_RMON_R_JAB 0x2A0 252#define FEC_RMON_R_RESVD_0 0x2A4 253#define FEC_RMON_R_P64 0x2A8 254#define FEC_RMON_R_P65TO127 0x2AC 255#define FEC_RMON_R_P128TO255 0x2B0 256#define FEC_RMON_R_P256TO511 0x2B4 257#define FEC_RMON_R_P512TO1023 0x2B8 258#define FEC_RMON_R_P1024TO2047 0x2BC 259#define FEC_RMON_R_P_GTE2048 0x2C0 260#define FEC_RMON_R_OCTETS 0x2C4 261#define FEC_IEEE_R_DROP 0x2C8 262#define FEC_IEEE_R_FRAME_OK 0x2CC 263#define FEC_IEEE_R_CRC 0x2D0 264#define FEC_IEEE_R_ALIGN 0x2D4 265#define FEC_IEEE_R_MACERR 0x2D8 266#define FEC_IEEE_R_FDXFC 0x2DC 267#define FEC_IEEE_R_OCTETS_OK 0x2E0 268 269#define FEC_MIIGSK_CFGR 0x300 270#define FEC_MIIGSK_CFGR_FRCONT (1 << 6) /* Freq: 0=50MHz, 1=5MHz */ 271#define FEC_MIIGSK_CFGR_LBMODE (1 << 4) /* loopback mode */ 272#define FEC_MIIGSK_CFGR_EMODE (1 << 3) /* echo mode */ 273#define FEC_MIIGSK_CFGR_IF_MODE_MASK (0x3 << 0) 274#define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0) 275#define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0) 276 277#define FEC_MIIGSK_ENR 0x308 278#define FEC_MIIGSK_ENR_READY (1 << 2) 279#define FEC_MIIGSK_ENR_EN (1 << 1) 280 281/* 282 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 283 * layout, but the bits in the flags field have different meanings. 284 */ 285struct ffec_hwdesc 286{ 287 uint32_t flags_len; 288 uint32_t buf_paddr; 289}; 290 291#define FEC_TXDESC_READY (1U << 31) 292#define FEC_TXDESC_T01 (1 << 30) 293#define FEC_TXDESC_WRAP (1 << 29) 294#define FEC_TXDESC_T02 (1 << 28) 295#define FEC_TXDESC_L (1 << 27) 296#define FEC_TXDESC_TC (1 << 26) 297#define FEC_TXDESC_ABC (1 << 25) 298#define FEC_TXDESC_LEN_MASK (0xffff) 299 300#define FEC_RXDESC_EMPTY (1U << 31) 301#define FEC_RXDESC_R01 (1 << 30) 302#define FEC_RXDESC_WRAP (1 << 29) 303#define FEC_RXDESC_R02 (1 << 28) 304#define FEC_RXDESC_L (1 << 27) 305#define FEC_RXDESC_M (1 << 24) 306#define FEC_RXDESC_BC (1 << 23) 307#define FEC_RXDESC_MC (1 << 22) 308#define FEC_RXDESC_LG (1 << 21) 309#define FEC_RXDESC_NO (1 << 20) 310#define FEC_RXDESC_CR (1 << 18) 311#define FEC_RXDESC_OV (1 << 17) 312#define FEC_RXDESC_TR (1 << 16) 313#define FEC_RXDESC_LEN_MASK (0xffff) 314 315#define FEC_RXDESC_ERROR_BITS (FEC_RXDESC_LG | FEC_RXDESC_NO | \ 316 FEC_RXDESC_OV | FEC_RXDESC_TR) 317 318/* 319 * The hardware imposes alignment restrictions on various objects involved in 320 * DMA transfers. These values are expressed in bytes (not bits). 321 */ 322#define FEC_DESC_RING_ALIGN 64 323 324#endif /* IF_FFECREG_H */ 325