1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31#include <sys/param.h> 32#include <sys/bus.h> 33#include <sys/errno.h> 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/socket.h> 37#include <sys/sockio.h> 38#include <sys/sysctl.h> 39#include <sys/systm.h> 40 41#include <net/if.h> 42#include <net/if_arp.h> 43#include <net/ethernet.h> 44#include <net/if_dl.h> 45#include <net/if_media.h> 46#include <net/if_types.h> 47 48#include <machine/bus.h> 49#include <dev/iicbus/iic.h> 50#include <dev/iicbus/iiconf.h> 51#include <dev/iicbus/iicbus.h> 52#include <dev/mii/mii.h> 53#include <dev/mii/miivar.h> 54#include <dev/mdio/mdio.h> 55 56#include <dev/etherswitch/etherswitch.h> 57 58#include <dev/etherswitch/arswitch/arswitchreg.h> 59#include <dev/etherswitch/arswitch/arswitchvar.h> 60#include <dev/etherswitch/arswitch/arswitch_reg.h> 61 62#include "mdio_if.h" 63#include "miibus_if.h" 64#include "etherswitch_if.h" 65 66static inline void 67arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy, 68 uint16_t *reg) 69{ 70 struct arswitch_softc *sc = device_get_softc(dev); 71 uint16_t page; 72 73 page = (addr >> 9) & 0x1ff; 74 *phy = (addr >> 6) & 0x7; 75 *reg = (addr >> 1) & 0x1f; 76 77 if (sc->page != page) { 78 MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page); 79 DELAY(2000); 80 sc->page = page; 81 } 82} 83 84/* 85 * Read half a register. Some of the registers define control bits, and 86 * the sequence of half-word accesses matters. The register addresses 87 * are word-even (mod 4). 88 */ 89static inline int 90arswitch_readreg16(device_t dev, int addr) 91{ 92 uint16_t phy, reg; 93 94 arswitch_split_setpage(dev, addr, &phy, ®); 95 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg)); 96} 97 98/* 99 * Write half a register. See above! 100 */ 101static inline int 102arswitch_writereg16(device_t dev, int addr, int data) 103{ 104 uint16_t phy, reg; 105 106 arswitch_split_setpage(dev, addr, &phy, ®); 107 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data)); 108} 109 110/* 111 * XXX NOTE: 112 * 113 * This may not work for AR7240 series embedded switches - 114 * the per-PHY register space doesn't seem to be exposed. 115 * 116 * In that instance, it may be required to speak via 117 * the internal switch PHY MDIO bus indirection. 118 */ 119void 120arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr, 121 uint16_t dbg_data) 122{ 123 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 124 MII_ATH_DBG_ADDR, dbg_addr); 125 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 126 MII_ATH_DBG_DATA, dbg_data); 127} 128 129void 130arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr, 131 uint16_t dbg_data) 132{ 133 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 134 MII_ATH_MMD_ADDR, dbg_addr); 135 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 136 MII_ATH_MMD_DATA, dbg_data); 137} 138 139static uint32_t 140arswitch_reg_read32(device_t dev, int phy, int reg) 141{ 142 uint16_t lo, hi; 143 lo = MDIO_READREG(device_get_parent(dev), phy, reg); 144 hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1); 145 146 return (hi << 16) | lo; 147} 148 149static int 150arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value) 151{ 152 struct arswitch_softc *sc; 153 int r; 154 uint16_t lo, hi; 155 156 sc = device_get_softc(dev); 157 lo = value & 0xffff; 158 hi = (uint16_t) (value >> 16); 159 160 if (sc->mii_lo_first) { 161 r = MDIO_WRITEREG(device_get_parent(dev), 162 phy, reg, lo); 163 r |= MDIO_WRITEREG(device_get_parent(dev), 164 phy, reg + 1, hi); 165 } else { 166 r = MDIO_WRITEREG(device_get_parent(dev), 167 phy, reg + 1, hi); 168 r |= MDIO_WRITEREG(device_get_parent(dev), 169 phy, reg, lo); 170 } 171 172 return r; 173} 174 175int 176arswitch_readreg(device_t dev, int addr) 177{ 178 uint16_t phy, reg; 179 180 arswitch_split_setpage(dev, addr, &phy, ®); 181 return arswitch_reg_read32(dev, 0x10 | phy, reg); 182} 183 184int 185arswitch_writereg(device_t dev, int addr, int value) 186{ 187 struct arswitch_softc *sc; 188 uint16_t phy, reg; 189 190 sc = device_get_softc(dev); 191 192 arswitch_split_setpage(dev, addr, &phy, ®); 193 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 194} 195 196/* 197 * Read/write 16 bit values in the switch register space. 198 * 199 * Some of the registers are control registers (eg the MDIO 200 * data versus control space) and so need to be treated 201 * differently. 202 */ 203int 204arswitch_readreg_lsb(device_t dev, int addr) 205{ 206 207 return (arswitch_readreg16(dev, addr)); 208} 209 210int 211arswitch_readreg_msb(device_t dev, int addr) 212{ 213 214 return (arswitch_readreg16(dev, addr + 2) << 16); 215} 216 217int 218arswitch_writereg_lsb(device_t dev, int addr, int data) 219{ 220 221 return (arswitch_writereg16(dev, addr, data & 0xffff)); 222} 223 224int 225arswitch_writereg_msb(device_t dev, int addr, int data) 226{ 227 228 return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff)); 229} 230 231int 232arswitch_modifyreg(device_t dev, int addr, int mask, int set) 233{ 234 int value; 235 uint16_t phy, reg; 236 237 ARSWITCH_LOCK_ASSERT((struct arswitch_softc *)device_get_softc(dev), 238 MA_OWNED); 239 240 arswitch_split_setpage(dev, addr, &phy, ®); 241 242 value = arswitch_reg_read32(dev, 0x10 | phy, reg); 243 value &= ~mask; 244 value |= set; 245 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 246} 247 248int 249arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout) 250{ 251 struct arswitch_softc *sc = device_get_softc(dev); 252 int err, v; 253 uint16_t phy, reg; 254 255 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); 256 257 arswitch_split_setpage(dev, addr, &phy, ®); 258 259 err = -1; 260 while (1) { 261 v = arswitch_reg_read32(dev, 0x10 | phy, reg); 262 v &= mask; 263 if (v == val) { 264 err = 0; 265 break; 266 } 267 if (!timeout) 268 break; 269 DELAY(1); 270 timeout--; 271 } 272 if (err != 0) { 273 DPRINTF(sc, ARSWITCH_DBG_ANY, 274 "%s: waitreg failed; addr=0x%08x, mask=0x%08x, val=0x%08x\n", 275 __func__, addr, mask, val); 276 } 277 return (err); 278} 279