1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32/* This file is automatically generated --- changes will be lost */ 33 34#ifndef _T4_TCB_DEFS_H 35#define _T4_TCB_DEFS_H 36 37/* 3:0 */ 38#define W_TCB_ULP_TYPE 0 39#define S_TCB_ULP_TYPE 0 40#define M_TCB_ULP_TYPE 0xfULL 41#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) 42 43/* 11:4 */ 44#define W_TCB_ULP_RAW 0 45#define S_TCB_ULP_RAW 4 46#define M_TCB_ULP_RAW 0xffULL 47#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) 48 49/* 23:12 */ 50#define W_TCB_L2T_IX 0 51#define S_TCB_L2T_IX 12 52#define M_TCB_L2T_IX 0xfffULL 53#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) 54 55/* 31:24 */ 56#define W_TCB_SMAC_SEL 0 57#define S_TCB_SMAC_SEL 24 58#define M_TCB_SMAC_SEL 0xffULL 59#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) 60 61/* 95:32 */ 62#define W_TCB_T_FLAGS 1 63#define S_TCB_T_FLAGS 0 64#define M_TCB_T_FLAGS 0xffffffffffffffffULL 65#define V_TCB_T_FLAGS(x) ((__u64)(x) << S_TCB_T_FLAGS) 66 67/* 105:96 */ 68#define W_TCB_RSS_INFO 3 69#define S_TCB_RSS_INFO 0 70#define M_TCB_RSS_INFO 0x3ffULL 71#define V_TCB_RSS_INFO(x) ((x) << S_TCB_RSS_INFO) 72 73/* 111:106 */ 74#define W_TCB_TOS 3 75#define S_TCB_TOS 10 76#define M_TCB_TOS 0x3fULL 77#define V_TCB_TOS(x) ((x) << S_TCB_TOS) 78 79/* 115:112 */ 80#define W_TCB_T_STATE 3 81#define S_TCB_T_STATE 16 82#define M_TCB_T_STATE 0xfULL 83#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) 84 85/* 119:116 */ 86#define W_TCB_MAX_RT 3 87#define S_TCB_MAX_RT 20 88#define M_TCB_MAX_RT 0xfULL 89#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) 90 91/* 123:120 */ 92#define W_TCB_T_MAXSEG 3 93#define S_TCB_T_MAXSEG 24 94#define M_TCB_T_MAXSEG 0xfULL 95#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) 96 97/* 127:124 */ 98#define W_TCB_SND_SCALE 3 99#define S_TCB_SND_SCALE 28 100#define M_TCB_SND_SCALE 0xfULL 101#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) 102 103/* 131:128 */ 104#define W_TCB_RCV_SCALE 4 105#define S_TCB_RCV_SCALE 0 106#define M_TCB_RCV_SCALE 0xfULL 107#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) 108 109/* 135:132 */ 110#define W_TCB_T_RXTSHIFT 4 111#define S_TCB_T_RXTSHIFT 4 112#define M_TCB_T_RXTSHIFT 0xfULL 113#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) 114 115/* 139:136 */ 116#define W_TCB_T_DUPACKS 4 117#define S_TCB_T_DUPACKS 8 118#define M_TCB_T_DUPACKS 0xfULL 119#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) 120 121/* 143:140 */ 122#define W_TCB_TIMESTAMP_OFFSET 4 123#define S_TCB_TIMESTAMP_OFFSET 12 124#define M_TCB_TIMESTAMP_OFFSET 0xfULL 125#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) 126 127/* 159:144 */ 128#define W_TCB_RCV_ADV 4 129#define S_TCB_RCV_ADV 16 130#define M_TCB_RCV_ADV 0xffffULL 131#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) 132 133/* 191:160 */ 134#define W_TCB_TIMESTAMP 5 135#define S_TCB_TIMESTAMP 0 136#define M_TCB_TIMESTAMP 0xffffffffULL 137#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) 138 139/* 223:192 */ 140#define W_TCB_T_RTT_TS_RECENT_AGE 6 141#define S_TCB_T_RTT_TS_RECENT_AGE 0 142#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL 143#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) 144 145/* 255:224 */ 146#define W_TCB_T_RTSEQ_RECENT 7 147#define S_TCB_T_RTSEQ_RECENT 0 148#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL 149#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) 150 151/* 271:256 */ 152#define W_TCB_T_SRTT 8 153#define S_TCB_T_SRTT 0 154#define M_TCB_T_SRTT 0xffffULL 155#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) 156 157/* 287:272 */ 158#define W_TCB_T_RTTVAR 8 159#define S_TCB_T_RTTVAR 16 160#define M_TCB_T_RTTVAR 0xffffULL 161#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) 162 163/* 319:288 */ 164#define W_TCB_TX_MAX 9 165#define S_TCB_TX_MAX 0 166#define M_TCB_TX_MAX 0xffffffffULL 167#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) 168 169/* 347:320 */ 170#define W_TCB_SND_UNA_RAW 10 171#define S_TCB_SND_UNA_RAW 0 172#define M_TCB_SND_UNA_RAW 0xfffffffULL 173#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) 174 175/* 375:348 */ 176#define W_TCB_SND_NXT_RAW 10 177#define S_TCB_SND_NXT_RAW 28 178#define M_TCB_SND_NXT_RAW 0xfffffffULL 179#define V_TCB_SND_NXT_RAW(x) ((__u64)(x) << S_TCB_SND_NXT_RAW) 180 181/* 403:376 */ 182#define W_TCB_SND_MAX_RAW 11 183#define S_TCB_SND_MAX_RAW 24 184#define M_TCB_SND_MAX_RAW 0xfffffffULL 185#define V_TCB_SND_MAX_RAW(x) ((__u64)(x) << S_TCB_SND_MAX_RAW) 186 187/* 431:404 */ 188#define W_TCB_SND_REC_RAW 12 189#define S_TCB_SND_REC_RAW 20 190#define M_TCB_SND_REC_RAW 0xfffffffULL 191#define V_TCB_SND_REC_RAW(x) ((__u64)(x) << S_TCB_SND_REC_RAW) 192 193/* 459:432 */ 194#define W_TCB_SND_CWND 13 195#define S_TCB_SND_CWND 16 196#define M_TCB_SND_CWND 0xfffffffULL 197#define V_TCB_SND_CWND(x) ((__u64)(x) << S_TCB_SND_CWND) 198 199/* 487:460 */ 200#define W_TCB_SND_SSTHRESH 14 201#define S_TCB_SND_SSTHRESH 12 202#define M_TCB_SND_SSTHRESH 0xfffffffULL 203#define V_TCB_SND_SSTHRESH(x) ((__u64)(x) << S_TCB_SND_SSTHRESH) 204 205/* 504:488 */ 206#define W_TCB_TX_HDR_PTR_RAW 15 207#define S_TCB_TX_HDR_PTR_RAW 8 208#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL 209#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) 210 211/* 521:505 */ 212#define W_TCB_TX_LAST_PTR_RAW 15 213#define S_TCB_TX_LAST_PTR_RAW 25 214#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL 215#define V_TCB_TX_LAST_PTR_RAW(x) ((__u64)(x) << S_TCB_TX_LAST_PTR_RAW) 216 217/* 553:522 */ 218#define W_TCB_RCV_NXT 16 219#define S_TCB_RCV_NXT 10 220#define M_TCB_RCV_NXT 0xffffffffULL 221#define V_TCB_RCV_NXT(x) ((__u64)(x) << S_TCB_RCV_NXT) 222 223/* 581:554 */ 224#define W_TCB_RCV_WND 17 225#define S_TCB_RCV_WND 10 226#define M_TCB_RCV_WND 0xfffffffULL 227#define V_TCB_RCV_WND(x) ((__u64)(x) << S_TCB_RCV_WND) 228 229/* 609:582 */ 230#define W_TCB_RX_HDR_OFFSET 18 231#define S_TCB_RX_HDR_OFFSET 6 232#define M_TCB_RX_HDR_OFFSET 0xfffffffULL 233#define V_TCB_RX_HDR_OFFSET(x) ((__u64)(x) << S_TCB_RX_HDR_OFFSET) 234 235/* 637:610 */ 236#define W_TCB_TS_LAST_ACK_SENT_RAW 19 237#define S_TCB_TS_LAST_ACK_SENT_RAW 2 238#define M_TCB_TS_LAST_ACK_SENT_RAW 0xfffffffULL 239#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) 240 241/* 665:638 */ 242#define W_TCB_RX_FRAG0_START_IDX_RAW 19 243#define S_TCB_RX_FRAG0_START_IDX_RAW 30 244#define M_TCB_RX_FRAG0_START_IDX_RAW 0xfffffffULL 245#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG0_START_IDX_RAW) 246 247/* 693:666 */ 248#define W_TCB_RX_FRAG1_START_IDX_OFFSET 20 249#define S_TCB_RX_FRAG1_START_IDX_OFFSET 26 250#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0xfffffffULL 251#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((__u64)(x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) 252 253/* 721:694 */ 254#define W_TCB_RX_FRAG0_LEN 21 255#define S_TCB_RX_FRAG0_LEN 22 256#define M_TCB_RX_FRAG0_LEN 0xfffffffULL 257#define V_TCB_RX_FRAG0_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG0_LEN) 258 259/* 749:722 */ 260#define W_TCB_RX_FRAG1_LEN 22 261#define S_TCB_RX_FRAG1_LEN 18 262#define M_TCB_RX_FRAG1_LEN 0xfffffffULL 263#define V_TCB_RX_FRAG1_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG1_LEN) 264 265/* 765:750 */ 266#define W_TCB_PDU_LEN 23 267#define S_TCB_PDU_LEN 14 268#define M_TCB_PDU_LEN 0xffffULL 269#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) 270 271/* 782:766 */ 272#define W_TCB_RX_PTR_RAW 23 273#define S_TCB_RX_PTR_RAW 30 274#define M_TCB_RX_PTR_RAW 0x1ffffULL 275#define V_TCB_RX_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_PTR_RAW) 276 277/* 799:783 */ 278#define W_TCB_RX_FRAG1_PTR_RAW 24 279#define S_TCB_RX_FRAG1_PTR_RAW 15 280#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL 281#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) 282 283/* 831:800 */ 284#define W_TCB_MAIN_SLUSH 25 285#define S_TCB_MAIN_SLUSH 0 286#define M_TCB_MAIN_SLUSH 0xffffffffULL 287#define V_TCB_MAIN_SLUSH(x) ((x) << S_TCB_MAIN_SLUSH) 288 289/* 846:832 */ 290#define W_TCB_AUX1_SLUSH0 26 291#define S_TCB_AUX1_SLUSH0 0 292#define M_TCB_AUX1_SLUSH0 0x7fffULL 293#define V_TCB_AUX1_SLUSH0(x) ((x) << S_TCB_AUX1_SLUSH0) 294 295/* 874:847 */ 296#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 297#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 298#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0xfffffffULL 299#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) 300 301/* 891:875 */ 302#define W_TCB_RX_FRAG2_PTR_RAW 27 303#define S_TCB_RX_FRAG2_PTR_RAW 11 304#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL 305#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) 306 307/* 919:892 */ 308#define W_TCB_RX_FRAG2_LEN_RAW 27 309#define S_TCB_RX_FRAG2_LEN_RAW 28 310#define M_TCB_RX_FRAG2_LEN_RAW 0xfffffffULL 311#define V_TCB_RX_FRAG2_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_LEN_RAW) 312 313/* 936:920 */ 314#define W_TCB_RX_FRAG3_PTR_RAW 28 315#define S_TCB_RX_FRAG3_PTR_RAW 24 316#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL 317#define V_TCB_RX_FRAG3_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_PTR_RAW) 318 319/* 964:937 */ 320#define W_TCB_RX_FRAG3_LEN_RAW 29 321#define S_TCB_RX_FRAG3_LEN_RAW 9 322#define M_TCB_RX_FRAG3_LEN_RAW 0xfffffffULL 323#define V_TCB_RX_FRAG3_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_LEN_RAW) 324 325/* 992:965 */ 326#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 327#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 5 328#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0xfffffffULL 329#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) 330 331/* 1000:993 */ 332#define W_TCB_PDU_HDR_LEN 31 333#define S_TCB_PDU_HDR_LEN 1 334#define M_TCB_PDU_HDR_LEN 0xffULL 335#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) 336 337/* 1019:1001 */ 338#define W_TCB_AUX1_SLUSH1 31 339#define S_TCB_AUX1_SLUSH1 9 340#define M_TCB_AUX1_SLUSH1 0x7ffffULL 341#define V_TCB_AUX1_SLUSH1(x) ((x) << S_TCB_AUX1_SLUSH1) 342 343/* 1023:1020 */ 344#define W_TCB_ULP_EXT 31 345#define S_TCP_ULP_EXT 28 346#define M_TCB_ULP_EXT 0xfULL 347#define V_TCB_ULP_EXT(x) ((x) << S_TCP_ULP_EXT) 348 349 350/* 840:832 */ 351#define W_TCB_IRS_ULP 26 352#define S_TCB_IRS_ULP 0 353#define M_TCB_IRS_ULP 0x1ffULL 354#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) 355 356/* 849:841 */ 357#define W_TCB_ISS_ULP 26 358#define S_TCB_ISS_ULP 9 359#define M_TCB_ISS_ULP 0x1ffULL 360#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) 361 362/* 863:850 */ 363#define W_TCB_TX_PDU_LEN 26 364#define S_TCB_TX_PDU_LEN 18 365#define M_TCB_TX_PDU_LEN 0x3fffULL 366#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) 367 368/* 879:864 */ 369#define W_TCB_CQ_IDX_SQ 27 370#define S_TCB_CQ_IDX_SQ 0 371#define M_TCB_CQ_IDX_SQ 0xffffULL 372#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) 373 374/* 895:880 */ 375#define W_TCB_CQ_IDX_RQ 27 376#define S_TCB_CQ_IDX_RQ 16 377#define M_TCB_CQ_IDX_RQ 0xffffULL 378#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) 379 380/* 911:896 */ 381#define W_TCB_QP_ID 28 382#define S_TCB_QP_ID 0 383#define M_TCB_QP_ID 0xffffULL 384#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) 385 386/* 927:912 */ 387#define W_TCB_PD_ID 28 388#define S_TCB_PD_ID 16 389#define M_TCB_PD_ID 0xffffULL 390#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) 391 392/* 959:928 */ 393#define W_TCB_STAG 29 394#define S_TCB_STAG 0 395#define M_TCB_STAG 0xffffffffULL 396#define V_TCB_STAG(x) ((x) << S_TCB_STAG) 397 398/* 985:960 */ 399#define W_TCB_RQ_START 30 400#define S_TCB_RQ_START 0 401#define M_TCB_RQ_START 0x3ffffffULL 402#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) 403 404/* 998:986 */ 405#define W_TCB_RQ_MSN 30 406#define S_TCB_RQ_MSN 26 407#define M_TCB_RQ_MSN 0x1fffULL 408#define V_TCB_RQ_MSN(x) ((__u64)(x) << S_TCB_RQ_MSN) 409 410/* 1002:999 */ 411#define W_TCB_RQ_MAX_OFFSET 31 412#define S_TCB_RQ_MAX_OFFSET 7 413#define M_TCB_RQ_MAX_OFFSET 0xfULL 414#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) 415 416/* 1015:1003 */ 417#define W_TCB_RQ_WRITE_PTR 31 418#define S_TCB_RQ_WRITE_PTR 11 419#define M_TCB_RQ_WRITE_PTR 0x1fffULL 420#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) 421 422/* 1019:1016 */ 423#define W_TCB_RDMAP_OPCODE 31 424#define S_TCB_RDMAP_OPCODE 24 425#define M_TCB_RDMAP_OPCODE 0xfULL 426#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) 427 428/* 1020:1020 */ 429#define W_TCB_ORD_L_BIT_VLD 31 430#define S_TCB_ORD_L_BIT_VLD 28 431#define M_TCB_ORD_L_BIT_VLD 0x1ULL 432#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) 433 434/* 1021:1021 */ 435#define W_TCB_TX_FLUSH 31 436#define S_TCB_TX_FLUSH 29 437#define M_TCB_TX_FLUSH 0x1ULL 438#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) 439 440/* 1022:1022 */ 441#define W_TCB_TX_OOS_RXMT 31 442#define S_TCB_TX_OOS_RXMT 30 443#define M_TCB_TX_OOS_RXMT 0x1ULL 444#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) 445 446/* 1023:1023 */ 447#define W_TCB_TX_OOS_TXMT 31 448#define S_TCB_TX_OOS_TXMT 31 449#define M_TCB_TX_OOS_TXMT 0x1ULL 450#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) 451 452/* 855:832 */ 453#define W_TCB_RX_DDP_BUF0_OFFSET 26 454#define S_TCB_RX_DDP_BUF0_OFFSET 0 455#define M_TCB_RX_DDP_BUF0_OFFSET 0xffffffULL 456#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) 457 458/* 879:856 */ 459#define W_TCB_RX_DDP_BUF0_LEN 26 460#define S_TCB_RX_DDP_BUF0_LEN 24 461#define M_TCB_RX_DDP_BUF0_LEN 0xffffffULL 462#define V_TCB_RX_DDP_BUF0_LEN(x) ((__u64)(x) << S_TCB_RX_DDP_BUF0_LEN) 463 464/* 903:880 */ 465#define W_TCB_RX_DDP_FLAGS 27 466#define S_TCB_RX_DDP_FLAGS 16 467#define M_TCB_RX_DDP_FLAGS 0xffffffULL 468#define V_TCB_RX_DDP_FLAGS(x) ((__u64)(x) << S_TCB_RX_DDP_FLAGS) 469 470/* 927:904 */ 471#define W_TCB_RX_DDP_BUF1_OFFSET 28 472#define S_TCB_RX_DDP_BUF1_OFFSET 8 473#define M_TCB_RX_DDP_BUF1_OFFSET 0xffffffULL 474#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) 475 476/* 951:928 */ 477#define W_TCB_RX_DDP_BUF1_LEN 29 478#define S_TCB_RX_DDP_BUF1_LEN 0 479#define M_TCB_RX_DDP_BUF1_LEN 0xffffffULL 480#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) 481 482/* 959:952 */ 483#define W_TCB_AUX3_SLUSH 29 484#define S_TCB_AUX3_SLUSH 24 485#define M_TCB_AUX3_SLUSH 0xffULL 486#define V_TCB_AUX3_SLUSH(x) ((x) << S_TCB_AUX3_SLUSH) 487 488/* 991:960 */ 489#define W_TCB_RX_DDP_BUF0_TAG 30 490#define S_TCB_RX_DDP_BUF0_TAG 0 491#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL 492#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) 493 494/* 1023:992 */ 495#define W_TCB_RX_DDP_BUF1_TAG 31 496#define S_TCB_RX_DDP_BUF1_TAG 0 497#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL 498#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) 499 500/* 855:832 */ 501#define W_TCB_RX_TLS_BUF_OFFSET 26 502#define S_TCB_RX_TLS_BUF_OFFSET 0 503#define M_TCB_RX_TLS_BUF_OFFSET 0xffffffULL 504#define V_TCB_RX_TLS_BUF_OFFSET(x) ((x) << S_TCB_RX_TLS_BUF_OFFSET) 505 506/* 876:856 */ 507#define W_TCB_RX_TLS_BUF_LEN 26 508#define S_TCB_RX_TLS_BUF_LEN 24 509#define M_TCB_RX_TLS_BUF_LEN 0xffffffULL 510#define V_TCB_RX_TLS_BUF_LEN(x) ((__u64)(x) << S_TCB_RX_TLS_BUF_LEN) 511 512/* 895:880 */ 513#define W_TCB_RX_TLS_FLAGS 26 514#define S_TCB_RX_TLS_FLAGS 48 515#define M_TCB_RX_TLS_FLAGS 0xffffULL 516#define V_TCB_RX_TLS_FLAGS(x) ((__u64)(x) << S_TCB_RX_TLS_FLAGS) 517 518/* 959:896 */ 519#define W_TCB_TLS_SEQ 28 520#define S_TCB_TLS_SEQ 0 521#define M_TCB_TLS_SEQ 0xffffffffffffffffULL 522#define V_TCB_TLS_SEQ(x) ((__u64)(x) << S_TCB_TLS_SEQ) 523 524/* 991:960 */ 525#define W_TCB_RX_TLS_BUF_TAG 30 526#define S_TCB_RX_TLS_BUF_TAG 0 527#define M_TCB_RX_TLS_BUF_TAG 0xffffffffULL 528#define V_TCB_RX_TLS_BUF_TAG(x) ((x) << S_TCB_RX_TLS_BUF_TAG) 529 530/* 1023:992 */ 531#define W_TCB_RX_TLS_KEY_TAG 31 532#define S_TCB_RX_TLS_KEY_TAG 0 533#define M_TCB_RX_TLS_KEY_TAG 0xffffffffULL 534#define V_TCB_RX_TLS_KEY_TAG(x) ((x) << S_TCB_RX_TLS_KEY_TAG) 535 536#define S_TF_TLS_KEY_SIZE 7 537#define V_TF_TLS_KEY_SIZE(x) ((x) << S_TF_TLS_KEY_SIZE) 538 539#define S_TF_TLS_CONTROL 2 540#define V_TF_TLS_CONTROL(x) ((x) << S_TF_TLS_CONTROL) 541 542#define S_TF_TLS_ACTIVE 1 543#define V_TF_TLS_ACTIVE(x) ((x) << S_TF_TLS_ACTIVE) 544 545#define S_TF_TLS_ENABLE 0 546#define V_TF_TLS_ENABLE(x) ((x) << S_TF_TLS_ENABLE) 547 548#define S_TF_MIGRATING 0 549#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) 550 551#define S_TF_NON_OFFLOAD 1 552#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) 553 554#define S_TF_LOCK_TID 2 555#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) 556 557#define S_TF_KEEPALIVE 3 558#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) 559 560#define S_TF_DACK 4 561#define V_TF_DACK(x) ((x) << S_TF_DACK) 562 563#define S_TF_DACK_MSS 5 564#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) 565 566#define S_TF_DACK_NOT_ACKED 6 567#define V_TF_DACK_NOT_ACKED(x) ((x) << S_TF_DACK_NOT_ACKED) 568 569#define S_TF_NAGLE 7 570#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) 571 572#define S_TF_SSWS_DISABLED 8 573#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) 574 575#define S_TF_RX_FLOW_CONTROL_DDP 9 576#define V_TF_RX_FLOW_CONTROL_DDP(x) ((x) << S_TF_RX_FLOW_CONTROL_DDP) 577 578#define S_TF_RX_FLOW_CONTROL_DISABLE 10 579#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) 580 581#define S_TF_RX_CHANNEL 11 582#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) 583 584#define S_TF_TX_CHANNEL0 12 585#define V_TF_TX_CHANNEL0(x) ((x) << S_TF_TX_CHANNEL0) 586 587#define S_TF_TX_CHANNEL1 13 588#define V_TF_TX_CHANNEL1(x) ((x) << S_TF_TX_CHANNEL1) 589 590#define S_TF_TX_QUIESCE 14 591#define V_TF_TX_QUIESCE(x) ((x) << S_TF_TX_QUIESCE) 592 593#define S_TF_RX_QUIESCE 15 594#define V_TF_RX_QUIESCE(x) ((x) << S_TF_RX_QUIESCE) 595 596#define S_TF_TX_PACE_AUTO 16 597#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) 598 599#define S_TF_MASK_HASH 16 600#define V_TF_MASK_HASH(x) ((x) << S_TF_MASK_HASH) 601 602#define S_TF_TX_PACE_FIXED 17 603#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) 604 605#define S_TF_DIRECT_STEER_HASH 17 606#define V_TF_DIRECT_STEER_HASH(x) ((x) << S_TF_DIRECT_STEER_HASH) 607 608#define S_TF_TX_QUEUE 18 609#define M_TF_TX_QUEUE 0x7ULL 610#define V_TF_TX_QUEUE(x) ((x) << S_TF_TX_QUEUE) 611 612#define S_TF_TURBO 21 613#define V_TF_TURBO(x) ((x) << S_TF_TURBO) 614 615#define S_TF_REPORT_TID 21 616#define V_TF_REPORT_TID(x) ((x) << S_TF_REPORT_TID) 617 618#define S_TF_CCTRL_SEL0 22 619#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) 620 621#define S_TF_DROP 22 622#define V_TF_DROP(x) ((x) << S_TF_DROP) 623 624#define S_TF_CCTRL_SEL1 23 625#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) 626 627#define S_TF_DIRECT_STEER 23 628#define V_TF_DIRECT_STEER(x) ((x) << S_TF_DIRECT_STEER) 629 630#define S_TF_CORE_FIN 24 631#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) 632 633#define S_TF_CORE_URG 25 634#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) 635 636#define S_TF_CORE_MORE 26 637#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) 638 639#define S_TF_CORE_PUSH 27 640#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) 641 642#define S_TF_CORE_FLUSH 28 643#define V_TF_CORE_FLUSH(x) ((x) << S_TF_CORE_FLUSH) 644 645#define S_TF_RCV_COALESCE_ENABLE 29 646#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) 647 648#define S_TF_RCV_COALESCE_PUSH 30 649#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) 650 651#define S_TF_RCV_COALESCE_LAST_PSH 31 652#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) 653 654#define S_TF_RCV_COALESCE_HEARTBEAT 32 655#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT) 656 657#define S_TF_INIT 33 658#define V_TF_INIT(x) ((__u64)(x) << S_TF_INIT) 659 660#define S_TF_ACTIVE_OPEN 34 661#define V_TF_ACTIVE_OPEN(x) ((__u64)(x) << S_TF_ACTIVE_OPEN) 662 663#define S_TF_ASK_MODE 35 664#define V_TF_ASK_MODE(x) ((__u64)(x) << S_TF_ASK_MODE) 665 666#define S_TF_MOD_SCHD_REASON0 36 667#define V_TF_MOD_SCHD_REASON0(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON0) 668 669#define S_TF_MOD_SCHD_REASON1 37 670#define V_TF_MOD_SCHD_REASON1(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON1) 671 672#define S_TF_MOD_SCHD_REASON2 38 673#define V_TF_MOD_SCHD_REASON2(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON2) 674 675#define S_TF_MOD_SCHD_TX 39 676#define V_TF_MOD_SCHD_TX(x) ((__u64)(x) << S_TF_MOD_SCHD_TX) 677 678#define S_TF_MOD_SCHD_RX 40 679#define V_TF_MOD_SCHD_RX(x) ((__u64)(x) << S_TF_MOD_SCHD_RX) 680 681#define S_TF_TIMER 41 682#define V_TF_TIMER(x) ((__u64)(x) << S_TF_TIMER) 683 684#define S_TF_DACK_TIMER 42 685#define V_TF_DACK_TIMER(x) ((__u64)(x) << S_TF_DACK_TIMER) 686 687#define S_TF_PEER_FIN 43 688#define V_TF_PEER_FIN(x) ((__u64)(x) << S_TF_PEER_FIN) 689 690#define S_TF_TX_COMPACT 44 691#define V_TF_TX_COMPACT(x) ((__u64)(x) << S_TF_TX_COMPACT) 692 693#define S_TF_RX_COMPACT 45 694#define V_TF_RX_COMPACT(x) ((__u64)(x) << S_TF_RX_COMPACT) 695 696#define S_TF_RDMA_ERROR 46 697#define V_TF_RDMA_ERROR(x) ((__u64)(x) << S_TF_RDMA_ERROR) 698 699#define S_TF_RDMA_FLM_ERROR 47 700#define V_TF_RDMA_FLM_ERROR(x) ((__u64)(x) << S_TF_RDMA_FLM_ERROR) 701 702#define S_TF_TX_PDU_OUT 48 703#define V_TF_TX_PDU_OUT(x) ((__u64)(x) << S_TF_TX_PDU_OUT) 704 705#define S_TF_RX_PDU_OUT 49 706#define V_TF_RX_PDU_OUT(x) ((__u64)(x) << S_TF_RX_PDU_OUT) 707 708#define S_TF_DUPACK_COUNT_ODD 50 709#define V_TF_DUPACK_COUNT_ODD(x) ((__u64)(x) << S_TF_DUPACK_COUNT_ODD) 710 711#define S_TF_FAST_RECOVERY 51 712#define V_TF_FAST_RECOVERY(x) ((__u64)(x) << S_TF_FAST_RECOVERY) 713 714#define S_TF_RECV_SCALE 52 715#define V_TF_RECV_SCALE(x) ((__u64)(x) << S_TF_RECV_SCALE) 716 717#define S_TF_RECV_TSTMP 53 718#define V_TF_RECV_TSTMP(x) ((__u64)(x) << S_TF_RECV_TSTMP) 719 720#define S_TF_RECV_SACK 54 721#define V_TF_RECV_SACK(x) ((__u64)(x) << S_TF_RECV_SACK) 722 723#define S_TF_PEND_CTL0 55 724#define V_TF_PEND_CTL0(x) ((__u64)(x) << S_TF_PEND_CTL0) 725 726#define S_TF_PEND_CTL1 56 727#define V_TF_PEND_CTL1(x) ((__u64)(x) << S_TF_PEND_CTL1) 728 729#define S_TF_PEND_CTL2 57 730#define V_TF_PEND_CTL2(x) ((__u64)(x) << S_TF_PEND_CTL2) 731 732#define S_TF_IP_VERSION 58 733#define V_TF_IP_VERSION(x) ((__u64)(x) << S_TF_IP_VERSION) 734 735#define S_TF_CCTRL_ECN 59 736#define V_TF_CCTRL_ECN(x) ((__u64)(x) << S_TF_CCTRL_ECN) 737 738#define S_TF_LPBK 59 739#define V_TF_LPBK(x) ((__u64)(x) << S_TF_LPBK) 740 741#define S_TF_CCTRL_ECE 60 742#define V_TF_CCTRL_ECE(x) ((__u64)(x) << S_TF_CCTRL_ECE) 743 744#define S_TF_REWRITE_DMAC 60 745#define V_TF_REWRITE_DMAC(x) ((__u64)(x) << S_TF_REWRITE_DMAC) 746 747#define S_TF_CCTRL_CWR 61 748#define V_TF_CCTRL_CWR(x) ((__u64)(x) << S_TF_CCTRL_CWR) 749 750#define S_TF_REWRITE_SMAC 61 751#define V_TF_REWRITE_SMAC(x) ((__u64)(x) << S_TF_REWRITE_SMAC) 752 753#define S_TF_CCTRL_RFR 62 754#define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR) 755 756#define S_TF_CORE_BYPASS 63 757#define V_TF_CORE_BYPASS(x) ((__u64)(x) << S_TF_CORE_BYPASS) 758 759#define S_TF_DDP_INDICATE_OUT 16 760#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) 761 762#define S_TF_DDP_ACTIVE_BUF 17 763#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) 764 765#define S_TF_DDP_OFF 18 766#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) 767 768#define S_TF_DDP_WAIT_FRAG 19 769#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) 770 771#define S_TF_DDP_BUF_INF 20 772#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) 773 774#define S_TF_DDP_RX2TX 21 775#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) 776 777#define S_TF_DDP_BUF0_VALID 24 778#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) 779 780#define S_TF_DDP_BUF0_INDICATE 25 781#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) 782 783#define S_TF_DDP_BUF0_FLUSH 26 784#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) 785 786#define S_TF_DDP_PSHF_ENABLE_0 27 787#define V_TF_DDP_PSHF_ENABLE_0(x) ((x) << S_TF_DDP_PSHF_ENABLE_0) 788 789#define S_TF_DDP_PUSH_DISABLE_0 28 790#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) 791 792#define S_TF_DDP_PSH_NO_INVALIDATE0 29 793#define V_TF_DDP_PSH_NO_INVALIDATE0(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE0) 794 795#define S_TF_DDP_BUF1_VALID 32 796#define V_TF_DDP_BUF1_VALID(x) ((__u64)(x) << S_TF_DDP_BUF1_VALID) 797 798#define S_TF_DDP_BUF1_INDICATE 33 799#define V_TF_DDP_BUF1_INDICATE(x) ((__u64)(x) << S_TF_DDP_BUF1_INDICATE) 800 801#define S_TF_DDP_BUF1_FLUSH 34 802#define V_TF_DDP_BUF1_FLUSH(x) ((__u64)(x) << S_TF_DDP_BUF1_FLUSH) 803 804#define S_TF_DDP_PSHF_ENABLE_1 35 805#define V_TF_DDP_PSHF_ENABLE_1(x) ((__u64)(x) << S_TF_DDP_PSHF_ENABLE_1) 806 807#define S_TF_DDP_PUSH_DISABLE_1 36 808#define V_TF_DDP_PUSH_DISABLE_1(x) ((__u64)(x) << S_TF_DDP_PUSH_DISABLE_1) 809 810#define S_TF_DDP_PSH_NO_INVALIDATE1 37 811#define V_TF_DDP_PSH_NO_INVALIDATE1(x) ((__u64)(x) << S_TF_DDP_PSH_NO_INVALIDATE1) 812 813#endif /* _T4_TCB_DEFS_H */ 814