1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#ifndef ELINK_H 33#define ELINK_H 34 35#define ELINK_DEBUG 36 37 38 39 40 41 42/***********************************************************/ 43/* CLC Call backs functions */ 44/***********************************************************/ 45/* CLC device structure */ 46struct bxe_softc; 47 48extern uint32_t elink_cb_reg_read(struct bxe_softc *sc, uint32_t reg_addr); 49extern void elink_cb_reg_write(struct bxe_softc *sc, uint32_t reg_addr, uint32_t val); 50/* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/ 51extern void elink_cb_reg_wb_write(struct bxe_softc *sc, uint32_t offset, 52 uint32_t *wb_write, uint16_t len); 53extern void elink_cb_reg_wb_read(struct bxe_softc *sc, uint32_t offset, 54 uint32_t *wb_write, uint16_t len); 55 56/* mode - 0( LOW ) /1(HIGH)*/ 57extern uint8_t elink_cb_gpio_write(struct bxe_softc *sc, 58 uint16_t gpio_num, 59 uint8_t mode, uint8_t port); 60extern uint8_t elink_cb_gpio_mult_write(struct bxe_softc *sc, 61 uint8_t pins, 62 uint8_t mode); 63 64extern uint32_t elink_cb_gpio_read(struct bxe_softc *sc, uint16_t gpio_num, uint8_t port); 65extern uint8_t elink_cb_gpio_int_write(struct bxe_softc *sc, 66 uint16_t gpio_num, 67 uint8_t mode, uint8_t port); 68 69extern uint32_t elink_cb_fw_command(struct bxe_softc *sc, uint32_t command, uint32_t param); 70 71/* Delay */ 72extern void elink_cb_udelay(struct bxe_softc *sc, uint32_t microsecond); 73 74/* This function is called every 1024 bytes downloading of phy firmware. 75Driver can use it to print to screen indication for download progress */ 76extern void elink_cb_download_progress(struct bxe_softc *sc, uint32_t cur, uint32_t total); 77 78/* Each log type has its own parameters */ 79typedef enum elink_log_id { 80 ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */ 81 ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */ 82 ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */ 83 ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */ 84 ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */ 85}elink_log_id_t; 86 87typedef enum elink_status { 88 ELINK_STATUS_OK = 0, 89 ELINK_STATUS_ERROR, 90 ELINK_STATUS_TIMEOUT, 91 ELINK_STATUS_NO_LINK, 92 ELINK_STATUS_INVALID_IMAGE, 93 ELINK_OP_NOT_SUPPORTED = 122 94} elink_status_t; 95extern void elink_cb_event_log(struct bxe_softc *sc, const elink_log_id_t log_id, ...); 96extern void elink_cb_load_warpcore_microcode(void); 97 98extern uint8_t elink_cb_path_id(struct bxe_softc *sc); 99 100extern void elink_cb_notify_link_changed(struct bxe_softc *sc); 101 102#define ELINK_EVENT_LOG_LEVEL_ERROR 1 103#define ELINK_EVENT_LOG_LEVEL_WARNING 2 104#define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1 105#define ELINK_EVENT_ID_SFP_POWER_FAULT 2 106 107#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 108/* Debug prints */ 109#ifdef ELINK_DEBUG 110 111extern void elink_cb_dbg(struct bxe_softc *sc, char *fmt); 112extern void elink_cb_dbg1(struct bxe_softc *sc, char *fmt, uint32_t arg1); 113extern void elink_cb_dbg2(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2); 114extern void elink_cb_dbg3(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2, 115 uint32_t arg3); 116 117#define ELINK_DEBUG_P0(sc, fmt) elink_cb_dbg(sc, fmt) 118#define ELINK_DEBUG_P1(sc, fmt, arg1) elink_cb_dbg1(sc, fmt, arg1) 119#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) elink_cb_dbg2(sc, fmt, arg1, arg2) 120#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \ 121 elink_cb_dbg3(sc, fmt, arg1, arg2, arg3) 122#else 123#define ELINK_DEBUG_P0(sc, fmt) 124#define ELINK_DEBUG_P1(sc, fmt, arg1) 125#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) 126#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) 127#endif 128 129/***********************************************************/ 130/* Defines */ 131/***********************************************************/ 132#define ELINK_DEFAULT_PHY_DEV_ADDR 3 133#define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5 134 135 136#define DUPLEX_FULL 1 137#define DUPLEX_HALF 2 138 139#define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO 140#define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX 141#define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX 142#define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH 143#define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE 144 145#define ELINK_NET_SERDES_IF_XFI 1 146#define ELINK_NET_SERDES_IF_SFI 2 147#define ELINK_NET_SERDES_IF_KR 3 148#define ELINK_NET_SERDES_IF_DXGXS 4 149 150#define ELINK_SPEED_AUTO_NEG 0 151#define ELINK_SPEED_10 10 152#define ELINK_SPEED_100 100 153#define ELINK_SPEED_1000 1000 154#define ELINK_SPEED_2500 2500 155#define ELINK_SPEED_10000 10000 156#define ELINK_SPEED_20000 20000 157 158#define ELINK_I2C_DEV_ADDR_A0 0xa0 159#define ELINK_I2C_DEV_ADDR_A2 0xa2 160 161#define ELINK_SFP_EEPROM_PAGE_SIZE 16 162#define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14 163#define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16 164#define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25 165#define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3 166#define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28 167#define ELINK_SFP_EEPROM_PART_NO_SIZE 16 168#define ELINK_SFP_EEPROM_REVISION_ADDR 0x38 169#define ELINK_SFP_EEPROM_REVISION_SIZE 4 170#define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44 171#define ELINK_SFP_EEPROM_SERIAL_SIZE 16 172#define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ 173#define ELINK_SFP_EEPROM_DATE_SIZE 6 174#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c 175#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1 176#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2) 177#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e 178#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1 179#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR 0x60 180#define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE 16 181 182 183#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e 184#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f 185 186#define ELINK_PWR_FLT_ERR_MSG_LEN 250 187 188#define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \ 189 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 190#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \ 191 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ 192 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) 193#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \ 194 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) 195 196/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ 197#define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) 198/* Single Media board contains single external phy */ 199#define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2) 200/* Dual Media board contains two external phy with different media */ 201#define ELINK_DUAL_MEDIA(params) (params->num_phys == 3) 202 203#define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF 204#define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00 205#define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 206#define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16 207#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ 208 ELINK_FW_PARAM_PHY_ADDR_MASK) 209#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ 210 ELINK_FW_PARAM_PHY_TYPE_MASK) 211#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ 212 ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \ 213 ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 214#define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ 215 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 216 217 218#define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 219#define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250 220 221#define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) 222 223#define ELINK_BMAC_CONTROL_RX_ENABLE 2 224/***********************************************************/ 225/* Structs */ 226/***********************************************************/ 227#define ELINK_INT_PHY 0 228#define ELINK_EXT_PHY1 1 229#define ELINK_EXT_PHY2 2 230#define ELINK_MAX_PHYS 3 231 232/* Same configuration is shared between the XGXS and the first external phy */ 233#define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1) 234#define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \ 235 0 : (_phy_idx - 1)) 236/***********************************************************/ 237/* elink_phy struct */ 238/* Defines the required arguments and function per phy */ 239/***********************************************************/ 240struct elink_vars; 241struct elink_params; 242struct elink_phy; 243 244typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params, 245 struct elink_vars *vars); 246typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params, 247 struct elink_vars *vars); 248typedef void (*link_reset_t)(struct elink_phy *phy, 249 struct elink_params *params); 250typedef void (*config_loopback_t)(struct elink_phy *phy, 251 struct elink_params *params); 252typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len); 253typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params); 254typedef void (*set_link_led_t)(struct elink_phy *phy, 255 struct elink_params *params, uint8_t mode); 256typedef void (*phy_specific_func_t)(struct elink_phy *phy, 257 struct elink_params *params, uint32_t action); 258struct elink_reg_set { 259 uint8_t devad; 260 uint16_t reg; 261 uint16_t val; 262}; 263 264struct elink_phy { 265 uint32_t type; 266 267 /* Loaded during init */ 268 uint8_t addr; 269 uint8_t def_md_devad; 270 uint16_t flags; 271 /* No Over-Current detection */ 272#define ELINK_FLAGS_NOC (1<<1) 273 /* Fan failure detection required */ 274#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2) 275 /* Initialize first the XGXS and only then the phy itself */ 276#define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3) 277#define ELINK_FLAGS_WC_DUAL_MODE (1<<4) 278#define ELINK_FLAGS_4_PORT_MODE (1<<5) 279#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6) 280#define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7) 281#define ELINK_FLAGS_MDC_MDIO_WA (1<<8) 282#define ELINK_FLAGS_DUMMY_READ (1<<9) 283#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10) 284#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11) 285#define ELINK_FLAGS_TX_ERROR_CHECK (1<<12) 286#define ELINK_FLAGS_EEE (1<<13) 287#define ELINK_FLAGS_TEMPERATURE (1<<14) 288#define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15) 289 290 /* preemphasis values for the rx side */ 291 uint16_t rx_preemphasis[4]; 292 293 /* preemphasis values for the tx side */ 294 uint16_t tx_preemphasis[4]; 295 296 /* EMAC address for access MDIO */ 297 uint32_t mdio_ctrl; 298 299 uint32_t supported; 300#define ELINK_SUPPORTED_10baseT_Half (1<<0) 301#define ELINK_SUPPORTED_10baseT_Full (1<<1) 302#define ELINK_SUPPORTED_100baseT_Half (1<<2) 303#define ELINK_SUPPORTED_100baseT_Full (1<<3) 304#define ELINK_SUPPORTED_1000baseT_Full (1<<4) 305#define ELINK_SUPPORTED_2500baseX_Full (1<<5) 306#define ELINK_SUPPORTED_10000baseT_Full (1<<6) 307#define ELINK_SUPPORTED_TP (1<<7) 308#define ELINK_SUPPORTED_FIBRE (1<<8) 309#define ELINK_SUPPORTED_Autoneg (1<<9) 310#define ELINK_SUPPORTED_Pause (1<<10) 311#define ELINK_SUPPORTED_Asym_Pause (1<<11) 312#define ELINK_SUPPORTED_1000baseKX_Full (1<<17) 313#define ELINK_SUPPORTED_10000baseKR_Full (1<<19) 314#define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21) 315#define ELINK_SUPPORTED_20000baseKR2_Full (1<<22) 316 317 uint32_t media_type; 318#define ELINK_ETH_PHY_UNSPECIFIED 0x0 319#define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1 320#define ELINK_ETH_PHY_XFP_FIBER 0x2 321#define ELINK_ETH_PHY_DA_TWINAX 0x3 322#define ELINK_ETH_PHY_BASE_T 0x4 323#define ELINK_ETH_PHY_SFP_1G_FIBER 0x5 324#define ELINK_ETH_PHY_KR 0xf0 325#define ELINK_ETH_PHY_CX4 0xf1 326#define ELINK_ETH_PHY_NOT_PRESENT 0xff 327 328 /* The address in which version is located*/ 329 uint32_t ver_addr; 330 331 uint16_t req_flow_ctrl; 332 333 uint16_t req_line_speed; 334 335 uint32_t speed_cap_mask; 336 337 uint16_t req_duplex; 338 uint16_t rsrv; 339 /* Called per phy/port init, and it configures LASI, speed, autoneg, 340 duplex, flow control negotiation, etc. */ 341 config_init_t config_init; 342 343 /* Called due to interrupt. It determines the link, speed */ 344 read_status_t read_status; 345 346 /* Called when driver is unloading. Should reset the phy */ 347 link_reset_t link_reset; 348 349 /* Set the loopback configuration for the phy */ 350 config_loopback_t config_loopback; 351 352 /* Format the given raw number into str up to len */ 353 format_fw_ver_t format_fw_ver; 354 355 /* Reset the phy (both ports) */ 356 hw_reset_t hw_reset; 357 358 /* Set link led mode (on/off/oper)*/ 359 set_link_led_t set_link_led; 360 361 /* PHY Specific tasks */ 362 phy_specific_func_t phy_specific_func; 363#define ELINK_DISABLE_TX 1 364#define ELINK_ENABLE_TX 2 365#define ELINK_PHY_INIT 3 366}; 367 368/* Inputs parameters to the CLC */ 369struct elink_params { 370 371 uint8_t port; 372 373 /* Default / User Configuration */ 374 uint8_t loopback_mode; 375#define ELINK_LOOPBACK_NONE 0 376#define ELINK_LOOPBACK_EMAC 1 377#define ELINK_LOOPBACK_BMAC 2 378#define ELINK_LOOPBACK_XGXS 3 379#define ELINK_LOOPBACK_EXT_PHY 4 380#define ELINK_LOOPBACK_EXT 5 381#define ELINK_LOOPBACK_UMAC 6 382#define ELINK_LOOPBACK_XMAC 7 383 384 /* Device parameters */ 385 uint8_t mac_addr[6]; 386 387 uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE]; 388 uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE]; 389 390 uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ 391 392 /* shmem parameters */ 393 uint32_t shmem_base; 394 uint32_t shmem2_base; 395 uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; 396 uint32_t switch_cfg; 397#define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH 398#define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH 399#define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT 400 401 uint32_t lane_config; 402 403 /* Phy register parameter */ 404 uint32_t chip_id; 405 406 /* features */ 407 uint32_t feature_config_flags; 408#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 409#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1) 410#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) 411#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) 412#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4) 413#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5) 414#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6) 415#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7) 416#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8) 417#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9) 418#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10) 419#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11) 420#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12) 421#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13) 422#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14) 423#define ELINK_FEATURE_CONFIG_DISABLE_PD (1<<15) 424 425 /* Will be populated during common init */ 426 struct elink_phy phy[ELINK_MAX_PHYS]; 427 428 /* Will be populated during common init */ 429 uint8_t num_phys; 430 431 uint8_t rsrv; 432 433 /* Used to configure the EEE Tx LPI timer, has several modes of 434 * operation, according to bits 29:28 - 435 * 2'b00: Timer will be configured by nvram, output will be the value 436 * from nvram. 437 * 2'b01: Timer will be configured by nvram, output will be in 438 * microseconds. 439 * 2'b10: bits 1:0 contain an nvram value which will be used instead 440 * of the one located in the nvram. Output will be that value. 441 * 2'b11: bits 19:0 contain the idle timer in microseconds; output 442 * will be in microseconds. 443 * Bits 31:30 should be 2'b11 in order for EEE to be enabled. 444 */ 445 uint32_t eee_mode; 446#define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00) 447#define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100) 448#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000) 449#define ELINK_EEE_MODE_NVRAM_MASK (0x3) 450#define ELINK_EEE_MODE_TIMER_MASK (0xfffff) 451#define ELINK_EEE_MODE_OUTPUT_TIME (1<<28) 452#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29) 453#define ELINK_EEE_MODE_ENABLE_LPI (1<<30) 454#define ELINK_EEE_MODE_ADV_LPI (1<<31) 455 456 uint16_t hw_led_mode; /* part of the hw_config read from the shmem */ 457 uint32_t multi_phy_config; 458 459 /* Device pointer passed to all callback functions */ 460 struct bxe_softc *sc; 461 uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when 462 req_flow_ctrl is set to AUTO */ 463 uint16_t link_flags; 464#define ELINK_LINK_FLAGS_INT_DISABLED (1<<0) 465#define ELINK_PHY_INITIALIZED (1<<1) 466 uint32_t lfa_base; 467 468 /* The same definitions as the shmem2 parameter */ 469 uint32_t link_attr_sync; 470}; 471 472/* Output parameters */ 473struct elink_vars { 474 uint8_t phy_flags; 475#define PHY_XGXS_FLAG (1<<0) 476#define PHY_SGMII_FLAG (1<<1) 477#define PHY_PHYSICAL_LINK_FLAG (1<<2) 478#define PHY_HALF_OPEN_CONN_FLAG (1<<3) 479#define PHY_OVER_CURRENT_FLAG (1<<4) 480#define PHY_SFP_TX_FAULT_FLAG (1<<5) 481 482 uint8_t mac_type; 483#define ELINK_MAC_TYPE_NONE 0 484#define ELINK_MAC_TYPE_EMAC 1 485#define ELINK_MAC_TYPE_BMAC 2 486#define ELINK_MAC_TYPE_UMAC 3 487#define ELINK_MAC_TYPE_XMAC 4 488 489 uint8_t phy_link_up; /* internal phy link indication */ 490 uint8_t link_up; 491 492 uint16_t line_speed; 493 uint16_t duplex; 494 495 uint16_t flow_ctrl; 496 uint16_t ieee_fc; 497 498 /* The same definitions as the shmem parameter */ 499 uint32_t link_status; 500 uint32_t eee_status; 501 uint8_t fault_detected; 502 uint8_t check_kr2_recovery_cnt; 503#define ELINK_CHECK_KR2_RECOVERY_CNT 5 504 uint16_t periodic_flags; 505#define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001 506 507 uint32_t aeu_int_mask; 508 uint8_t rx_tx_asic_rst; 509 uint8_t turn_to_run_wc_rt; 510 uint16_t rsrv2; 511 512}; 513 514/***********************************************************/ 515/* Functions */ 516/***********************************************************/ 517elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars); 518 519/* Reset the link. Should be called when driver or interface goes down 520 Before calling phy firmware upgrade, the reset_ext_phy should be set 521 to 0 */ 522elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 523 uint8_t reset_ext_phy); 524elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars); 525/* elink_link_update should be called upon link interrupt */ 526elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars); 527 528/* use the following phy functions to read/write from external_phy 529 In order to use it to read/write internal phy registers, use 530 ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as 531 the register */ 532elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr, 533 uint8_t devad, uint16_t reg, uint16_t *ret_val); 534 535elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr, 536 uint8_t devad, uint16_t reg, uint16_t val); 537 538/* Reads the link_status from the shmem, 539 and update the link vars accordingly */ 540void elink_link_status_update(struct elink_params *input, 541 struct elink_vars *output); 542/* returns string representing the fw_version of the external phy */ 543elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version, 544 uint16_t len); 545 546/* Set/Unset the led 547 Basically, the CLC takes care of the led for the link, but in case one needs 548 to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to 549 blink the led, and ELINK_LED_MODE_OFF to set the led off.*/ 550elink_status_t elink_set_led(struct elink_params *params, 551 struct elink_vars *vars, uint8_t mode, uint32_t speed); 552#define ELINK_LED_MODE_OFF 0 553#define ELINK_LED_MODE_ON 1 554#define ELINK_LED_MODE_OPER 2 555#define ELINK_LED_MODE_FRONT_PANEL_OFF 3 556 557/* elink_handle_module_detect_int should be called upon module detection 558 interrupt */ 559void elink_handle_module_detect_int(struct elink_params *params); 560 561/* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up, 562 otherwise link is down*/ 563elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 564 uint8_t is_serdes); 565 566 567/* One-time initialization for external phy after power up */ 568elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[], 569 uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled); 570 571/* Reset the external PHY using GPIO */ 572void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port); 573 574/* Reset the external of SFX7101 */ 575void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy); 576 577/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ 578elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 579 struct elink_params *params, uint8_t dev_addr, 580 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf); 581 582void elink_hw_reset_phy(struct elink_params *params); 583 584/* Check swap bit and adjust PHY order */ 585uint32_t elink_phy_selection(struct elink_params *params); 586 587/* Probe the phys on board, and populate them in "params" */ 588elink_status_t elink_phy_probe(struct elink_params *params); 589 590/* Checks if fan failure detection is required on one of the phys on board */ 591uint8_t elink_fan_failure_det_req(struct bxe_softc *sc, uint32_t shmem_base, 592 uint32_t shmem2_base, uint8_t port); 593 594/* Open / close the gate between the NIG and the BRB */ 595void elink_set_rx_filter(struct elink_params *params, uint8_t en); 596 597/* DCBX structs */ 598 599/* Number of maximum COS per chip */ 600#define ELINK_DCBX_E2E3_MAX_NUM_COS (2) 601#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6) 602#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3) 603#define ELINK_DCBX_E3B0_MAX_NUM_COS ( \ 604 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \ 605 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1)) 606 607#define ELINK_DCBX_MAX_NUM_COS ( \ 608 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \ 609 ELINK_DCBX_E2E3_MAX_NUM_COS)) 610 611/* PFC port configuration params */ 612struct elink_nig_brb_pfc_port_params { 613 /* NIG */ 614 uint32_t pause_enable; 615 uint32_t llfc_out_en; 616 uint32_t llfc_enable; 617 uint32_t pkt_priority_to_cos; 618 uint8_t num_of_rx_cos_priority_mask; 619 uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS]; 620 uint32_t llfc_high_priority_classes; 621 uint32_t llfc_low_priority_classes; 622}; 623 624 625/* ETS port configuration params */ 626struct elink_ets_bw_params { 627 uint8_t bw; 628}; 629 630struct elink_ets_sp_params { 631 /** 632 * valid values are 0 - 5. 0 is highest strict priority. 633 * There can't be two COS's with the same pri. 634 */ 635 uint8_t pri; 636}; 637 638enum elink_cos_state { 639 elink_cos_state_strict = 0, 640 elink_cos_state_bw = 1, 641}; 642 643struct elink_ets_cos_params { 644 enum elink_cos_state state ; 645 union { 646 struct elink_ets_bw_params bw_params; 647 struct elink_ets_sp_params sp_params; 648 } params; 649}; 650 651struct elink_ets_params { 652 uint8_t num_of_cos; /* Number of valid COS entries*/ 653 struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS]; 654}; 655 656/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB 657 * when link is already up 658 */ 659elink_status_t elink_update_pfc(struct elink_params *params, 660 struct elink_vars *vars, 661 struct elink_nig_brb_pfc_port_params *pfc_params); 662 663 664/* Used to configure the ETS to disable */ 665elink_status_t elink_ets_disabled(struct elink_params *params, 666 struct elink_vars *vars); 667 668/* Used to configure the ETS to BW limited */ 669void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw, 670 const uint32_t cos1_bw); 671 672/* Used to configure the ETS to strict */ 673elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos); 674 675 676/* Configure the COS to ETS according to BW and SP settings.*/ 677elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 678 const struct elink_vars *vars, 679 struct elink_ets_params *ets_params); 680/* Read pfc statistic*/ 681void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 682 uint32_t pfc_frames_sent[2], 683 uint32_t pfc_frames_received[2]); 684void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars, 685 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base, 686 uint8_t port); 687//elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 688// struct elink_params *params); 689 690void elink_period_func(struct elink_params *params, struct elink_vars *vars); 691 692//elink_status_t elink_check_half_open_conn(struct elink_params *params, 693// struct elink_vars *vars, uint8_t notify); 694 695void elink_enable_pmd_tx(struct elink_params *params); 696 697 698 699#endif /* ELINK_H */ 700 701