1/*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
3 * Copyright (c) 2017 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Landon Fuller
7 * under sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer,
14 *    without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
17 *    redistribution must be conditioned upon including a substantially
18 *    similar Disclaimer requirement for further binary redistribution.
19 *
20 * NO WARRANTY
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGES.
32 *
33 * $FreeBSD$
34 */
35
36#ifndef _BHND_BHNDB_PCIVAR_H_
37#define _BHND_BHNDB_PCIVAR_H_
38
39#include "bhndbvar.h"
40
41/*
42 * bhndb(4) PCI driver subclass.
43 */
44
45DECLARE_CLASS(bhndb_pci_driver);
46
47struct bhndb_pci_softc;
48
49/*
50 * An interconnect-specific function implementing BHNDB_SET_WINDOW_ADDR
51 */
52typedef int (*bhndb_pci_set_regwin_t)(device_t dev, device_t pci_dev,
53	         const struct bhndb_regwin *rw, bhnd_addr_t addr);
54
55/**
56 * PCI/PCIe bridge-level device quirks
57 */
58enum {
59	/** No quirks */
60	BHNDB_PCI_QUIRK_NONE		= 0,
61
62	/**
63	 * The core requires fixup of the BAR0 SROM shadow to point at the
64	 * current PCI core.
65	 */
66	BHNDB_PCI_QUIRK_SRSH_WAR	= (1<<0),
67
68	/**
69	 * The PCI (rev <= 5) core does not provide interrupt status/mask
70	 * registers; these siba-only devices require routing backplane
71	 * interrupt flags via the SIBA_CFG0_INTVEC register.
72	 */
73	BHNDB_PCI_QUIRK_SIBA_INTVEC	= (1<<1),
74};
75
76/** bhndb_pci quirk table entry */
77struct bhndb_pci_quirk {
78	struct bhnd_chip_match	chip_desc;	/**< chip match descriptor */
79	struct bhnd_core_match	core_desc;	/**< core match descriptor */
80	uint32_t		quirks;		/**< quirk flags */
81};
82
83#define	BHNDB_PCI_QUIRK(_rev, _flags)	{			\
84	{ BHND_MATCH_ANY },						\
85	{ BHND_MATCH_CORE_REV(_rev) },					\
86	_flags,								\
87}
88
89#define	BHNDB_PCI_QUIRK_END	\
90	{ { BHND_MATCH_ANY },  { BHND_MATCH_ANY }, 0 }
91
92#define	BHNDB_PCI_IS_QUIRK_END(_q)	\
93	(BHND_MATCH_IS_ANY(&(_q)->core_desc) &&	\
94	 BHND_MATCH_IS_ANY(&(_q)->chip_desc) &&	\
95	 (_q)->quirks == 0)
96
97/** bhndb_pci core table entry */
98struct bhndb_pci_core {
99	struct bhnd_core_match	 match;		/**< core match descriptor */
100	struct bhndb_pci_quirk	*quirks;	/**< quirk table */
101};
102
103#define	BHNDB_PCI_CORE(_device, _quirks) {				\
104	{ BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_ ## _device) },	\
105	_quirks								\
106}
107#define	BHNDB_PCI_CORE_END		{ { BHND_MATCH_ANY }, NULL }
108#define	BHNDB_PCI_IS_CORE_END(_c)	BHND_MATCH_IS_ANY(&(_c)->match)
109
110struct bhndb_pci_softc {
111	struct bhndb_softc	 bhndb;		/**< parent softc */
112	device_t		 dev;		/**< bridge device */
113	device_t		 parent;	/**< parent PCI device */
114	bhnd_devclass_t		 pci_devclass;	/**< PCI core's devclass */
115	uint32_t		 pci_quirks;	/**< PCI bridge-level quirks */
116	int			 msi_count;	/**< MSI count, or 0 */
117	struct bhndb_intr_isrc	*isrc;		/**< host interrupt source */
118
119	struct mtx		 mtx;
120	bhndb_pci_set_regwin_t	 set_regwin;	/**< regwin handler */
121};
122
123#define	BHNDB_PCI_LOCK_INIT(sc) \
124	mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
125	    "bhndb_pc state", MTX_DEF)
126#define	BHNDB_PCI_LOCK(sc)			mtx_lock(&(sc)->mtx)
127#define	BHNDB_PCI_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
128#define	BHNDB_PCI_LOCK_ASSERT(sc, what)		mtx_assert(&(sc)->mtx, what)
129#define	BHNDB_PCI_LOCK_DESTROY(sc)		mtx_destroy(&(sc)->mtx)
130
131#endif /* _BHND_BHNDB_PCIVAR_H_ */
132