1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/endian.h> 36#include <sys/ata.h> 37#include <sys/bio.h> 38#include <sys/conf.h> 39#include <sys/ctype.h> 40#include <sys/bus.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/bus.h> 45#include <sys/rman.h> 46#include <dev/ata/ata-all.h> 47#include <dev/ata/ata-pci.h> 48#include <ata_if.h> 49 50#include <vm/vm.h> 51#include <vm/pmap.h> 52 53#include <cam/cam.h> 54#include <cam/cam_ccb.h> 55 56/* prototypes */ 57static int ata_generic_status(device_t dev); 58static int ata_wait(struct ata_channel *ch, int unit, u_int8_t); 59static void ata_pio_read(struct ata_request *, int); 60static void ata_pio_write(struct ata_request *, int); 61static void ata_tf_read(struct ata_request *); 62static void ata_tf_write(struct ata_request *); 63 64/* 65 * low level ATA functions 66 */ 67void 68ata_generic_hw(device_t dev) 69{ 70 struct ata_channel *ch = device_get_softc(dev); 71 72 ch->hw.begin_transaction = ata_begin_transaction; 73 ch->hw.end_transaction = ata_end_transaction; 74 ch->hw.status = ata_generic_status; 75 ch->hw.softreset = NULL; 76 ch->hw.command = ata_generic_command; 77 ch->hw.tf_read = ata_tf_read; 78 ch->hw.tf_write = ata_tf_write; 79 ch->hw.pm_read = NULL; 80 ch->hw.pm_write = NULL; 81} 82 83/* must be called with ATA channel locked and state_mtx held */ 84int 85ata_begin_transaction(struct ata_request *request) 86{ 87 struct ata_channel *ch = device_get_softc(request->parent); 88 int dummy, error; 89 90 ATA_DEBUG_RQ(request, "begin transaction"); 91 92 /* disable ATAPI DMA writes if HW doesn't support it */ 93 if ((ch->flags & ATA_NO_ATAPI_DMA) && 94 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI) 95 request->flags &= ~ATA_R_DMA; 96 if ((ch->flags & ATA_ATAPI_DMA_RO) && 97 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 98 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 99 request->flags &= ~ATA_R_DMA; 100 101 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 102 /* ATA PIO data transfer and control commands */ 103 default: 104 { 105 /* record command direction here as our request might be gone later */ 106 int write = (request->flags & ATA_R_WRITE); 107 108 /* issue command */ 109 if (ch->hw.command(request)) { 110 device_printf(request->parent, "error issuing %s command\n", 111 ata_cmd2str(request)); 112 request->result = EIO; 113 goto begin_finished; 114 } 115 116 /* device reset doesn't interrupt */ 117 if (request->u.ata.command == ATA_DEVICE_RESET) { 118 int timeout = 1000000; 119 do { 120 DELAY(10); 121 request->status = ATA_IDX_INB(ch, ATA_STATUS); 122 } while (request->status & ATA_S_BUSY && timeout--); 123 if (request->status & ATA_S_ERROR) 124 request->error = ATA_IDX_INB(ch, ATA_ERROR); 125 ch->hw.tf_read(request); 126 goto begin_finished; 127 } 128 129 /* if write command output the data */ 130 if (write) { 131 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 132 device_printf(request->parent, 133 "timeout waiting for write DRQ\n"); 134 request->result = EIO; 135 goto begin_finished; 136 } 137 ata_pio_write(request, request->transfersize); 138 } 139 } 140 goto begin_continue; 141 142 /* ATA DMA data transfer commands */ 143 case ATA_R_DMA: 144 /* check sanity, setup SG list and DMA engine */ 145 if ((error = ch->dma.load(request, NULL, &dummy))) { 146 device_printf(request->parent, "setting up DMA failed\n"); 147 request->result = error; 148 goto begin_finished; 149 } 150 151 /* start DMA engine if necessary */ 152 if ((ch->flags & ATA_DMA_BEFORE_CMD) && 153 ch->dma.start && ch->dma.start(request)) { 154 device_printf(request->parent, "error starting DMA\n"); 155 request->result = EIO; 156 goto begin_finished; 157 } 158 159 /* issue command */ 160 if (ch->hw.command(request)) { 161 device_printf(request->parent, "error issuing %s command\n", 162 ata_cmd2str(request)); 163 request->result = EIO; 164 goto begin_finished; 165 } 166 167 /* start DMA engine */ 168 if (!(ch->flags & ATA_DMA_BEFORE_CMD) && 169 ch->dma.start && ch->dma.start(request)) { 170 device_printf(request->parent, "error starting DMA\n"); 171 request->result = EIO; 172 goto begin_finished; 173 } 174 goto begin_continue; 175 176 /* ATAPI PIO commands */ 177 case ATA_R_ATAPI: 178 /* is this just a POLL DSC command ? */ 179 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 180 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 181 DELAY(10); 182 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 183 request->result = EBUSY; 184 goto begin_finished; 185 } 186 187 /* start ATAPI operation */ 188 if (ch->hw.command(request)) { 189 device_printf(request->parent, "error issuing ATA PACKET command\n"); 190 request->result = EIO; 191 goto begin_finished; 192 } 193 goto begin_continue; 194 195 /* ATAPI DMA commands */ 196 case ATA_R_ATAPI|ATA_R_DMA: 197 /* is this just a POLL DSC command ? */ 198 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 199 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 200 DELAY(10); 201 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 202 request->result = EBUSY; 203 goto begin_finished; 204 } 205 206 /* check sanity, setup SG list and DMA engine */ 207 if ((error = ch->dma.load(request, NULL, &dummy))) { 208 device_printf(request->parent, "setting up DMA failed\n"); 209 request->result = error; 210 goto begin_finished; 211 } 212 213 /* start ATAPI operation */ 214 if (ch->hw.command(request)) { 215 device_printf(request->parent, "error issuing ATA PACKET command\n"); 216 request->result = EIO; 217 goto begin_finished; 218 } 219 220 /* start DMA engine */ 221 if (ch->dma.start && ch->dma.start(request)) { 222 request->result = EIO; 223 goto begin_finished; 224 } 225 goto begin_continue; 226 } 227 /* NOT REACHED */ 228 printf("ata_begin_transaction OOPS!!!\n"); 229 230begin_finished: 231 if (ch->dma.unload) { 232 ch->dma.unload(request); 233 } 234 return ATA_OP_FINISHED; 235 236begin_continue: 237 callout_reset(&request->callout, request->timeout * hz, 238 ata_timeout, request); 239 return ATA_OP_CONTINUES; 240} 241 242/* must be called with ATA channel locked and state_mtx held */ 243int 244ata_end_transaction(struct ata_request *request) 245{ 246 struct ata_channel *ch = device_get_softc(request->parent); 247 int length; 248 249 ATA_DEBUG_RQ(request, "end transaction"); 250 251 /* clear interrupt and get status */ 252 request->status = ATA_IDX_INB(ch, ATA_STATUS); 253 254 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 255 /* ATA PIO data transfer and control commands */ 256 default: 257 258 /* on timeouts we have no data or anything so just return */ 259 if (request->flags & ATA_R_TIMEOUT) 260 goto end_finished; 261 262 /* Read back registers to the request struct. */ 263 if ((request->status & ATA_S_ERROR) || 264 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) { 265 ch->hw.tf_read(request); 266 } 267 268 /* if we got an error we are done with the HW */ 269 if (request->status & ATA_S_ERROR) { 270 request->error = ATA_IDX_INB(ch, ATA_ERROR); 271 goto end_finished; 272 } 273 274 /* are we moving data ? */ 275 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 276 /* if read data get it */ 277 if (request->flags & ATA_R_READ) { 278 int flags = ATA_S_DRQ; 279 280 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 281 flags |= ATA_S_READY; 282 if (ata_wait(ch, request->unit, flags) < 0) { 283 device_printf(request->parent, 284 "timeout waiting for read DRQ\n"); 285 request->result = EIO; 286 goto end_finished; 287 } 288 ata_pio_read(request, request->transfersize); 289 } 290 291 /* update how far we've gotten */ 292 request->donecount += request->transfersize; 293 294 /* do we need a scoop more ? */ 295 if (request->bytecount > request->donecount) { 296 /* set this transfer size according to HW capabilities */ 297 request->transfersize = 298 min((request->bytecount - request->donecount), 299 request->transfersize); 300 301 /* if data write command, output the data */ 302 if (request->flags & ATA_R_WRITE) { 303 /* if we get an error here we are done with the HW */ 304 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 305 device_printf(request->parent, 306 "timeout waiting for write DRQ\n"); 307 request->status = ATA_IDX_INB(ch, ATA_STATUS); 308 goto end_finished; 309 } 310 311 /* output data and return waiting for new interrupt */ 312 ata_pio_write(request, request->transfersize); 313 goto end_continue; 314 } 315 316 /* if data read command, return & wait for interrupt */ 317 if (request->flags & ATA_R_READ) 318 goto end_continue; 319 } 320 } 321 /* done with HW */ 322 goto end_finished; 323 324 /* ATA DMA data transfer commands */ 325 case ATA_R_DMA: 326 327 /* stop DMA engine and get status */ 328 if (ch->dma.stop) 329 request->dma->status = ch->dma.stop(request); 330 331 /* did we get error or data */ 332 if (request->status & ATA_S_ERROR) 333 request->error = ATA_IDX_INB(ch, ATA_ERROR); 334 else if (request->dma->status & ATA_BMSTAT_ERROR) 335 request->status |= ATA_S_ERROR; 336 else if (!(request->flags & ATA_R_TIMEOUT)) 337 request->donecount = request->bytecount; 338 339 /* Read back registers to the request struct. */ 340 if ((request->status & ATA_S_ERROR) || 341 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) { 342 ch->hw.tf_read(request); 343 } 344 345 /* release SG list etc */ 346 ch->dma.unload(request); 347 348 /* done with HW */ 349 goto end_finished; 350 351 /* ATAPI PIO commands */ 352 case ATA_R_ATAPI: 353 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 354 355 /* on timeouts we have no data or anything so just return */ 356 if (request->flags & ATA_R_TIMEOUT) 357 goto end_finished; 358 359 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 360 (request->status & ATA_S_DRQ)) { 361 case ATAPI_P_CMDOUT: 362 /* this seems to be needed for some (slow) devices */ 363 DELAY(10); 364 365 if (!(request->status & ATA_S_DRQ)) { 366 device_printf(request->parent, "command interrupt without DRQ\n"); 367 request->status = ATA_S_ERROR; 368 goto end_finished; 369 } 370 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 371 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 372 /* return wait for interrupt */ 373 goto end_continue; 374 375 case ATAPI_P_WRITE: 376 if (request->flags & ATA_R_READ) { 377 request->status = ATA_S_ERROR; 378 device_printf(request->parent, 379 "%s trying to write on read buffer\n", 380 ata_cmd2str(request)); 381 goto end_finished; 382 } 383 ata_pio_write(request, length); 384 request->donecount += length; 385 386 /* set next transfer size according to HW capabilities */ 387 request->transfersize = min((request->bytecount-request->donecount), 388 request->transfersize); 389 /* return wait for interrupt */ 390 goto end_continue; 391 392 case ATAPI_P_READ: 393 if (request->flags & ATA_R_WRITE) { 394 request->status = ATA_S_ERROR; 395 device_printf(request->parent, 396 "%s trying to read on write buffer\n", 397 ata_cmd2str(request)); 398 goto end_finished; 399 } 400 ata_pio_read(request, length); 401 request->donecount += length; 402 403 /* set next transfer size according to HW capabilities */ 404 request->transfersize = min((request->bytecount-request->donecount), 405 request->transfersize); 406 /* return wait for interrupt */ 407 goto end_continue; 408 409 case ATAPI_P_DONEDRQ: 410 device_printf(request->parent, 411 "WARNING - %s DONEDRQ non conformant device\n", 412 ata_cmd2str(request)); 413 if (request->flags & ATA_R_READ) { 414 ata_pio_read(request, length); 415 request->donecount += length; 416 } 417 else if (request->flags & ATA_R_WRITE) { 418 ata_pio_write(request, length); 419 request->donecount += length; 420 } 421 else 422 request->status = ATA_S_ERROR; 423 /* FALLTHROUGH */ 424 425 case ATAPI_P_ABORT: 426 case ATAPI_P_DONE: 427 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 428 request->error = ATA_IDX_INB(ch, ATA_ERROR); 429 goto end_finished; 430 431 default: 432 device_printf(request->parent, "unknown transfer phase\n"); 433 request->status = ATA_S_ERROR; 434 } 435 436 /* done with HW */ 437 goto end_finished; 438 439 /* ATAPI DMA commands */ 440 case ATA_R_ATAPI|ATA_R_DMA: 441 442 /* stop DMA engine and get status */ 443 if (ch->dma.stop) 444 request->dma->status = ch->dma.stop(request); 445 446 /* did we get error or data */ 447 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 448 request->error = ATA_IDX_INB(ch, ATA_ERROR); 449 else if (request->dma->status & ATA_BMSTAT_ERROR) 450 request->status |= ATA_S_ERROR; 451 else if (!(request->flags & ATA_R_TIMEOUT)) 452 request->donecount = request->bytecount; 453 454 /* release SG list etc */ 455 ch->dma.unload(request); 456 457 /* done with HW */ 458 goto end_finished; 459 } 460 /* NOT REACHED */ 461 printf("ata_end_transaction OOPS!!\n"); 462 463end_finished: 464 callout_stop(&request->callout); 465 return ATA_OP_FINISHED; 466 467end_continue: 468 return ATA_OP_CONTINUES; 469} 470 471/* must be called with ATA channel locked and state_mtx held */ 472void 473ata_generic_reset(device_t dev) 474{ 475 struct ata_channel *ch = device_get_softc(dev); 476 477 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 478 u_int8_t err = 0, lsb = 0, msb = 0; 479 int mask = 0, timeout; 480 481 /* do we have any signs of ATA/ATAPI HW being present ? */ 482 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 483 DELAY(10); 484 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 485 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 486 ostat0 != 0xa5) { 487 stat0 = ATA_S_BUSY; 488 mask |= 0x01; 489 } 490 491 /* in some setups we dont want to test for a slave */ 492 if (!(ch->flags & ATA_NO_SLAVE)) { 493 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 494 DELAY(10); 495 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 496 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 497 ostat1 != 0xa5) { 498 stat1 = ATA_S_BUSY; 499 mask |= 0x02; 500 } 501 } 502 503 if (bootverbose) 504 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 505 mask, ostat0, ostat1); 506 507 /* if nothing showed up there is no need to get any further */ 508 /* XXX SOS is that too strong?, we just might lose devices here */ 509 ch->devices = 0; 510 if (!mask) 511 return; 512 513 /* reset (both) devices on this channel */ 514 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 515 DELAY(10); 516 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 517 ata_udelay(10000); 518 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 519 ata_udelay(100000); 520 ATA_IDX_INB(ch, ATA_ERROR); 521 522 /* wait for BUSY to go inactive */ 523 for (timeout = 0; timeout < 310; timeout++) { 524 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 525 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 526 DELAY(10); 527 if (ch->flags & ATA_STATUS_IS_LONG) 528 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 529 else 530 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 531 err = ATA_IDX_INB(ch, ATA_ERROR); 532 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 533 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 534 if (bootverbose) 535 device_printf(dev, 536 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 537 stat0, err, lsb, msb); 538 if (stat0 == err && lsb == err && msb == err && 539 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 540 mask &= ~0x01; 541 if (!(stat0 & ATA_S_BUSY)) { 542 if ((err & 0x7f) == ATA_E_ILI) { 543 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 544 ch->devices |= ATA_ATAPI_MASTER; 545 } 546 else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) { 547 ch->devices |= ATA_ATA_MASTER; 548 } 549 } 550 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 551 stat0 |= ATA_S_BUSY; 552 } 553 } 554 } 555 556 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 557 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 558 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 559 DELAY(10); 560 if (ch->flags & ATA_STATUS_IS_LONG) 561 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 562 else 563 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 564 err = ATA_IDX_INB(ch, ATA_ERROR); 565 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 566 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 567 if (bootverbose) 568 device_printf(dev, 569 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 570 stat1, err, lsb, msb); 571 if (stat1 == err && lsb == err && msb == err && 572 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 573 mask &= ~0x02; 574 if (!(stat1 & ATA_S_BUSY)) { 575 if ((err & 0x7f) == ATA_E_ILI) { 576 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 577 ch->devices |= ATA_ATAPI_SLAVE; 578 } 579 else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) { 580 ch->devices |= ATA_ATA_SLAVE; 581 } 582 } 583 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 584 stat1 |= ATA_S_BUSY; 585 } 586 } 587 } 588 589 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 && 590 timeout > ((mask == 0x03) ? 20 : 10)) { 591 if ((mask & 0x01) && stat0 == 0xff) 592 mask &= ~0x01; 593 if ((mask & 0x02) && stat1 == 0xff) 594 mask &= ~0x02; 595 } 596 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) && 597 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY))) 598 break; 599 ata_udelay(100000); 600 } 601 602 if (bootverbose) 603 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 604 stat0, stat1, ch->devices); 605} 606 607/* must be called with ATA channel locked and state_mtx held */ 608static int 609ata_generic_status(device_t dev) 610{ 611 struct ata_channel *ch = device_get_softc(dev); 612 613 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 614 DELAY(100); 615 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 616 return 0; 617 } 618 return 1; 619} 620 621static int 622ata_wait(struct ata_channel *ch, int unit, u_int8_t mask) 623{ 624 u_int8_t status; 625 int timeout = 0; 626 627 DELAY(1); 628 629 /* wait at max 1 second for device to get !BUSY */ 630 while (timeout < 1000000) { 631 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 632 633 /* if drive fails status, reselect the drive and try again */ 634 if (status == 0xff) { 635 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit)); 636 timeout += 1000; 637 DELAY(1000); 638 continue; 639 } 640 641 /* are we done ? */ 642 if (!(status & ATA_S_BUSY)) 643 break; 644 645 if (timeout > 1000) { 646 timeout += 1000; 647 DELAY(1000); 648 } 649 else { 650 timeout += 10; 651 DELAY(10); 652 } 653 } 654 if (timeout >= 1000000) 655 return -2; 656 if (!mask) 657 return (status & ATA_S_ERROR); 658 659 DELAY(1); 660 661 /* wait 50 msec for bits wanted */ 662 timeout = 5000; 663 while (timeout--) { 664 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 665 if ((status & mask) == mask) 666 return (status & ATA_S_ERROR); 667 DELAY(10); 668 } 669 return -3; 670} 671 672int 673ata_generic_command(struct ata_request *request) 674{ 675 struct ata_channel *ch = device_get_softc(request->parent); 676 677 /* select device */ 678 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit)); 679 680 /* ready to issue command ? */ 681 if (ata_wait(ch, request->unit, 0) < 0) { 682 device_printf(request->parent, "timeout waiting to issue command\n"); 683 request->flags |= ATA_R_TIMEOUT; 684 return (-1); 685 } 686 687 /* enable interrupt */ 688 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 689 690 if (request->flags & ATA_R_ATAPI) { 691 int timeout = 5000; 692 int res; 693 694 /* issue packet command to controller */ 695 if (request->flags & ATA_R_DMA) { 696 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 697 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 698 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 699 } 700 else { 701 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 702 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 703 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 704 } 705 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 706 707 /* command interrupt device ? just return and wait for interrupt */ 708 if (request->flags & ATA_R_ATAPI_INTR) 709 return (0); 710 711 /* command processed ? */ 712 res = ata_wait(ch, request->unit, 0); 713 if (res != 0) { 714 if (res < 0) { 715 device_printf(request->parent, 716 "timeout waiting for PACKET command\n"); 717 request->flags |= ATA_R_TIMEOUT; 718 } 719 return (-1); 720 } 721 /* wait for ready to write ATAPI command block */ 722 while (timeout--) { 723 int reason = ATA_IDX_INB(ch, ATA_IREASON); 724 int status = ATA_IDX_INB(ch, ATA_STATUS); 725 726 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 727 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 728 break; 729 DELAY(20); 730 } 731 if (timeout <= 0) { 732 device_printf(request->parent, 733 "timeout waiting for ATAPI ready\n"); 734 request->flags |= ATA_R_TIMEOUT; 735 return (-1); 736 } 737 738 /* this seems to be needed for some (slow) devices */ 739 DELAY(10); 740 741 /* output command block */ 742 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 743 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 744 } 745 else { 746 ch->hw.tf_write(request); 747 748 /* issue command to controller */ 749 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 750 } 751 return (0); 752} 753 754static void 755ata_tf_read(struct ata_request *request) 756{ 757 struct ata_channel *ch = device_get_softc(request->parent); 758 759 if (request->flags & ATA_R_48BIT) { 760 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 761 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 762 request->u.ata.lba = 763 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 764 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 765 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 766 767 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 768 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 769 request->u.ata.lba |= 770 (ATA_IDX_INB(ch, ATA_SECTOR) | 771 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 772 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 773 } 774 else { 775 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 776 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 777 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 778 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 779 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 780 } 781} 782 783static void 784ata_tf_write(struct ata_request *request) 785{ 786 struct ata_channel *ch = device_get_softc(request->parent); 787 788 if (request->flags & ATA_R_48BIT) { 789 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 790 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 791 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 792 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 793 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 794 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 795 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 796 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 797 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 798 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 799 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 800 } 801 else { 802 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 803 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 804 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 805 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 806 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 807 ATA_IDX_OUTB(ch, ATA_DRIVE, 808 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 809 ((request->u.ata.lba >> 24) & 0x0f)); 810 } 811} 812 813static void 814ata_pio_read(struct ata_request *request, int length) 815{ 816 struct ata_channel *ch = device_get_softc(request->parent); 817 struct bio *bio; 818 uint8_t *addr; 819 vm_offset_t page; 820 int todo, done, off, moff, resid, size, i; 821 uint8_t buf[2] __aligned(2); 822 823 todo = min(request->transfersize, length); 824 page = done = resid = 0; 825 while (done < todo) { 826 size = todo - done; 827 828 /* Prepare data address and limit size (if not sequential). */ 829 off = request->donecount + done; 830 if ((request->flags & ATA_R_DATA_IN_CCB) == 0 || 831 (request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 832 addr = (uint8_t *)request->data + off; 833 } else if ((request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) { 834 bio = (struct bio *)request->data; 835 if ((bio->bio_flags & BIO_UNMAPPED) == 0) { 836 addr = (uint8_t *)bio->bio_data + off; 837 } else { 838 moff = bio->bio_ma_offset + off; 839 page = pmap_quick_enter_page( 840 bio->bio_ma[moff / PAGE_SIZE]); 841 moff %= PAGE_SIZE; 842 size = min(size, PAGE_SIZE - moff); 843 addr = (void *)(page + moff); 844 } 845 } else 846 panic("ata_pio_read: Unsupported CAM data type %x\n", 847 (request->ccb->ccb_h.flags & CAM_DATA_MASK)); 848 849 /* We may have extra byte already read but not stored. */ 850 if (resid) { 851 addr[0] = buf[1]; 852 addr++; 853 done++; 854 size--; 855 } 856 857 /* Process main part of data. */ 858 resid = size % 2; 859 if (__predict_false((ch->flags & ATA_USE_16BIT) || 860 (size % 4) != 0 || ((uintptr_t)addr % 4) != 0)) { 861#ifndef __NO_STRICT_ALIGNMENT 862 if (__predict_false((uintptr_t)addr % 2)) { 863 for (i = 0; i + 1 < size; i += 2) { 864 *(uint16_t *)&buf = 865 ATA_IDX_INW_STRM(ch, ATA_DATA); 866 addr[i] = buf[0]; 867 addr[i + 1] = buf[1]; 868 } 869 } else 870#endif 871 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr, 872 size / 2); 873 874 /* If we have extra byte of data, leave it for later. */ 875 if (resid) { 876 *(uint16_t *)&buf = 877 ATA_IDX_INW_STRM(ch, ATA_DATA); 878 addr[size - 1] = buf[0]; 879 } 880 } else 881 ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / 4); 882 883 if (page) { 884 pmap_quick_remove_page(page); 885 page = 0; 886 } 887 done += size; 888 } 889 890 if (length > done) { 891 device_printf(request->parent, 892 "WARNING - %s read data overrun %d > %d\n", 893 ata_cmd2str(request), length, done); 894 for (i = done + resid; i < length; i += 2) 895 ATA_IDX_INW(ch, ATA_DATA); 896 } 897} 898 899static void 900ata_pio_write(struct ata_request *request, int length) 901{ 902 struct ata_channel *ch = device_get_softc(request->parent); 903 struct bio *bio; 904 uint8_t *addr; 905 vm_offset_t page; 906 int todo, done, off, moff, resid, size, i; 907 uint8_t buf[2] __aligned(2); 908 909 todo = min(request->transfersize, length); 910 page = done = resid = 0; 911 while (done < todo) { 912 size = todo - done; 913 914 /* Prepare data address and limit size (if not sequential). */ 915 off = request->donecount + done; 916 if ((request->flags & ATA_R_DATA_IN_CCB) == 0 || 917 (request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 918 addr = (uint8_t *)request->data + off; 919 } else if ((request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) { 920 bio = (struct bio *)request->data; 921 if ((bio->bio_flags & BIO_UNMAPPED) == 0) { 922 addr = (uint8_t *)bio->bio_data + off; 923 } else { 924 moff = bio->bio_ma_offset + off; 925 page = pmap_quick_enter_page( 926 bio->bio_ma[moff / PAGE_SIZE]); 927 moff %= PAGE_SIZE; 928 size = min(size, PAGE_SIZE - moff); 929 addr = (void *)(page + moff); 930 } 931 } else 932 panic("ata_pio_write: Unsupported CAM data type %x\n", 933 (request->ccb->ccb_h.flags & CAM_DATA_MASK)); 934 935 /* We may have extra byte to be written first. */ 936 if (resid) { 937 buf[1] = addr[0]; 938 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf); 939 addr++; 940 done++; 941 size--; 942 } 943 944 /* Process main part of data. */ 945 resid = size % 2; 946 if (__predict_false((ch->flags & ATA_USE_16BIT) || 947 (size % 4) != 0 || ((uintptr_t)addr % 4) != 0)) { 948#ifndef __NO_STRICT_ALIGNMENT 949 if (__predict_false((uintptr_t)addr % 2)) { 950 for (i = 0; i + 1 < size; i += 2) { 951 buf[0] = addr[i]; 952 buf[1] = addr[i + 1]; 953 ATA_IDX_OUTW_STRM(ch, ATA_DATA, 954 *(uint16_t *)&buf); 955 } 956 } else 957#endif 958 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr, 959 size / 2); 960 961 /* If we have extra byte of data, save it for later. */ 962 if (resid) 963 buf[0] = addr[size - 1]; 964 } else 965 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, 966 (void*)addr, size / sizeof(int32_t)); 967 968 if (page) { 969 pmap_quick_remove_page(page); 970 page = 0; 971 } 972 done += size; 973 } 974 975 /* We may have extra byte of data to be written. Pad it with zero. */ 976 if (resid) { 977 buf[1] = 0; 978 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf); 979 } 980 981 if (length > done) { 982 device_printf(request->parent, 983 "WARNING - %s write data underrun %d > %d\n", 984 ata_cmd2str(request), length, done); 985 for (i = done + resid; i < length; i += 2) 986 ATA_IDX_OUTW(ch, ATA_DATA, 0); 987 } 988} 989