1/* 2 * DO NOT EDIT - This file is automatically generated 3 * from the following source files: 4 * 5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $ 7 * 8 * $FreeBSD$ 9 */ 10typedef int (ahd_reg_print_t)(u_int, u_int *, u_int); 11typedef struct ahd_reg_parse_entry { 12 char *name; 13 uint8_t value; 14 uint8_t mask; 15} ahd_reg_parse_entry_t; 16 17#if AIC_DEBUG_REGISTERS 18ahd_reg_print_t ahd_mode_ptr_print; 19#else 20#define ahd_mode_ptr_print(regvalue, cur_col, wrap) \ 21 ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap) 22#endif 23 24#if AIC_DEBUG_REGISTERS 25ahd_reg_print_t ahd_intstat_print; 26#else 27#define ahd_intstat_print(regvalue, cur_col, wrap) \ 28 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap) 29#endif 30 31#if AIC_DEBUG_REGISTERS 32ahd_reg_print_t ahd_seqintcode_print; 33#else 34#define ahd_seqintcode_print(regvalue, cur_col, wrap) \ 35 ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap) 36#endif 37 38#if AIC_DEBUG_REGISTERS 39ahd_reg_print_t ahd_clrint_print; 40#else 41#define ahd_clrint_print(regvalue, cur_col, wrap) \ 42 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap) 43#endif 44 45#if AIC_DEBUG_REGISTERS 46ahd_reg_print_t ahd_error_print; 47#else 48#define ahd_error_print(regvalue, cur_col, wrap) \ 49 ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap) 50#endif 51 52#if AIC_DEBUG_REGISTERS 53ahd_reg_print_t ahd_clrerr_print; 54#else 55#define ahd_clrerr_print(regvalue, cur_col, wrap) \ 56 ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap) 57#endif 58 59#if AIC_DEBUG_REGISTERS 60ahd_reg_print_t ahd_hcntrl_print; 61#else 62#define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 63 ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap) 64#endif 65 66#if AIC_DEBUG_REGISTERS 67ahd_reg_print_t ahd_hnscb_qoff_print; 68#else 69#define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \ 70 ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap) 71#endif 72 73#if AIC_DEBUG_REGISTERS 74ahd_reg_print_t ahd_hescb_qoff_print; 75#else 76#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ 77 ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap) 78#endif 79 80#if AIC_DEBUG_REGISTERS 81ahd_reg_print_t ahd_hs_mailbox_print; 82#else 83#define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \ 84 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap) 85#endif 86 87#if AIC_DEBUG_REGISTERS 88ahd_reg_print_t ahd_seqintstat_print; 89#else 90#define ahd_seqintstat_print(regvalue, cur_col, wrap) \ 91 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 92#endif 93 94#if AIC_DEBUG_REGISTERS 95ahd_reg_print_t ahd_clrseqintstat_print; 96#else 97#define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \ 98 ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 99#endif 100 101#if AIC_DEBUG_REGISTERS 102ahd_reg_print_t ahd_swtimer_print; 103#else 104#define ahd_swtimer_print(regvalue, cur_col, wrap) \ 105 ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap) 106#endif 107 108#if AIC_DEBUG_REGISTERS 109ahd_reg_print_t ahd_snscb_qoff_print; 110#else 111#define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \ 112 ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap) 113#endif 114 115#if AIC_DEBUG_REGISTERS 116ahd_reg_print_t ahd_sescb_qoff_print; 117#else 118#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ 119 ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap) 120#endif 121 122#if AIC_DEBUG_REGISTERS 123ahd_reg_print_t ahd_sdscb_qoff_print; 124#else 125#define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \ 126 ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap) 127#endif 128 129#if AIC_DEBUG_REGISTERS 130ahd_reg_print_t ahd_qoff_ctlsta_print; 131#else 132#define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 133 ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap) 134#endif 135 136#if AIC_DEBUG_REGISTERS 137ahd_reg_print_t ahd_intctl_print; 138#else 139#define ahd_intctl_print(regvalue, cur_col, wrap) \ 140 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap) 141#endif 142 143#if AIC_DEBUG_REGISTERS 144ahd_reg_print_t ahd_dfcntrl_print; 145#else 146#define ahd_dfcntrl_print(regvalue, cur_col, wrap) \ 147 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap) 148#endif 149 150#if AIC_DEBUG_REGISTERS 151ahd_reg_print_t ahd_dscommand0_print; 152#else 153#define ahd_dscommand0_print(regvalue, cur_col, wrap) \ 154 ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap) 155#endif 156 157#if AIC_DEBUG_REGISTERS 158ahd_reg_print_t ahd_dfstatus_print; 159#else 160#define ahd_dfstatus_print(regvalue, cur_col, wrap) \ 161 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap) 162#endif 163 164#if AIC_DEBUG_REGISTERS 165ahd_reg_print_t ahd_sg_cache_shadow_print; 166#else 167#define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 168 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap) 169#endif 170 171#if AIC_DEBUG_REGISTERS 172ahd_reg_print_t ahd_sg_cache_pre_print; 173#else 174#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 175 ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap) 176#endif 177 178#if AIC_DEBUG_REGISTERS 179ahd_reg_print_t ahd_arbctl_print; 180#else 181#define ahd_arbctl_print(regvalue, cur_col, wrap) \ 182 ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap) 183#endif 184 185#if AIC_DEBUG_REGISTERS 186ahd_reg_print_t ahd_lqin_print; 187#else 188#define ahd_lqin_print(regvalue, cur_col, wrap) \ 189 ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap) 190#endif 191 192#if AIC_DEBUG_REGISTERS 193ahd_reg_print_t ahd_typeptr_print; 194#else 195#define ahd_typeptr_print(regvalue, cur_col, wrap) \ 196 ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap) 197#endif 198 199#if AIC_DEBUG_REGISTERS 200ahd_reg_print_t ahd_tagptr_print; 201#else 202#define ahd_tagptr_print(regvalue, cur_col, wrap) \ 203 ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap) 204#endif 205 206#if AIC_DEBUG_REGISTERS 207ahd_reg_print_t ahd_lunptr_print; 208#else 209#define ahd_lunptr_print(regvalue, cur_col, wrap) \ 210 ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap) 211#endif 212 213#if AIC_DEBUG_REGISTERS 214ahd_reg_print_t ahd_datalenptr_print; 215#else 216#define ahd_datalenptr_print(regvalue, cur_col, wrap) \ 217 ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap) 218#endif 219 220#if AIC_DEBUG_REGISTERS 221ahd_reg_print_t ahd_statlenptr_print; 222#else 223#define ahd_statlenptr_print(regvalue, cur_col, wrap) \ 224 ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap) 225#endif 226 227#if AIC_DEBUG_REGISTERS 228ahd_reg_print_t ahd_cmdlenptr_print; 229#else 230#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 231 ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap) 232#endif 233 234#if AIC_DEBUG_REGISTERS 235ahd_reg_print_t ahd_attrptr_print; 236#else 237#define ahd_attrptr_print(regvalue, cur_col, wrap) \ 238 ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap) 239#endif 240 241#if AIC_DEBUG_REGISTERS 242ahd_reg_print_t ahd_flagptr_print; 243#else 244#define ahd_flagptr_print(regvalue, cur_col, wrap) \ 245 ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap) 246#endif 247 248#if AIC_DEBUG_REGISTERS 249ahd_reg_print_t ahd_cmdptr_print; 250#else 251#define ahd_cmdptr_print(regvalue, cur_col, wrap) \ 252 ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap) 253#endif 254 255#if AIC_DEBUG_REGISTERS 256ahd_reg_print_t ahd_qnextptr_print; 257#else 258#define ahd_qnextptr_print(regvalue, cur_col, wrap) \ 259 ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap) 260#endif 261 262#if AIC_DEBUG_REGISTERS 263ahd_reg_print_t ahd_idptr_print; 264#else 265#define ahd_idptr_print(regvalue, cur_col, wrap) \ 266 ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap) 267#endif 268 269#if AIC_DEBUG_REGISTERS 270ahd_reg_print_t ahd_abrtbyteptr_print; 271#else 272#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 273 ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap) 274#endif 275 276#if AIC_DEBUG_REGISTERS 277ahd_reg_print_t ahd_abrtbitptr_print; 278#else 279#define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \ 280 ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap) 281#endif 282 283#if AIC_DEBUG_REGISTERS 284ahd_reg_print_t ahd_maxcmdbytes_print; 285#else 286#define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \ 287 ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap) 288#endif 289 290#if AIC_DEBUG_REGISTERS 291ahd_reg_print_t ahd_maxcmd2rcv_print; 292#else 293#define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \ 294 ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap) 295#endif 296 297#if AIC_DEBUG_REGISTERS 298ahd_reg_print_t ahd_shortthresh_print; 299#else 300#define ahd_shortthresh_print(regvalue, cur_col, wrap) \ 301 ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap) 302#endif 303 304#if AIC_DEBUG_REGISTERS 305ahd_reg_print_t ahd_lunlen_print; 306#else 307#define ahd_lunlen_print(regvalue, cur_col, wrap) \ 308 ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap) 309#endif 310 311#if AIC_DEBUG_REGISTERS 312ahd_reg_print_t ahd_cdblimit_print; 313#else 314#define ahd_cdblimit_print(regvalue, cur_col, wrap) \ 315 ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap) 316#endif 317 318#if AIC_DEBUG_REGISTERS 319ahd_reg_print_t ahd_maxcmd_print; 320#else 321#define ahd_maxcmd_print(regvalue, cur_col, wrap) \ 322 ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap) 323#endif 324 325#if AIC_DEBUG_REGISTERS 326ahd_reg_print_t ahd_maxcmdcnt_print; 327#else 328#define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \ 329 ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap) 330#endif 331 332#if AIC_DEBUG_REGISTERS 333ahd_reg_print_t ahd_lqrsvd01_print; 334#else 335#define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \ 336 ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap) 337#endif 338 339#if AIC_DEBUG_REGISTERS 340ahd_reg_print_t ahd_lqrsvd16_print; 341#else 342#define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \ 343 ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap) 344#endif 345 346#if AIC_DEBUG_REGISTERS 347ahd_reg_print_t ahd_lqrsvd17_print; 348#else 349#define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \ 350 ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap) 351#endif 352 353#if AIC_DEBUG_REGISTERS 354ahd_reg_print_t ahd_cmdrsvd0_print; 355#else 356#define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \ 357 ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap) 358#endif 359 360#if AIC_DEBUG_REGISTERS 361ahd_reg_print_t ahd_lqctl0_print; 362#else 363#define ahd_lqctl0_print(regvalue, cur_col, wrap) \ 364 ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap) 365#endif 366 367#if AIC_DEBUG_REGISTERS 368ahd_reg_print_t ahd_lqctl1_print; 369#else 370#define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 371 ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap) 372#endif 373 374#if AIC_DEBUG_REGISTERS 375ahd_reg_print_t ahd_lqctl2_print; 376#else 377#define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 378 ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap) 379#endif 380 381#if AIC_DEBUG_REGISTERS 382ahd_reg_print_t ahd_scsbist0_print; 383#else 384#define ahd_scsbist0_print(regvalue, cur_col, wrap) \ 385 ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap) 386#endif 387 388#if AIC_DEBUG_REGISTERS 389ahd_reg_print_t ahd_scsiseq0_print; 390#else 391#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 392 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap) 393#endif 394 395#if AIC_DEBUG_REGISTERS 396ahd_reg_print_t ahd_scsbist1_print; 397#else 398#define ahd_scsbist1_print(regvalue, cur_col, wrap) \ 399 ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap) 400#endif 401 402#if AIC_DEBUG_REGISTERS 403ahd_reg_print_t ahd_scsiseq1_print; 404#else 405#define ahd_scsiseq1_print(regvalue, cur_col, wrap) \ 406 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap) 407#endif 408 409#if AIC_DEBUG_REGISTERS 410ahd_reg_print_t ahd_businitid_print; 411#else 412#define ahd_businitid_print(regvalue, cur_col, wrap) \ 413 ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap) 414#endif 415 416#if AIC_DEBUG_REGISTERS 417ahd_reg_print_t ahd_sxfrctl0_print; 418#else 419#define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \ 420 ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap) 421#endif 422 423#if AIC_DEBUG_REGISTERS 424ahd_reg_print_t ahd_dlcount_print; 425#else 426#define ahd_dlcount_print(regvalue, cur_col, wrap) \ 427 ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap) 428#endif 429 430#if AIC_DEBUG_REGISTERS 431ahd_reg_print_t ahd_sxfrctl1_print; 432#else 433#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 434 ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap) 435#endif 436 437#if AIC_DEBUG_REGISTERS 438ahd_reg_print_t ahd_bustargid_print; 439#else 440#define ahd_bustargid_print(regvalue, cur_col, wrap) \ 441 ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap) 442#endif 443 444#if AIC_DEBUG_REGISTERS 445ahd_reg_print_t ahd_sxfrctl2_print; 446#else 447#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \ 448 ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap) 449#endif 450 451#if AIC_DEBUG_REGISTERS 452ahd_reg_print_t ahd_dffstat_print; 453#else 454#define ahd_dffstat_print(regvalue, cur_col, wrap) \ 455 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap) 456#endif 457 458#if AIC_DEBUG_REGISTERS 459ahd_reg_print_t ahd_scsisigo_print; 460#else 461#define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 462 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 463#endif 464 465#if AIC_DEBUG_REGISTERS 466ahd_reg_print_t ahd_multargid_print; 467#else 468#define ahd_multargid_print(regvalue, cur_col, wrap) \ 469 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 470#endif 471 472#if AIC_DEBUG_REGISTERS 473ahd_reg_print_t ahd_scsisigi_print; 474#else 475#define ahd_scsisigi_print(regvalue, cur_col, wrap) \ 476 ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap) 477#endif 478 479#if AIC_DEBUG_REGISTERS 480ahd_reg_print_t ahd_scsiphase_print; 481#else 482#define ahd_scsiphase_print(regvalue, cur_col, wrap) \ 483 ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap) 484#endif 485 486#if AIC_DEBUG_REGISTERS 487ahd_reg_print_t ahd_scsidat0_img_print; 488#else 489#define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \ 490 ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap) 491#endif 492 493#if AIC_DEBUG_REGISTERS 494ahd_reg_print_t ahd_scsidat_print; 495#else 496#define ahd_scsidat_print(regvalue, cur_col, wrap) \ 497 ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap) 498#endif 499 500#if AIC_DEBUG_REGISTERS 501ahd_reg_print_t ahd_scsibus_print; 502#else 503#define ahd_scsibus_print(regvalue, cur_col, wrap) \ 504 ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap) 505#endif 506 507#if AIC_DEBUG_REGISTERS 508ahd_reg_print_t ahd_targidin_print; 509#else 510#define ahd_targidin_print(regvalue, cur_col, wrap) \ 511 ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap) 512#endif 513 514#if AIC_DEBUG_REGISTERS 515ahd_reg_print_t ahd_selid_print; 516#else 517#define ahd_selid_print(regvalue, cur_col, wrap) \ 518 ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap) 519#endif 520 521#if AIC_DEBUG_REGISTERS 522ahd_reg_print_t ahd_optionmode_print; 523#else 524#define ahd_optionmode_print(regvalue, cur_col, wrap) \ 525 ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap) 526#endif 527 528#if AIC_DEBUG_REGISTERS 529ahd_reg_print_t ahd_sblkctl_print; 530#else 531#define ahd_sblkctl_print(regvalue, cur_col, wrap) \ 532 ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap) 533#endif 534 535#if AIC_DEBUG_REGISTERS 536ahd_reg_print_t ahd_simode0_print; 537#else 538#define ahd_simode0_print(regvalue, cur_col, wrap) \ 539 ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap) 540#endif 541 542#if AIC_DEBUG_REGISTERS 543ahd_reg_print_t ahd_sstat0_print; 544#else 545#define ahd_sstat0_print(regvalue, cur_col, wrap) \ 546 ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap) 547#endif 548 549#if AIC_DEBUG_REGISTERS 550ahd_reg_print_t ahd_clrsint0_print; 551#else 552#define ahd_clrsint0_print(regvalue, cur_col, wrap) \ 553 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap) 554#endif 555 556#if AIC_DEBUG_REGISTERS 557ahd_reg_print_t ahd_sstat1_print; 558#else 559#define ahd_sstat1_print(regvalue, cur_col, wrap) \ 560 ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap) 561#endif 562 563#if AIC_DEBUG_REGISTERS 564ahd_reg_print_t ahd_clrsint1_print; 565#else 566#define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 567 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 568#endif 569 570#if AIC_DEBUG_REGISTERS 571ahd_reg_print_t ahd_sstat2_print; 572#else 573#define ahd_sstat2_print(regvalue, cur_col, wrap) \ 574 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 575#endif 576 577#if AIC_DEBUG_REGISTERS 578ahd_reg_print_t ahd_clrsint2_print; 579#else 580#define ahd_clrsint2_print(regvalue, cur_col, wrap) \ 581 ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap) 582#endif 583 584#if AIC_DEBUG_REGISTERS 585ahd_reg_print_t ahd_simode2_print; 586#else 587#define ahd_simode2_print(regvalue, cur_col, wrap) \ 588 ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap) 589#endif 590 591#if AIC_DEBUG_REGISTERS 592ahd_reg_print_t ahd_perrdiag_print; 593#else 594#define ahd_perrdiag_print(regvalue, cur_col, wrap) \ 595 ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap) 596#endif 597 598#if AIC_DEBUG_REGISTERS 599ahd_reg_print_t ahd_lqistate_print; 600#else 601#define ahd_lqistate_print(regvalue, cur_col, wrap) \ 602 ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap) 603#endif 604 605#if AIC_DEBUG_REGISTERS 606ahd_reg_print_t ahd_soffcnt_print; 607#else 608#define ahd_soffcnt_print(regvalue, cur_col, wrap) \ 609 ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap) 610#endif 611 612#if AIC_DEBUG_REGISTERS 613ahd_reg_print_t ahd_lqostate_print; 614#else 615#define ahd_lqostate_print(regvalue, cur_col, wrap) \ 616 ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap) 617#endif 618 619#if AIC_DEBUG_REGISTERS 620ahd_reg_print_t ahd_lqistat0_print; 621#else 622#define ahd_lqistat0_print(regvalue, cur_col, wrap) \ 623 ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap) 624#endif 625 626#if AIC_DEBUG_REGISTERS 627ahd_reg_print_t ahd_clrlqiint0_print; 628#else 629#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 630 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 631#endif 632 633#if AIC_DEBUG_REGISTERS 634ahd_reg_print_t ahd_lqimode0_print; 635#else 636#define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 637 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 638#endif 639 640#if AIC_DEBUG_REGISTERS 641ahd_reg_print_t ahd_lqistat1_print; 642#else 643#define ahd_lqistat1_print(regvalue, cur_col, wrap) \ 644 ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap) 645#endif 646 647#if AIC_DEBUG_REGISTERS 648ahd_reg_print_t ahd_clrlqiint1_print; 649#else 650#define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \ 651 ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap) 652#endif 653 654#if AIC_DEBUG_REGISTERS 655ahd_reg_print_t ahd_lqimode1_print; 656#else 657#define ahd_lqimode1_print(regvalue, cur_col, wrap) \ 658 ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap) 659#endif 660 661#if AIC_DEBUG_REGISTERS 662ahd_reg_print_t ahd_lqistat2_print; 663#else 664#define ahd_lqistat2_print(regvalue, cur_col, wrap) \ 665 ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap) 666#endif 667 668#if AIC_DEBUG_REGISTERS 669ahd_reg_print_t ahd_sstat3_print; 670#else 671#define ahd_sstat3_print(regvalue, cur_col, wrap) \ 672 ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap) 673#endif 674 675#if AIC_DEBUG_REGISTERS 676ahd_reg_print_t ahd_clrsint3_print; 677#else 678#define ahd_clrsint3_print(regvalue, cur_col, wrap) \ 679 ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap) 680#endif 681 682#if AIC_DEBUG_REGISTERS 683ahd_reg_print_t ahd_simode3_print; 684#else 685#define ahd_simode3_print(regvalue, cur_col, wrap) \ 686 ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap) 687#endif 688 689#if AIC_DEBUG_REGISTERS 690ahd_reg_print_t ahd_lqomode0_print; 691#else 692#define ahd_lqomode0_print(regvalue, cur_col, wrap) \ 693 ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap) 694#endif 695 696#if AIC_DEBUG_REGISTERS 697ahd_reg_print_t ahd_lqostat0_print; 698#else 699#define ahd_lqostat0_print(regvalue, cur_col, wrap) \ 700 ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap) 701#endif 702 703#if AIC_DEBUG_REGISTERS 704ahd_reg_print_t ahd_clrlqoint0_print; 705#else 706#define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \ 707 ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap) 708#endif 709 710#if AIC_DEBUG_REGISTERS 711ahd_reg_print_t ahd_lqomode1_print; 712#else 713#define ahd_lqomode1_print(regvalue, cur_col, wrap) \ 714 ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap) 715#endif 716 717#if AIC_DEBUG_REGISTERS 718ahd_reg_print_t ahd_lqostat1_print; 719#else 720#define ahd_lqostat1_print(regvalue, cur_col, wrap) \ 721 ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap) 722#endif 723 724#if AIC_DEBUG_REGISTERS 725ahd_reg_print_t ahd_clrlqoint1_print; 726#else 727#define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \ 728 ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap) 729#endif 730 731#if AIC_DEBUG_REGISTERS 732ahd_reg_print_t ahd_os_space_cnt_print; 733#else 734#define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \ 735 ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap) 736#endif 737 738#if AIC_DEBUG_REGISTERS 739ahd_reg_print_t ahd_lqostat2_print; 740#else 741#define ahd_lqostat2_print(regvalue, cur_col, wrap) \ 742 ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap) 743#endif 744 745#if AIC_DEBUG_REGISTERS 746ahd_reg_print_t ahd_simode1_print; 747#else 748#define ahd_simode1_print(regvalue, cur_col, wrap) \ 749 ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap) 750#endif 751 752#if AIC_DEBUG_REGISTERS 753ahd_reg_print_t ahd_gsfifo_print; 754#else 755#define ahd_gsfifo_print(regvalue, cur_col, wrap) \ 756 ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap) 757#endif 758 759#if AIC_DEBUG_REGISTERS 760ahd_reg_print_t ahd_dffsxfrctl_print; 761#else 762#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \ 763 ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap) 764#endif 765 766#if AIC_DEBUG_REGISTERS 767ahd_reg_print_t ahd_nextscb_print; 768#else 769#define ahd_nextscb_print(regvalue, cur_col, wrap) \ 770 ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap) 771#endif 772 773#if AIC_DEBUG_REGISTERS 774ahd_reg_print_t ahd_lqoscsctl_print; 775#else 776#define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \ 777 ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap) 778#endif 779 780#if AIC_DEBUG_REGISTERS 781ahd_reg_print_t ahd_seqintsrc_print; 782#else 783#define ahd_seqintsrc_print(regvalue, cur_col, wrap) \ 784 ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap) 785#endif 786 787#if AIC_DEBUG_REGISTERS 788ahd_reg_print_t ahd_clrseqintsrc_print; 789#else 790#define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \ 791 ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap) 792#endif 793 794#if AIC_DEBUG_REGISTERS 795ahd_reg_print_t ahd_currscb_print; 796#else 797#define ahd_currscb_print(regvalue, cur_col, wrap) \ 798 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) 799#endif 800 801#if AIC_DEBUG_REGISTERS 802ahd_reg_print_t ahd_seqimode_print; 803#else 804#define ahd_seqimode_print(regvalue, cur_col, wrap) \ 805 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) 806#endif 807 808#if AIC_DEBUG_REGISTERS 809ahd_reg_print_t ahd_mdffstat_print; 810#else 811#define ahd_mdffstat_print(regvalue, cur_col, wrap) \ 812 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap) 813#endif 814 815#if AIC_DEBUG_REGISTERS 816ahd_reg_print_t ahd_crccontrol_print; 817#else 818#define ahd_crccontrol_print(regvalue, cur_col, wrap) \ 819 ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap) 820#endif 821 822#if AIC_DEBUG_REGISTERS 823ahd_reg_print_t ahd_scsitest_print; 824#else 825#define ahd_scsitest_print(regvalue, cur_col, wrap) \ 826 ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap) 827#endif 828 829#if AIC_DEBUG_REGISTERS 830ahd_reg_print_t ahd_dfftag_print; 831#else 832#define ahd_dfftag_print(regvalue, cur_col, wrap) \ 833 ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap) 834#endif 835 836#if AIC_DEBUG_REGISTERS 837ahd_reg_print_t ahd_lastscb_print; 838#else 839#define ahd_lastscb_print(regvalue, cur_col, wrap) \ 840 ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap) 841#endif 842 843#if AIC_DEBUG_REGISTERS 844ahd_reg_print_t ahd_iopdnctl_print; 845#else 846#define ahd_iopdnctl_print(regvalue, cur_col, wrap) \ 847 ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap) 848#endif 849 850#if AIC_DEBUG_REGISTERS 851ahd_reg_print_t ahd_negoaddr_print; 852#else 853#define ahd_negoaddr_print(regvalue, cur_col, wrap) \ 854 ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap) 855#endif 856 857#if AIC_DEBUG_REGISTERS 858ahd_reg_print_t ahd_shaddr_print; 859#else 860#define ahd_shaddr_print(regvalue, cur_col, wrap) \ 861 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap) 862#endif 863 864#if AIC_DEBUG_REGISTERS 865ahd_reg_print_t ahd_dgrpcrci_print; 866#else 867#define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \ 868 ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap) 869#endif 870 871#if AIC_DEBUG_REGISTERS 872ahd_reg_print_t ahd_negperiod_print; 873#else 874#define ahd_negperiod_print(regvalue, cur_col, wrap) \ 875 ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap) 876#endif 877 878#if AIC_DEBUG_REGISTERS 879ahd_reg_print_t ahd_packcrci_print; 880#else 881#define ahd_packcrci_print(regvalue, cur_col, wrap) \ 882 ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap) 883#endif 884 885#if AIC_DEBUG_REGISTERS 886ahd_reg_print_t ahd_negoffset_print; 887#else 888#define ahd_negoffset_print(regvalue, cur_col, wrap) \ 889 ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap) 890#endif 891 892#if AIC_DEBUG_REGISTERS 893ahd_reg_print_t ahd_negppropts_print; 894#else 895#define ahd_negppropts_print(regvalue, cur_col, wrap) \ 896 ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap) 897#endif 898 899#if AIC_DEBUG_REGISTERS 900ahd_reg_print_t ahd_negconopts_print; 901#else 902#define ahd_negconopts_print(regvalue, cur_col, wrap) \ 903 ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap) 904#endif 905 906#if AIC_DEBUG_REGISTERS 907ahd_reg_print_t ahd_annexcol_print; 908#else 909#define ahd_annexcol_print(regvalue, cur_col, wrap) \ 910 ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap) 911#endif 912 913#if AIC_DEBUG_REGISTERS 914ahd_reg_print_t ahd_annexdat_print; 915#else 916#define ahd_annexdat_print(regvalue, cur_col, wrap) \ 917 ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap) 918#endif 919 920#if AIC_DEBUG_REGISTERS 921ahd_reg_print_t ahd_scschkn_print; 922#else 923#define ahd_scschkn_print(regvalue, cur_col, wrap) \ 924 ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap) 925#endif 926 927#if AIC_DEBUG_REGISTERS 928ahd_reg_print_t ahd_iownid_print; 929#else 930#define ahd_iownid_print(regvalue, cur_col, wrap) \ 931 ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap) 932#endif 933 934#if AIC_DEBUG_REGISTERS 935ahd_reg_print_t ahd_shcnt_print; 936#else 937#define ahd_shcnt_print(regvalue, cur_col, wrap) \ 938 ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap) 939#endif 940 941#if AIC_DEBUG_REGISTERS 942ahd_reg_print_t ahd_pll960ctl0_print; 943#else 944#define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \ 945 ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap) 946#endif 947 948#if AIC_DEBUG_REGISTERS 949ahd_reg_print_t ahd_pll960ctl1_print; 950#else 951#define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \ 952 ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap) 953#endif 954 955#if AIC_DEBUG_REGISTERS 956ahd_reg_print_t ahd_townid_print; 957#else 958#define ahd_townid_print(regvalue, cur_col, wrap) \ 959 ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap) 960#endif 961 962#if AIC_DEBUG_REGISTERS 963ahd_reg_print_t ahd_xsig_print; 964#else 965#define ahd_xsig_print(regvalue, cur_col, wrap) \ 966 ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap) 967#endif 968 969#if AIC_DEBUG_REGISTERS 970ahd_reg_print_t ahd_pll960cnt0_print; 971#else 972#define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \ 973 ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap) 974#endif 975 976#if AIC_DEBUG_REGISTERS 977ahd_reg_print_t ahd_seloid_print; 978#else 979#define ahd_seloid_print(regvalue, cur_col, wrap) \ 980 ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap) 981#endif 982 983#if AIC_DEBUG_REGISTERS 984ahd_reg_print_t ahd_fairness_print; 985#else 986#define ahd_fairness_print(regvalue, cur_col, wrap) \ 987 ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap) 988#endif 989 990#if AIC_DEBUG_REGISTERS 991ahd_reg_print_t ahd_pll400ctl0_print; 992#else 993#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \ 994 ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap) 995#endif 996 997#if AIC_DEBUG_REGISTERS 998ahd_reg_print_t ahd_pll400ctl1_print; 999#else 1000#define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \ 1001 ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap) 1002#endif 1003 1004#if AIC_DEBUG_REGISTERS 1005ahd_reg_print_t ahd_pll400cnt0_print; 1006#else 1007#define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \ 1008 ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap) 1009#endif 1010 1011#if AIC_DEBUG_REGISTERS 1012ahd_reg_print_t ahd_unfairness_print; 1013#else 1014#define ahd_unfairness_print(regvalue, cur_col, wrap) \ 1015 ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap) 1016#endif 1017 1018#if AIC_DEBUG_REGISTERS 1019ahd_reg_print_t ahd_hodmaadr_print; 1020#else 1021#define ahd_hodmaadr_print(regvalue, cur_col, wrap) \ 1022 ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap) 1023#endif 1024 1025#if AIC_DEBUG_REGISTERS 1026ahd_reg_print_t ahd_haddr_print; 1027#else 1028#define ahd_haddr_print(regvalue, cur_col, wrap) \ 1029 ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap) 1030#endif 1031 1032#if AIC_DEBUG_REGISTERS 1033ahd_reg_print_t ahd_plldelay_print; 1034#else 1035#define ahd_plldelay_print(regvalue, cur_col, wrap) \ 1036 ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap) 1037#endif 1038 1039#if AIC_DEBUG_REGISTERS 1040ahd_reg_print_t ahd_hcnt_print; 1041#else 1042#define ahd_hcnt_print(regvalue, cur_col, wrap) \ 1043 ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap) 1044#endif 1045 1046#if AIC_DEBUG_REGISTERS 1047ahd_reg_print_t ahd_hodmacnt_print; 1048#else 1049#define ahd_hodmacnt_print(regvalue, cur_col, wrap) \ 1050 ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap) 1051#endif 1052 1053#if AIC_DEBUG_REGISTERS 1054ahd_reg_print_t ahd_hodmaen_print; 1055#else 1056#define ahd_hodmaen_print(regvalue, cur_col, wrap) \ 1057 ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap) 1058#endif 1059 1060#if AIC_DEBUG_REGISTERS 1061ahd_reg_print_t ahd_scbhaddr_print; 1062#else 1063#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ 1064 ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap) 1065#endif 1066 1067#if AIC_DEBUG_REGISTERS 1068ahd_reg_print_t ahd_sghaddr_print; 1069#else 1070#define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 1071 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 1072#endif 1073 1074#if AIC_DEBUG_REGISTERS 1075ahd_reg_print_t ahd_scbhcnt_print; 1076#else 1077#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \ 1078 ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap) 1079#endif 1080 1081#if AIC_DEBUG_REGISTERS 1082ahd_reg_print_t ahd_sghcnt_print; 1083#else 1084#define ahd_sghcnt_print(regvalue, cur_col, wrap) \ 1085 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) 1086#endif 1087 1088#if AIC_DEBUG_REGISTERS 1089ahd_reg_print_t ahd_dff_thrsh_print; 1090#else 1091#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 1092 ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) 1093#endif 1094 1095#if AIC_DEBUG_REGISTERS 1096ahd_reg_print_t ahd_romaddr_print; 1097#else 1098#define ahd_romaddr_print(regvalue, cur_col, wrap) \ 1099 ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap) 1100#endif 1101 1102#if AIC_DEBUG_REGISTERS 1103ahd_reg_print_t ahd_romcntrl_print; 1104#else 1105#define ahd_romcntrl_print(regvalue, cur_col, wrap) \ 1106 ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap) 1107#endif 1108 1109#if AIC_DEBUG_REGISTERS 1110ahd_reg_print_t ahd_romdata_print; 1111#else 1112#define ahd_romdata_print(regvalue, cur_col, wrap) \ 1113 ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap) 1114#endif 1115 1116#if AIC_DEBUG_REGISTERS 1117ahd_reg_print_t ahd_dchrxmsg0_print; 1118#else 1119#define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \ 1120 ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap) 1121#endif 1122 1123#if AIC_DEBUG_REGISTERS 1124ahd_reg_print_t ahd_ovlyrxmsg0_print; 1125#else 1126#define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \ 1127 ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap) 1128#endif 1129 1130#if AIC_DEBUG_REGISTERS 1131ahd_reg_print_t ahd_cmcrxmsg0_print; 1132#else 1133#define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \ 1134 ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap) 1135#endif 1136 1137#if AIC_DEBUG_REGISTERS 1138ahd_reg_print_t ahd_roenable_print; 1139#else 1140#define ahd_roenable_print(regvalue, cur_col, wrap) \ 1141 ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap) 1142#endif 1143 1144#if AIC_DEBUG_REGISTERS 1145ahd_reg_print_t ahd_dchrxmsg1_print; 1146#else 1147#define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \ 1148 ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap) 1149#endif 1150 1151#if AIC_DEBUG_REGISTERS 1152ahd_reg_print_t ahd_ovlyrxmsg1_print; 1153#else 1154#define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \ 1155 ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap) 1156#endif 1157 1158#if AIC_DEBUG_REGISTERS 1159ahd_reg_print_t ahd_cmcrxmsg1_print; 1160#else 1161#define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \ 1162 ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap) 1163#endif 1164 1165#if AIC_DEBUG_REGISTERS 1166ahd_reg_print_t ahd_nsenable_print; 1167#else 1168#define ahd_nsenable_print(regvalue, cur_col, wrap) \ 1169 ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap) 1170#endif 1171 1172#if AIC_DEBUG_REGISTERS 1173ahd_reg_print_t ahd_dchrxmsg2_print; 1174#else 1175#define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \ 1176 ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap) 1177#endif 1178 1179#if AIC_DEBUG_REGISTERS 1180ahd_reg_print_t ahd_ovlyrxmsg2_print; 1181#else 1182#define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \ 1183 ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap) 1184#endif 1185 1186#if AIC_DEBUG_REGISTERS 1187ahd_reg_print_t ahd_cmcrxmsg2_print; 1188#else 1189#define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \ 1190 ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap) 1191#endif 1192 1193#if AIC_DEBUG_REGISTERS 1194ahd_reg_print_t ahd_ost_print; 1195#else 1196#define ahd_ost_print(regvalue, cur_col, wrap) \ 1197 ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap) 1198#endif 1199 1200#if AIC_DEBUG_REGISTERS 1201ahd_reg_print_t ahd_dchrxmsg3_print; 1202#else 1203#define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \ 1204 ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap) 1205#endif 1206 1207#if AIC_DEBUG_REGISTERS 1208ahd_reg_print_t ahd_ovlyrxmsg3_print; 1209#else 1210#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \ 1211 ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap) 1212#endif 1213 1214#if AIC_DEBUG_REGISTERS 1215ahd_reg_print_t ahd_cmcrxmsg3_print; 1216#else 1217#define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \ 1218 ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap) 1219#endif 1220 1221#if AIC_DEBUG_REGISTERS 1222ahd_reg_print_t ahd_pcixctl_print; 1223#else 1224#define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 1225 ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap) 1226#endif 1227 1228#if AIC_DEBUG_REGISTERS 1229ahd_reg_print_t ahd_cmcseqbcnt_print; 1230#else 1231#define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \ 1232 ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap) 1233#endif 1234 1235#if AIC_DEBUG_REGISTERS 1236ahd_reg_print_t ahd_dchseqbcnt_print; 1237#else 1238#define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \ 1239 ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap) 1240#endif 1241 1242#if AIC_DEBUG_REGISTERS 1243ahd_reg_print_t ahd_ovlyseqbcnt_print; 1244#else 1245#define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \ 1246 ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap) 1247#endif 1248 1249#if AIC_DEBUG_REGISTERS 1250ahd_reg_print_t ahd_cmcspltstat0_print; 1251#else 1252#define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \ 1253 ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1254#endif 1255 1256#if AIC_DEBUG_REGISTERS 1257ahd_reg_print_t ahd_dchspltstat0_print; 1258#else 1259#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 1260 ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1261#endif 1262 1263#if AIC_DEBUG_REGISTERS 1264ahd_reg_print_t ahd_ovlyspltstat0_print; 1265#else 1266#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \ 1267 ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1268#endif 1269 1270#if AIC_DEBUG_REGISTERS 1271ahd_reg_print_t ahd_cmcspltstat1_print; 1272#else 1273#define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \ 1274 ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1275#endif 1276 1277#if AIC_DEBUG_REGISTERS 1278ahd_reg_print_t ahd_dchspltstat1_print; 1279#else 1280#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 1281 ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1282#endif 1283 1284#if AIC_DEBUG_REGISTERS 1285ahd_reg_print_t ahd_ovlyspltstat1_print; 1286#else 1287#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \ 1288 ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1289#endif 1290 1291#if AIC_DEBUG_REGISTERS 1292ahd_reg_print_t ahd_sgrxmsg0_print; 1293#else 1294#define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \ 1295 ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap) 1296#endif 1297 1298#if AIC_DEBUG_REGISTERS 1299ahd_reg_print_t ahd_slvspltoutadr0_print; 1300#else 1301#define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \ 1302 ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap) 1303#endif 1304 1305#if AIC_DEBUG_REGISTERS 1306ahd_reg_print_t ahd_sgrxmsg1_print; 1307#else 1308#define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \ 1309 ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap) 1310#endif 1311 1312#if AIC_DEBUG_REGISTERS 1313ahd_reg_print_t ahd_slvspltoutadr1_print; 1314#else 1315#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \ 1316 ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap) 1317#endif 1318 1319#if AIC_DEBUG_REGISTERS 1320ahd_reg_print_t ahd_sgrxmsg2_print; 1321#else 1322#define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \ 1323 ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap) 1324#endif 1325 1326#if AIC_DEBUG_REGISTERS 1327ahd_reg_print_t ahd_slvspltoutadr2_print; 1328#else 1329#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \ 1330 ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap) 1331#endif 1332 1333#if AIC_DEBUG_REGISTERS 1334ahd_reg_print_t ahd_sgrxmsg3_print; 1335#else 1336#define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \ 1337 ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap) 1338#endif 1339 1340#if AIC_DEBUG_REGISTERS 1341ahd_reg_print_t ahd_slvspltoutadr3_print; 1342#else 1343#define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \ 1344 ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap) 1345#endif 1346 1347#if AIC_DEBUG_REGISTERS 1348ahd_reg_print_t ahd_slvspltoutattr0_print; 1349#else 1350#define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \ 1351 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap) 1352#endif 1353 1354#if AIC_DEBUG_REGISTERS 1355ahd_reg_print_t ahd_sgseqbcnt_print; 1356#else 1357#define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \ 1358 ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap) 1359#endif 1360 1361#if AIC_DEBUG_REGISTERS 1362ahd_reg_print_t ahd_slvspltoutattr1_print; 1363#else 1364#define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \ 1365 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap) 1366#endif 1367 1368#if AIC_DEBUG_REGISTERS 1369ahd_reg_print_t ahd_slvspltoutattr2_print; 1370#else 1371#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \ 1372 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap) 1373#endif 1374 1375#if AIC_DEBUG_REGISTERS 1376ahd_reg_print_t ahd_sgspltstat0_print; 1377#else 1378#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 1379 ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap) 1380#endif 1381 1382#if AIC_DEBUG_REGISTERS 1383ahd_reg_print_t ahd_sfunct_print; 1384#else 1385#define ahd_sfunct_print(regvalue, cur_col, wrap) \ 1386 ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) 1387#endif 1388 1389#if AIC_DEBUG_REGISTERS 1390ahd_reg_print_t ahd_sgspltstat1_print; 1391#else 1392#define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \ 1393 ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap) 1394#endif 1395 1396#if AIC_DEBUG_REGISTERS 1397ahd_reg_print_t ahd_df0pcistat_print; 1398#else 1399#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 1400 ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap) 1401#endif 1402 1403#if AIC_DEBUG_REGISTERS 1404ahd_reg_print_t ahd_reg0_print; 1405#else 1406#define ahd_reg0_print(regvalue, cur_col, wrap) \ 1407 ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap) 1408#endif 1409 1410#if AIC_DEBUG_REGISTERS 1411ahd_reg_print_t ahd_df1pcistat_print; 1412#else 1413#define ahd_df1pcistat_print(regvalue, cur_col, wrap) \ 1414 ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap) 1415#endif 1416 1417#if AIC_DEBUG_REGISTERS 1418ahd_reg_print_t ahd_sgpcistat_print; 1419#else 1420#define ahd_sgpcistat_print(regvalue, cur_col, wrap) \ 1421 ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap) 1422#endif 1423 1424#if AIC_DEBUG_REGISTERS 1425ahd_reg_print_t ahd_reg1_print; 1426#else 1427#define ahd_reg1_print(regvalue, cur_col, wrap) \ 1428 ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap) 1429#endif 1430 1431#if AIC_DEBUG_REGISTERS 1432ahd_reg_print_t ahd_cmcpcistat_print; 1433#else 1434#define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \ 1435 ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap) 1436#endif 1437 1438#if AIC_DEBUG_REGISTERS 1439ahd_reg_print_t ahd_ovlypcistat_print; 1440#else 1441#define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \ 1442 ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap) 1443#endif 1444 1445#if AIC_DEBUG_REGISTERS 1446ahd_reg_print_t ahd_reg_isr_print; 1447#else 1448#define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 1449 ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap) 1450#endif 1451 1452#if AIC_DEBUG_REGISTERS 1453ahd_reg_print_t ahd_msipcistat_print; 1454#else 1455#define ahd_msipcistat_print(regvalue, cur_col, wrap) \ 1456 ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap) 1457#endif 1458 1459#if AIC_DEBUG_REGISTERS 1460ahd_reg_print_t ahd_sg_state_print; 1461#else 1462#define ahd_sg_state_print(regvalue, cur_col, wrap) \ 1463 ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap) 1464#endif 1465 1466#if AIC_DEBUG_REGISTERS 1467ahd_reg_print_t ahd_targpcistat_print; 1468#else 1469#define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 1470 ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap) 1471#endif 1472 1473#if AIC_DEBUG_REGISTERS 1474ahd_reg_print_t ahd_data_count_odd_print; 1475#else 1476#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \ 1477 ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap) 1478#endif 1479 1480#if AIC_DEBUG_REGISTERS 1481ahd_reg_print_t ahd_scbptr_print; 1482#else 1483#define ahd_scbptr_print(regvalue, cur_col, wrap) \ 1484 ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap) 1485#endif 1486 1487#if AIC_DEBUG_REGISTERS 1488ahd_reg_print_t ahd_ccscbacnt_print; 1489#else 1490#define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \ 1491 ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap) 1492#endif 1493 1494#if AIC_DEBUG_REGISTERS 1495ahd_reg_print_t ahd_scbautoptr_print; 1496#else 1497#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 1498 ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap) 1499#endif 1500 1501#if AIC_DEBUG_REGISTERS 1502ahd_reg_print_t ahd_ccscbadr_bk_print; 1503#else 1504#define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \ 1505 ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap) 1506#endif 1507 1508#if AIC_DEBUG_REGISTERS 1509ahd_reg_print_t ahd_ccsgaddr_print; 1510#else 1511#define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \ 1512 ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap) 1513#endif 1514 1515#if AIC_DEBUG_REGISTERS 1516ahd_reg_print_t ahd_ccscbaddr_print; 1517#else 1518#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 1519 ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap) 1520#endif 1521 1522#if AIC_DEBUG_REGISTERS 1523ahd_reg_print_t ahd_ccscbctl_print; 1524#else 1525#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 1526 ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap) 1527#endif 1528 1529#if AIC_DEBUG_REGISTERS 1530ahd_reg_print_t ahd_ccsgctl_print; 1531#else 1532#define ahd_ccsgctl_print(regvalue, cur_col, wrap) \ 1533 ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap) 1534#endif 1535 1536#if AIC_DEBUG_REGISTERS 1537ahd_reg_print_t ahd_cmc_rambist_print; 1538#else 1539#define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \ 1540 ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap) 1541#endif 1542 1543#if AIC_DEBUG_REGISTERS 1544ahd_reg_print_t ahd_ccsgram_print; 1545#else 1546#define ahd_ccsgram_print(regvalue, cur_col, wrap) \ 1547 ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap) 1548#endif 1549 1550#if AIC_DEBUG_REGISTERS 1551ahd_reg_print_t ahd_ccscbram_print; 1552#else 1553#define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 1554 ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap) 1555#endif 1556 1557#if AIC_DEBUG_REGISTERS 1558ahd_reg_print_t ahd_flexadr_print; 1559#else 1560#define ahd_flexadr_print(regvalue, cur_col, wrap) \ 1561 ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap) 1562#endif 1563 1564#if AIC_DEBUG_REGISTERS 1565ahd_reg_print_t ahd_flexcnt_print; 1566#else 1567#define ahd_flexcnt_print(regvalue, cur_col, wrap) \ 1568 ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap) 1569#endif 1570 1571#if AIC_DEBUG_REGISTERS 1572ahd_reg_print_t ahd_flexdmastat_print; 1573#else 1574#define ahd_flexdmastat_print(regvalue, cur_col, wrap) \ 1575 ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap) 1576#endif 1577 1578#if AIC_DEBUG_REGISTERS 1579ahd_reg_print_t ahd_flexdata_print; 1580#else 1581#define ahd_flexdata_print(regvalue, cur_col, wrap) \ 1582 ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap) 1583#endif 1584 1585#if AIC_DEBUG_REGISTERS 1586ahd_reg_print_t ahd_brddat_print; 1587#else 1588#define ahd_brddat_print(regvalue, cur_col, wrap) \ 1589 ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap) 1590#endif 1591 1592#if AIC_DEBUG_REGISTERS 1593ahd_reg_print_t ahd_brdctl_print; 1594#else 1595#define ahd_brdctl_print(regvalue, cur_col, wrap) \ 1596 ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap) 1597#endif 1598 1599#if AIC_DEBUG_REGISTERS 1600ahd_reg_print_t ahd_seeadr_print; 1601#else 1602#define ahd_seeadr_print(regvalue, cur_col, wrap) \ 1603 ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap) 1604#endif 1605 1606#if AIC_DEBUG_REGISTERS 1607ahd_reg_print_t ahd_seedat_print; 1608#else 1609#define ahd_seedat_print(regvalue, cur_col, wrap) \ 1610 ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap) 1611#endif 1612 1613#if AIC_DEBUG_REGISTERS 1614ahd_reg_print_t ahd_seectl_print; 1615#else 1616#define ahd_seectl_print(regvalue, cur_col, wrap) \ 1617 ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap) 1618#endif 1619 1620#if AIC_DEBUG_REGISTERS 1621ahd_reg_print_t ahd_seestat_print; 1622#else 1623#define ahd_seestat_print(regvalue, cur_col, wrap) \ 1624 ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap) 1625#endif 1626 1627#if AIC_DEBUG_REGISTERS 1628ahd_reg_print_t ahd_scbcnt_print; 1629#else 1630#define ahd_scbcnt_print(regvalue, cur_col, wrap) \ 1631 ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap) 1632#endif 1633 1634#if AIC_DEBUG_REGISTERS 1635ahd_reg_print_t ahd_dspfltrctl_print; 1636#else 1637#define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \ 1638 ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap) 1639#endif 1640 1641#if AIC_DEBUG_REGISTERS 1642ahd_reg_print_t ahd_dfwaddr_print; 1643#else 1644#define ahd_dfwaddr_print(regvalue, cur_col, wrap) \ 1645 ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap) 1646#endif 1647 1648#if AIC_DEBUG_REGISTERS 1649ahd_reg_print_t ahd_dspdatactl_print; 1650#else 1651#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 1652 ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap) 1653#endif 1654 1655#if AIC_DEBUG_REGISTERS 1656ahd_reg_print_t ahd_dspreqctl_print; 1657#else 1658#define ahd_dspreqctl_print(regvalue, cur_col, wrap) \ 1659 ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap) 1660#endif 1661 1662#if AIC_DEBUG_REGISTERS 1663ahd_reg_print_t ahd_dfraddr_print; 1664#else 1665#define ahd_dfraddr_print(regvalue, cur_col, wrap) \ 1666 ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap) 1667#endif 1668 1669#if AIC_DEBUG_REGISTERS 1670ahd_reg_print_t ahd_dspackctl_print; 1671#else 1672#define ahd_dspackctl_print(regvalue, cur_col, wrap) \ 1673 ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap) 1674#endif 1675 1676#if AIC_DEBUG_REGISTERS 1677ahd_reg_print_t ahd_dfdat_print; 1678#else 1679#define ahd_dfdat_print(regvalue, cur_col, wrap) \ 1680 ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap) 1681#endif 1682 1683#if AIC_DEBUG_REGISTERS 1684ahd_reg_print_t ahd_dspselect_print; 1685#else 1686#define ahd_dspselect_print(regvalue, cur_col, wrap) \ 1687 ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap) 1688#endif 1689 1690#if AIC_DEBUG_REGISTERS 1691ahd_reg_print_t ahd_wrtbiasctl_print; 1692#else 1693#define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \ 1694 ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap) 1695#endif 1696 1697#if AIC_DEBUG_REGISTERS 1698ahd_reg_print_t ahd_rcvrbiosctl_print; 1699#else 1700#define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \ 1701 ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap) 1702#endif 1703 1704#if AIC_DEBUG_REGISTERS 1705ahd_reg_print_t ahd_wrtbiascalc_print; 1706#else 1707#define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \ 1708 ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap) 1709#endif 1710 1711#if AIC_DEBUG_REGISTERS 1712ahd_reg_print_t ahd_dfptrs_print; 1713#else 1714#define ahd_dfptrs_print(regvalue, cur_col, wrap) \ 1715 ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap) 1716#endif 1717 1718#if AIC_DEBUG_REGISTERS 1719ahd_reg_print_t ahd_rcvrbiascalc_print; 1720#else 1721#define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \ 1722 ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap) 1723#endif 1724 1725#if AIC_DEBUG_REGISTERS 1726ahd_reg_print_t ahd_dfbkptr_print; 1727#else 1728#define ahd_dfbkptr_print(regvalue, cur_col, wrap) \ 1729 ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap) 1730#endif 1731 1732#if AIC_DEBUG_REGISTERS 1733ahd_reg_print_t ahd_skewcalc_print; 1734#else 1735#define ahd_skewcalc_print(regvalue, cur_col, wrap) \ 1736 ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap) 1737#endif 1738 1739#if AIC_DEBUG_REGISTERS 1740ahd_reg_print_t ahd_dfdbctl_print; 1741#else 1742#define ahd_dfdbctl_print(regvalue, cur_col, wrap) \ 1743 ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap) 1744#endif 1745 1746#if AIC_DEBUG_REGISTERS 1747ahd_reg_print_t ahd_dfscnt_print; 1748#else 1749#define ahd_dfscnt_print(regvalue, cur_col, wrap) \ 1750 ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap) 1751#endif 1752 1753#if AIC_DEBUG_REGISTERS 1754ahd_reg_print_t ahd_dfbcnt_print; 1755#else 1756#define ahd_dfbcnt_print(regvalue, cur_col, wrap) \ 1757 ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap) 1758#endif 1759 1760#if AIC_DEBUG_REGISTERS 1761ahd_reg_print_t ahd_ovlyaddr_print; 1762#else 1763#define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \ 1764 ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap) 1765#endif 1766 1767#if AIC_DEBUG_REGISTERS 1768ahd_reg_print_t ahd_seqctl0_print; 1769#else 1770#define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 1771 ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap) 1772#endif 1773 1774#if AIC_DEBUG_REGISTERS 1775ahd_reg_print_t ahd_seqctl1_print; 1776#else 1777#define ahd_seqctl1_print(regvalue, cur_col, wrap) \ 1778 ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap) 1779#endif 1780 1781#if AIC_DEBUG_REGISTERS 1782ahd_reg_print_t ahd_flags_print; 1783#else 1784#define ahd_flags_print(regvalue, cur_col, wrap) \ 1785 ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap) 1786#endif 1787 1788#if AIC_DEBUG_REGISTERS 1789ahd_reg_print_t ahd_seqintctl_print; 1790#else 1791#define ahd_seqintctl_print(regvalue, cur_col, wrap) \ 1792 ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap) 1793#endif 1794 1795#if AIC_DEBUG_REGISTERS 1796ahd_reg_print_t ahd_seqram_print; 1797#else 1798#define ahd_seqram_print(regvalue, cur_col, wrap) \ 1799 ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap) 1800#endif 1801 1802#if AIC_DEBUG_REGISTERS 1803ahd_reg_print_t ahd_prgmcnt_print; 1804#else 1805#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ 1806 ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap) 1807#endif 1808 1809#if AIC_DEBUG_REGISTERS 1810ahd_reg_print_t ahd_accum_print; 1811#else 1812#define ahd_accum_print(regvalue, cur_col, wrap) \ 1813 ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap) 1814#endif 1815 1816#if AIC_DEBUG_REGISTERS 1817ahd_reg_print_t ahd_sindex_print; 1818#else 1819#define ahd_sindex_print(regvalue, cur_col, wrap) \ 1820 ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap) 1821#endif 1822 1823#if AIC_DEBUG_REGISTERS 1824ahd_reg_print_t ahd_dindex_print; 1825#else 1826#define ahd_dindex_print(regvalue, cur_col, wrap) \ 1827 ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap) 1828#endif 1829 1830#if AIC_DEBUG_REGISTERS 1831ahd_reg_print_t ahd_brkaddr1_print; 1832#else 1833#define ahd_brkaddr1_print(regvalue, cur_col, wrap) \ 1834 ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap) 1835#endif 1836 1837#if AIC_DEBUG_REGISTERS 1838ahd_reg_print_t ahd_brkaddr0_print; 1839#else 1840#define ahd_brkaddr0_print(regvalue, cur_col, wrap) \ 1841 ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap) 1842#endif 1843 1844#if AIC_DEBUG_REGISTERS 1845ahd_reg_print_t ahd_allones_print; 1846#else 1847#define ahd_allones_print(regvalue, cur_col, wrap) \ 1848 ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap) 1849#endif 1850 1851#if AIC_DEBUG_REGISTERS 1852ahd_reg_print_t ahd_none_print; 1853#else 1854#define ahd_none_print(regvalue, cur_col, wrap) \ 1855 ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap) 1856#endif 1857 1858#if AIC_DEBUG_REGISTERS 1859ahd_reg_print_t ahd_allzeros_print; 1860#else 1861#define ahd_allzeros_print(regvalue, cur_col, wrap) \ 1862 ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap) 1863#endif 1864 1865#if AIC_DEBUG_REGISTERS 1866ahd_reg_print_t ahd_sindir_print; 1867#else 1868#define ahd_sindir_print(regvalue, cur_col, wrap) \ 1869 ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap) 1870#endif 1871 1872#if AIC_DEBUG_REGISTERS 1873ahd_reg_print_t ahd_dindir_print; 1874#else 1875#define ahd_dindir_print(regvalue, cur_col, wrap) \ 1876 ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap) 1877#endif 1878 1879#if AIC_DEBUG_REGISTERS 1880ahd_reg_print_t ahd_function1_print; 1881#else 1882#define ahd_function1_print(regvalue, cur_col, wrap) \ 1883 ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap) 1884#endif 1885 1886#if AIC_DEBUG_REGISTERS 1887ahd_reg_print_t ahd_stack_print; 1888#else 1889#define ahd_stack_print(regvalue, cur_col, wrap) \ 1890 ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap) 1891#endif 1892 1893#if AIC_DEBUG_REGISTERS 1894ahd_reg_print_t ahd_intvec1_addr_print; 1895#else 1896#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ 1897 ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap) 1898#endif 1899 1900#if AIC_DEBUG_REGISTERS 1901ahd_reg_print_t ahd_curaddr_print; 1902#else 1903#define ahd_curaddr_print(regvalue, cur_col, wrap) \ 1904 ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap) 1905#endif 1906 1907#if AIC_DEBUG_REGISTERS 1908ahd_reg_print_t ahd_intvec2_addr_print; 1909#else 1910#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1911 ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap) 1912#endif 1913 1914#if AIC_DEBUG_REGISTERS 1915ahd_reg_print_t ahd_lastaddr_print; 1916#else 1917#define ahd_lastaddr_print(regvalue, cur_col, wrap) \ 1918 ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap) 1919#endif 1920 1921#if AIC_DEBUG_REGISTERS 1922ahd_reg_print_t ahd_longjmp_addr_print; 1923#else 1924#define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \ 1925 ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap) 1926#endif 1927 1928#if AIC_DEBUG_REGISTERS 1929ahd_reg_print_t ahd_accum_save_print; 1930#else 1931#define ahd_accum_save_print(regvalue, cur_col, wrap) \ 1932 ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap) 1933#endif 1934 1935#if AIC_DEBUG_REGISTERS 1936ahd_reg_print_t ahd_sram_base_print; 1937#else 1938#define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1939 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1940#endif 1941 1942#if AIC_DEBUG_REGISTERS 1943ahd_reg_print_t ahd_waiting_scb_tails_print; 1944#else 1945#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ 1946 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) 1947#endif 1948 1949#if AIC_DEBUG_REGISTERS 1950ahd_reg_print_t ahd_ahd_pci_config_base_print; 1951#else 1952#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \ 1953 ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap) 1954#endif 1955 1956#if AIC_DEBUG_REGISTERS 1957ahd_reg_print_t ahd_waiting_tid_head_print; 1958#else 1959#define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \ 1960 ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap) 1961#endif 1962 1963#if AIC_DEBUG_REGISTERS 1964ahd_reg_print_t ahd_waiting_tid_tail_print; 1965#else 1966#define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \ 1967 ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap) 1968#endif 1969 1970#if AIC_DEBUG_REGISTERS 1971ahd_reg_print_t ahd_next_queued_scb_addr_print; 1972#else 1973#define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \ 1974 ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap) 1975#endif 1976 1977#if AIC_DEBUG_REGISTERS 1978ahd_reg_print_t ahd_complete_scb_head_print; 1979#else 1980#define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \ 1981 ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap) 1982#endif 1983 1984#if AIC_DEBUG_REGISTERS 1985ahd_reg_print_t ahd_complete_scb_dmainprog_head_print; 1986#else 1987#define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \ 1988 ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap) 1989#endif 1990 1991#if AIC_DEBUG_REGISTERS 1992ahd_reg_print_t ahd_complete_dma_scb_head_print; 1993#else 1994#define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \ 1995 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap) 1996#endif 1997 1998#if AIC_DEBUG_REGISTERS 1999ahd_reg_print_t ahd_complete_dma_scb_tail_print; 2000#else 2001#define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \ 2002 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap) 2003#endif 2004 2005#if AIC_DEBUG_REGISTERS 2006ahd_reg_print_t ahd_complete_on_qfreeze_head_print; 2007#else 2008#define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \ 2009 ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap) 2010#endif 2011 2012#if AIC_DEBUG_REGISTERS 2013ahd_reg_print_t ahd_qfreeze_count_print; 2014#else 2015#define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \ 2016 ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap) 2017#endif 2018 2019#if AIC_DEBUG_REGISTERS 2020ahd_reg_print_t ahd_kernel_qfreeze_count_print; 2021#else 2022#define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \ 2023 ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap) 2024#endif 2025 2026#if AIC_DEBUG_REGISTERS 2027ahd_reg_print_t ahd_saved_mode_print; 2028#else 2029#define ahd_saved_mode_print(regvalue, cur_col, wrap) \ 2030 ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap) 2031#endif 2032 2033#if AIC_DEBUG_REGISTERS 2034ahd_reg_print_t ahd_msg_out_print; 2035#else 2036#define ahd_msg_out_print(regvalue, cur_col, wrap) \ 2037 ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap) 2038#endif 2039 2040#if AIC_DEBUG_REGISTERS 2041ahd_reg_print_t ahd_dmaparams_print; 2042#else 2043#define ahd_dmaparams_print(regvalue, cur_col, wrap) \ 2044 ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap) 2045#endif 2046 2047#if AIC_DEBUG_REGISTERS 2048ahd_reg_print_t ahd_seq_flags_print; 2049#else 2050#define ahd_seq_flags_print(regvalue, cur_col, wrap) \ 2051 ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap) 2052#endif 2053 2054#if AIC_DEBUG_REGISTERS 2055ahd_reg_print_t ahd_saved_scsiid_print; 2056#else 2057#define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \ 2058 ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap) 2059#endif 2060 2061#if AIC_DEBUG_REGISTERS 2062ahd_reg_print_t ahd_saved_lun_print; 2063#else 2064#define ahd_saved_lun_print(regvalue, cur_col, wrap) \ 2065 ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap) 2066#endif 2067 2068#if AIC_DEBUG_REGISTERS 2069ahd_reg_print_t ahd_lastphase_print; 2070#else 2071#define ahd_lastphase_print(regvalue, cur_col, wrap) \ 2072 ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap) 2073#endif 2074 2075#if AIC_DEBUG_REGISTERS 2076ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print; 2077#else 2078#define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \ 2079 ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap) 2080#endif 2081 2082#if AIC_DEBUG_REGISTERS 2083ahd_reg_print_t ahd_kernel_tqinpos_print; 2084#else 2085#define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 2086 ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap) 2087#endif 2088 2089#if AIC_DEBUG_REGISTERS 2090ahd_reg_print_t ahd_tqinpos_print; 2091#else 2092#define ahd_tqinpos_print(regvalue, cur_col, wrap) \ 2093 ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap) 2094#endif 2095 2096#if AIC_DEBUG_REGISTERS 2097ahd_reg_print_t ahd_shared_data_addr_print; 2098#else 2099#define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \ 2100 ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap) 2101#endif 2102 2103#if AIC_DEBUG_REGISTERS 2104ahd_reg_print_t ahd_qoutfifo_next_addr_print; 2105#else 2106#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ 2107 ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap) 2108#endif 2109 2110#if AIC_DEBUG_REGISTERS 2111ahd_reg_print_t ahd_arg_1_print; 2112#else 2113#define ahd_arg_1_print(regvalue, cur_col, wrap) \ 2114 ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap) 2115#endif 2116 2117#if AIC_DEBUG_REGISTERS 2118ahd_reg_print_t ahd_arg_2_print; 2119#else 2120#define ahd_arg_2_print(regvalue, cur_col, wrap) \ 2121 ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap) 2122#endif 2123 2124#if AIC_DEBUG_REGISTERS 2125ahd_reg_print_t ahd_last_msg_print; 2126#else 2127#define ahd_last_msg_print(regvalue, cur_col, wrap) \ 2128 ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap) 2129#endif 2130 2131#if AIC_DEBUG_REGISTERS 2132ahd_reg_print_t ahd_scsiseq_template_print; 2133#else 2134#define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \ 2135 ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap) 2136#endif 2137 2138#if AIC_DEBUG_REGISTERS 2139ahd_reg_print_t ahd_initiator_tag_print; 2140#else 2141#define ahd_initiator_tag_print(regvalue, cur_col, wrap) \ 2142 ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap) 2143#endif 2144 2145#if AIC_DEBUG_REGISTERS 2146ahd_reg_print_t ahd_seq_flags2_print; 2147#else 2148#define ahd_seq_flags2_print(regvalue, cur_col, wrap) \ 2149 ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap) 2150#endif 2151 2152#if AIC_DEBUG_REGISTERS 2153ahd_reg_print_t ahd_allocfifo_scbptr_print; 2154#else 2155#define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \ 2156 ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap) 2157#endif 2158 2159#if AIC_DEBUG_REGISTERS 2160ahd_reg_print_t ahd_int_coalescing_timer_print; 2161#else 2162#define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \ 2163 ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap) 2164#endif 2165 2166#if AIC_DEBUG_REGISTERS 2167ahd_reg_print_t ahd_int_coalescing_maxcmds_print; 2168#else 2169#define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \ 2170 ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap) 2171#endif 2172 2173#if AIC_DEBUG_REGISTERS 2174ahd_reg_print_t ahd_int_coalescing_mincmds_print; 2175#else 2176#define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \ 2177 ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap) 2178#endif 2179 2180#if AIC_DEBUG_REGISTERS 2181ahd_reg_print_t ahd_cmds_pending_print; 2182#else 2183#define ahd_cmds_pending_print(regvalue, cur_col, wrap) \ 2184 ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap) 2185#endif 2186 2187#if AIC_DEBUG_REGISTERS 2188ahd_reg_print_t ahd_int_coalescing_cmdcount_print; 2189#else 2190#define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \ 2191 ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap) 2192#endif 2193 2194#if AIC_DEBUG_REGISTERS 2195ahd_reg_print_t ahd_local_hs_mailbox_print; 2196#else 2197#define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \ 2198 ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap) 2199#endif 2200 2201#if AIC_DEBUG_REGISTERS 2202ahd_reg_print_t ahd_cmdsize_table_print; 2203#else 2204#define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \ 2205 ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap) 2206#endif 2207 2208#if AIC_DEBUG_REGISTERS 2209ahd_reg_print_t ahd_mk_message_scb_print; 2210#else 2211#define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \ 2212 ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap) 2213#endif 2214 2215#if AIC_DEBUG_REGISTERS 2216ahd_reg_print_t ahd_mk_message_scsiid_print; 2217#else 2218#define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \ 2219 ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap) 2220#endif 2221 2222#if AIC_DEBUG_REGISTERS 2223ahd_reg_print_t ahd_scb_base_print; 2224#else 2225#define ahd_scb_base_print(regvalue, cur_col, wrap) \ 2226 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 2227#endif 2228 2229#if AIC_DEBUG_REGISTERS 2230ahd_reg_print_t ahd_scb_residual_datacnt_print; 2231#else 2232#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 2233 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 2234#endif 2235 2236#if AIC_DEBUG_REGISTERS 2237ahd_reg_print_t ahd_scb_residual_sgptr_print; 2238#else 2239#define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 2240 ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap) 2241#endif 2242 2243#if AIC_DEBUG_REGISTERS 2244ahd_reg_print_t ahd_scb_scsi_status_print; 2245#else 2246#define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ 2247 ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) 2248#endif 2249 2250#if AIC_DEBUG_REGISTERS 2251ahd_reg_print_t ahd_scb_target_phases_print; 2252#else 2253#define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \ 2254 ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap) 2255#endif 2256 2257#if AIC_DEBUG_REGISTERS 2258ahd_reg_print_t ahd_scb_target_data_dir_print; 2259#else 2260#define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \ 2261 ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap) 2262#endif 2263 2264#if AIC_DEBUG_REGISTERS 2265ahd_reg_print_t ahd_scb_target_itag_print; 2266#else 2267#define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \ 2268 ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap) 2269#endif 2270 2271#if AIC_DEBUG_REGISTERS 2272ahd_reg_print_t ahd_scb_sense_busaddr_print; 2273#else 2274#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 2275 ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap) 2276#endif 2277 2278#if AIC_DEBUG_REGISTERS 2279ahd_reg_print_t ahd_scb_tag_print; 2280#else 2281#define ahd_scb_tag_print(regvalue, cur_col, wrap) \ 2282 ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap) 2283#endif 2284 2285#if AIC_DEBUG_REGISTERS 2286ahd_reg_print_t ahd_scb_control_print; 2287#else 2288#define ahd_scb_control_print(regvalue, cur_col, wrap) \ 2289 ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap) 2290#endif 2291 2292#if AIC_DEBUG_REGISTERS 2293ahd_reg_print_t ahd_scb_scsiid_print; 2294#else 2295#define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \ 2296 ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap) 2297#endif 2298 2299#if AIC_DEBUG_REGISTERS 2300ahd_reg_print_t ahd_scb_lun_print; 2301#else 2302#define ahd_scb_lun_print(regvalue, cur_col, wrap) \ 2303 ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap) 2304#endif 2305 2306#if AIC_DEBUG_REGISTERS 2307ahd_reg_print_t ahd_scb_task_attribute_print; 2308#else 2309#define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \ 2310 ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap) 2311#endif 2312 2313#if AIC_DEBUG_REGISTERS 2314ahd_reg_print_t ahd_scb_cdb_len_print; 2315#else 2316#define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \ 2317 ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap) 2318#endif 2319 2320#if AIC_DEBUG_REGISTERS 2321ahd_reg_print_t ahd_scb_task_management_print; 2322#else 2323#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ 2324 ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap) 2325#endif 2326 2327#if AIC_DEBUG_REGISTERS 2328ahd_reg_print_t ahd_scb_dataptr_print; 2329#else 2330#define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \ 2331 ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap) 2332#endif 2333 2334#if AIC_DEBUG_REGISTERS 2335ahd_reg_print_t ahd_scb_datacnt_print; 2336#else 2337#define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \ 2338 ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap) 2339#endif 2340 2341#if AIC_DEBUG_REGISTERS 2342ahd_reg_print_t ahd_scb_sgptr_print; 2343#else 2344#define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \ 2345 ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap) 2346#endif 2347 2348#if AIC_DEBUG_REGISTERS 2349ahd_reg_print_t ahd_scb_busaddr_print; 2350#else 2351#define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \ 2352 ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap) 2353#endif 2354 2355#if AIC_DEBUG_REGISTERS 2356ahd_reg_print_t ahd_scb_next_print; 2357#else 2358#define ahd_scb_next_print(regvalue, cur_col, wrap) \ 2359 ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap) 2360#endif 2361 2362#if AIC_DEBUG_REGISTERS 2363ahd_reg_print_t ahd_scb_next2_print; 2364#else 2365#define ahd_scb_next2_print(regvalue, cur_col, wrap) \ 2366 ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap) 2367#endif 2368 2369#if AIC_DEBUG_REGISTERS 2370ahd_reg_print_t ahd_scb_spare_print; 2371#else 2372#define ahd_scb_spare_print(regvalue, cur_col, wrap) \ 2373 ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap) 2374#endif 2375 2376#if AIC_DEBUG_REGISTERS 2377ahd_reg_print_t ahd_scb_disconnected_lists_print; 2378#else 2379#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 2380 ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap) 2381#endif 2382 2383#define MODE_PTR 0x00 2384#define DST_MODE 0x70 2385#define SRC_MODE 0x07 2386 2387#define INTSTAT 0x01 2388#define INT_PEND 0xff 2389#define HWERRINT 0x80 2390#define BRKADRINT 0x40 2391#define SWTMINT 0x20 2392#define PCIINT 0x10 2393#define SCSIINT 0x08 2394#define SEQINT 0x04 2395#define CMDCMPLT 0x02 2396#define SPLTINT 0x01 2397 2398#define SEQINTCODE 0x02 2399#define BAD_SCB_STATUS 0x1a 2400#define SAW_HWERR 0x19 2401#define TRACEPOINT3 0x18 2402#define TRACEPOINT2 0x17 2403#define TRACEPOINT1 0x16 2404#define TRACEPOINT0 0x15 2405#define TASKMGMT_CMD_CMPLT_OKAY 0x14 2406#define TASKMGMT_FUNC_COMPLETE 0x13 2407#define ENTERING_NONPACK 0x12 2408#define CFG4OVERRUN 0x11 2409#define STATUS_OVERRUN 0x10 2410#define CFG4ISTAT_INTR 0x0f 2411#define INVALID_SEQINT 0x0e 2412#define ILLEGAL_PHASE 0x0d 2413#define DUMP_CARD_STATE 0x0c 2414#define MISSED_BUSFREE 0x0b 2415#define MKMSG_FAILED 0x0a 2416#define DATA_OVERRUN 0x09 2417#define BAD_STATUS 0x08 2418#define HOST_MSG_LOOP 0x07 2419#define PDATA_REINIT 0x06 2420#define IGN_WIDE_RES 0x05 2421#define NO_MATCH 0x04 2422#define PROTO_VIOLATION 0x03 2423#define SEND_REJECT 0x02 2424#define BAD_PHASE 0x01 2425#define NO_SEQINT 0x00 2426 2427#define CLRINT 0x03 2428#define CLRHWERRINT 0x80 2429#define CLRBRKADRINT 0x40 2430#define CLRSWTMINT 0x20 2431#define CLRPCIINT 0x10 2432#define CLRSCSIINT 0x08 2433#define CLRSEQINT 0x04 2434#define CLRCMDINT 0x02 2435#define CLRSPLTINT 0x01 2436 2437#define ERROR 0x04 2438#define CIOPARERR 0x80 2439#define CIOACCESFAIL 0x40 2440#define MPARERR 0x20 2441#define DPARERR 0x10 2442#define SQPARERR 0x08 2443#define ILLOPCODE 0x04 2444#define DSCTMOUT 0x02 2445 2446#define CLRERR 0x04 2447#define CLRCIOPARERR 0x80 2448#define CLRCIOACCESFAIL 0x40 2449#define CLRMPARERR 0x20 2450#define CLRDPARERR 0x10 2451#define CLRSQPARERR 0x08 2452#define CLRILLOPCODE 0x04 2453#define CLRDSCTMOUT 0x02 2454 2455#define HCNTRL 0x05 2456#define SEQ_RESET 0x80 2457#define POWRDN 0x40 2458#define SWINT 0x10 2459#define SWTIMER_START_B 0x08 2460#define PAUSE 0x04 2461#define INTEN 0x02 2462#define CHIPRST 0x01 2463#define CHIPRSTACK 0x01 2464 2465#define HNSCB_QOFF 0x06 2466 2467#define HESCB_QOFF 0x08 2468 2469#define HS_MAILBOX 0x0b 2470#define HOST_TQINPOS 0x80 2471#define ENINT_COALESCE 0x40 2472 2473#define SEQINTSTAT 0x0c 2474#define SEQ_SWTMRTO 0x10 2475#define SEQ_SEQINT 0x08 2476#define SEQ_SCSIINT 0x04 2477#define SEQ_PCIINT 0x02 2478#define SEQ_SPLTINT 0x01 2479 2480#define CLRSEQINTSTAT 0x0c 2481#define CLRSEQ_SWTMRTO 0x10 2482#define CLRSEQ_SEQINT 0x08 2483#define CLRSEQ_SCSIINT 0x04 2484#define CLRSEQ_PCIINT 0x02 2485#define CLRSEQ_SPLTINT 0x01 2486 2487#define SWTIMER 0x0e 2488 2489#define SNSCB_QOFF 0x10 2490 2491#define SESCB_QOFF 0x12 2492 2493#define SDSCB_QOFF 0x14 2494 2495#define QOFF_CTLSTA 0x16 2496#define EMPTY_SCB_AVAIL 0x80 2497#define NEW_SCB_AVAIL 0x40 2498#define SDSCB_ROLLOVR 0x20 2499#define HS_MAILBOX_ACT 0x10 2500#define SCB_QSIZE 0x0f 2501#define SCB_QSIZE_16384 0x0c 2502#define SCB_QSIZE_8192 0x0b 2503#define SCB_QSIZE_4096 0x0a 2504#define SCB_QSIZE_2048 0x09 2505#define SCB_QSIZE_1024 0x08 2506#define SCB_QSIZE_512 0x07 2507#define SCB_QSIZE_256 0x06 2508#define SCB_QSIZE_128 0x05 2509#define SCB_QSIZE_64 0x04 2510#define SCB_QSIZE_32 0x03 2511#define SCB_QSIZE_16 0x02 2512#define SCB_QSIZE_8 0x01 2513#define SCB_QSIZE_4 0x00 2514 2515#define INTCTL 0x18 2516#define SWTMINTMASK 0x80 2517#define SWTMINTEN 0x40 2518#define SWTIMER_START 0x20 2519#define AUTOCLRCMDINT 0x10 2520#define PCIINTEN 0x08 2521#define SCSIINTEN 0x04 2522#define SEQINTEN 0x02 2523#define SPLTINTEN 0x01 2524 2525#define DFCNTRL 0x19 2526#define SCSIENWRDIS 0x40 2527#define SCSIENACK 0x20 2528#define DIRECTIONACK 0x04 2529#define FIFOFLUSHACK 0x02 2530#define DIRECTIONEN 0x01 2531 2532#define DSCOMMAND0 0x19 2533#define CACHETHEN 0x80 2534#define DPARCKEN 0x40 2535#define MPARCKEN 0x20 2536#define EXTREQLCK 0x10 2537#define DISABLE_TWATE 0x02 2538#define CIOPARCKEN 0x01 2539 2540#define DFSTATUS 0x1a 2541#define PRELOAD_AVAIL 0x80 2542#define PKT_PRELOAD_AVAIL 0x40 2543#define MREQPEND 0x10 2544#define HDONE 0x08 2545#define DFTHRESH 0x04 2546#define FIFOFULL 0x02 2547#define FIFOEMP 0x01 2548 2549#define SG_CACHE_SHADOW 0x1b 2550#define ODD_SEG 0x04 2551#define LAST_SEG 0x02 2552#define LAST_SEG_DONE 0x01 2553 2554#define SG_CACHE_PRE 0x1b 2555 2556#define ARBCTL 0x1b 2557#define RESET_HARB 0x80 2558#define RETRY_SWEN 0x08 2559#define USE_TIME 0x07 2560 2561#define LQIN 0x20 2562 2563#define TYPEPTR 0x20 2564 2565#define TAGPTR 0x21 2566 2567#define LUNPTR 0x22 2568 2569#define DATALENPTR 0x23 2570 2571#define STATLENPTR 0x24 2572 2573#define CMDLENPTR 0x25 2574 2575#define ATTRPTR 0x26 2576 2577#define FLAGPTR 0x27 2578 2579#define CMDPTR 0x28 2580 2581#define QNEXTPTR 0x29 2582 2583#define IDPTR 0x2a 2584 2585#define ABRTBYTEPTR 0x2b 2586 2587#define ABRTBITPTR 0x2c 2588 2589#define MAXCMDBYTES 0x2d 2590 2591#define MAXCMD2RCV 0x2e 2592 2593#define SHORTTHRESH 0x2f 2594 2595#define LUNLEN 0x30 2596#define TLUNLEN 0xf0 2597#define ILUNLEN 0x0f 2598 2599#define CDBLIMIT 0x31 2600 2601#define MAXCMD 0x32 2602 2603#define MAXCMDCNT 0x33 2604 2605#define LQRSVD01 0x34 2606 2607#define LQRSVD16 0x35 2608 2609#define LQRSVD17 0x36 2610 2611#define CMDRSVD0 0x37 2612 2613#define LQCTL0 0x38 2614#define LQITARGCLT 0xc0 2615#define LQIINITGCLT 0x30 2616#define LQ0TARGCLT 0x0c 2617#define LQ0INITGCLT 0x03 2618 2619#define LQCTL1 0x38 2620#define PCI2PCI 0x04 2621#define SINGLECMD 0x02 2622#define ABORTPENDING 0x01 2623 2624#define LQCTL2 0x39 2625#define LQIRETRY 0x80 2626#define LQICONTINUE 0x40 2627#define LQITOIDLE 0x20 2628#define LQIPAUSE 0x10 2629#define LQORETRY 0x08 2630#define LQOCONTINUE 0x04 2631#define LQOTOIDLE 0x02 2632#define LQOPAUSE 0x01 2633 2634#define SCSBIST0 0x39 2635#define GSBISTERR 0x40 2636#define GSBISTDONE 0x20 2637#define GSBISTRUN 0x10 2638#define OSBISTERR 0x04 2639#define OSBISTDONE 0x02 2640#define OSBISTRUN 0x01 2641 2642#define SCSISEQ0 0x3a 2643#define TEMODEO 0x80 2644#define ENSELO 0x40 2645#define ENARBO 0x20 2646#define FORCEBUSFREE 0x10 2647#define SCSIRSTO 0x01 2648 2649#define SCSBIST1 0x3a 2650#define NTBISTERR 0x04 2651#define NTBISTDONE 0x02 2652#define NTBISTRUN 0x01 2653 2654#define SCSISEQ1 0x3b 2655 2656#define BUSINITID 0x3c 2657 2658#define SXFRCTL0 0x3c 2659#define DFON 0x80 2660#define DFPEXP 0x40 2661#define BIOSCANCELEN 0x10 2662#define SPIOEN 0x08 2663 2664#define DLCOUNT 0x3c 2665 2666#define SXFRCTL1 0x3d 2667#define BITBUCKET 0x80 2668#define ENSACHK 0x40 2669#define ENSPCHK 0x20 2670#define STIMESEL 0x18 2671#define ENSTIMER 0x04 2672#define ACTNEGEN 0x02 2673#define STPWEN 0x01 2674 2675#define BUSTARGID 0x3e 2676 2677#define SXFRCTL2 0x3e 2678#define AUTORSTDIS 0x10 2679#define CMDDMAEN 0x08 2680#define ASU 0x07 2681 2682#define DFFSTAT 0x3f 2683#define CURRFIFO 0x03 2684#define FIFO1FREE 0x20 2685#define FIFO0FREE 0x10 2686#define CURRFIFO_NONE 0x03 2687#define CURRFIFO_1 0x01 2688#define CURRFIFO_0 0x00 2689 2690#define SCSISIGO 0x40 2691#define CDO 0x80 2692#define IOO 0x40 2693#define MSGO 0x20 2694#define ATNO 0x10 2695#define SELO 0x08 2696#define BSYO 0x04 2697#define REQO 0x02 2698#define ACKO 0x01 2699 2700#define MULTARGID 0x40 2701 2702#define SCSISIGI 0x41 2703#define ATNI 0x10 2704#define SELI 0x08 2705#define BSYI 0x04 2706#define REQI 0x02 2707#define ACKI 0x01 2708 2709#define SCSIPHASE 0x42 2710#define STATUS_PHASE 0x20 2711#define COMMAND_PHASE 0x10 2712#define MSG_IN_PHASE 0x08 2713#define MSG_OUT_PHASE 0x04 2714#define DATA_PHASE_MASK 0x03 2715#define DATA_IN_PHASE 0x02 2716#define DATA_OUT_PHASE 0x01 2717 2718#define SCSIDAT0_IMG 0x43 2719 2720#define SCSIDAT 0x44 2721 2722#define SCSIBUS 0x46 2723 2724#define TARGIDIN 0x48 2725#define CLKOUT 0x80 2726#define TARGID 0x0f 2727 2728#define SELID 0x49 2729#define SELID_MASK 0xf0 2730#define ONEBIT 0x08 2731 2732#define OPTIONMODE 0x4a 2733#define OPTIONMODE_DEFAULTS 0x02 2734#define BIOSCANCTL 0x80 2735#define AUTOACKEN 0x40 2736#define BIASCANCTL 0x20 2737#define BUSFREEREV 0x10 2738#define ENDGFORMCHK 0x04 2739#define AUTO_MSGOUT_DE 0x02 2740 2741#define SBLKCTL 0x4a 2742#define DIAGLEDEN 0x80 2743#define DIAGLEDON 0x40 2744#define ENAB40 0x08 2745#define ENAB20 0x04 2746#define SELWIDE 0x02 2747 2748#define SIMODE0 0x4b 2749#define ENSELDO 0x40 2750#define ENSELDI 0x20 2751#define ENSELINGO 0x10 2752#define ENIOERR 0x08 2753#define ENOVERRUN 0x04 2754#define ENSPIORDY 0x02 2755#define ENARBDO 0x01 2756 2757#define SSTAT0 0x4b 2758#define TARGET 0x80 2759#define SELDO 0x40 2760#define SELDI 0x20 2761#define SELINGO 0x10 2762#define IOERR 0x08 2763#define OVERRUN 0x04 2764#define SPIORDY 0x02 2765#define ARBDO 0x01 2766 2767#define CLRSINT0 0x4b 2768#define CLRSELDO 0x40 2769#define CLRSELDI 0x20 2770#define CLRSELINGO 0x10 2771#define CLRIOERR 0x08 2772#define CLROVERRUN 0x04 2773#define CLRSPIORDY 0x02 2774#define CLRARBDO 0x01 2775 2776#define SSTAT1 0x4c 2777#define SELTO 0x80 2778#define ATNTARG 0x40 2779#define SCSIRSTI 0x20 2780#define PHASEMIS 0x10 2781#define BUSFREE 0x08 2782#define SCSIPERR 0x04 2783#define STRB2FAST 0x02 2784#define REQINIT 0x01 2785 2786#define CLRSINT1 0x4c 2787#define CLRSELTIMEO 0x80 2788#define CLRATNO 0x40 2789#define CLRSCSIRSTI 0x20 2790#define CLRBUSFREE 0x08 2791#define CLRSCSIPERR 0x04 2792#define CLRSTRB2FAST 0x02 2793#define CLRREQINIT 0x01 2794 2795#define SSTAT2 0x4d 2796#define BUSFREETIME 0xc0 2797#define NONPACKREQ 0x20 2798#define EXP_ACTIVE 0x10 2799#define BSYX 0x08 2800#define WIDE_RES 0x04 2801#define SDONE 0x02 2802#define DMADONE 0x01 2803#define BUSFREE_DFF1 0xc0 2804#define BUSFREE_DFF0 0x80 2805#define BUSFREE_LQO 0x40 2806 2807#define CLRSINT2 0x4d 2808#define CLRNONPACKREQ 0x20 2809#define CLRWIDE_RES 0x04 2810#define CLRSDONE 0x02 2811#define CLRDMADONE 0x01 2812 2813#define SIMODE2 0x4d 2814#define ENWIDE_RES 0x04 2815#define ENSDONE 0x02 2816#define ENDMADONE 0x01 2817 2818#define PERRDIAG 0x4e 2819#define HIZERO 0x80 2820#define HIPERR 0x40 2821#define PREVPHASE 0x20 2822#define PARITYERR 0x10 2823#define AIPERR 0x08 2824#define CRCERR 0x04 2825#define DGFORMERR 0x02 2826#define DTERR 0x01 2827 2828#define LQISTATE 0x4e 2829 2830#define SOFFCNT 0x4f 2831 2832#define LQOSTATE 0x4f 2833 2834#define LQISTAT0 0x50 2835#define LQIATNQAS 0x20 2836#define LQICRCT1 0x10 2837#define LQICRCT2 0x08 2838#define LQIBADLQT 0x04 2839#define LQIATNLQ 0x02 2840#define LQIATNCMD 0x01 2841 2842#define CLRLQIINT0 0x50 2843#define CLRLQIATNQAS 0x20 2844#define CLRLQICRCT1 0x10 2845#define CLRLQICRCT2 0x08 2846#define CLRLQIBADLQT 0x04 2847#define CLRLQIATNLQ 0x02 2848#define CLRLQIATNCMD 0x01 2849 2850#define LQIMODE0 0x50 2851#define ENLQIATNQASK 0x20 2852#define ENLQICRCT1 0x10 2853#define ENLQICRCT2 0x08 2854#define ENLQIBADLQT 0x04 2855#define ENLQIATNLQ 0x02 2856#define ENLQIATNCMD 0x01 2857 2858#define LQISTAT1 0x51 2859#define LQIPHASE_LQ 0x80 2860#define LQIPHASE_NLQ 0x40 2861#define LQIABORT 0x20 2862#define LQICRCI_LQ 0x10 2863#define LQICRCI_NLQ 0x08 2864#define LQIBADLQI 0x04 2865#define LQIOVERI_LQ 0x02 2866#define LQIOVERI_NLQ 0x01 2867 2868#define CLRLQIINT1 0x51 2869#define CLRLQIPHASE_LQ 0x80 2870#define CLRLQIPHASE_NLQ 0x40 2871#define CLRLIQABORT 0x20 2872#define CLRLQICRCI_LQ 0x10 2873#define CLRLQICRCI_NLQ 0x08 2874#define CLRLQIBADLQI 0x04 2875#define CLRLQIOVERI_LQ 0x02 2876#define CLRLQIOVERI_NLQ 0x01 2877 2878#define LQIMODE1 0x51 2879#define ENLQIPHASE_LQ 0x80 2880#define ENLQIPHASE_NLQ 0x40 2881#define ENLIQABORT 0x20 2882#define ENLQICRCI_LQ 0x10 2883#define ENLQICRCI_NLQ 0x08 2884#define ENLQIBADLQI 0x04 2885#define ENLQIOVERI_LQ 0x02 2886#define ENLQIOVERI_NLQ 0x01 2887 2888#define LQISTAT2 0x52 2889#define PACKETIZED 0x80 2890#define LQIPHASE_OUTPKT 0x40 2891#define LQIWORKONLQ 0x20 2892#define LQIWAITFIFO 0x10 2893#define LQISTOPPKT 0x08 2894#define LQISTOPLQ 0x04 2895#define LQISTOPCMD 0x02 2896#define LQIGSAVAIL 0x01 2897 2898#define SSTAT3 0x53 2899#define NTRAMPERR 0x02 2900#define OSRAMPERR 0x01 2901 2902#define CLRSINT3 0x53 2903#define CLRNTRAMPERR 0x02 2904#define CLROSRAMPERR 0x01 2905 2906#define SIMODE3 0x53 2907#define ENNTRAMPERR 0x02 2908#define ENOSRAMPERR 0x01 2909 2910#define LQOMODE0 0x54 2911#define ENLQOTARGSCBPERR 0x10 2912#define ENLQOSTOPT2 0x08 2913#define ENLQOATNLQ 0x04 2914#define ENLQOATNPKT 0x02 2915#define ENLQOTCRC 0x01 2916 2917#define LQOSTAT0 0x54 2918#define LQOTARGSCBPERR 0x10 2919#define LQOSTOPT2 0x08 2920#define LQOATNLQ 0x04 2921#define LQOATNPKT 0x02 2922#define LQOTCRC 0x01 2923 2924#define CLRLQOINT0 0x54 2925#define CLRLQOTARGSCBPERR 0x10 2926#define CLRLQOSTOPT2 0x08 2927#define CLRLQOATNLQ 0x04 2928#define CLRLQOATNPKT 0x02 2929#define CLRLQOTCRC 0x01 2930 2931#define LQOMODE1 0x55 2932#define ENLQOINITSCBPERR 0x10 2933#define ENLQOSTOPI2 0x08 2934#define ENLQOBADQAS 0x04 2935#define ENLQOBUSFREE 0x02 2936#define ENLQOPHACHGINPKT 0x01 2937 2938#define LQOSTAT1 0x55 2939#define LQOINITSCBPERR 0x10 2940#define LQOSTOPI2 0x08 2941#define LQOBADQAS 0x04 2942#define LQOBUSFREE 0x02 2943#define LQOPHACHGINPKT 0x01 2944 2945#define CLRLQOINT1 0x55 2946#define CLRLQOINITSCBPERR 0x10 2947#define CLRLQOSTOPI2 0x08 2948#define CLRLQOBADQAS 0x04 2949#define CLRLQOBUSFREE 0x02 2950#define CLRLQOPHACHGINPKT 0x01 2951 2952#define OS_SPACE_CNT 0x56 2953 2954#define LQOSTAT2 0x56 2955#define LQOPKT 0xe0 2956#define LQOWAITFIFO 0x10 2957#define LQOPHACHGOUTPKT 0x02 2958#define LQOSTOP0 0x01 2959 2960#define SIMODE1 0x57 2961#define ENSELTIMO 0x80 2962#define ENATNTARG 0x40 2963#define ENSCSIRST 0x20 2964#define ENPHASEMIS 0x10 2965#define ENBUSFREE 0x08 2966#define ENSCSIPERR 0x04 2967#define ENSTRB2FAST 0x02 2968#define ENREQINIT 0x01 2969 2970#define GSFIFO 0x58 2971 2972#define DFFSXFRCTL 0x5a 2973#define DFFBITBUCKET 0x08 2974#define CLRSHCNT 0x04 2975#define CLRCHN 0x02 2976#define RSTCHN 0x01 2977 2978#define NEXTSCB 0x5a 2979 2980#define LQOSCSCTL 0x5a 2981#define LQOH2A_VERSION 0x80 2982#define LQONOCHKOVER 0x01 2983 2984#define SEQINTSRC 0x5b 2985#define CTXTDONE 0x40 2986#define SAVEPTRS 0x20 2987#define CFG4DATA 0x10 2988#define CFG4ISTAT 0x08 2989#define CFG4TSTAT 0x04 2990#define CFG4ICMD 0x02 2991#define CFG4TCMD 0x01 2992 2993#define CLRSEQINTSRC 0x5b 2994#define CLRCTXTDONE 0x40 2995#define CLRSAVEPTRS 0x20 2996#define CLRCFG4DATA 0x10 2997#define CLRCFG4ISTAT 0x08 2998#define CLRCFG4TSTAT 0x04 2999#define CLRCFG4ICMD 0x02 3000#define CLRCFG4TCMD 0x01 3001 3002#define CURRSCB 0x5c 3003 3004#define SEQIMODE 0x5c 3005#define ENCTXTDONE 0x40 3006#define ENSAVEPTRS 0x20 3007#define ENCFG4DATA 0x10 3008#define ENCFG4ISTAT 0x08 3009#define ENCFG4TSTAT 0x04 3010#define ENCFG4ICMD 0x02 3011#define ENCFG4TCMD 0x01 3012 3013#define MDFFSTAT 0x5d 3014#define SHCNTNEGATIVE 0x40 3015#define SHCNTMINUS1 0x20 3016#define LASTSDONE 0x10 3017#define SHVALID 0x08 3018#define DLZERO 0x04 3019#define DATAINFIFO 0x02 3020#define FIFOFREE 0x01 3021 3022#define CRCCONTROL 0x5d 3023#define CRCVALCHKEN 0x40 3024 3025#define SCSITEST 0x5e 3026#define CNTRTEST 0x08 3027#define SEL_TXPLL_DEBUG 0x04 3028 3029#define DFFTAG 0x5e 3030 3031#define LASTSCB 0x5e 3032 3033#define IOPDNCTL 0x5f 3034#define DISABLE_OE 0x80 3035#define PDN_IDIST 0x04 3036#define PDN_DIFFSENSE 0x01 3037 3038#define NEGOADDR 0x60 3039 3040#define SHADDR 0x60 3041 3042#define DGRPCRCI 0x60 3043 3044#define NEGPERIOD 0x61 3045 3046#define PACKCRCI 0x62 3047 3048#define NEGOFFSET 0x62 3049 3050#define NEGPPROPTS 0x63 3051#define PPROPT_PACE 0x08 3052#define PPROPT_QAS 0x04 3053#define PPROPT_DT 0x02 3054#define PPROPT_IUT 0x01 3055 3056#define NEGCONOPTS 0x64 3057#define ENSNAPSHOT 0x40 3058#define RTI_WRTDIS 0x20 3059#define RTI_OVRDTRN 0x10 3060#define ENSLOWCRC 0x08 3061#define ENAUTOATNI 0x04 3062#define ENAUTOATNO 0x02 3063#define WIDEXFER 0x01 3064 3065#define ANNEXCOL 0x65 3066 3067#define ANNEXDAT 0x66 3068 3069#define SCSCHKN 0x66 3070#define STSELSKIDDIS 0x40 3071#define CURRFIFODEF 0x20 3072#define WIDERESEN 0x10 3073#define SDONEMSKDIS 0x08 3074#define DFFACTCLR 0x04 3075#define SHVALIDSTDIS 0x02 3076#define LSTSGCLRDIS 0x01 3077 3078#define IOWNID 0x67 3079 3080#define SHCNT 0x68 3081 3082#define PLL960CTL0 0x68 3083 3084#define PLL960CTL1 0x69 3085 3086#define TOWNID 0x69 3087 3088#define XSIG 0x6a 3089 3090#define PLL960CNT0 0x6a 3091 3092#define SELOID 0x6b 3093 3094#define FAIRNESS 0x6c 3095 3096#define PLL400CTL0 0x6c 3097#define PLL_VCOSEL 0x80 3098#define PLL_PWDN 0x40 3099#define PLL_NS 0x30 3100#define PLL_ENLUD 0x08 3101#define PLL_ENLPF 0x04 3102#define PLL_DLPF 0x02 3103#define PLL_ENFBM 0x01 3104 3105#define PLL400CTL1 0x6d 3106#define PLL_CNTEN 0x80 3107#define PLL_CNTCLR 0x40 3108#define PLL_RST 0x01 3109 3110#define PLL400CNT0 0x6e 3111 3112#define UNFAIRNESS 0x6e 3113 3114#define HODMAADR 0x70 3115 3116#define HADDR 0x70 3117 3118#define PLLDELAY 0x70 3119#define SPLIT_DROP_REQ 0x80 3120 3121#define HCNT 0x78 3122 3123#define HODMACNT 0x78 3124 3125#define HODMAEN 0x7a 3126 3127#define SCBHADDR 0x7c 3128 3129#define SGHADDR 0x7c 3130 3131#define SCBHCNT 0x84 3132 3133#define SGHCNT 0x84 3134 3135#define DFF_THRSH 0x88 3136#define WR_DFTHRSH 0x70 3137#define RD_DFTHRSH 0x07 3138#define WR_DFTHRSH_MAX 0x70 3139#define WR_DFTHRSH_90 0x60 3140#define WR_DFTHRSH_85 0x50 3141#define WR_DFTHRSH_75 0x40 3142#define WR_DFTHRSH_63 0x30 3143#define WR_DFTHRSH_50 0x20 3144#define WR_DFTHRSH_25 0x10 3145#define RD_DFTHRSH_MAX 0x07 3146#define RD_DFTHRSH_90 0x06 3147#define RD_DFTHRSH_85 0x05 3148#define RD_DFTHRSH_75 0x04 3149#define RD_DFTHRSH_63 0x03 3150#define RD_DFTHRSH_50 0x02 3151#define RD_DFTHRSH_25 0x01 3152#define WR_DFTHRSH_MIN 0x00 3153#define RD_DFTHRSH_MIN 0x00 3154 3155#define ROMADDR 0x8a 3156 3157#define ROMCNTRL 0x8d 3158#define ROMOP 0xe0 3159#define ROMSPD 0x18 3160#define REPEAT 0x02 3161#define RDY 0x01 3162 3163#define ROMDATA 0x8e 3164 3165#define DCHRXMSG0 0x90 3166 3167#define OVLYRXMSG0 0x90 3168 3169#define CMCRXMSG0 0x90 3170 3171#define ROENABLE 0x90 3172#define MSIROEN 0x20 3173#define OVLYROEN 0x10 3174#define CMCROEN 0x08 3175#define SGROEN 0x04 3176#define DCH1ROEN 0x02 3177#define DCH0ROEN 0x01 3178 3179#define DCHRXMSG1 0x91 3180 3181#define OVLYRXMSG1 0x91 3182 3183#define CMCRXMSG1 0x91 3184 3185#define NSENABLE 0x91 3186#define MSINSEN 0x20 3187#define OVLYNSEN 0x10 3188#define CMCNSEN 0x08 3189#define SGNSEN 0x04 3190#define DCH1NSEN 0x02 3191#define DCH0NSEN 0x01 3192 3193#define DCHRXMSG2 0x92 3194 3195#define OVLYRXMSG2 0x92 3196 3197#define CMCRXMSG2 0x92 3198 3199#define OST 0x92 3200 3201#define DCHRXMSG3 0x93 3202 3203#define OVLYRXMSG3 0x93 3204 3205#define CMCRXMSG3 0x93 3206 3207#define PCIXCTL 0x93 3208#define SERRPULSE 0x80 3209#define UNEXPSCIEN 0x20 3210#define SPLTSMADIS 0x10 3211#define SPLTSTADIS 0x08 3212#define SRSPDPEEN 0x04 3213#define TSCSERREN 0x02 3214#define CMPABCDIS 0x01 3215 3216#define CMCSEQBCNT 0x94 3217 3218#define DCHSEQBCNT 0x94 3219 3220#define OVLYSEQBCNT 0x94 3221 3222#define CMCSPLTSTAT0 0x96 3223 3224#define DCHSPLTSTAT0 0x96 3225 3226#define OVLYSPLTSTAT0 0x96 3227 3228#define CMCSPLTSTAT1 0x97 3229 3230#define DCHSPLTSTAT1 0x97 3231 3232#define OVLYSPLTSTAT1 0x97 3233 3234#define SGRXMSG0 0x98 3235#define CDNUM 0xf8 3236#define CFNUM 0x07 3237 3238#define SLVSPLTOUTADR0 0x98 3239#define LOWER_ADDR 0x7f 3240 3241#define SGRXMSG1 0x99 3242#define CBNUM 0xff 3243 3244#define SLVSPLTOUTADR1 0x99 3245#define REQ_DNUM 0xf8 3246#define REQ_FNUM 0x07 3247 3248#define SGRXMSG2 0x9a 3249#define MINDEX 0xff 3250 3251#define SLVSPLTOUTADR2 0x9a 3252#define REQ_BNUM 0xff 3253 3254#define SGRXMSG3 0x9b 3255#define MCLASS 0x0f 3256 3257#define SLVSPLTOUTADR3 0x9b 3258#define TAG_NUM 0x1f 3259#define RLXORD 0x10 3260 3261#define SLVSPLTOUTATTR0 0x9c 3262#define LOWER_BCNT 0xff 3263 3264#define SGSEQBCNT 0x9c 3265 3266#define SLVSPLTOUTATTR1 0x9d 3267#define CMPLT_DNUM 0xf8 3268#define CMPLT_FNUM 0x07 3269 3270#define SLVSPLTOUTATTR2 0x9e 3271#define CMPLT_BNUM 0xff 3272 3273#define SGSPLTSTAT0 0x9e 3274#define STAETERM 0x80 3275#define SCBCERR 0x40 3276#define SCADERR 0x20 3277#define SCDATBUCKET 0x10 3278#define CNTNOTCMPLT 0x08 3279#define RXOVRUN 0x04 3280#define RXSCEMSG 0x02 3281#define RXSPLTRSP 0x01 3282 3283#define SFUNCT 0x9f 3284#define TEST_GROUP 0xf0 3285#define TEST_NUM 0x0f 3286 3287#define SGSPLTSTAT1 0x9f 3288#define RXDATABUCKET 0x01 3289 3290#define DF0PCISTAT 0xa0 3291 3292#define REG0 0xa0 3293 3294#define DF1PCISTAT 0xa1 3295 3296#define SGPCISTAT 0xa2 3297 3298#define REG1 0xa2 3299 3300#define CMCPCISTAT 0xa3 3301 3302#define OVLYPCISTAT 0xa4 3303#define SCAAPERR 0x08 3304#define RDPERR 0x04 3305 3306#define REG_ISR 0xa4 3307 3308#define MSIPCISTAT 0xa6 3309#define RMA 0x20 3310#define RTA 0x10 3311#define CLRPENDMSI 0x08 3312#define DPR 0x01 3313 3314#define SG_STATE 0xa6 3315#define FETCH_INPROG 0x04 3316#define LOADING_NEEDED 0x02 3317#define SEGS_AVAIL 0x01 3318 3319#define TARGPCISTAT 0xa7 3320#define DPE 0x80 3321#define SSE 0x40 3322#define STA 0x08 3323#define TWATERR 0x02 3324 3325#define DATA_COUNT_ODD 0xa7 3326 3327#define SCBPTR 0xa8 3328 3329#define CCSCBACNT 0xab 3330 3331#define SCBAUTOPTR 0xab 3332#define AUSCBPTR_EN 0x80 3333#define SCBPTR_ADDR 0x38 3334#define SCBPTR_OFF 0x07 3335 3336#define CCSCBADR_BK 0xac 3337 3338#define CCSGADDR 0xac 3339 3340#define CCSCBADDR 0xac 3341 3342#define CCSCBCTL 0xad 3343#define CCSCBDONE 0x80 3344#define ARRDONE 0x40 3345#define CCARREN 0x10 3346#define CCSCBEN 0x08 3347#define CCSCBDIR 0x04 3348#define CCSCBRESET 0x01 3349 3350#define CCSGCTL 0xad 3351#define CCSGEN 0x0c 3352#define CCSGDONE 0x80 3353#define SG_CACHE_AVAIL 0x10 3354#define CCSGENACK 0x08 3355#define SG_FETCH_REQ 0x02 3356#define CCSGRESET 0x01 3357 3358#define CMC_RAMBIST 0xad 3359#define SG_ELEMENT_SIZE 0x80 3360#define SCBRAMBIST_FAIL 0x40 3361#define SG_BIST_FAIL 0x20 3362#define SG_BIST_EN 0x10 3363#define CMC_BUFFER_BIST_FAIL 0x02 3364#define CMC_BUFFER_BIST_EN 0x01 3365 3366#define CCSGRAM 0xb0 3367 3368#define CCSCBRAM 0xb0 3369 3370#define FLEXADR 0xb0 3371 3372#define FLEXCNT 0xb3 3373 3374#define FLEXDMASTAT 0xb5 3375#define FLEXDMAERR 0x02 3376#define FLEXDMADONE 0x01 3377 3378#define FLEXDATA 0xb6 3379 3380#define BRDDAT 0xb8 3381 3382#define BRDCTL 0xb9 3383#define FLXARBACK 0x80 3384#define FLXARBREQ 0x40 3385#define BRDADDR 0x38 3386#define BRDEN 0x04 3387#define BRDRW 0x02 3388#define BRDSTB 0x01 3389 3390#define SEEADR 0xba 3391 3392#define SEEDAT 0xbc 3393 3394#define SEECTL 0xbe 3395#define SEEOP_EWEN 0x40 3396#define SEEOP_EWDS 0x40 3397#define SEEOP_WALL 0x40 3398#define SEEOPCODE 0x70 3399#define SEERST 0x02 3400#define SEESTART 0x01 3401#define SEEOP_ERASE 0x70 3402#define SEEOP_READ 0x60 3403#define SEEOP_WRITE 0x50 3404#define SEEOP_ERAL 0x40 3405 3406#define SEESTAT 0xbe 3407#define INIT_DONE 0x80 3408#define LDALTID_L 0x08 3409#define SEEARBACK 0x04 3410#define SEEBUSY 0x02 3411 3412#define SCBCNT 0xbf 3413 3414#define DSPFLTRCTL 0xc0 3415#define FLTRDISABLE 0x20 3416#define EDGESENSE 0x10 3417#define DSPFCNTSEL 0x0f 3418 3419#define DFWADDR 0xc0 3420 3421#define DSPDATACTL 0xc1 3422#define BYPASSENAB 0x80 3423#define DESQDIS 0x10 3424#define RCVROFFSTDIS 0x04 3425#define XMITOFFSTDIS 0x02 3426 3427#define DSPREQCTL 0xc2 3428#define MANREQCTL 0xc0 3429#define MANREQDLY 0x3f 3430 3431#define DFRADDR 0xc2 3432 3433#define DSPACKCTL 0xc3 3434#define MANACKCTL 0xc0 3435#define MANACKDLY 0x3f 3436 3437#define DFDAT 0xc4 3438 3439#define DSPSELECT 0xc4 3440#define AUTOINCEN 0x80 3441#define DSPSEL 0x1f 3442 3443#define WRTBIASCTL 0xc5 3444#define AUTOXBCDIS 0x80 3445#define XMITMANVAL 0x3f 3446 3447#define RCVRBIOSCTL 0xc6 3448#define AUTORBCDIS 0x80 3449#define RCVRMANVAL 0x3f 3450 3451#define WRTBIASCALC 0xc7 3452 3453#define DFPTRS 0xc8 3454 3455#define RCVRBIASCALC 0xc8 3456 3457#define DFBKPTR 0xc9 3458 3459#define SKEWCALC 0xc9 3460 3461#define DFDBCTL 0xcb 3462#define DFF_CIO_WR_RDY 0x20 3463#define DFF_CIO_RD_RDY 0x10 3464#define DFF_DIR_ERR 0x08 3465#define DFF_RAMBIST_FAIL 0x04 3466#define DFF_RAMBIST_DONE 0x02 3467#define DFF_RAMBIST_EN 0x01 3468 3469#define DFSCNT 0xcc 3470 3471#define DFBCNT 0xce 3472 3473#define OVLYADDR 0xd4 3474 3475#define SEQCTL0 0xd6 3476#define PERRORDIS 0x80 3477#define PAUSEDIS 0x40 3478#define FAILDIS 0x20 3479#define FASTMODE 0x10 3480#define BRKADRINTEN 0x08 3481#define STEP 0x04 3482#define SEQRESET 0x02 3483#define LOADRAM 0x01 3484 3485#define SEQCTL1 0xd7 3486#define OVRLAY_DATA_CHK 0x08 3487#define RAMBIST_DONE 0x04 3488#define RAMBIST_FAIL 0x02 3489#define RAMBIST_EN 0x01 3490 3491#define FLAGS 0xd8 3492#define ZERO 0x02 3493#define CARRY 0x01 3494 3495#define SEQINTCTL 0xd9 3496#define INTVEC1DSL 0x80 3497#define INT1_CONTEXT 0x20 3498#define SCS_SEQ_INT1M1 0x10 3499#define SCS_SEQ_INT1M0 0x08 3500#define INTMASK2 0x04 3501#define INTMASK1 0x02 3502#define IRET 0x01 3503 3504#define SEQRAM 0xda 3505 3506#define PRGMCNT 0xde 3507 3508#define ACCUM 0xe0 3509 3510#define SINDEX 0xe2 3511 3512#define DINDEX 0xe4 3513 3514#define BRKADDR1 0xe6 3515#define BRKDIS 0x80 3516 3517#define BRKADDR0 0xe6 3518 3519#define ALLONES 0xe8 3520 3521#define NONE 0xea 3522 3523#define ALLZEROS 0xea 3524 3525#define SINDIR 0xec 3526 3527#define DINDIR 0xed 3528 3529#define FUNCTION1 0xf0 3530 3531#define STACK 0xf2 3532 3533#define INTVEC1_ADDR 0xf4 3534 3535#define CURADDR 0xf4 3536 3537#define INTVEC2_ADDR 0xf6 3538 3539#define LASTADDR 0xf6 3540 3541#define LONGJMP_ADDR 0xf8 3542 3543#define ACCUM_SAVE 0xfa 3544 3545#define SRAM_BASE 0x100 3546 3547#define WAITING_SCB_TAILS 0x100 3548 3549#define AHD_PCI_CONFIG_BASE 0x100 3550 3551#define WAITING_TID_HEAD 0x120 3552 3553#define WAITING_TID_TAIL 0x122 3554 3555#define NEXT_QUEUED_SCB_ADDR 0x124 3556 3557#define COMPLETE_SCB_HEAD 0x128 3558 3559#define COMPLETE_SCB_DMAINPROG_HEAD 0x12a 3560 3561#define COMPLETE_DMA_SCB_HEAD 0x12c 3562 3563#define COMPLETE_DMA_SCB_TAIL 0x12e 3564 3565#define COMPLETE_ON_QFREEZE_HEAD 0x130 3566 3567#define QFREEZE_COUNT 0x132 3568 3569#define KERNEL_QFREEZE_COUNT 0x134 3570 3571#define SAVED_MODE 0x136 3572 3573#define MSG_OUT 0x137 3574 3575#define DMAPARAMS 0x138 3576#define PRELOADEN 0x80 3577#define WIDEODD 0x40 3578#define SCSIEN 0x20 3579#define SDMAEN 0x10 3580#define SDMAENACK 0x10 3581#define HDMAEN 0x08 3582#define HDMAENACK 0x08 3583#define DIRECTION 0x04 3584#define FIFOFLUSH 0x02 3585#define FIFORESET 0x01 3586 3587#define SEQ_FLAGS 0x139 3588#define NOT_IDENTIFIED 0x80 3589#define NO_CDB_SENT 0x40 3590#define TARGET_CMD_IS_TAGGED 0x40 3591#define DPHASE 0x20 3592#define TARG_CMD_PENDING 0x10 3593#define CMDPHASE_PENDING 0x08 3594#define DPHASE_PENDING 0x04 3595#define SPHASE_PENDING 0x02 3596#define NO_DISCONNECT 0x01 3597 3598#define SAVED_SCSIID 0x13a 3599 3600#define SAVED_LUN 0x13b 3601 3602#define LASTPHASE 0x13c 3603#define PHASE_MASK 0xe0 3604#define CDI 0x80 3605#define IOI 0x40 3606#define MSGI 0x20 3607#define P_BUSFREE 0x01 3608#define P_MESGIN 0xe0 3609#define P_STATUS 0xc0 3610#define P_MESGOUT 0xa0 3611#define P_COMMAND 0x80 3612#define P_DATAIN_DT 0x60 3613#define P_DATAIN 0x40 3614#define P_DATAOUT_DT 0x20 3615#define P_DATAOUT 0x00 3616 3617#define QOUTFIFO_ENTRY_VALID_TAG 0x13d 3618 3619#define KERNEL_TQINPOS 0x13e 3620 3621#define TQINPOS 0x13f 3622 3623#define SHARED_DATA_ADDR 0x140 3624 3625#define QOUTFIFO_NEXT_ADDR 0x144 3626 3627#define ARG_1 0x148 3628#define RETURN_1 0x148 3629#define SEND_MSG 0x80 3630#define SEND_SENSE 0x40 3631#define SEND_REJ 0x20 3632#define MSGOUT_PHASEMIS 0x10 3633#define EXIT_MSG_LOOP 0x08 3634#define CONT_MSG_LOOP_WRITE 0x04 3635#define CONT_MSG_LOOP_READ 0x03 3636#define CONT_MSG_LOOP_TARG 0x02 3637 3638#define ARG_2 0x149 3639#define RETURN_2 0x149 3640 3641#define LAST_MSG 0x14a 3642 3643#define SCSISEQ_TEMPLATE 0x14b 3644#define MANUALCTL 0x40 3645#define ENSELI 0x20 3646#define ENRSELI 0x10 3647#define MANUALP 0x0c 3648#define ENAUTOATNP 0x02 3649#define ALTSTIM 0x01 3650 3651#define INITIATOR_TAG 0x14c 3652 3653#define SEQ_FLAGS2 0x14d 3654#define SELECTOUT_QFROZEN 0x04 3655#define TARGET_MSG_PENDING 0x02 3656#define PENDING_MK_MESSAGE 0x01 3657 3658#define ALLOCFIFO_SCBPTR 0x14e 3659 3660#define INT_COALESCING_TIMER 0x150 3661 3662#define INT_COALESCING_MAXCMDS 0x152 3663 3664#define INT_COALESCING_MINCMDS 0x153 3665 3666#define CMDS_PENDING 0x154 3667 3668#define INT_COALESCING_CMDCOUNT 0x156 3669 3670#define LOCAL_HS_MAILBOX 0x157 3671 3672#define CMDSIZE_TABLE 0x158 3673 3674#define MK_MESSAGE_SCB 0x160 3675 3676#define MK_MESSAGE_SCSIID 0x162 3677 3678#define SCB_BASE 0x180 3679 3680#define SCB_RESIDUAL_DATACNT 0x180 3681#define SCB_HOST_CDB_PTR 0x180 3682#define SCB_CDB_STORE 0x180 3683 3684#define SCB_RESIDUAL_SGPTR 0x184 3685#define SG_ADDR_MASK 0xf8 3686#define SG_ADDR_BIT 0x04 3687#define SG_OVERRUN_RESID 0x02 3688 3689#define SCB_SCSI_STATUS 0x188 3690#define SCB_HOST_CDB_LEN 0x188 3691 3692#define SCB_TARGET_PHASES 0x189 3693 3694#define SCB_TARGET_DATA_DIR 0x18a 3695 3696#define SCB_TARGET_ITAG 0x18b 3697 3698#define SCB_SENSE_BUSADDR 0x18c 3699#define SCB_NEXT_COMPLETE 0x18c 3700 3701#define SCB_TAG 0x190 3702#define SCB_FIFO_USE_COUNT 0x190 3703 3704#define SCB_CONTROL 0x192 3705#define TARGET_SCB 0x80 3706#define DISCENB 0x40 3707#define TAG_ENB 0x20 3708#define MK_MESSAGE 0x10 3709#define STATUS_RCVD 0x08 3710#define DISCONNECTED 0x04 3711#define SCB_TAG_TYPE 0x03 3712 3713#define SCB_SCSIID 0x193 3714#define TID 0xf0 3715#define OID 0x0f 3716 3717#define SCB_LUN 0x194 3718#define LID 0xff 3719 3720#define SCB_TASK_ATTRIBUTE 0x195 3721#define SCB_XFERLEN_ODD 0x01 3722 3723#define SCB_CDB_LEN 0x196 3724#define SCB_CDB_LEN_PTR 0x80 3725 3726#define SCB_TASK_MANAGEMENT 0x197 3727 3728#define SCB_DATAPTR 0x198 3729 3730#define SCB_DATACNT 0x1a0 3731#define SG_LAST_SEG 0x80 3732#define SG_HIGH_ADDR_BITS 0x7f 3733 3734#define SCB_SGPTR 0x1a4 3735#define SG_STATUS_VALID 0x04 3736#define SG_FULL_RESID 0x02 3737#define SG_LIST_NULL 0x01 3738 3739#define SCB_BUSADDR 0x1a8 3740 3741#define SCB_NEXT 0x1ac 3742#define SCB_NEXT_SCB_BUSADDR 0x1ac 3743 3744#define SCB_NEXT2 0x1ae 3745 3746#define SCB_SPARE 0x1b0 3747#define SCB_PKT_LUN 0x1b0 3748 3749#define SCB_DISCONNECTED_LISTS 0x1b8 3750 3751#define STATUS_QUEUE_FULL 0x28 3752#define WRTBIASCTL_HP_DEFAULT 0x00 3753#define NUMDSPS 0x14 3754#define AHD_NUM_PER_DEV_ANNEXCOLS 0x04 3755#define AHD_TIMER_MAX_US 0x18ffe7 3756#define STIMESEL_MIN 0x18 3757#define TARGET_CMD_CMPLT 0xfe 3758#define SEEOP_ERAL_ADDR 0x80 3759#define SRC_MODE_SHIFT 0x00 3760#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 3761#define MAX_OFFSET_PACED 0xfe 3762#define SEEOP_EWDS_ADDR 0x00 3763#define AHD_ANNEXCOL_AMPLITUDE 0x06 3764#define AHD_PRECOMP_CUTBACK_29 0x06 3765#define AHD_ANNEXCOL_PER_DEV0 0x04 3766#define AHD_TIMER_MAX_TICKS 0xffff 3767#define STATUS_PKT_SENSE 0xff 3768#define CMD_GROUP_CODE_SHIFT 0x05 3769#define BUS_8_BIT 0x00 3770#define CCSGRAM_MAXSEGS 0x10 3771#define AHD_AMPLITUDE_DEF 0x07 3772#define AHD_SLEWRATE_DEF_REVB 0x08 3773#define AHD_PRECOMP_CUTBACK_37 0x07 3774#define AHD_PRECOMP_SHIFT 0x00 3775#define PKT_OVERRUN_BUFSIZE 0x200 3776#define SCB_TRANSFER_SIZE_FULL_LUN 0x38 3777#define TARGET_DATA_IN 0x01 3778#define STATUS_BUSY 0x08 3779#define BUS_16_BIT 0x01 3780#define CCSCBADDR_MAX 0x80 3781#define TID_SHIFT 0x04 3782#define AHD_AMPLITUDE_SHIFT 0x00 3783#define AHD_SLEWRATE_DEF_REVA 0x08 3784#define AHD_SLEWRATE_MASK 0x78 3785#define MAX_OFFSET_PACED_BUG 0x7f 3786#define AHD_PRECOMP_CUTBACK_17 0x04 3787#define AHD_PRECOMP_MASK 0x07 3788#define AHD_TIMER_US_PER_TICK 0x19 3789#define HOST_MSG 0xff 3790#define MAX_OFFSET 0xfe 3791#define BUS_32_BIT 0x02 3792#define SEEOP_EWEN_ADDR 0xc0 3793#define AHD_AMPLITUDE_MASK 0x07 3794#define LUNLEN_SINGLE_LEVEL_LUN 0x0f 3795#define DST_MODE_SHIFT 0x04 3796#define STIMESEL_SHIFT 0x03 3797#define SEEOP_WRAL_ADDR 0x40 3798#define AHD_ANNEXCOL_PRECOMP_SLEW 0x04 3799#define MAX_OFFSET_NON_PACED 0x7f 3800#define NVRAM_SCB_OFFSET 0x2c 3801#define AHD_SENSE_BUFSIZE 0x100 3802#define STIMESEL_BUG_ADJ 0x08 3803#define INVALID_ADDR 0x80 3804#define CCSGADDR_MAX 0x80 3805#define MK_MESSAGE_BIT_OFFSET 0x04 3806#define AHD_SLEWRATE_SHIFT 0x03 3807#define B_CURRFIFO_0 0x02 3808 3809/* Downloaded Constant Definitions */ 3810#define SG_SIZEOF 0x04 3811#define CACHELINE_MASK 0x07 3812#define SG_PREFETCH_ADDR_MASK 0x03 3813#define SG_PREFETCH_ALIGN_MASK 0x02 3814#define SCB_TRANSFER_SIZE 0x06 3815#define SG_PREFETCH_CNT 0x00 3816#define SG_PREFETCH_CNT_LIMIT 0x01 3817#define PKT_OVERRUN_BUFOFFSET 0x05 3818#define DOWNLOAD_CONST_COUNT 0x08 3819 3820/* Exported Labels */ 3821#define LABEL_seq_isr 0x28f 3822#define LABEL_timer_isr 0x28b 3823