1/*- 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 44 */ 45 46#ifdef __linux__ 47#include "aic79xx_osm.h" 48#include "aic79xx_inline.h" 49#else 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD$"); 52#include <dev/aic7xxx/aic79xx_osm.h> 53#include <dev/aic7xxx/aic79xx_inline.h> 54#endif 55 56static __inline uint64_t 57ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 58{ 59 uint64_t id; 60 61 id = subvendor 62 | (subdevice << 16) 63 | ((uint64_t)vendor << 32) 64 | ((uint64_t)device << 48); 65 66 return (id); 67} 68 69#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 70#define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 71#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 72#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 73#define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 74 75#define ID_AIC7901 0x800F9005FFFF9005ull 76#define ID_AHA_29320A 0x8000900500609005ull 77#define ID_AHA_29320ALP 0x8017900500449005ull 78#define ID_AHA_29320LPE 0x8017900500459005ull 79 80#define ID_AIC7901A 0x801E9005FFFF9005ull 81#define ID_AHA_29320LP 0x8014900500449005ull 82 83#define ID_AIC7902 0x801F9005FFFF9005ull 84#define ID_AIC7902_B 0x801D9005FFFF9005ull 85#define ID_AHA_39320 0x8010900500409005ull 86#define ID_AHA_29320 0x8012900500429005ull 87#define ID_AHA_29320B 0x8013900500439005ull 88#define ID_AHA_39320_B 0x8015900500409005ull 89#define ID_AHA_39320_B_DELL 0x8015900501681028ull 90#define ID_AHA_39320A 0x8016900500409005ull 91#define ID_AHA_39320D 0x8011900500419005ull 92#define ID_AHA_39320D_B 0x801C900500419005ull 93#define ID_AHA_39320D_HP 0x8011900500AC0E11ull 94#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 95#define ID_AIC7902_PCI_REV_A4 0x3 96#define ID_AIC7902_PCI_REV_B0 0x10 97#define SUBID_HP 0x0E11 98#define DEVICE8081 0x8081 99#define DEVICE8088 0x8088 100#define DEVICE8089 0x8089 101#define ADAPTECVENDORID 0x9005 102#define SUBVENDOR9005 0x9005 103 104#define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 105 106#define DEVID_9005_TYPE(id) ((id) & 0xF) 107#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 108#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 109#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 110 111#define DEVID_9005_MFUNC(id) ((id) & 0x10) 112 113#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 114 115#define SUBID_9005_TYPE(id) ((id) & 0xF) 116#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 117#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 118 119#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 120 121#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 122 123#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 124#define SUBID_9005_SEEPTYPE_NONE 0x0 125#define SUBID_9005_SEEPTYPE_4K 0x1 126 127static ahd_device_setup_t ahd_aic7901_setup; 128static ahd_device_setup_t ahd_aic7901A_setup; 129static ahd_device_setup_t ahd_aic7902_setup; 130static ahd_device_setup_t ahd_aic790X_setup; 131 132struct ahd_pci_identity ahd_pci_ident_table [] = 133{ 134 /* aic7901 based controllers */ 135 { 136 ID_AHA_29320A, 137 ID_ALL_MASK, 138 "Adaptec 29320A Ultra320 SCSI adapter", 139 ahd_aic7901_setup 140 }, 141 { 142 ID_AHA_29320ALP, 143 ID_ALL_MASK, 144 "Adaptec 29320ALP Ultra320 SCSI adapter", 145 ahd_aic7901_setup 146 }, 147 { 148 ID_AHA_29320LPE, 149 ID_ALL_MASK, 150 "Adaptec 29320LPE Ultra320 SCSI adapter", 151 ahd_aic7901_setup 152 }, 153 /* aic7901A based controllers */ 154 { 155 ID_AHA_29320LP, 156 ID_ALL_MASK, 157 "Adaptec 29320LP Ultra320 SCSI adapter", 158 ahd_aic7901A_setup 159 }, 160 /* aic7902 based controllers */ 161 { 162 ID_AHA_29320, 163 ID_ALL_MASK, 164 "Adaptec 29320 Ultra320 SCSI adapter", 165 ahd_aic7902_setup 166 }, 167 { 168 ID_AHA_29320B, 169 ID_ALL_MASK, 170 "Adaptec 29320B Ultra320 SCSI adapter", 171 ahd_aic7902_setup 172 }, 173 { 174 ID_AHA_39320, 175 ID_ALL_MASK, 176 "Adaptec 39320 Ultra320 SCSI adapter", 177 ahd_aic7902_setup 178 }, 179 { 180 ID_AHA_39320_B, 181 ID_ALL_MASK, 182 "Adaptec 39320 Ultra320 SCSI adapter", 183 ahd_aic7902_setup 184 }, 185 { 186 ID_AHA_39320_B_DELL, 187 ID_ALL_MASK, 188 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 189 ahd_aic7902_setup 190 }, 191 { 192 ID_AHA_39320A, 193 ID_ALL_MASK, 194 "Adaptec 39320A Ultra320 SCSI adapter", 195 ahd_aic7902_setup 196 }, 197 { 198 ID_AHA_39320D, 199 ID_ALL_MASK, 200 "Adaptec 39320D Ultra320 SCSI adapter", 201 ahd_aic7902_setup 202 }, 203 { 204 ID_AHA_39320D_HP, 205 ID_ALL_MASK, 206 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 207 ahd_aic7902_setup 208 }, 209 { 210 ID_AHA_39320D_B, 211 ID_ALL_MASK, 212 "Adaptec 39320D Ultra320 SCSI adapter", 213 ahd_aic7902_setup 214 }, 215 { 216 ID_AHA_39320D_B_HP, 217 ID_ALL_MASK, 218 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 219 ahd_aic7902_setup 220 }, 221 /* Generic chip probes for devices we don't know 'exactly' */ 222 { 223 ID_AIC7901 & ID_9005_GENERIC_MASK, 224 ID_9005_GENERIC_MASK, 225 "Adaptec AIC7901 Ultra320 SCSI adapter", 226 ahd_aic7901_setup 227 }, 228 { 229 ID_AIC7901A & ID_DEV_VENDOR_MASK, 230 ID_DEV_VENDOR_MASK, 231 "Adaptec AIC7901A Ultra320 SCSI adapter", 232 ahd_aic7901A_setup 233 }, 234 { 235 ID_AIC7902 & ID_9005_GENERIC_MASK, 236 ID_9005_GENERIC_MASK, 237 "Adaptec AIC7902 Ultra320 SCSI adapter", 238 ahd_aic7902_setup 239 } 240}; 241 242const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 243 244#define DEVCONFIG 0x40 245#define PCIXINITPAT 0x0000E000ul 246#define PCIXINIT_PCI33_66 0x0000E000ul 247#define PCIXINIT_PCIX50_66 0x0000C000ul 248#define PCIXINIT_PCIX66_100 0x0000A000ul 249#define PCIXINIT_PCIX100_133 0x00008000ul 250#define PCI_BUS_MODES_INDEX(devconfig) \ 251 (((devconfig) & PCIXINITPAT) >> 13) 252static const char *pci_bus_modes[] = 253{ 254 "PCI bus mode unknown", 255 "PCI bus mode unknown", 256 "PCI bus mode unknown", 257 "PCI bus mode unknown", 258 "PCI-X 101-133MHz", 259 "PCI-X 67-100MHz", 260 "PCI-X 50-66MHz", 261 "PCI 33 or 66MHz" 262}; 263 264#define TESTMODE 0x00000800ul 265#define IRDY_RST 0x00000200ul 266#define FRAME_RST 0x00000100ul 267#define PCI64BIT 0x00000080ul 268#define MRDCEN 0x00000040ul 269#define ENDIANSEL 0x00000020ul 270#define MIXQWENDIANEN 0x00000008ul 271#define DACEN 0x00000004ul 272#define STPWLEVEL 0x00000002ul 273#define QWENDIANSEL 0x00000001ul 274 275#define DEVCONFIG1 0x44 276#define PREQDIS 0x01 277 278#define CSIZE_LATTIME 0x0c 279#define CACHESIZE 0x000000fful 280#define LATTIME 0x0000ff00ul 281 282static int ahd_check_extport(struct ahd_softc *ahd); 283static void ahd_configure_termination(struct ahd_softc *ahd, 284 u_int adapter_control); 285static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 286 287struct ahd_pci_identity * 288ahd_find_pci_device(aic_dev_softc_t pci) 289{ 290 uint64_t full_id; 291 uint16_t device; 292 uint16_t vendor; 293 uint16_t subdevice; 294 uint16_t subvendor; 295 struct ahd_pci_identity *entry; 296 u_int i; 297 298 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 299 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 300 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 301 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 302 303 if ((vendor == ADAPTECVENDORID) && (subvendor == SUBVENDOR9005)) { 304 if ((device == DEVICE8081) || (device == DEVICE8088) || 305 (device == DEVICE8089)) { 306 printf("Controller device ID conflict with PMC Adaptec HBA\n"); 307 return (NULL); 308 } 309 } 310 311 full_id = ahd_compose_id(device, 312 vendor, 313 subdevice, 314 subvendor); 315 316 /* 317 * If we are configured to attach to HostRAID 318 * controllers, mask out the IROC/HostRAID bit 319 * in the 320 */ 321 if (ahd_attach_to_HostRAID_controllers) 322 full_id &= ID_ALL_IROC_MASK; 323 324 for (i = 0; i < ahd_num_pci_devs; i++) { 325 entry = &ahd_pci_ident_table[i]; 326 if (entry->full_id == (full_id & entry->id_mask)) { 327 /* Honor exclusion entries. */ 328 if (entry->name == NULL) 329 return (NULL); 330 return (entry); 331 } 332 } 333 return (NULL); 334} 335 336int 337ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 338{ 339 u_int command; 340 uint32_t devconfig; 341 uint16_t device; 342 uint16_t subvendor; 343 int error; 344 345 ahd->description = entry->name; 346 /* 347 * Record if this is a HostRAID board. 348 */ 349 device = aic_pci_read_config(ahd->dev_softc, 350 PCIR_DEVICE, /*bytes*/2); 351 if (DEVID_9005_HOSTRAID(device)) 352 ahd->flags |= AHD_HOSTRAID_BOARD; 353 354 /* 355 * Record if this is an HP board. 356 */ 357 subvendor = aic_pci_read_config(ahd->dev_softc, 358 PCIR_SUBVEND_0, /*bytes*/2); 359 if (subvendor == SUBID_HP) 360 ahd->flags |= AHD_HP_BOARD; 361 362 error = entry->setup(ahd); 363 if (error != 0) 364 return (error); 365 366 /* 367 * Find the PCI-X cap pointer. If we don't find it, 368 * pcix_ptr will be 0. 369 */ 370 pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 371 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 372 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 373 ahd->chip |= AHD_PCI; 374 /* Disable PCIX workarounds when running in PCI mode. */ 375 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 376 } else { 377 ahd->chip |= AHD_PCIX; 378 if (ahd->pcix_ptr == 0) 379 return (ENXIO); 380 } 381 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 382 383 aic_power_state_change(ahd, AIC_POWER_STATE_D0); 384 385 error = ahd_pci_map_registers(ahd); 386 if (error != 0) 387 return (error); 388 389 /* 390 * If we need to support high memory, enable dual 391 * address cycles. This bit must be set to enable 392 * high address bit generation even if we are on a 393 * 64bit bus (PCI64BIT set in devconfig). 394 */ 395 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 396 uint32_t devconfig; 397 398 if (bootverbose) 399 printf("%s: Enabling 39Bit Addressing\n", 400 ahd_name(ahd)); 401 devconfig = aic_pci_read_config(ahd->dev_softc, 402 DEVCONFIG, /*bytes*/4); 403 devconfig |= DACEN; 404 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 405 devconfig, /*bytes*/4); 406 } 407 408 /* Ensure busmastering is enabled */ 409 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 410 command |= PCIM_CMD_BUSMASTEREN; 411 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 412 413 error = ahd_softc_init(ahd); 414 if (error != 0) 415 return (error); 416 417 ahd->bus_intr = ahd_pci_intr; 418 419 error = ahd_reset(ahd, /*reinit*/FALSE); 420 if (error != 0) 421 return (ENXIO); 422 423 ahd->pci_cachesize = 424 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 425 /*bytes*/1) & CACHESIZE; 426 ahd->pci_cachesize *= 4; 427 428 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 429 /* See if we have a SEEPROM and perform auto-term */ 430 error = ahd_check_extport(ahd); 431 if (error != 0) 432 return (error); 433 434 /* Core initialization */ 435 error = ahd_init(ahd); 436 if (error != 0) 437 return (error); 438 439 /* 440 * Allow interrupts now that we are completely setup. 441 */ 442 error = ahd_pci_map_int(ahd); 443 if (error != 0) 444 return (error); 445 446 ahd_lock(ahd); 447 /* 448 * Link this softc in with all other ahd instances. 449 */ 450 ahd_softc_insert(ahd); 451 ahd_unlock(ahd); 452 return (0); 453} 454 455/* 456 * Perform some simple tests that should catch situations where 457 * our registers are invalidly mapped. 458 */ 459int 460ahd_pci_test_register_access(struct ahd_softc *ahd) 461{ 462 uint32_t cmd; 463 u_int targpcistat; 464 u_int pci_status1; 465 int error; 466 uint8_t hcntrl; 467 468 error = EIO; 469 470 /* 471 * Enable PCI error interrupt status, but suppress NMIs 472 * generated by SERR raised due to target aborts. 473 */ 474 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 475 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 476 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 477 478 /* 479 * First a simple test to see if any 480 * registers can be read. Reading 481 * HCNTRL has no side effects and has 482 * at least one bit that is guaranteed to 483 * be zero so it is a good register to 484 * use for this test. 485 */ 486 hcntrl = ahd_inb(ahd, HCNTRL); 487 if (hcntrl == 0xFF) 488 goto fail; 489 490 /* 491 * Next create a situation where write combining 492 * or read prefetching could be initiated by the 493 * CPU or host bridge. Our device does not support 494 * either, so look for data corruption and/or flagged 495 * PCI errors. First pause without causing another 496 * chip reset. 497 */ 498 hcntrl &= ~CHIPRST; 499 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 500 while (ahd_is_paused(ahd) == 0) 501 ; 502 503 /* Clear any PCI errors that occurred before our driver attached. */ 504 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 505 targpcistat = ahd_inb(ahd, TARGPCISTAT); 506 ahd_outb(ahd, TARGPCISTAT, targpcistat); 507 pci_status1 = aic_pci_read_config(ahd->dev_softc, 508 PCIR_STATUS + 1, /*bytes*/1); 509 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 510 pci_status1, /*bytes*/1); 511 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 512 ahd_outb(ahd, CLRINT, CLRPCIINT); 513 514 ahd_outb(ahd, SEQCTL0, PERRORDIS); 515 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 516 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 517 goto fail; 518 519 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 520 u_int targpcistat; 521 522 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 523 targpcistat = ahd_inb(ahd, TARGPCISTAT); 524 if ((targpcistat & STA) != 0) 525 goto fail; 526 } 527 528 error = 0; 529 530fail: 531 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 532 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 533 targpcistat = ahd_inb(ahd, TARGPCISTAT); 534 535 /* Silently clear any latched errors. */ 536 ahd_outb(ahd, TARGPCISTAT, targpcistat); 537 pci_status1 = aic_pci_read_config(ahd->dev_softc, 538 PCIR_STATUS + 1, /*bytes*/1); 539 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 540 pci_status1, /*bytes*/1); 541 ahd_outb(ahd, CLRINT, CLRPCIINT); 542 } 543 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 544 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 545 return (error); 546} 547 548/* 549 * Check the external port logic for a serial eeprom 550 * and termination/cable detection contrls. 551 */ 552static int 553ahd_check_extport(struct ahd_softc *ahd) 554{ 555 struct vpd_config vpd; 556 struct seeprom_config *sc; 557 u_int adapter_control; 558 int have_seeprom; 559 int error; 560 561 sc = ahd->seep_config; 562 have_seeprom = ahd_acquire_seeprom(ahd); 563 if (have_seeprom) { 564 u_int start_addr; 565 566 /* 567 * Fetch VPD for this function and parse it. 568 */ 569 if (bootverbose) 570 printf("%s: Reading VPD from SEEPROM...", 571 ahd_name(ahd)); 572 573 /* Address is always in units of 16bit words */ 574 start_addr = ((2 * sizeof(*sc)) 575 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 576 577 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 578 start_addr, sizeof(vpd)/2, 579 /*bytestream*/TRUE); 580 if (error == 0) 581 error = ahd_parse_vpddata(ahd, &vpd); 582 if (bootverbose) 583 printf("%s: VPD parsing %s\n", 584 ahd_name(ahd), 585 error == 0 ? "successful" : "failed"); 586 587 if (bootverbose) 588 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 589 590 /* Address is always in units of 16bit words */ 591 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 592 593 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 594 start_addr, sizeof(*sc)/2, 595 /*bytestream*/FALSE); 596 597 if (error != 0) { 598 printf("Unable to read SEEPROM\n"); 599 have_seeprom = 0; 600 } else { 601 have_seeprom = ahd_verify_cksum(sc); 602 603 if (bootverbose) { 604 if (have_seeprom == 0) 605 printf ("checksum error\n"); 606 else 607 printf ("done.\n"); 608 } 609 } 610 ahd_release_seeprom(ahd); 611 } 612 613 if (!have_seeprom) { 614 u_int nvram_scb; 615 616 /* 617 * Pull scratch ram settings and treat them as 618 * if they are the contents of an seeprom if 619 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 620 * in SCB 0xFF. We manually compose the data as 16bit 621 * values to avoid endian issues. 622 */ 623 ahd_set_scbptr(ahd, 0xFF); 624 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 625 if (nvram_scb != 0xFF 626 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 627 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 628 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 629 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 630 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 631 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 632 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 633 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 634 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 635 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 636 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 637 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 638 uint16_t *sc_data; 639 int i; 640 641 ahd_set_scbptr(ahd, nvram_scb); 642 sc_data = (uint16_t *)sc; 643 for (i = 0; i < 64; i += 2) 644 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 645 have_seeprom = ahd_verify_cksum(sc); 646 if (have_seeprom) 647 ahd->flags |= AHD_SCB_CONFIG_USED; 648 } 649 } 650 651#ifdef AHD_DEBUG 652 if (have_seeprom != 0 653 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 654 uint16_t *sc_data; 655 int i; 656 657 printf("%s: Seeprom Contents:", ahd_name(ahd)); 658 sc_data = (uint16_t *)sc; 659 for (i = 0; i < (sizeof(*sc)); i += 2) 660 printf("\n\t0x%.4x", sc_data[i]); 661 printf("\n"); 662 } 663#endif 664 665 if (!have_seeprom) { 666 if (bootverbose) 667 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 668 ahd->flags |= AHD_USEDEFAULTS; 669 error = ahd_default_config(ahd); 670 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 671 free(ahd->seep_config, M_DEVBUF); 672 ahd->seep_config = NULL; 673 } else { 674 error = ahd_parse_cfgdata(ahd, sc); 675 adapter_control = sc->adapter_control; 676 } 677 if (error != 0) 678 return (error); 679 680 ahd_configure_termination(ahd, adapter_control); 681 682 return (0); 683} 684 685static void 686ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 687{ 688 int error; 689 u_int sxfrctl1; 690 uint8_t termctl; 691 uint32_t devconfig; 692 693 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 694 devconfig &= ~STPWLEVEL; 695 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 696 devconfig |= STPWLEVEL; 697 if (bootverbose) 698 printf("%s: STPWLEVEL is %s\n", 699 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 700 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 701 702 /* Make sure current sensing is off. */ 703 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 704 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 705 } 706 707 /* 708 * Read to sense. Write to set. 709 */ 710 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 711 if ((adapter_control & CFAUTOTERM) == 0) { 712 if (bootverbose) 713 printf("%s: Manual Primary Termination\n", 714 ahd_name(ahd)); 715 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 716 if ((adapter_control & CFSTERM) != 0) 717 termctl |= FLX_TERMCTL_ENPRILOW; 718 if ((adapter_control & CFWSTERM) != 0) 719 termctl |= FLX_TERMCTL_ENPRIHIGH; 720 } else if (error != 0) { 721 printf("%s: Primary Auto-Term Sensing failed! " 722 "Using Defaults.\n", ahd_name(ahd)); 723 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 724 } 725 726 if ((adapter_control & CFSEAUTOTERM) == 0) { 727 if (bootverbose) 728 printf("%s: Manual Secondary Termination\n", 729 ahd_name(ahd)); 730 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 731 if ((adapter_control & CFSELOWTERM) != 0) 732 termctl |= FLX_TERMCTL_ENSECLOW; 733 if ((adapter_control & CFSEHIGHTERM) != 0) 734 termctl |= FLX_TERMCTL_ENSECHIGH; 735 } else if (error != 0) { 736 printf("%s: Secondary Auto-Term Sensing failed! " 737 "Using Defaults.\n", ahd_name(ahd)); 738 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 739 } 740 741 /* 742 * Now set the termination based on what we found. 743 */ 744 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 745 ahd->flags &= ~AHD_TERM_ENB_A; 746 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 747 ahd->flags |= AHD_TERM_ENB_A; 748 sxfrctl1 |= STPWEN; 749 } 750 /* Must set the latch once in order to be effective. */ 751 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 752 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 753 754 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 755 if (error != 0) { 756 printf("%s: Unable to set termination settings!\n", 757 ahd_name(ahd)); 758 } else if (bootverbose) { 759 printf("%s: Primary High byte termination %sabled\n", 760 ahd_name(ahd), 761 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 762 763 printf("%s: Primary Low byte termination %sabled\n", 764 ahd_name(ahd), 765 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 766 767 printf("%s: Secondary High byte termination %sabled\n", 768 ahd_name(ahd), 769 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 770 771 printf("%s: Secondary Low byte termination %sabled\n", 772 ahd_name(ahd), 773 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 774 } 775 return; 776} 777 778#define DPE 0x80 779#define SSE 0x40 780#define RMA 0x20 781#define RTA 0x10 782#define STA 0x08 783#define DPR 0x01 784 785static const char *split_status_source[] = 786{ 787 "DFF0", 788 "DFF1", 789 "OVLY", 790 "CMC", 791}; 792 793static const char *pci_status_source[] = 794{ 795 "DFF0", 796 "DFF1", 797 "SG", 798 "CMC", 799 "OVLY", 800 "NONE", 801 "MSI", 802 "TARG" 803}; 804 805static const char *split_status_strings[] = 806{ 807 "%s: Received split response in %s.\n", 808 "%s: Received split completion error message in %s\n", 809 "%s: Receive overrun in %s\n", 810 "%s: Count not complete in %s\n", 811 "%s: Split completion data bucket in %s\n", 812 "%s: Split completion address error in %s\n", 813 "%s: Split completion byte count error in %s\n", 814 "%s: Signaled Target-abort to early terminate a split in %s\n" 815}; 816 817static const char *pci_status_strings[] = 818{ 819 "%s: Data Parity Error has been reported via PERR# in %s\n", 820 "%s: Target initial wait state error in %s\n", 821 "%s: Split completion read data parity error in %s\n", 822 "%s: Split completion address attribute parity error in %s\n", 823 "%s: Received a Target Abort in %s\n", 824 "%s: Received a Master Abort in %s\n", 825 "%s: Signal System Error Detected in %s\n", 826 "%s: Address or Write Phase Parity Error Detected in %s.\n" 827}; 828 829void 830ahd_pci_intr(struct ahd_softc *ahd) 831{ 832 uint8_t pci_status[8]; 833 ahd_mode_state saved_modes; 834 u_int pci_status1; 835 u_int intstat; 836 u_int i; 837 u_int reg; 838 839 intstat = ahd_inb(ahd, INTSTAT); 840 841 if ((intstat & SPLTINT) != 0) 842 ahd_pci_split_intr(ahd, intstat); 843 844 if ((intstat & PCIINT) == 0) 845 return; 846 847 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 848 saved_modes = ahd_save_modes(ahd); 849 ahd_dump_card_state(ahd); 850 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 851 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 852 if (i == 5) 853 continue; 854 pci_status[i] = ahd_inb(ahd, reg); 855 /* Clear latched errors. So our interrupt deasserts. */ 856 ahd_outb(ahd, reg, pci_status[i]); 857 } 858 859 for (i = 0; i < 8; i++) { 860 u_int bit; 861 862 if (i == 5) 863 continue; 864 865 for (bit = 0; bit < 8; bit++) { 866 if ((pci_status[i] & (0x1 << bit)) != 0) { 867 static const char *s; 868 869 s = pci_status_strings[bit]; 870 if (i == 7/*TARG*/ && bit == 3) 871 s = "%s: Signaled Target Abort\n"; 872 printf(s, ahd_name(ahd), pci_status_source[i]); 873 } 874 } 875 } 876 pci_status1 = aic_pci_read_config(ahd->dev_softc, 877 PCIR_STATUS + 1, /*bytes*/1); 878 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 879 pci_status1, /*bytes*/1); 880 ahd_restore_modes(ahd, saved_modes); 881 ahd_outb(ahd, CLRINT, CLRPCIINT); 882 ahd_unpause(ahd); 883} 884 885static void 886ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 887{ 888 uint8_t split_status[4]; 889 uint8_t split_status1[4]; 890 uint8_t sg_split_status[2]; 891 uint8_t sg_split_status1[2]; 892 ahd_mode_state saved_modes; 893 u_int i; 894 uint32_t pcix_status; 895 896 /* 897 * Check for splits in all modes. Modes 0 and 1 898 * additionally have SG engine splits to look at. 899 */ 900 pcix_status = aic_pci_read_config(ahd->dev_softc, 901 ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 902 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 903 ahd_name(ahd), pcix_status >> 16); 904 saved_modes = ahd_save_modes(ahd); 905 for (i = 0; i < 4; i++) { 906 ahd_set_modes(ahd, i, i); 907 908 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 909 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 910 /* Clear latched errors. So our interrupt deasserts. */ 911 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 912 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 913 if (i > 1) 914 continue; 915 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 916 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 917 /* Clear latched errors. So our interrupt deasserts. */ 918 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 919 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 920 } 921 922 for (i = 0; i < 4; i++) { 923 u_int bit; 924 925 for (bit = 0; bit < 8; bit++) { 926 if ((split_status[i] & (0x1 << bit)) != 0) { 927 static const char *s; 928 929 s = split_status_strings[bit]; 930 printf(s, ahd_name(ahd), 931 split_status_source[i]); 932 } 933 934 if (i > 1) 935 continue; 936 937 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 938 static const char *s; 939 940 s = split_status_strings[bit]; 941 printf(s, ahd_name(ahd), "SG"); 942 } 943 } 944 } 945 /* 946 * Clear PCI-X status bits. 947 */ 948 aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 949 pcix_status, /*bytes*/4); 950 ahd_outb(ahd, CLRINT, CLRSPLTINT); 951 ahd_restore_modes(ahd, saved_modes); 952} 953 954static int 955ahd_aic7901_setup(struct ahd_softc *ahd) 956{ 957 958 ahd->chip = AHD_AIC7901; 959 ahd->features = AHD_AIC7901_FE; 960 return (ahd_aic790X_setup(ahd)); 961} 962 963static int 964ahd_aic7901A_setup(struct ahd_softc *ahd) 965{ 966 967 ahd->chip = AHD_AIC7901A; 968 ahd->features = AHD_AIC7901A_FE; 969 return (ahd_aic790X_setup(ahd)); 970} 971 972static int 973ahd_aic7902_setup(struct ahd_softc *ahd) 974{ 975 ahd->chip = AHD_AIC7902; 976 ahd->features = AHD_AIC7902_FE; 977 return (ahd_aic790X_setup(ahd)); 978} 979 980static int 981ahd_aic790X_setup(struct ahd_softc *ahd) 982{ 983 aic_dev_softc_t pci; 984 u_int rev; 985 986 pci = ahd->dev_softc; 987 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 988 if (rev < ID_AIC7902_PCI_REV_A4) { 989 printf("%s: Unable to attach to unsupported chip revision %d\n", 990 ahd_name(ahd), rev); 991 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 992 return (ENXIO); 993 } 994 ahd->channel = aic_get_pci_function(pci) + 'A'; 995 if (rev < ID_AIC7902_PCI_REV_B0) { 996 /* 997 * Enable A series workarounds. 998 */ 999 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1000 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1001 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1002 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1003 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1004 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1005 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1006 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1007 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1008 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1009 | AHD_FAINT_LED_BUG; 1010 1011 /* 1012 * IO Cell parameter setup. 1013 */ 1014 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1015 1016 if ((ahd->flags & AHD_HP_BOARD) == 0) 1017 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1018 } else { 1019 u_int devconfig1; 1020 1021 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1022 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1023 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1024 1025 /* 1026 * Some issues have been resolved in the 7901B. 1027 */ 1028 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1029 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1030 | AHD_BUSFREEREV_BUG; 1031 1032 /* 1033 * IO Cell parameter setup. 1034 */ 1035 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1036 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1037 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1038 1039 /* 1040 * Set the PREQDIS bit for H2B which disables some workaround 1041 * that doesn't work on regular PCI busses. 1042 * XXX - Find out exactly what this does from the hardware 1043 * folks! 1044 */ 1045 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1046 aic_pci_write_config(pci, DEVCONFIG1, 1047 devconfig1|PREQDIS, /*bytes*/1); 1048 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1049 } 1050 1051 return (0); 1052} 1053