1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pko-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pko. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PKO_DEFS_H__ 53#define __CVMX_PKO_DEFS_H__ 54 55#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull)) 56#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull)) 57#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull)) 58#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull)) 59#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull)) 60#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull)) 61#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull)) 62#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull)) 63#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 64#define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC() 65static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void) 66{ 67 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 68 cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n"); 69 return CVMX_ADD_IO_SEG(0x0001180050001170ull); 70} 71#else 72#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull)) 73#endif 74#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull)) 75#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull)) 76#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull)) 77#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull)) 78#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull)) 79#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull)) 80#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull)) 81#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull)) 82#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 83#define CVMX_PKO_MEM_IPORT_PTRS CVMX_PKO_MEM_IPORT_PTRS_FUNC() 84static inline uint64_t CVMX_PKO_MEM_IPORT_PTRS_FUNC(void) 85{ 86 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 87 cvmx_warn("CVMX_PKO_MEM_IPORT_PTRS not supported on this chip\n"); 88 return CVMX_ADD_IO_SEG(0x0001180050001030ull); 89} 90#else 91#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull)) 92#endif 93#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 94#define CVMX_PKO_MEM_IPORT_QOS CVMX_PKO_MEM_IPORT_QOS_FUNC() 95static inline uint64_t CVMX_PKO_MEM_IPORT_QOS_FUNC(void) 96{ 97 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 98 cvmx_warn("CVMX_PKO_MEM_IPORT_QOS not supported on this chip\n"); 99 return CVMX_ADD_IO_SEG(0x0001180050001038ull); 100} 101#else 102#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull)) 103#endif 104#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 105#define CVMX_PKO_MEM_IQUEUE_PTRS CVMX_PKO_MEM_IQUEUE_PTRS_FUNC() 106static inline uint64_t CVMX_PKO_MEM_IQUEUE_PTRS_FUNC(void) 107{ 108 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 109 cvmx_warn("CVMX_PKO_MEM_IQUEUE_PTRS not supported on this chip\n"); 110 return CVMX_ADD_IO_SEG(0x0001180050001040ull); 111} 112#else 113#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull)) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116#define CVMX_PKO_MEM_IQUEUE_QOS CVMX_PKO_MEM_IQUEUE_QOS_FUNC() 117static inline uint64_t CVMX_PKO_MEM_IQUEUE_QOS_FUNC(void) 118{ 119 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 120 cvmx_warn("CVMX_PKO_MEM_IQUEUE_QOS not supported on this chip\n"); 121 return CVMX_ADD_IO_SEG(0x0001180050001048ull); 122} 123#else 124#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull)) 125#endif 126#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 127#define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC() 128static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void) 129{ 130 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 131 cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n"); 132 return CVMX_ADD_IO_SEG(0x0001180050001010ull); 133} 134#else 135#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull)) 136#endif 137#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 138#define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC() 139static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void) 140{ 141 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 142 cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n"); 143 return CVMX_ADD_IO_SEG(0x0001180050001018ull); 144} 145#else 146#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull)) 147#endif 148#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 149#define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC() 150static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void) 151{ 152 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 153 cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n"); 154 return CVMX_ADD_IO_SEG(0x0001180050001020ull); 155} 156#else 157#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull)) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160#define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC() 161static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void) 162{ 163 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 164 cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n"); 165 return CVMX_ADD_IO_SEG(0x0001180050001028ull); 166} 167#else 168#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull)) 169#endif 170#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 171#define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC() 172static inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void) 173{ 174 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 175 cvmx_warn("CVMX_PKO_MEM_QUEUE_PTRS not supported on this chip\n"); 176 return CVMX_ADD_IO_SEG(0x0001180050001000ull); 177} 178#else 179#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull)) 180#endif 181#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 182#define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC() 183static inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void) 184{ 185 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 186 cvmx_warn("CVMX_PKO_MEM_QUEUE_QOS not supported on this chip\n"); 187 return CVMX_ADD_IO_SEG(0x0001180050001008ull); 188} 189#else 190#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull)) 191#endif 192#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 193#define CVMX_PKO_MEM_THROTTLE_INT CVMX_PKO_MEM_THROTTLE_INT_FUNC() 194static inline uint64_t CVMX_PKO_MEM_THROTTLE_INT_FUNC(void) 195{ 196 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 197 cvmx_warn("CVMX_PKO_MEM_THROTTLE_INT not supported on this chip\n"); 198 return CVMX_ADD_IO_SEG(0x0001180050001058ull); 199} 200#else 201#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull)) 202#endif 203#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 204#define CVMX_PKO_MEM_THROTTLE_PIPE CVMX_PKO_MEM_THROTTLE_PIPE_FUNC() 205static inline uint64_t CVMX_PKO_MEM_THROTTLE_PIPE_FUNC(void) 206{ 207 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 208 cvmx_warn("CVMX_PKO_MEM_THROTTLE_PIPE not supported on this chip\n"); 209 return CVMX_ADD_IO_SEG(0x0001180050001050ull); 210} 211#else 212#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull)) 213#endif 214#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull)) 215#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull)) 216#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 217static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset) 218{ 219 if (!( 220 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 221 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 222 cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset); 223 return CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8; 224} 225#else 226#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8) 227#endif 228#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 229#define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC() 230static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void) 231{ 232 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 233 cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n"); 234 return CVMX_ADD_IO_SEG(0x0001180050000020ull); 235} 236#else 237#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull)) 238#endif 239#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 240static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset) 241{ 242 if (!( 243 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 244 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 245 cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset); 246 return CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8; 247} 248#else 249#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8) 250#endif 251#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull)) 252#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 253#define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC() 254static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void) 255{ 256 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 257 cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n"); 258 return CVMX_ADD_IO_SEG(0x00011800500000A0ull); 259} 260#else 261#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull)) 262#endif 263#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264#define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC() 265static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void) 266{ 267 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 268 cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n"); 269 return CVMX_ADD_IO_SEG(0x00011800500000A8ull); 270} 271#else 272#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull)) 273#endif 274#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 275#define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC() 276static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void) 277{ 278 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 279 cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n"); 280 return CVMX_ADD_IO_SEG(0x00011800500000B0ull); 281} 282#else 283#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull)) 284#endif 285#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 286#define CVMX_PKO_REG_DEBUG4 CVMX_PKO_REG_DEBUG4_FUNC() 287static inline uint64_t CVMX_PKO_REG_DEBUG4_FUNC(void) 288{ 289 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 290 cvmx_warn("CVMX_PKO_REG_DEBUG4 not supported on this chip\n"); 291 return CVMX_ADD_IO_SEG(0x00011800500000B8ull); 292} 293#else 294#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull)) 295#endif 296#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 297#define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC() 298static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void) 299{ 300 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 301 cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n"); 302 return CVMX_ADD_IO_SEG(0x0001180050000050ull); 303} 304#else 305#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull)) 306#endif 307#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308#define CVMX_PKO_REG_ENGINE_INFLIGHT1 CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC() 309static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT1_FUNC(void) 310{ 311 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 312 cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT1 not supported on this chip\n"); 313 return CVMX_ADD_IO_SEG(0x0001180050000318ull); 314} 315#else 316#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull)) 317#endif 318#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319static inline uint64_t CVMX_PKO_REG_ENGINE_STORAGEX(unsigned long offset) 320{ 321 if (!( 322 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 323 cvmx_warn("CVMX_PKO_REG_ENGINE_STORAGEX(%lu) is invalid on this chip\n", offset); 324 return CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8; 325} 326#else 327#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8) 328#endif 329#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 330#define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC() 331static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void) 332{ 333 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 334 cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n"); 335 return CVMX_ADD_IO_SEG(0x0001180050000058ull); 336} 337#else 338#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull)) 339#endif 340#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull)) 341#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull)) 342#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 343#define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC() 344static inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void) 345{ 346 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 347 cvmx_warn("CVMX_PKO_REG_GMX_PORT_MODE not supported on this chip\n"); 348 return CVMX_ADD_IO_SEG(0x0001180050000018ull); 349} 350#else 351#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull)) 352#endif 353#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull)) 354#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355#define CVMX_PKO_REG_LOOPBACK_BPID CVMX_PKO_REG_LOOPBACK_BPID_FUNC() 356static inline uint64_t CVMX_PKO_REG_LOOPBACK_BPID_FUNC(void) 357{ 358 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 359 cvmx_warn("CVMX_PKO_REG_LOOPBACK_BPID not supported on this chip\n"); 360 return CVMX_ADD_IO_SEG(0x0001180050000118ull); 361} 362#else 363#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull)) 364#endif 365#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 366#define CVMX_PKO_REG_LOOPBACK_PKIND CVMX_PKO_REG_LOOPBACK_PKIND_FUNC() 367static inline uint64_t CVMX_PKO_REG_LOOPBACK_PKIND_FUNC(void) 368{ 369 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 370 cvmx_warn("CVMX_PKO_REG_LOOPBACK_PKIND not supported on this chip\n"); 371 return CVMX_ADD_IO_SEG(0x0001180050000068ull); 372} 373#else 374#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull)) 375#endif 376#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 377#define CVMX_PKO_REG_MIN_PKT CVMX_PKO_REG_MIN_PKT_FUNC() 378static inline uint64_t CVMX_PKO_REG_MIN_PKT_FUNC(void) 379{ 380 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 381 cvmx_warn("CVMX_PKO_REG_MIN_PKT not supported on this chip\n"); 382 return CVMX_ADD_IO_SEG(0x0001180050000070ull); 383} 384#else 385#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull)) 386#endif 387#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 388#define CVMX_PKO_REG_PREEMPT CVMX_PKO_REG_PREEMPT_FUNC() 389static inline uint64_t CVMX_PKO_REG_PREEMPT_FUNC(void) 390{ 391 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 392 cvmx_warn("CVMX_PKO_REG_PREEMPT not supported on this chip\n"); 393 return CVMX_ADD_IO_SEG(0x0001180050000110ull); 394} 395#else 396#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull)) 397#endif 398#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull)) 399#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 400#define CVMX_PKO_REG_QUEUE_PREEMPT CVMX_PKO_REG_QUEUE_PREEMPT_FUNC() 401static inline uint64_t CVMX_PKO_REG_QUEUE_PREEMPT_FUNC(void) 402{ 403 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 404 cvmx_warn("CVMX_PKO_REG_QUEUE_PREEMPT not supported on this chip\n"); 405 return CVMX_ADD_IO_SEG(0x0001180050000108ull); 406} 407#else 408#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull)) 409#endif 410#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 411#define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC() 412static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void) 413{ 414 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 415 cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n"); 416 return CVMX_ADD_IO_SEG(0x0001180050000100ull); 417} 418#else 419#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull)) 420#endif 421#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull)) 422#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 423#define CVMX_PKO_REG_THROTTLE CVMX_PKO_REG_THROTTLE_FUNC() 424static inline uint64_t CVMX_PKO_REG_THROTTLE_FUNC(void) 425{ 426 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 427 cvmx_warn("CVMX_PKO_REG_THROTTLE not supported on this chip\n"); 428 return CVMX_ADD_IO_SEG(0x0001180050000078ull); 429} 430#else 431#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull)) 432#endif 433#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 434#define CVMX_PKO_REG_TIMESTAMP CVMX_PKO_REG_TIMESTAMP_FUNC() 435static inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void) 436{ 437 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 438 cvmx_warn("CVMX_PKO_REG_TIMESTAMP not supported on this chip\n"); 439 return CVMX_ADD_IO_SEG(0x0001180050000060ull); 440} 441#else 442#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull)) 443#endif 444 445/** 446 * cvmx_pko_mem_count0 447 * 448 * Notes: 449 * Total number of packets seen by PKO, per port 450 * A write to this address will clear the entry whose index is specified as COUNT[5:0]. 451 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 452 * CSR read operations to this address can be performed. A read of any entry that has not been 453 * previously written is illegal and will result in unpredictable CSR read data. 454 */ 455union cvmx_pko_mem_count0 { 456 uint64_t u64; 457 struct cvmx_pko_mem_count0_s { 458#ifdef __BIG_ENDIAN_BITFIELD 459 uint64_t reserved_32_63 : 32; 460 uint64_t count : 32; /**< Total number of packets seen by PKO */ 461#else 462 uint64_t count : 32; 463 uint64_t reserved_32_63 : 32; 464#endif 465 } s; 466 struct cvmx_pko_mem_count0_s cn30xx; 467 struct cvmx_pko_mem_count0_s cn31xx; 468 struct cvmx_pko_mem_count0_s cn38xx; 469 struct cvmx_pko_mem_count0_s cn38xxp2; 470 struct cvmx_pko_mem_count0_s cn50xx; 471 struct cvmx_pko_mem_count0_s cn52xx; 472 struct cvmx_pko_mem_count0_s cn52xxp1; 473 struct cvmx_pko_mem_count0_s cn56xx; 474 struct cvmx_pko_mem_count0_s cn56xxp1; 475 struct cvmx_pko_mem_count0_s cn58xx; 476 struct cvmx_pko_mem_count0_s cn58xxp1; 477 struct cvmx_pko_mem_count0_s cn61xx; 478 struct cvmx_pko_mem_count0_s cn63xx; 479 struct cvmx_pko_mem_count0_s cn63xxp1; 480 struct cvmx_pko_mem_count0_s cn66xx; 481 struct cvmx_pko_mem_count0_s cn68xx; 482 struct cvmx_pko_mem_count0_s cn68xxp1; 483 struct cvmx_pko_mem_count0_s cnf71xx; 484}; 485typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t; 486 487/** 488 * cvmx_pko_mem_count1 489 * 490 * Notes: 491 * Total number of bytes seen by PKO, per port 492 * A write to this address will clear the entry whose index is specified as COUNT[5:0]. 493 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 494 * CSR read operations to this address can be performed. A read of any entry that has not been 495 * previously written is illegal and will result in unpredictable CSR read data. 496 */ 497union cvmx_pko_mem_count1 { 498 uint64_t u64; 499 struct cvmx_pko_mem_count1_s { 500#ifdef __BIG_ENDIAN_BITFIELD 501 uint64_t reserved_48_63 : 16; 502 uint64_t count : 48; /**< Total number of bytes seen by PKO */ 503#else 504 uint64_t count : 48; 505 uint64_t reserved_48_63 : 16; 506#endif 507 } s; 508 struct cvmx_pko_mem_count1_s cn30xx; 509 struct cvmx_pko_mem_count1_s cn31xx; 510 struct cvmx_pko_mem_count1_s cn38xx; 511 struct cvmx_pko_mem_count1_s cn38xxp2; 512 struct cvmx_pko_mem_count1_s cn50xx; 513 struct cvmx_pko_mem_count1_s cn52xx; 514 struct cvmx_pko_mem_count1_s cn52xxp1; 515 struct cvmx_pko_mem_count1_s cn56xx; 516 struct cvmx_pko_mem_count1_s cn56xxp1; 517 struct cvmx_pko_mem_count1_s cn58xx; 518 struct cvmx_pko_mem_count1_s cn58xxp1; 519 struct cvmx_pko_mem_count1_s cn61xx; 520 struct cvmx_pko_mem_count1_s cn63xx; 521 struct cvmx_pko_mem_count1_s cn63xxp1; 522 struct cvmx_pko_mem_count1_s cn66xx; 523 struct cvmx_pko_mem_count1_s cn68xx; 524 struct cvmx_pko_mem_count1_s cn68xxp1; 525 struct cvmx_pko_mem_count1_s cnf71xx; 526}; 527typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t; 528 529/** 530 * cvmx_pko_mem_debug0 531 * 532 * Notes: 533 * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0] 534 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 535 * CSR read operations to this address can be performed. 536 */ 537union cvmx_pko_mem_debug0 { 538 uint64_t u64; 539 struct cvmx_pko_mem_debug0_s { 540#ifdef __BIG_ENDIAN_BITFIELD 541 uint64_t fau : 28; /**< Fetch and add command words */ 542 uint64_t cmd : 14; /**< Command word */ 543 uint64_t segs : 6; /**< Number of segments/gather size */ 544 uint64_t size : 16; /**< Packet length in bytes */ 545#else 546 uint64_t size : 16; 547 uint64_t segs : 6; 548 uint64_t cmd : 14; 549 uint64_t fau : 28; 550#endif 551 } s; 552 struct cvmx_pko_mem_debug0_s cn30xx; 553 struct cvmx_pko_mem_debug0_s cn31xx; 554 struct cvmx_pko_mem_debug0_s cn38xx; 555 struct cvmx_pko_mem_debug0_s cn38xxp2; 556 struct cvmx_pko_mem_debug0_s cn50xx; 557 struct cvmx_pko_mem_debug0_s cn52xx; 558 struct cvmx_pko_mem_debug0_s cn52xxp1; 559 struct cvmx_pko_mem_debug0_s cn56xx; 560 struct cvmx_pko_mem_debug0_s cn56xxp1; 561 struct cvmx_pko_mem_debug0_s cn58xx; 562 struct cvmx_pko_mem_debug0_s cn58xxp1; 563 struct cvmx_pko_mem_debug0_s cn61xx; 564 struct cvmx_pko_mem_debug0_s cn63xx; 565 struct cvmx_pko_mem_debug0_s cn63xxp1; 566 struct cvmx_pko_mem_debug0_s cn66xx; 567 struct cvmx_pko_mem_debug0_s cn68xx; 568 struct cvmx_pko_mem_debug0_s cn68xxp1; 569 struct cvmx_pko_mem_debug0_s cnf71xx; 570}; 571typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t; 572 573/** 574 * cvmx_pko_mem_debug1 575 * 576 * Notes: 577 * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0] 578 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 579 * CSR read operations to this address can be performed. 580 */ 581union cvmx_pko_mem_debug1 { 582 uint64_t u64; 583 struct cvmx_pko_mem_debug1_s { 584#ifdef __BIG_ENDIAN_BITFIELD 585 uint64_t i : 1; /**< "I" value used for free operation */ 586 uint64_t back : 4; /**< Back value used for free operation */ 587 uint64_t pool : 3; /**< Pool value used for free operation */ 588 uint64_t size : 16; /**< Size in bytes */ 589 uint64_t ptr : 40; /**< Data pointer */ 590#else 591 uint64_t ptr : 40; 592 uint64_t size : 16; 593 uint64_t pool : 3; 594 uint64_t back : 4; 595 uint64_t i : 1; 596#endif 597 } s; 598 struct cvmx_pko_mem_debug1_s cn30xx; 599 struct cvmx_pko_mem_debug1_s cn31xx; 600 struct cvmx_pko_mem_debug1_s cn38xx; 601 struct cvmx_pko_mem_debug1_s cn38xxp2; 602 struct cvmx_pko_mem_debug1_s cn50xx; 603 struct cvmx_pko_mem_debug1_s cn52xx; 604 struct cvmx_pko_mem_debug1_s cn52xxp1; 605 struct cvmx_pko_mem_debug1_s cn56xx; 606 struct cvmx_pko_mem_debug1_s cn56xxp1; 607 struct cvmx_pko_mem_debug1_s cn58xx; 608 struct cvmx_pko_mem_debug1_s cn58xxp1; 609 struct cvmx_pko_mem_debug1_s cn61xx; 610 struct cvmx_pko_mem_debug1_s cn63xx; 611 struct cvmx_pko_mem_debug1_s cn63xxp1; 612 struct cvmx_pko_mem_debug1_s cn66xx; 613 struct cvmx_pko_mem_debug1_s cn68xx; 614 struct cvmx_pko_mem_debug1_s cn68xxp1; 615 struct cvmx_pko_mem_debug1_s cnf71xx; 616}; 617typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t; 618 619/** 620 * cvmx_pko_mem_debug10 621 * 622 * Notes: 623 * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2 624 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 625 * CSR read operations to this address can be performed. 626 */ 627union cvmx_pko_mem_debug10 { 628 uint64_t u64; 629 struct cvmx_pko_mem_debug10_s { 630#ifdef __BIG_ENDIAN_BITFIELD 631 uint64_t reserved_0_63 : 64; 632#else 633 uint64_t reserved_0_63 : 64; 634#endif 635 } s; 636 struct cvmx_pko_mem_debug10_cn30xx { 637#ifdef __BIG_ENDIAN_BITFIELD 638 uint64_t fau : 28; /**< Fetch and add command words */ 639 uint64_t cmd : 14; /**< Command word */ 640 uint64_t segs : 6; /**< Number of segments/gather size */ 641 uint64_t size : 16; /**< Packet length in bytes */ 642#else 643 uint64_t size : 16; 644 uint64_t segs : 6; 645 uint64_t cmd : 14; 646 uint64_t fau : 28; 647#endif 648 } cn30xx; 649 struct cvmx_pko_mem_debug10_cn30xx cn31xx; 650 struct cvmx_pko_mem_debug10_cn30xx cn38xx; 651 struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; 652 struct cvmx_pko_mem_debug10_cn50xx { 653#ifdef __BIG_ENDIAN_BITFIELD 654 uint64_t reserved_49_63 : 15; 655 uint64_t ptrs1 : 17; /**< Internal state */ 656 uint64_t reserved_17_31 : 15; 657 uint64_t ptrs2 : 17; /**< Internal state */ 658#else 659 uint64_t ptrs2 : 17; 660 uint64_t reserved_17_31 : 15; 661 uint64_t ptrs1 : 17; 662 uint64_t reserved_49_63 : 15; 663#endif 664 } cn50xx; 665 struct cvmx_pko_mem_debug10_cn50xx cn52xx; 666 struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; 667 struct cvmx_pko_mem_debug10_cn50xx cn56xx; 668 struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; 669 struct cvmx_pko_mem_debug10_cn50xx cn58xx; 670 struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; 671 struct cvmx_pko_mem_debug10_cn50xx cn61xx; 672 struct cvmx_pko_mem_debug10_cn50xx cn63xx; 673 struct cvmx_pko_mem_debug10_cn50xx cn63xxp1; 674 struct cvmx_pko_mem_debug10_cn50xx cn66xx; 675 struct cvmx_pko_mem_debug10_cn50xx cn68xx; 676 struct cvmx_pko_mem_debug10_cn50xx cn68xxp1; 677 struct cvmx_pko_mem_debug10_cn50xx cnf71xx; 678}; 679typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t; 680 681/** 682 * cvmx_pko_mem_debug11 683 * 684 * Notes: 685 * Internal per-port state intended for debug use only - pko.out.sta.state[22:0] 686 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 687 * CSR read operations to this address can be performed. 688 */ 689union cvmx_pko_mem_debug11 { 690 uint64_t u64; 691 struct cvmx_pko_mem_debug11_s { 692#ifdef __BIG_ENDIAN_BITFIELD 693 uint64_t i : 1; /**< "I" value used for free operation */ 694 uint64_t back : 4; /**< Back value used for free operation */ 695 uint64_t pool : 3; /**< Pool value used for free operation */ 696 uint64_t size : 16; /**< Size in bytes */ 697 uint64_t reserved_0_39 : 40; 698#else 699 uint64_t reserved_0_39 : 40; 700 uint64_t size : 16; 701 uint64_t pool : 3; 702 uint64_t back : 4; 703 uint64_t i : 1; 704#endif 705 } s; 706 struct cvmx_pko_mem_debug11_cn30xx { 707#ifdef __BIG_ENDIAN_BITFIELD 708 uint64_t i : 1; /**< "I" value used for free operation */ 709 uint64_t back : 4; /**< Back value used for free operation */ 710 uint64_t pool : 3; /**< Pool value used for free operation */ 711 uint64_t size : 16; /**< Size in bytes */ 712 uint64_t ptr : 40; /**< Data pointer */ 713#else 714 uint64_t ptr : 40; 715 uint64_t size : 16; 716 uint64_t pool : 3; 717 uint64_t back : 4; 718 uint64_t i : 1; 719#endif 720 } cn30xx; 721 struct cvmx_pko_mem_debug11_cn30xx cn31xx; 722 struct cvmx_pko_mem_debug11_cn30xx cn38xx; 723 struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; 724 struct cvmx_pko_mem_debug11_cn50xx { 725#ifdef __BIG_ENDIAN_BITFIELD 726 uint64_t reserved_23_63 : 41; 727 uint64_t maj : 1; /**< Internal state */ 728 uint64_t uid : 3; /**< Internal state */ 729 uint64_t sop : 1; /**< Internal state */ 730 uint64_t len : 1; /**< Internal state */ 731 uint64_t chk : 1; /**< Internal state */ 732 uint64_t cnt : 13; /**< Internal state */ 733 uint64_t mod : 3; /**< Internal state */ 734#else 735 uint64_t mod : 3; 736 uint64_t cnt : 13; 737 uint64_t chk : 1; 738 uint64_t len : 1; 739 uint64_t sop : 1; 740 uint64_t uid : 3; 741 uint64_t maj : 1; 742 uint64_t reserved_23_63 : 41; 743#endif 744 } cn50xx; 745 struct cvmx_pko_mem_debug11_cn50xx cn52xx; 746 struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; 747 struct cvmx_pko_mem_debug11_cn50xx cn56xx; 748 struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; 749 struct cvmx_pko_mem_debug11_cn50xx cn58xx; 750 struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; 751 struct cvmx_pko_mem_debug11_cn50xx cn61xx; 752 struct cvmx_pko_mem_debug11_cn50xx cn63xx; 753 struct cvmx_pko_mem_debug11_cn50xx cn63xxp1; 754 struct cvmx_pko_mem_debug11_cn50xx cn66xx; 755 struct cvmx_pko_mem_debug11_cn50xx cn68xx; 756 struct cvmx_pko_mem_debug11_cn50xx cn68xxp1; 757 struct cvmx_pko_mem_debug11_cn50xx cnf71xx; 758}; 759typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t; 760 761/** 762 * cvmx_pko_mem_debug12 763 * 764 * Notes: 765 * Internal per-port state intended for debug use only - pko.out.ctl.cmnd[63:0] 766 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 767 * CSR read operations to this address can be performed. 768 */ 769union cvmx_pko_mem_debug12 { 770 uint64_t u64; 771 struct cvmx_pko_mem_debug12_s { 772#ifdef __BIG_ENDIAN_BITFIELD 773 uint64_t reserved_0_63 : 64; 774#else 775 uint64_t reserved_0_63 : 64; 776#endif 777 } s; 778 struct cvmx_pko_mem_debug12_cn30xx { 779#ifdef __BIG_ENDIAN_BITFIELD 780 uint64_t data : 64; /**< WorkQ data or Store0 pointer */ 781#else 782 uint64_t data : 64; 783#endif 784 } cn30xx; 785 struct cvmx_pko_mem_debug12_cn30xx cn31xx; 786 struct cvmx_pko_mem_debug12_cn30xx cn38xx; 787 struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; 788 struct cvmx_pko_mem_debug12_cn50xx { 789#ifdef __BIG_ENDIAN_BITFIELD 790 uint64_t fau : 28; /**< Fetch and add command words */ 791 uint64_t cmd : 14; /**< Command word */ 792 uint64_t segs : 6; /**< Number of segments/gather size */ 793 uint64_t size : 16; /**< Packet length in bytes */ 794#else 795 uint64_t size : 16; 796 uint64_t segs : 6; 797 uint64_t cmd : 14; 798 uint64_t fau : 28; 799#endif 800 } cn50xx; 801 struct cvmx_pko_mem_debug12_cn50xx cn52xx; 802 struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; 803 struct cvmx_pko_mem_debug12_cn50xx cn56xx; 804 struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; 805 struct cvmx_pko_mem_debug12_cn50xx cn58xx; 806 struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; 807 struct cvmx_pko_mem_debug12_cn50xx cn61xx; 808 struct cvmx_pko_mem_debug12_cn50xx cn63xx; 809 struct cvmx_pko_mem_debug12_cn50xx cn63xxp1; 810 struct cvmx_pko_mem_debug12_cn50xx cn66xx; 811 struct cvmx_pko_mem_debug12_cn68xx { 812#ifdef __BIG_ENDIAN_BITFIELD 813 uint64_t state : 64; /**< Internal state */ 814#else 815 uint64_t state : 64; 816#endif 817 } cn68xx; 818 struct cvmx_pko_mem_debug12_cn68xx cn68xxp1; 819 struct cvmx_pko_mem_debug12_cn50xx cnf71xx; 820}; 821typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t; 822 823/** 824 * cvmx_pko_mem_debug13 825 * 826 * Notes: 827 * Internal per-port state intended for debug use only - pko.out.ctl.head[63:0] 828 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 829 * CSR read operations to this address can be performed. 830 */ 831union cvmx_pko_mem_debug13 { 832 uint64_t u64; 833 struct cvmx_pko_mem_debug13_s { 834#ifdef __BIG_ENDIAN_BITFIELD 835 uint64_t reserved_0_63 : 64; 836#else 837 uint64_t reserved_0_63 : 64; 838#endif 839 } s; 840 struct cvmx_pko_mem_debug13_cn30xx { 841#ifdef __BIG_ENDIAN_BITFIELD 842 uint64_t reserved_51_63 : 13; 843 uint64_t widx : 17; /**< PDB widx */ 844 uint64_t ridx2 : 17; /**< PDB ridx2 */ 845 uint64_t widx2 : 17; /**< PDB widx2 */ 846#else 847 uint64_t widx2 : 17; 848 uint64_t ridx2 : 17; 849 uint64_t widx : 17; 850 uint64_t reserved_51_63 : 13; 851#endif 852 } cn30xx; 853 struct cvmx_pko_mem_debug13_cn30xx cn31xx; 854 struct cvmx_pko_mem_debug13_cn30xx cn38xx; 855 struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; 856 struct cvmx_pko_mem_debug13_cn50xx { 857#ifdef __BIG_ENDIAN_BITFIELD 858 uint64_t i : 1; /**< "I" value used for free operation */ 859 uint64_t back : 4; /**< Back value used for free operation */ 860 uint64_t pool : 3; /**< Pool value used for free operation */ 861 uint64_t size : 16; /**< Size in bytes */ 862 uint64_t ptr : 40; /**< Data pointer */ 863#else 864 uint64_t ptr : 40; 865 uint64_t size : 16; 866 uint64_t pool : 3; 867 uint64_t back : 4; 868 uint64_t i : 1; 869#endif 870 } cn50xx; 871 struct cvmx_pko_mem_debug13_cn50xx cn52xx; 872 struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; 873 struct cvmx_pko_mem_debug13_cn50xx cn56xx; 874 struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; 875 struct cvmx_pko_mem_debug13_cn50xx cn58xx; 876 struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; 877 struct cvmx_pko_mem_debug13_cn50xx cn61xx; 878 struct cvmx_pko_mem_debug13_cn50xx cn63xx; 879 struct cvmx_pko_mem_debug13_cn50xx cn63xxp1; 880 struct cvmx_pko_mem_debug13_cn50xx cn66xx; 881 struct cvmx_pko_mem_debug13_cn68xx { 882#ifdef __BIG_ENDIAN_BITFIELD 883 uint64_t state : 64; /**< Internal state */ 884#else 885 uint64_t state : 64; 886#endif 887 } cn68xx; 888 struct cvmx_pko_mem_debug13_cn68xx cn68xxp1; 889 struct cvmx_pko_mem_debug13_cn50xx cnf71xx; 890}; 891typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t; 892 893/** 894 * cvmx_pko_mem_debug14 895 * 896 * Notes: 897 * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0] 898 * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 899 * CSR read operations to this address can be performed. 900 */ 901union cvmx_pko_mem_debug14 { 902 uint64_t u64; 903 struct cvmx_pko_mem_debug14_s { 904#ifdef __BIG_ENDIAN_BITFIELD 905 uint64_t reserved_0_63 : 64; 906#else 907 uint64_t reserved_0_63 : 64; 908#endif 909 } s; 910 struct cvmx_pko_mem_debug14_cn30xx { 911#ifdef __BIG_ENDIAN_BITFIELD 912 uint64_t reserved_17_63 : 47; 913 uint64_t ridx : 17; /**< PDB ridx */ 914#else 915 uint64_t ridx : 17; 916 uint64_t reserved_17_63 : 47; 917#endif 918 } cn30xx; 919 struct cvmx_pko_mem_debug14_cn30xx cn31xx; 920 struct cvmx_pko_mem_debug14_cn30xx cn38xx; 921 struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; 922 struct cvmx_pko_mem_debug14_cn52xx { 923#ifdef __BIG_ENDIAN_BITFIELD 924 uint64_t data : 64; /**< Command words */ 925#else 926 uint64_t data : 64; 927#endif 928 } cn52xx; 929 struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; 930 struct cvmx_pko_mem_debug14_cn52xx cn56xx; 931 struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; 932 struct cvmx_pko_mem_debug14_cn52xx cn61xx; 933 struct cvmx_pko_mem_debug14_cn52xx cn63xx; 934 struct cvmx_pko_mem_debug14_cn52xx cn63xxp1; 935 struct cvmx_pko_mem_debug14_cn52xx cn66xx; 936 struct cvmx_pko_mem_debug14_cn52xx cnf71xx; 937}; 938typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t; 939 940/** 941 * cvmx_pko_mem_debug2 942 * 943 * Notes: 944 * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0] 945 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 946 * CSR read operations to this address can be performed. 947 */ 948union cvmx_pko_mem_debug2 { 949 uint64_t u64; 950 struct cvmx_pko_mem_debug2_s { 951#ifdef __BIG_ENDIAN_BITFIELD 952 uint64_t i : 1; /**< "I" value used for free operation */ 953 uint64_t back : 4; /**< Back value used for free operation */ 954 uint64_t pool : 3; /**< Pool value used for free operation */ 955 uint64_t size : 16; /**< Size in bytes */ 956 uint64_t ptr : 40; /**< Data pointer */ 957#else 958 uint64_t ptr : 40; 959 uint64_t size : 16; 960 uint64_t pool : 3; 961 uint64_t back : 4; 962 uint64_t i : 1; 963#endif 964 } s; 965 struct cvmx_pko_mem_debug2_s cn30xx; 966 struct cvmx_pko_mem_debug2_s cn31xx; 967 struct cvmx_pko_mem_debug2_s cn38xx; 968 struct cvmx_pko_mem_debug2_s cn38xxp2; 969 struct cvmx_pko_mem_debug2_s cn50xx; 970 struct cvmx_pko_mem_debug2_s cn52xx; 971 struct cvmx_pko_mem_debug2_s cn52xxp1; 972 struct cvmx_pko_mem_debug2_s cn56xx; 973 struct cvmx_pko_mem_debug2_s cn56xxp1; 974 struct cvmx_pko_mem_debug2_s cn58xx; 975 struct cvmx_pko_mem_debug2_s cn58xxp1; 976 struct cvmx_pko_mem_debug2_s cn61xx; 977 struct cvmx_pko_mem_debug2_s cn63xx; 978 struct cvmx_pko_mem_debug2_s cn63xxp1; 979 struct cvmx_pko_mem_debug2_s cn66xx; 980 struct cvmx_pko_mem_debug2_s cn68xx; 981 struct cvmx_pko_mem_debug2_s cn68xxp1; 982 struct cvmx_pko_mem_debug2_s cnf71xx; 983}; 984typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t; 985 986/** 987 * cvmx_pko_mem_debug3 988 * 989 * Notes: 990 * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0] 991 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 992 * CSR read operations to this address can be performed. 993 */ 994union cvmx_pko_mem_debug3 { 995 uint64_t u64; 996 struct cvmx_pko_mem_debug3_s { 997#ifdef __BIG_ENDIAN_BITFIELD 998 uint64_t reserved_0_63 : 64; 999#else 1000 uint64_t reserved_0_63 : 64; 1001#endif 1002 } s; 1003 struct cvmx_pko_mem_debug3_cn30xx { 1004#ifdef __BIG_ENDIAN_BITFIELD 1005 uint64_t i : 1; /**< "I" value used for free operation */ 1006 uint64_t back : 4; /**< Back value used for free operation */ 1007 uint64_t pool : 3; /**< Pool value used for free operation */ 1008 uint64_t size : 16; /**< Size in bytes */ 1009 uint64_t ptr : 40; /**< Data pointer */ 1010#else 1011 uint64_t ptr : 40; 1012 uint64_t size : 16; 1013 uint64_t pool : 3; 1014 uint64_t back : 4; 1015 uint64_t i : 1; 1016#endif 1017 } cn30xx; 1018 struct cvmx_pko_mem_debug3_cn30xx cn31xx; 1019 struct cvmx_pko_mem_debug3_cn30xx cn38xx; 1020 struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; 1021 struct cvmx_pko_mem_debug3_cn50xx { 1022#ifdef __BIG_ENDIAN_BITFIELD 1023 uint64_t data : 64; /**< WorkQ data or Store0 pointer */ 1024#else 1025 uint64_t data : 64; 1026#endif 1027 } cn50xx; 1028 struct cvmx_pko_mem_debug3_cn50xx cn52xx; 1029 struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; 1030 struct cvmx_pko_mem_debug3_cn50xx cn56xx; 1031 struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; 1032 struct cvmx_pko_mem_debug3_cn50xx cn58xx; 1033 struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; 1034 struct cvmx_pko_mem_debug3_cn50xx cn61xx; 1035 struct cvmx_pko_mem_debug3_cn50xx cn63xx; 1036 struct cvmx_pko_mem_debug3_cn50xx cn63xxp1; 1037 struct cvmx_pko_mem_debug3_cn50xx cn66xx; 1038 struct cvmx_pko_mem_debug3_cn50xx cn68xx; 1039 struct cvmx_pko_mem_debug3_cn50xx cn68xxp1; 1040 struct cvmx_pko_mem_debug3_cn50xx cnf71xx; 1041}; 1042typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t; 1043 1044/** 1045 * cvmx_pko_mem_debug4 1046 * 1047 * Notes: 1048 * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0] 1049 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1050 * CSR read operations to this address can be performed. 1051 */ 1052union cvmx_pko_mem_debug4 { 1053 uint64_t u64; 1054 struct cvmx_pko_mem_debug4_s { 1055#ifdef __BIG_ENDIAN_BITFIELD 1056 uint64_t reserved_0_63 : 64; 1057#else 1058 uint64_t reserved_0_63 : 64; 1059#endif 1060 } s; 1061 struct cvmx_pko_mem_debug4_cn30xx { 1062#ifdef __BIG_ENDIAN_BITFIELD 1063 uint64_t data : 64; /**< WorkQ data or Store0 pointer */ 1064#else 1065 uint64_t data : 64; 1066#endif 1067 } cn30xx; 1068 struct cvmx_pko_mem_debug4_cn30xx cn31xx; 1069 struct cvmx_pko_mem_debug4_cn30xx cn38xx; 1070 struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; 1071 struct cvmx_pko_mem_debug4_cn50xx { 1072#ifdef __BIG_ENDIAN_BITFIELD 1073 uint64_t cmnd_segs : 3; /**< Internal state */ 1074 uint64_t cmnd_siz : 16; /**< Internal state */ 1075 uint64_t cmnd_off : 6; /**< Internal state */ 1076 uint64_t uid : 3; /**< Internal state */ 1077 uint64_t dread_sop : 1; /**< Internal state */ 1078 uint64_t init_dwrite : 1; /**< Internal state */ 1079 uint64_t chk_once : 1; /**< Internal state */ 1080 uint64_t chk_mode : 1; /**< Internal state */ 1081 uint64_t active : 1; /**< Internal state */ 1082 uint64_t static_p : 1; /**< Internal state */ 1083 uint64_t qos : 3; /**< Internal state */ 1084 uint64_t qcb_ridx : 5; /**< Internal state */ 1085 uint64_t qid_off_max : 4; /**< Internal state */ 1086 uint64_t qid_off : 4; /**< Internal state */ 1087 uint64_t qid_base : 8; /**< Internal state */ 1088 uint64_t wait : 1; /**< Internal state */ 1089 uint64_t minor : 2; /**< Internal state */ 1090 uint64_t major : 3; /**< Internal state */ 1091#else 1092 uint64_t major : 3; 1093 uint64_t minor : 2; 1094 uint64_t wait : 1; 1095 uint64_t qid_base : 8; 1096 uint64_t qid_off : 4; 1097 uint64_t qid_off_max : 4; 1098 uint64_t qcb_ridx : 5; 1099 uint64_t qos : 3; 1100 uint64_t static_p : 1; 1101 uint64_t active : 1; 1102 uint64_t chk_mode : 1; 1103 uint64_t chk_once : 1; 1104 uint64_t init_dwrite : 1; 1105 uint64_t dread_sop : 1; 1106 uint64_t uid : 3; 1107 uint64_t cmnd_off : 6; 1108 uint64_t cmnd_siz : 16; 1109 uint64_t cmnd_segs : 3; 1110#endif 1111 } cn50xx; 1112 struct cvmx_pko_mem_debug4_cn52xx { 1113#ifdef __BIG_ENDIAN_BITFIELD 1114 uint64_t curr_siz : 8; /**< Internal state */ 1115 uint64_t curr_off : 16; /**< Internal state */ 1116 uint64_t cmnd_segs : 6; /**< Internal state */ 1117 uint64_t cmnd_siz : 16; /**< Internal state */ 1118 uint64_t cmnd_off : 6; /**< Internal state */ 1119 uint64_t uid : 2; /**< Internal state */ 1120 uint64_t dread_sop : 1; /**< Internal state */ 1121 uint64_t init_dwrite : 1; /**< Internal state */ 1122 uint64_t chk_once : 1; /**< Internal state */ 1123 uint64_t chk_mode : 1; /**< Internal state */ 1124 uint64_t wait : 1; /**< Internal state */ 1125 uint64_t minor : 2; /**< Internal state */ 1126 uint64_t major : 3; /**< Internal state */ 1127#else 1128 uint64_t major : 3; 1129 uint64_t minor : 2; 1130 uint64_t wait : 1; 1131 uint64_t chk_mode : 1; 1132 uint64_t chk_once : 1; 1133 uint64_t init_dwrite : 1; 1134 uint64_t dread_sop : 1; 1135 uint64_t uid : 2; 1136 uint64_t cmnd_off : 6; 1137 uint64_t cmnd_siz : 16; 1138 uint64_t cmnd_segs : 6; 1139 uint64_t curr_off : 16; 1140 uint64_t curr_siz : 8; 1141#endif 1142 } cn52xx; 1143 struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; 1144 struct cvmx_pko_mem_debug4_cn52xx cn56xx; 1145 struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; 1146 struct cvmx_pko_mem_debug4_cn50xx cn58xx; 1147 struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; 1148 struct cvmx_pko_mem_debug4_cn52xx cn61xx; 1149 struct cvmx_pko_mem_debug4_cn52xx cn63xx; 1150 struct cvmx_pko_mem_debug4_cn52xx cn63xxp1; 1151 struct cvmx_pko_mem_debug4_cn52xx cn66xx; 1152 struct cvmx_pko_mem_debug4_cn52xx cn68xx; 1153 struct cvmx_pko_mem_debug4_cn52xx cn68xxp1; 1154 struct cvmx_pko_mem_debug4_cn52xx cnf71xx; 1155}; 1156typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t; 1157 1158/** 1159 * cvmx_pko_mem_debug5 1160 * 1161 * Notes: 1162 * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64] 1163 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1164 * CSR read operations to this address can be performed. 1165 */ 1166union cvmx_pko_mem_debug5 { 1167 uint64_t u64; 1168 struct cvmx_pko_mem_debug5_s { 1169#ifdef __BIG_ENDIAN_BITFIELD 1170 uint64_t reserved_0_63 : 64; 1171#else 1172 uint64_t reserved_0_63 : 64; 1173#endif 1174 } s; 1175 struct cvmx_pko_mem_debug5_cn30xx { 1176#ifdef __BIG_ENDIAN_BITFIELD 1177 uint64_t dwri_mod : 1; /**< Dwrite mod */ 1178 uint64_t dwri_sop : 1; /**< Dwrite sop needed */ 1179 uint64_t dwri_len : 1; /**< Dwrite len */ 1180 uint64_t dwri_cnt : 13; /**< Dwrite count */ 1181 uint64_t cmnd_siz : 16; /**< Copy of cmnd.size */ 1182 uint64_t uid : 1; /**< UID */ 1183 uint64_t xfer_wor : 1; /**< Transfer work needed */ 1184 uint64_t xfer_dwr : 1; /**< Transfer dwrite needed */ 1185 uint64_t cbuf_fre : 1; /**< Cbuf needs free */ 1186 uint64_t reserved_27_27 : 1; 1187 uint64_t chk_mode : 1; /**< Checksum mode */ 1188 uint64_t active : 1; /**< Port is active */ 1189 uint64_t qos : 3; /**< Current QOS round */ 1190 uint64_t qcb_ridx : 5; /**< Buffer read index for QCB */ 1191 uint64_t qid_off : 3; /**< Offset to be added to QID_BASE for current queue */ 1192 uint64_t qid_base : 7; /**< Absolute QID of the queue array base = &QUEUES[0] */ 1193 uint64_t wait : 1; /**< State wait when set */ 1194 uint64_t minor : 2; /**< State minor code */ 1195 uint64_t major : 4; /**< State major code */ 1196#else 1197 uint64_t major : 4; 1198 uint64_t minor : 2; 1199 uint64_t wait : 1; 1200 uint64_t qid_base : 7; 1201 uint64_t qid_off : 3; 1202 uint64_t qcb_ridx : 5; 1203 uint64_t qos : 3; 1204 uint64_t active : 1; 1205 uint64_t chk_mode : 1; 1206 uint64_t reserved_27_27 : 1; 1207 uint64_t cbuf_fre : 1; 1208 uint64_t xfer_dwr : 1; 1209 uint64_t xfer_wor : 1; 1210 uint64_t uid : 1; 1211 uint64_t cmnd_siz : 16; 1212 uint64_t dwri_cnt : 13; 1213 uint64_t dwri_len : 1; 1214 uint64_t dwri_sop : 1; 1215 uint64_t dwri_mod : 1; 1216#endif 1217 } cn30xx; 1218 struct cvmx_pko_mem_debug5_cn30xx cn31xx; 1219 struct cvmx_pko_mem_debug5_cn30xx cn38xx; 1220 struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; 1221 struct cvmx_pko_mem_debug5_cn50xx { 1222#ifdef __BIG_ENDIAN_BITFIELD 1223 uint64_t curr_ptr : 29; /**< Internal state */ 1224 uint64_t curr_siz : 16; /**< Internal state */ 1225 uint64_t curr_off : 16; /**< Internal state */ 1226 uint64_t cmnd_segs : 3; /**< Internal state */ 1227#else 1228 uint64_t cmnd_segs : 3; 1229 uint64_t curr_off : 16; 1230 uint64_t curr_siz : 16; 1231 uint64_t curr_ptr : 29; 1232#endif 1233 } cn50xx; 1234 struct cvmx_pko_mem_debug5_cn52xx { 1235#ifdef __BIG_ENDIAN_BITFIELD 1236 uint64_t reserved_54_63 : 10; 1237 uint64_t nxt_inflt : 6; /**< Internal state */ 1238 uint64_t curr_ptr : 40; /**< Internal state */ 1239 uint64_t curr_siz : 8; /**< Internal state */ 1240#else 1241 uint64_t curr_siz : 8; 1242 uint64_t curr_ptr : 40; 1243 uint64_t nxt_inflt : 6; 1244 uint64_t reserved_54_63 : 10; 1245#endif 1246 } cn52xx; 1247 struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; 1248 struct cvmx_pko_mem_debug5_cn52xx cn56xx; 1249 struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; 1250 struct cvmx_pko_mem_debug5_cn50xx cn58xx; 1251 struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; 1252 struct cvmx_pko_mem_debug5_cn61xx { 1253#ifdef __BIG_ENDIAN_BITFIELD 1254 uint64_t reserved_56_63 : 8; 1255 uint64_t ptp : 1; /**< Internal state */ 1256 uint64_t major_3 : 1; /**< Internal state */ 1257 uint64_t nxt_inflt : 6; /**< Internal state */ 1258 uint64_t curr_ptr : 40; /**< Internal state */ 1259 uint64_t curr_siz : 8; /**< Internal state */ 1260#else 1261 uint64_t curr_siz : 8; 1262 uint64_t curr_ptr : 40; 1263 uint64_t nxt_inflt : 6; 1264 uint64_t major_3 : 1; 1265 uint64_t ptp : 1; 1266 uint64_t reserved_56_63 : 8; 1267#endif 1268 } cn61xx; 1269 struct cvmx_pko_mem_debug5_cn61xx cn63xx; 1270 struct cvmx_pko_mem_debug5_cn61xx cn63xxp1; 1271 struct cvmx_pko_mem_debug5_cn61xx cn66xx; 1272 struct cvmx_pko_mem_debug5_cn68xx { 1273#ifdef __BIG_ENDIAN_BITFIELD 1274 uint64_t reserved_57_63 : 7; 1275 uint64_t uid_2 : 1; /**< Internal state */ 1276 uint64_t ptp : 1; /**< Internal state */ 1277 uint64_t major_3 : 1; /**< Internal state */ 1278 uint64_t nxt_inflt : 6; /**< Internal state */ 1279 uint64_t curr_ptr : 40; /**< Internal state */ 1280 uint64_t curr_siz : 8; /**< Internal state */ 1281#else 1282 uint64_t curr_siz : 8; 1283 uint64_t curr_ptr : 40; 1284 uint64_t nxt_inflt : 6; 1285 uint64_t major_3 : 1; 1286 uint64_t ptp : 1; 1287 uint64_t uid_2 : 1; 1288 uint64_t reserved_57_63 : 7; 1289#endif 1290 } cn68xx; 1291 struct cvmx_pko_mem_debug5_cn68xx cn68xxp1; 1292 struct cvmx_pko_mem_debug5_cn61xx cnf71xx; 1293}; 1294typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t; 1295 1296/** 1297 * cvmx_pko_mem_debug6 1298 * 1299 * Notes: 1300 * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0] 1301 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1302 * CSR read operations to this address can be performed. 1303 */ 1304union cvmx_pko_mem_debug6 { 1305 uint64_t u64; 1306 struct cvmx_pko_mem_debug6_s { 1307#ifdef __BIG_ENDIAN_BITFIELD 1308 uint64_t reserved_37_63 : 27; 1309 uint64_t qid_offres : 4; /**< Internal state */ 1310 uint64_t qid_offths : 4; /**< Internal state */ 1311 uint64_t preempter : 1; /**< Internal state */ 1312 uint64_t preemptee : 1; /**< Internal state */ 1313 uint64_t preempted : 1; /**< Internal state */ 1314 uint64_t active : 1; /**< Internal state */ 1315 uint64_t statc : 1; /**< Internal state */ 1316 uint64_t qos : 3; /**< Internal state */ 1317 uint64_t qcb_ridx : 5; /**< Internal state */ 1318 uint64_t qid_offmax : 4; /**< Internal state */ 1319 uint64_t reserved_0_11 : 12; 1320#else 1321 uint64_t reserved_0_11 : 12; 1322 uint64_t qid_offmax : 4; 1323 uint64_t qcb_ridx : 5; 1324 uint64_t qos : 3; 1325 uint64_t statc : 1; 1326 uint64_t active : 1; 1327 uint64_t preempted : 1; 1328 uint64_t preemptee : 1; 1329 uint64_t preempter : 1; 1330 uint64_t qid_offths : 4; 1331 uint64_t qid_offres : 4; 1332 uint64_t reserved_37_63 : 27; 1333#endif 1334 } s; 1335 struct cvmx_pko_mem_debug6_cn30xx { 1336#ifdef __BIG_ENDIAN_BITFIELD 1337 uint64_t reserved_11_63 : 53; 1338 uint64_t qid_offm : 3; /**< Qid offset max */ 1339 uint64_t static_p : 1; /**< Static port when set */ 1340 uint64_t work_min : 3; /**< Work minor */ 1341 uint64_t dwri_chk : 1; /**< Dwrite checksum mode */ 1342 uint64_t dwri_uid : 1; /**< Dwrite UID */ 1343 uint64_t dwri_mod : 2; /**< Dwrite mod */ 1344#else 1345 uint64_t dwri_mod : 2; 1346 uint64_t dwri_uid : 1; 1347 uint64_t dwri_chk : 1; 1348 uint64_t work_min : 3; 1349 uint64_t static_p : 1; 1350 uint64_t qid_offm : 3; 1351 uint64_t reserved_11_63 : 53; 1352#endif 1353 } cn30xx; 1354 struct cvmx_pko_mem_debug6_cn30xx cn31xx; 1355 struct cvmx_pko_mem_debug6_cn30xx cn38xx; 1356 struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; 1357 struct cvmx_pko_mem_debug6_cn50xx { 1358#ifdef __BIG_ENDIAN_BITFIELD 1359 uint64_t reserved_11_63 : 53; 1360 uint64_t curr_ptr : 11; /**< Internal state */ 1361#else 1362 uint64_t curr_ptr : 11; 1363 uint64_t reserved_11_63 : 53; 1364#endif 1365 } cn50xx; 1366 struct cvmx_pko_mem_debug6_cn52xx { 1367#ifdef __BIG_ENDIAN_BITFIELD 1368 uint64_t reserved_37_63 : 27; 1369 uint64_t qid_offres : 4; /**< Internal state */ 1370 uint64_t qid_offths : 4; /**< Internal state */ 1371 uint64_t preempter : 1; /**< Internal state */ 1372 uint64_t preemptee : 1; /**< Internal state */ 1373 uint64_t preempted : 1; /**< Internal state */ 1374 uint64_t active : 1; /**< Internal state */ 1375 uint64_t statc : 1; /**< Internal state */ 1376 uint64_t qos : 3; /**< Internal state */ 1377 uint64_t qcb_ridx : 5; /**< Internal state */ 1378 uint64_t qid_offmax : 4; /**< Internal state */ 1379 uint64_t qid_off : 4; /**< Internal state */ 1380 uint64_t qid_base : 8; /**< Internal state */ 1381#else 1382 uint64_t qid_base : 8; 1383 uint64_t qid_off : 4; 1384 uint64_t qid_offmax : 4; 1385 uint64_t qcb_ridx : 5; 1386 uint64_t qos : 3; 1387 uint64_t statc : 1; 1388 uint64_t active : 1; 1389 uint64_t preempted : 1; 1390 uint64_t preemptee : 1; 1391 uint64_t preempter : 1; 1392 uint64_t qid_offths : 4; 1393 uint64_t qid_offres : 4; 1394 uint64_t reserved_37_63 : 27; 1395#endif 1396 } cn52xx; 1397 struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; 1398 struct cvmx_pko_mem_debug6_cn52xx cn56xx; 1399 struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; 1400 struct cvmx_pko_mem_debug6_cn50xx cn58xx; 1401 struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; 1402 struct cvmx_pko_mem_debug6_cn52xx cn61xx; 1403 struct cvmx_pko_mem_debug6_cn52xx cn63xx; 1404 struct cvmx_pko_mem_debug6_cn52xx cn63xxp1; 1405 struct cvmx_pko_mem_debug6_cn52xx cn66xx; 1406 struct cvmx_pko_mem_debug6_cn52xx cn68xx; 1407 struct cvmx_pko_mem_debug6_cn52xx cn68xxp1; 1408 struct cvmx_pko_mem_debug6_cn52xx cnf71xx; 1409}; 1410typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t; 1411 1412/** 1413 * cvmx_pko_mem_debug7 1414 * 1415 * Notes: 1416 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0] 1417 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1418 * CSR read operations to this address can be performed. 1419 */ 1420union cvmx_pko_mem_debug7 { 1421 uint64_t u64; 1422 struct cvmx_pko_mem_debug7_s { 1423#ifdef __BIG_ENDIAN_BITFIELD 1424 uint64_t reserved_0_63 : 64; 1425#else 1426 uint64_t reserved_0_63 : 64; 1427#endif 1428 } s; 1429 struct cvmx_pko_mem_debug7_cn30xx { 1430#ifdef __BIG_ENDIAN_BITFIELD 1431 uint64_t reserved_58_63 : 6; 1432 uint64_t dwb : 9; /**< Calculated DWB count used for free operation */ 1433 uint64_t start : 33; /**< Calculated start address used for free operation */ 1434 uint64_t size : 16; /**< Packet length in bytes */ 1435#else 1436 uint64_t size : 16; 1437 uint64_t start : 33; 1438 uint64_t dwb : 9; 1439 uint64_t reserved_58_63 : 6; 1440#endif 1441 } cn30xx; 1442 struct cvmx_pko_mem_debug7_cn30xx cn31xx; 1443 struct cvmx_pko_mem_debug7_cn30xx cn38xx; 1444 struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; 1445 struct cvmx_pko_mem_debug7_cn50xx { 1446#ifdef __BIG_ENDIAN_BITFIELD 1447 uint64_t qos : 5; /**< QOS mask to enable the queue when set */ 1448 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1449 uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1450 uint64_t buf_ptr : 33; /**< Command word pointer */ 1451 uint64_t qcb_widx : 6; /**< Buffer write index for QCB */ 1452 uint64_t qcb_ridx : 6; /**< Buffer read index for QCB */ 1453#else 1454 uint64_t qcb_ridx : 6; 1455 uint64_t qcb_widx : 6; 1456 uint64_t buf_ptr : 33; 1457 uint64_t buf_siz : 13; 1458 uint64_t tail : 1; 1459 uint64_t qos : 5; 1460#endif 1461 } cn50xx; 1462 struct cvmx_pko_mem_debug7_cn50xx cn52xx; 1463 struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; 1464 struct cvmx_pko_mem_debug7_cn50xx cn56xx; 1465 struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; 1466 struct cvmx_pko_mem_debug7_cn50xx cn58xx; 1467 struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; 1468 struct cvmx_pko_mem_debug7_cn50xx cn61xx; 1469 struct cvmx_pko_mem_debug7_cn50xx cn63xx; 1470 struct cvmx_pko_mem_debug7_cn50xx cn63xxp1; 1471 struct cvmx_pko_mem_debug7_cn50xx cn66xx; 1472 struct cvmx_pko_mem_debug7_cn68xx { 1473#ifdef __BIG_ENDIAN_BITFIELD 1474 uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1475 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1476 uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1477 uint64_t buf_ptr : 33; /**< Command word pointer */ 1478 uint64_t qcb_widx : 7; /**< Buffer write index for QCB */ 1479 uint64_t qcb_ridx : 7; /**< Buffer read index for QCB */ 1480#else 1481 uint64_t qcb_ridx : 7; 1482 uint64_t qcb_widx : 7; 1483 uint64_t buf_ptr : 33; 1484 uint64_t buf_siz : 13; 1485 uint64_t tail : 1; 1486 uint64_t qos : 3; 1487#endif 1488 } cn68xx; 1489 struct cvmx_pko_mem_debug7_cn68xx cn68xxp1; 1490 struct cvmx_pko_mem_debug7_cn50xx cnf71xx; 1491}; 1492typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t; 1493 1494/** 1495 * cvmx_pko_mem_debug8 1496 * 1497 * Notes: 1498 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64] 1499 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1500 * CSR read operations to this address can be performed. 1501 */ 1502union cvmx_pko_mem_debug8 { 1503 uint64_t u64; 1504 struct cvmx_pko_mem_debug8_s { 1505#ifdef __BIG_ENDIAN_BITFIELD 1506 uint64_t reserved_59_63 : 5; 1507 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1508 uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1509 uint64_t reserved_0_44 : 45; 1510#else 1511 uint64_t reserved_0_44 : 45; 1512 uint64_t buf_siz : 13; 1513 uint64_t tail : 1; 1514 uint64_t reserved_59_63 : 5; 1515#endif 1516 } s; 1517 struct cvmx_pko_mem_debug8_cn30xx { 1518#ifdef __BIG_ENDIAN_BITFIELD 1519 uint64_t qos : 5; /**< QOS mask to enable the queue when set */ 1520 uint64_t tail : 1; /**< This queue is the last (tail) in the queue array */ 1521 uint64_t buf_siz : 13; /**< Command buffer remaining size in words */ 1522 uint64_t buf_ptr : 33; /**< Command word pointer */ 1523 uint64_t qcb_widx : 6; /**< Buffer write index for QCB */ 1524 uint64_t qcb_ridx : 6; /**< Buffer read index for QCB */ 1525#else 1526 uint64_t qcb_ridx : 6; 1527 uint64_t qcb_widx : 6; 1528 uint64_t buf_ptr : 33; 1529 uint64_t buf_siz : 13; 1530 uint64_t tail : 1; 1531 uint64_t qos : 5; 1532#endif 1533 } cn30xx; 1534 struct cvmx_pko_mem_debug8_cn30xx cn31xx; 1535 struct cvmx_pko_mem_debug8_cn30xx cn38xx; 1536 struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; 1537 struct cvmx_pko_mem_debug8_cn50xx { 1538#ifdef __BIG_ENDIAN_BITFIELD 1539 uint64_t reserved_28_63 : 36; 1540 uint64_t doorbell : 20; /**< Doorbell count */ 1541 uint64_t reserved_6_7 : 2; 1542 uint64_t static_p : 1; /**< Static priority */ 1543 uint64_t s_tail : 1; /**< Static tail */ 1544 uint64_t static_q : 1; /**< Static priority */ 1545 uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1546#else 1547 uint64_t qos : 3; 1548 uint64_t static_q : 1; 1549 uint64_t s_tail : 1; 1550 uint64_t static_p : 1; 1551 uint64_t reserved_6_7 : 2; 1552 uint64_t doorbell : 20; 1553 uint64_t reserved_28_63 : 36; 1554#endif 1555 } cn50xx; 1556 struct cvmx_pko_mem_debug8_cn52xx { 1557#ifdef __BIG_ENDIAN_BITFIELD 1558 uint64_t reserved_29_63 : 35; 1559 uint64_t preempter : 1; /**< Preempter */ 1560 uint64_t doorbell : 20; /**< Doorbell count */ 1561 uint64_t reserved_7_7 : 1; 1562 uint64_t preemptee : 1; /**< Preemptee */ 1563 uint64_t static_p : 1; /**< Static priority */ 1564 uint64_t s_tail : 1; /**< Static tail */ 1565 uint64_t static_q : 1; /**< Static priority */ 1566 uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1567#else 1568 uint64_t qos : 3; 1569 uint64_t static_q : 1; 1570 uint64_t s_tail : 1; 1571 uint64_t static_p : 1; 1572 uint64_t preemptee : 1; 1573 uint64_t reserved_7_7 : 1; 1574 uint64_t doorbell : 20; 1575 uint64_t preempter : 1; 1576 uint64_t reserved_29_63 : 35; 1577#endif 1578 } cn52xx; 1579 struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; 1580 struct cvmx_pko_mem_debug8_cn52xx cn56xx; 1581 struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; 1582 struct cvmx_pko_mem_debug8_cn50xx cn58xx; 1583 struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; 1584 struct cvmx_pko_mem_debug8_cn61xx { 1585#ifdef __BIG_ENDIAN_BITFIELD 1586 uint64_t reserved_42_63 : 22; 1587 uint64_t qid_qqos : 8; /**< QOS_MASK */ 1588 uint64_t reserved_33_33 : 1; 1589 uint64_t qid_idx : 4; /**< IDX */ 1590 uint64_t preempter : 1; /**< Preempter */ 1591 uint64_t doorbell : 20; /**< Doorbell count */ 1592 uint64_t reserved_7_7 : 1; 1593 uint64_t preemptee : 1; /**< Preemptee */ 1594 uint64_t static_p : 1; /**< Static priority */ 1595 uint64_t s_tail : 1; /**< Static tail */ 1596 uint64_t static_q : 1; /**< Static priority */ 1597 uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1598#else 1599 uint64_t qos : 3; 1600 uint64_t static_q : 1; 1601 uint64_t s_tail : 1; 1602 uint64_t static_p : 1; 1603 uint64_t preemptee : 1; 1604 uint64_t reserved_7_7 : 1; 1605 uint64_t doorbell : 20; 1606 uint64_t preempter : 1; 1607 uint64_t qid_idx : 4; 1608 uint64_t reserved_33_33 : 1; 1609 uint64_t qid_qqos : 8; 1610 uint64_t reserved_42_63 : 22; 1611#endif 1612 } cn61xx; 1613 struct cvmx_pko_mem_debug8_cn52xx cn63xx; 1614 struct cvmx_pko_mem_debug8_cn52xx cn63xxp1; 1615 struct cvmx_pko_mem_debug8_cn61xx cn66xx; 1616 struct cvmx_pko_mem_debug8_cn68xx { 1617#ifdef __BIG_ENDIAN_BITFIELD 1618 uint64_t reserved_37_63 : 27; 1619 uint64_t preempter : 1; /**< Preempter */ 1620 uint64_t doorbell : 20; /**< Doorbell count */ 1621 uint64_t reserved_9_15 : 7; 1622 uint64_t preemptee : 1; /**< Preemptee */ 1623 uint64_t static_p : 1; /**< Static priority */ 1624 uint64_t s_tail : 1; /**< Static tail */ 1625 uint64_t static_q : 1; /**< Static priority */ 1626 uint64_t qos : 5; /**< QOS mask to enable the queue when set */ 1627#else 1628 uint64_t qos : 5; 1629 uint64_t static_q : 1; 1630 uint64_t s_tail : 1; 1631 uint64_t static_p : 1; 1632 uint64_t preemptee : 1; 1633 uint64_t reserved_9_15 : 7; 1634 uint64_t doorbell : 20; 1635 uint64_t preempter : 1; 1636 uint64_t reserved_37_63 : 27; 1637#endif 1638 } cn68xx; 1639 struct cvmx_pko_mem_debug8_cn68xx cn68xxp1; 1640 struct cvmx_pko_mem_debug8_cn61xx cnf71xx; 1641}; 1642typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t; 1643 1644/** 1645 * cvmx_pko_mem_debug9 1646 * 1647 * Notes: 1648 * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3 1649 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1650 * CSR read operations to this address can be performed. 1651 */ 1652union cvmx_pko_mem_debug9 { 1653 uint64_t u64; 1654 struct cvmx_pko_mem_debug9_s { 1655#ifdef __BIG_ENDIAN_BITFIELD 1656 uint64_t reserved_49_63 : 15; 1657 uint64_t ptrs0 : 17; /**< Internal state */ 1658 uint64_t reserved_0_31 : 32; 1659#else 1660 uint64_t reserved_0_31 : 32; 1661 uint64_t ptrs0 : 17; 1662 uint64_t reserved_49_63 : 15; 1663#endif 1664 } s; 1665 struct cvmx_pko_mem_debug9_cn30xx { 1666#ifdef __BIG_ENDIAN_BITFIELD 1667 uint64_t reserved_28_63 : 36; 1668 uint64_t doorbell : 20; /**< Doorbell count */ 1669 uint64_t reserved_5_7 : 3; 1670 uint64_t s_tail : 1; /**< reads as zero (S_TAIL cannot be read) */ 1671 uint64_t static_q : 1; /**< reads as zero (STATIC_Q cannot be read) */ 1672 uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1673#else 1674 uint64_t qos : 3; 1675 uint64_t static_q : 1; 1676 uint64_t s_tail : 1; 1677 uint64_t reserved_5_7 : 3; 1678 uint64_t doorbell : 20; 1679 uint64_t reserved_28_63 : 36; 1680#endif 1681 } cn30xx; 1682 struct cvmx_pko_mem_debug9_cn30xx cn31xx; 1683 struct cvmx_pko_mem_debug9_cn38xx { 1684#ifdef __BIG_ENDIAN_BITFIELD 1685 uint64_t reserved_28_63 : 36; 1686 uint64_t doorbell : 20; /**< Doorbell count */ 1687 uint64_t reserved_6_7 : 2; 1688 uint64_t static_p : 1; /**< Static priority (port) */ 1689 uint64_t s_tail : 1; /**< Static tail */ 1690 uint64_t static_q : 1; /**< Static priority */ 1691 uint64_t qos : 3; /**< QOS mask to enable the queue when set */ 1692#else 1693 uint64_t qos : 3; 1694 uint64_t static_q : 1; 1695 uint64_t s_tail : 1; 1696 uint64_t static_p : 1; 1697 uint64_t reserved_6_7 : 2; 1698 uint64_t doorbell : 20; 1699 uint64_t reserved_28_63 : 36; 1700#endif 1701 } cn38xx; 1702 struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; 1703 struct cvmx_pko_mem_debug9_cn50xx { 1704#ifdef __BIG_ENDIAN_BITFIELD 1705 uint64_t reserved_49_63 : 15; 1706 uint64_t ptrs0 : 17; /**< Internal state */ 1707 uint64_t reserved_17_31 : 15; 1708 uint64_t ptrs3 : 17; /**< Internal state */ 1709#else 1710 uint64_t ptrs3 : 17; 1711 uint64_t reserved_17_31 : 15; 1712 uint64_t ptrs0 : 17; 1713 uint64_t reserved_49_63 : 15; 1714#endif 1715 } cn50xx; 1716 struct cvmx_pko_mem_debug9_cn50xx cn52xx; 1717 struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; 1718 struct cvmx_pko_mem_debug9_cn50xx cn56xx; 1719 struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; 1720 struct cvmx_pko_mem_debug9_cn50xx cn58xx; 1721 struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; 1722 struct cvmx_pko_mem_debug9_cn50xx cn61xx; 1723 struct cvmx_pko_mem_debug9_cn50xx cn63xx; 1724 struct cvmx_pko_mem_debug9_cn50xx cn63xxp1; 1725 struct cvmx_pko_mem_debug9_cn50xx cn66xx; 1726 struct cvmx_pko_mem_debug9_cn50xx cn68xx; 1727 struct cvmx_pko_mem_debug9_cn50xx cn68xxp1; 1728 struct cvmx_pko_mem_debug9_cn50xx cnf71xx; 1729}; 1730typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t; 1731 1732/** 1733 * cvmx_pko_mem_iport_ptrs 1734 * 1735 * Notes: 1736 * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1737 * CSR read operations to this address can be performed. The index to this CSR is an IPORT. A read of any 1738 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1739 */ 1740union cvmx_pko_mem_iport_ptrs { 1741 uint64_t u64; 1742 struct cvmx_pko_mem_iport_ptrs_s { 1743#ifdef __BIG_ENDIAN_BITFIELD 1744 uint64_t reserved_63_63 : 1; 1745 uint64_t crc : 1; /**< Set if this IPID uses CRC */ 1746 uint64_t static_p : 1; /**< Set if this IPID has static priority */ 1747 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1748 uint64_t min_pkt : 3; /**< Min packet size specified by PKO_REG_MIN_PKT[MIN_PKT] */ 1749 uint64_t reserved_31_49 : 19; 1750 uint64_t pipe : 7; /**< The PKO pipe or loopback port 1751 When INT != PIP/IPD: 1752 PIPE is the PKO pipe to which this port is mapped 1753 All used PKO-internal ports that map to the same 1754 PIPE must also map to the same INT and EID in 1755 this case. 1756 When INT == PIP/IPD: 1757 PIPE must be in the range 1758 0..PKO_REG_LOOPBACK[NUM_PORTS]-1 1759 in this case and selects one of the loopback 1760 ports. */ 1761 uint64_t reserved_21_23 : 3; 1762 uint64_t intr : 5; /**< The interface to which this port is mapped 1763 All used PKO-internal ports that map to the same EID 1764 must also map to the same INT. All used PKO-internal 1765 ports that map to the same INT must also map to the 1766 same EID. 1767 Encoding: 1768 0 = GMX0 XAUI/DXAUI/RXAUI0 or SGMII0 1769 1 = GMX0 SGMII1 1770 2 = GMX0 SGMII2 1771 3 = GMX0 SGMII3 1772 4 = GMX1 RXAUI 1773 8 = GMX2 XAUI/DXAUI or SGMII0 1774 9 = GMX2 SGMII1 1775 10 = GMX2 SGMII2 1776 11 = GMX2 SGMII3 1777 12 = GMX3 XAUI/DXAUI or SGMII0 1778 13 = GMX3 SGMII1 1779 14 = GMX3 SGMII2 1780 15 = GMX3 SGMII3 1781 16 = GMX4 XAUI/DXAUI or SGMII0 1782 17 = GMX4 SGMII1 1783 18 = GMX4 SGMII2 1784 19 = GMX4 SGMII3 1785 28 = ILK interface 0 1786 29 = ILK interface 1 1787 30 = DPI 1788 31 = PIP/IPD 1789 others = reserved */ 1790 uint64_t reserved_13_15 : 3; 1791 uint64_t eid : 5; /**< Engine ID to which this port is mapped 1792 EID==31 can be used with unused PKO-internal ports. 1793 Otherwise, 0-19 are legal EID values. */ 1794 uint64_t reserved_7_7 : 1; 1795 uint64_t ipid : 7; /**< PKO-internal Port ID to be accessed */ 1796#else 1797 uint64_t ipid : 7; 1798 uint64_t reserved_7_7 : 1; 1799 uint64_t eid : 5; 1800 uint64_t reserved_13_15 : 3; 1801 uint64_t intr : 5; 1802 uint64_t reserved_21_23 : 3; 1803 uint64_t pipe : 7; 1804 uint64_t reserved_31_49 : 19; 1805 uint64_t min_pkt : 3; 1806 uint64_t qos_mask : 8; 1807 uint64_t static_p : 1; 1808 uint64_t crc : 1; 1809 uint64_t reserved_63_63 : 1; 1810#endif 1811 } s; 1812 struct cvmx_pko_mem_iport_ptrs_s cn68xx; 1813 struct cvmx_pko_mem_iport_ptrs_s cn68xxp1; 1814}; 1815typedef union cvmx_pko_mem_iport_ptrs cvmx_pko_mem_iport_ptrs_t; 1816 1817/** 1818 * cvmx_pko_mem_iport_qos 1819 * 1820 * Notes: 1821 * Sets the QOS mask, per port. These QOS_MASK bits are logically and physically the same QOS_MASK 1822 * bits in PKO_MEM_IPORT_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 1823 * operation without affecting any other port state. The engine to which port PID is mapped is engine 1824 * EID. Note that the port to engine mapping must be the same as was previously programmed via the 1825 * PKO_MEM_IPORT_PTRS CSR. 1826 * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1827 * CSR read operations to this address can be performed. The index to this CSR is an IPORT. A read of 1828 * any entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1829 */ 1830union cvmx_pko_mem_iport_qos { 1831 uint64_t u64; 1832 struct cvmx_pko_mem_iport_qos_s { 1833#ifdef __BIG_ENDIAN_BITFIELD 1834 uint64_t reserved_61_63 : 3; 1835 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1836 uint64_t reserved_13_52 : 40; 1837 uint64_t eid : 5; /**< Engine ID to which this port is mapped */ 1838 uint64_t reserved_7_7 : 1; 1839 uint64_t ipid : 7; /**< PKO-internal Port ID */ 1840#else 1841 uint64_t ipid : 7; 1842 uint64_t reserved_7_7 : 1; 1843 uint64_t eid : 5; 1844 uint64_t reserved_13_52 : 40; 1845 uint64_t qos_mask : 8; 1846 uint64_t reserved_61_63 : 3; 1847#endif 1848 } s; 1849 struct cvmx_pko_mem_iport_qos_s cn68xx; 1850 struct cvmx_pko_mem_iport_qos_s cn68xxp1; 1851}; 1852typedef union cvmx_pko_mem_iport_qos cvmx_pko_mem_iport_qos_t; 1853 1854/** 1855 * cvmx_pko_mem_iqueue_ptrs 1856 * 1857 * Notes: 1858 * Sets the queue to port mapping and the initial command buffer pointer, per queue. Unused queues must 1859 * set BUF_PTR=0. Each queue may map to at most one port. No more than 32 queues may map to a port. 1860 * The set of queues that is mapped to a port must be a contiguous array of queues. The port to which 1861 * queue QID is mapped is port IPID. The index of queue QID in port IPID's queue list is IDX. The last 1862 * queue in port IPID's queue array must have its TAIL bit set. 1863 * STATIC_Q marks queue QID as having static priority. STATIC_P marks the port IPID to which QID is 1864 * mapped as having at least one queue with static priority. If any QID that maps to IPID has static 1865 * priority, then all QID that map to IPID must have STATIC_P set. Queues marked as static priority 1866 * must be contiguous and begin at IDX 0. The last queue that is marked as having static priority 1867 * must have its S_TAIL bit set. 1868 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1869 * CSR read operations to this address can be performed. The index to this CSR is an IQUEUE. A read of any 1870 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1871 */ 1872union cvmx_pko_mem_iqueue_ptrs { 1873 uint64_t u64; 1874 struct cvmx_pko_mem_iqueue_ptrs_s { 1875#ifdef __BIG_ENDIAN_BITFIELD 1876 uint64_t s_tail : 1; /**< Set if this QID is the tail of the static queues */ 1877 uint64_t static_p : 1; /**< Set if any QID in this IPID has static priority */ 1878 uint64_t static_q : 1; /**< Set if this QID has static priority */ 1879 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1880 uint64_t buf_ptr : 31; /**< Command buffer pointer[37:7] */ 1881 uint64_t tail : 1; /**< Set if this QID is the tail of the queue array */ 1882 uint64_t index : 5; /**< Index (distance from head) in the queue array */ 1883 uint64_t reserved_15_15 : 1; 1884 uint64_t ipid : 7; /**< PKO-Internal Port ID to which this queue is mapped */ 1885 uint64_t qid : 8; /**< Queue ID */ 1886#else 1887 uint64_t qid : 8; 1888 uint64_t ipid : 7; 1889 uint64_t reserved_15_15 : 1; 1890 uint64_t index : 5; 1891 uint64_t tail : 1; 1892 uint64_t buf_ptr : 31; 1893 uint64_t qos_mask : 8; 1894 uint64_t static_q : 1; 1895 uint64_t static_p : 1; 1896 uint64_t s_tail : 1; 1897#endif 1898 } s; 1899 struct cvmx_pko_mem_iqueue_ptrs_s cn68xx; 1900 struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1; 1901}; 1902typedef union cvmx_pko_mem_iqueue_ptrs cvmx_pko_mem_iqueue_ptrs_t; 1903 1904/** 1905 * cvmx_pko_mem_iqueue_qos 1906 * 1907 * Notes: 1908 * Sets the QOS mask, per queue. These QOS_MASK bits are logically and physically the same QOS_MASK 1909 * bits in PKO_MEM_IQUEUE_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 1910 * operation without affecting any other queue state. The port to which queue QID is mapped is port 1911 * IPID. Note that the queue to port mapping must be the same as was previously programmed via the 1912 * PKO_MEM_IQUEUE_PTRS CSR. 1913 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 1914 * CSR read operations to this address can be performed. The index to this CSR is an IQUEUE. A read of any 1915 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 1916 */ 1917union cvmx_pko_mem_iqueue_qos { 1918 uint64_t u64; 1919 struct cvmx_pko_mem_iqueue_qos_s { 1920#ifdef __BIG_ENDIAN_BITFIELD 1921 uint64_t reserved_61_63 : 3; 1922 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 1923 uint64_t reserved_15_52 : 38; 1924 uint64_t ipid : 7; /**< PKO-Internal Port ID to which this queue is mapped */ 1925 uint64_t qid : 8; /**< Queue ID */ 1926#else 1927 uint64_t qid : 8; 1928 uint64_t ipid : 7; 1929 uint64_t reserved_15_52 : 38; 1930 uint64_t qos_mask : 8; 1931 uint64_t reserved_61_63 : 3; 1932#endif 1933 } s; 1934 struct cvmx_pko_mem_iqueue_qos_s cn68xx; 1935 struct cvmx_pko_mem_iqueue_qos_s cn68xxp1; 1936}; 1937typedef union cvmx_pko_mem_iqueue_qos cvmx_pko_mem_iqueue_qos_t; 1938 1939/** 1940 * cvmx_pko_mem_port_ptrs 1941 * 1942 * Notes: 1943 * Sets the port to engine mapping, per port. Ports marked as static priority need not be contiguous, 1944 * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff. If EID==8 1945 * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface. 1946 * EID==15 can be used for unused PKO-internal ports. 1947 * BP_PORT==63 means that the PKO-internal port is not backpressured. 1948 * BP_PORTs are assumed to belong to an interface as follows: 1949 * 46 <= BP_PORT < 48 -> srio interface 3 1950 * 44 <= BP_PORT < 46 -> srio interface 2 1951 * 42 <= BP_PORT < 44 -> srio interface 1 1952 * 40 <= BP_PORT < 42 -> srio interface 0 1953 * 36 <= BP_PORT < 40 -> loopback interface 1954 * 32 <= BP_PORT < 36 -> PCIe interface 1955 * 0 <= BP_PORT < 16 -> SGMII/Xaui interface 0 1956 * 1957 * Note that the SRIO interfaces do not actually provide backpressure. Thus, ports that use 1958 * 40 <= BP_PORT < 48 for backpressure will never be backpressured. 1959 * 1960 * The reset configuration is the following: 1961 * PID EID(ext port) BP_PORT QOS_MASK STATIC_P 1962 * ------------------------------------------- 1963 * 0 0( 0) 0 0xff 0 1964 * 1 1( 1) 1 0xff 0 1965 * 2 2( 2) 2 0xff 0 1966 * 3 3( 3) 3 0xff 0 1967 * 4 0( 0) 4 0xff 0 1968 * 5 1( 1) 5 0xff 0 1969 * 6 2( 2) 6 0xff 0 1970 * 7 3( 3) 7 0xff 0 1971 * 8 0( 0) 8 0xff 0 1972 * 9 1( 1) 9 0xff 0 1973 * 10 2( 2) 10 0xff 0 1974 * 11 3( 3) 11 0xff 0 1975 * 12 0( 0) 12 0xff 0 1976 * 13 1( 1) 13 0xff 0 1977 * 14 2( 2) 14 0xff 0 1978 * 15 3( 3) 15 0xff 0 1979 * ------------------------------------------- 1980 * 16 4(16) 16 0xff 0 1981 * 17 5(17) 17 0xff 0 1982 * 18 6(18) 18 0xff 0 1983 * 19 7(19) 19 0xff 0 1984 * 20 4(16) 20 0xff 0 1985 * 21 5(17) 21 0xff 0 1986 * 22 6(18) 22 0xff 0 1987 * 23 7(19) 23 0xff 0 1988 * 24 4(16) 24 0xff 0 1989 * 25 5(17) 25 0xff 0 1990 * 26 6(18) 26 0xff 0 1991 * 27 7(19) 27 0xff 0 1992 * 28 4(16) 28 0xff 0 1993 * 29 5(17) 29 0xff 0 1994 * 30 6(18) 30 0xff 0 1995 * 31 7(19) 31 0xff 0 1996 * ------------------------------------------- 1997 * 32 8(32) 32 0xff 0 1998 * 33 8(33) 33 0xff 0 1999 * 34 8(34) 34 0xff 0 2000 * 35 8(35) 35 0xff 0 2001 * ------------------------------------------- 2002 * 36 9(36) 36 0xff 0 2003 * 37 9(37) 37 0xff 0 2004 * 38 9(38) 38 0xff 0 2005 * 39 9(39) 39 0xff 0 2006 * 2007 * This CSR is a memory of 48 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2008 * CSR read operations to this address can be performed. A read of any entry that has not been 2009 * previously written is illegal and will result in unpredictable CSR read data. 2010 */ 2011union cvmx_pko_mem_port_ptrs { 2012 uint64_t u64; 2013 struct cvmx_pko_mem_port_ptrs_s { 2014#ifdef __BIG_ENDIAN_BITFIELD 2015 uint64_t reserved_62_63 : 2; 2016 uint64_t static_p : 1; /**< Set if this PID has static priority */ 2017 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2018 uint64_t reserved_16_52 : 37; 2019 uint64_t bp_port : 6; /**< PID listens to BP_PORT for per-packet backpressure 2020 Legal BP_PORTs: 0-15, 32-47, 63 (63 means no BP) */ 2021 uint64_t eid : 4; /**< Engine ID to which this port is mapped 2022 Legal EIDs: 0-3, 8-13, 15 (15 only if port not used) */ 2023 uint64_t pid : 6; /**< Port ID[5:0] */ 2024#else 2025 uint64_t pid : 6; 2026 uint64_t eid : 4; 2027 uint64_t bp_port : 6; 2028 uint64_t reserved_16_52 : 37; 2029 uint64_t qos_mask : 8; 2030 uint64_t static_p : 1; 2031 uint64_t reserved_62_63 : 2; 2032#endif 2033 } s; 2034 struct cvmx_pko_mem_port_ptrs_s cn52xx; 2035 struct cvmx_pko_mem_port_ptrs_s cn52xxp1; 2036 struct cvmx_pko_mem_port_ptrs_s cn56xx; 2037 struct cvmx_pko_mem_port_ptrs_s cn56xxp1; 2038 struct cvmx_pko_mem_port_ptrs_s cn61xx; 2039 struct cvmx_pko_mem_port_ptrs_s cn63xx; 2040 struct cvmx_pko_mem_port_ptrs_s cn63xxp1; 2041 struct cvmx_pko_mem_port_ptrs_s cn66xx; 2042 struct cvmx_pko_mem_port_ptrs_s cnf71xx; 2043}; 2044typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t; 2045 2046/** 2047 * cvmx_pko_mem_port_qos 2048 * 2049 * Notes: 2050 * Sets the QOS mask, per port. These QOS_MASK bits are logically and physically the same QOS_MASK 2051 * bits in PKO_MEM_PORT_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 2052 * operation without affecting any other port state. The engine to which port PID is mapped is engine 2053 * EID. Note that the port to engine mapping must be the same as was previously programmed via the 2054 * PKO_MEM_PORT_PTRS CSR. 2055 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2056 * CSR read operations to this address can be performed. A read of any entry that has not been 2057 * previously written is illegal and will result in unpredictable CSR read data. 2058 */ 2059union cvmx_pko_mem_port_qos { 2060 uint64_t u64; 2061 struct cvmx_pko_mem_port_qos_s { 2062#ifdef __BIG_ENDIAN_BITFIELD 2063 uint64_t reserved_61_63 : 3; 2064 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2065 uint64_t reserved_10_52 : 43; 2066 uint64_t eid : 4; /**< Engine ID to which this port is mapped 2067 Legal EIDs: 0-3, 8-11 */ 2068 uint64_t pid : 6; /**< Port ID[5:0] */ 2069#else 2070 uint64_t pid : 6; 2071 uint64_t eid : 4; 2072 uint64_t reserved_10_52 : 43; 2073 uint64_t qos_mask : 8; 2074 uint64_t reserved_61_63 : 3; 2075#endif 2076 } s; 2077 struct cvmx_pko_mem_port_qos_s cn52xx; 2078 struct cvmx_pko_mem_port_qos_s cn52xxp1; 2079 struct cvmx_pko_mem_port_qos_s cn56xx; 2080 struct cvmx_pko_mem_port_qos_s cn56xxp1; 2081 struct cvmx_pko_mem_port_qos_s cn61xx; 2082 struct cvmx_pko_mem_port_qos_s cn63xx; 2083 struct cvmx_pko_mem_port_qos_s cn63xxp1; 2084 struct cvmx_pko_mem_port_qos_s cn66xx; 2085 struct cvmx_pko_mem_port_qos_s cnf71xx; 2086}; 2087typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t; 2088 2089/** 2090 * cvmx_pko_mem_port_rate0 2091 * 2092 * Notes: 2093 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2094 * CSR read operations to this address can be performed. A read of any entry that has not been 2095 * previously written is illegal and will result in unpredictable CSR read data. 2096 */ 2097union cvmx_pko_mem_port_rate0 { 2098 uint64_t u64; 2099 struct cvmx_pko_mem_port_rate0_s { 2100#ifdef __BIG_ENDIAN_BITFIELD 2101 uint64_t reserved_51_63 : 13; 2102 uint64_t rate_word : 19; /**< Rate limiting adder per 8 byte */ 2103 uint64_t rate_pkt : 24; /**< Rate limiting adder per packet */ 2104 uint64_t reserved_7_7 : 1; 2105 uint64_t pid : 7; /**< Port ID[5:0] */ 2106#else 2107 uint64_t pid : 7; 2108 uint64_t reserved_7_7 : 1; 2109 uint64_t rate_pkt : 24; 2110 uint64_t rate_word : 19; 2111 uint64_t reserved_51_63 : 13; 2112#endif 2113 } s; 2114 struct cvmx_pko_mem_port_rate0_cn52xx { 2115#ifdef __BIG_ENDIAN_BITFIELD 2116 uint64_t reserved_51_63 : 13; 2117 uint64_t rate_word : 19; /**< Rate limiting adder per 8 byte */ 2118 uint64_t rate_pkt : 24; /**< Rate limiting adder per packet */ 2119 uint64_t reserved_6_7 : 2; 2120 uint64_t pid : 6; /**< Port ID[5:0] */ 2121#else 2122 uint64_t pid : 6; 2123 uint64_t reserved_6_7 : 2; 2124 uint64_t rate_pkt : 24; 2125 uint64_t rate_word : 19; 2126 uint64_t reserved_51_63 : 13; 2127#endif 2128 } cn52xx; 2129 struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1; 2130 struct cvmx_pko_mem_port_rate0_cn52xx cn56xx; 2131 struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1; 2132 struct cvmx_pko_mem_port_rate0_cn52xx cn61xx; 2133 struct cvmx_pko_mem_port_rate0_cn52xx cn63xx; 2134 struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1; 2135 struct cvmx_pko_mem_port_rate0_cn52xx cn66xx; 2136 struct cvmx_pko_mem_port_rate0_s cn68xx; 2137 struct cvmx_pko_mem_port_rate0_s cn68xxp1; 2138 struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx; 2139}; 2140typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t; 2141 2142/** 2143 * cvmx_pko_mem_port_rate1 2144 * 2145 * Notes: 2146 * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding 2147 * accumulator to zero. 2148 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2149 * CSR read operations to this address can be performed. A read of any entry that has not been 2150 * previously written is illegal and will result in unpredictable CSR read data. 2151 */ 2152union cvmx_pko_mem_port_rate1 { 2153 uint64_t u64; 2154 struct cvmx_pko_mem_port_rate1_s { 2155#ifdef __BIG_ENDIAN_BITFIELD 2156 uint64_t reserved_32_63 : 32; 2157 uint64_t rate_lim : 24; /**< Rate limiting accumulator limit */ 2158 uint64_t reserved_7_7 : 1; 2159 uint64_t pid : 7; /**< Port ID[5:0] */ 2160#else 2161 uint64_t pid : 7; 2162 uint64_t reserved_7_7 : 1; 2163 uint64_t rate_lim : 24; 2164 uint64_t reserved_32_63 : 32; 2165#endif 2166 } s; 2167 struct cvmx_pko_mem_port_rate1_cn52xx { 2168#ifdef __BIG_ENDIAN_BITFIELD 2169 uint64_t reserved_32_63 : 32; 2170 uint64_t rate_lim : 24; /**< Rate limiting accumulator limit */ 2171 uint64_t reserved_6_7 : 2; 2172 uint64_t pid : 6; /**< Port ID[5:0] */ 2173#else 2174 uint64_t pid : 6; 2175 uint64_t reserved_6_7 : 2; 2176 uint64_t rate_lim : 24; 2177 uint64_t reserved_32_63 : 32; 2178#endif 2179 } cn52xx; 2180 struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1; 2181 struct cvmx_pko_mem_port_rate1_cn52xx cn56xx; 2182 struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1; 2183 struct cvmx_pko_mem_port_rate1_cn52xx cn61xx; 2184 struct cvmx_pko_mem_port_rate1_cn52xx cn63xx; 2185 struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1; 2186 struct cvmx_pko_mem_port_rate1_cn52xx cn66xx; 2187 struct cvmx_pko_mem_port_rate1_s cn68xx; 2188 struct cvmx_pko_mem_port_rate1_s cn68xxp1; 2189 struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx; 2190}; 2191typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t; 2192 2193/** 2194 * cvmx_pko_mem_queue_ptrs 2195 * 2196 * Notes: 2197 * Sets the queue to port mapping and the initial command buffer pointer, per queue 2198 * Each queue may map to at most one port. No more than 16 queues may map to a port. The set of 2199 * queues that is mapped to a port must be a contiguous array of queues. The port to which queue QID 2200 * is mapped is port PID. The index of queue QID in port PID's queue list is IDX. The last queue in 2201 * port PID's queue array must have its TAIL bit set. Unused queues must be mapped to port 63. 2202 * STATIC_Q marks queue QID as having static priority. STATIC_P marks the port PID to which QID is 2203 * mapped as having at least one queue with static priority. If any QID that maps to PID has static 2204 * priority, then all QID that map to PID must have STATIC_P set. Queues marked as static priority 2205 * must be contiguous and begin at IDX 0. The last queue that is marked as having static priority 2206 * must have its S_TAIL bit set. 2207 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2208 * CSR read operations to this address can be performed. A read of any entry that has not been 2209 * previously written is illegal and will result in unpredictable CSR read data. 2210 */ 2211union cvmx_pko_mem_queue_ptrs { 2212 uint64_t u64; 2213 struct cvmx_pko_mem_queue_ptrs_s { 2214#ifdef __BIG_ENDIAN_BITFIELD 2215 uint64_t s_tail : 1; /**< Set if this QID is the tail of the static queues */ 2216 uint64_t static_p : 1; /**< Set if any QID in this PID has static priority */ 2217 uint64_t static_q : 1; /**< Set if this QID has static priority */ 2218 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2219 uint64_t buf_ptr : 36; /**< Command buffer pointer, <23:17> MBZ */ 2220 uint64_t tail : 1; /**< Set if this QID is the tail of the queue array */ 2221 uint64_t index : 3; /**< Index[2:0] (distance from head) in the queue array */ 2222 uint64_t port : 6; /**< Port ID to which this queue is mapped */ 2223 uint64_t queue : 7; /**< Queue ID[6:0] */ 2224#else 2225 uint64_t queue : 7; 2226 uint64_t port : 6; 2227 uint64_t index : 3; 2228 uint64_t tail : 1; 2229 uint64_t buf_ptr : 36; 2230 uint64_t qos_mask : 8; 2231 uint64_t static_q : 1; 2232 uint64_t static_p : 1; 2233 uint64_t s_tail : 1; 2234#endif 2235 } s; 2236 struct cvmx_pko_mem_queue_ptrs_s cn30xx; 2237 struct cvmx_pko_mem_queue_ptrs_s cn31xx; 2238 struct cvmx_pko_mem_queue_ptrs_s cn38xx; 2239 struct cvmx_pko_mem_queue_ptrs_s cn38xxp2; 2240 struct cvmx_pko_mem_queue_ptrs_s cn50xx; 2241 struct cvmx_pko_mem_queue_ptrs_s cn52xx; 2242 struct cvmx_pko_mem_queue_ptrs_s cn52xxp1; 2243 struct cvmx_pko_mem_queue_ptrs_s cn56xx; 2244 struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; 2245 struct cvmx_pko_mem_queue_ptrs_s cn58xx; 2246 struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; 2247 struct cvmx_pko_mem_queue_ptrs_s cn61xx; 2248 struct cvmx_pko_mem_queue_ptrs_s cn63xx; 2249 struct cvmx_pko_mem_queue_ptrs_s cn63xxp1; 2250 struct cvmx_pko_mem_queue_ptrs_s cn66xx; 2251 struct cvmx_pko_mem_queue_ptrs_s cnf71xx; 2252}; 2253typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t; 2254 2255/** 2256 * cvmx_pko_mem_queue_qos 2257 * 2258 * Notes: 2259 * Sets the QOS mask, per queue. These QOS_MASK bits are logically and physically the same QOS_MASK 2260 * bits in PKO_MEM_QUEUE_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 2261 * operation without affecting any other queue state. The port to which queue QID is mapped is port 2262 * PID. Note that the queue to port mapping must be the same as was previously programmed via the 2263 * PKO_MEM_QUEUE_PTRS CSR. 2264 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2265 * CSR read operations to this address can be performed. A read of any entry that has not been 2266 * previously written is illegal and will result in unpredictable CSR read data. 2267 */ 2268union cvmx_pko_mem_queue_qos { 2269 uint64_t u64; 2270 struct cvmx_pko_mem_queue_qos_s { 2271#ifdef __BIG_ENDIAN_BITFIELD 2272 uint64_t reserved_61_63 : 3; 2273 uint64_t qos_mask : 8; /**< Mask to control priority across 8 QOS rounds */ 2274 uint64_t reserved_13_52 : 40; 2275 uint64_t pid : 6; /**< Port ID to which this queue is mapped */ 2276 uint64_t qid : 7; /**< Queue ID */ 2277#else 2278 uint64_t qid : 7; 2279 uint64_t pid : 6; 2280 uint64_t reserved_13_52 : 40; 2281 uint64_t qos_mask : 8; 2282 uint64_t reserved_61_63 : 3; 2283#endif 2284 } s; 2285 struct cvmx_pko_mem_queue_qos_s cn30xx; 2286 struct cvmx_pko_mem_queue_qos_s cn31xx; 2287 struct cvmx_pko_mem_queue_qos_s cn38xx; 2288 struct cvmx_pko_mem_queue_qos_s cn38xxp2; 2289 struct cvmx_pko_mem_queue_qos_s cn50xx; 2290 struct cvmx_pko_mem_queue_qos_s cn52xx; 2291 struct cvmx_pko_mem_queue_qos_s cn52xxp1; 2292 struct cvmx_pko_mem_queue_qos_s cn56xx; 2293 struct cvmx_pko_mem_queue_qos_s cn56xxp1; 2294 struct cvmx_pko_mem_queue_qos_s cn58xx; 2295 struct cvmx_pko_mem_queue_qos_s cn58xxp1; 2296 struct cvmx_pko_mem_queue_qos_s cn61xx; 2297 struct cvmx_pko_mem_queue_qos_s cn63xx; 2298 struct cvmx_pko_mem_queue_qos_s cn63xxp1; 2299 struct cvmx_pko_mem_queue_qos_s cn66xx; 2300 struct cvmx_pko_mem_queue_qos_s cnf71xx; 2301}; 2302typedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t; 2303 2304/** 2305 * cvmx_pko_mem_throttle_int 2306 * 2307 * Notes: 2308 * Writing PACKET and WORD with 0 resets both counts for INT to 0 rather than add 0. 2309 * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the interface INT. 2310 * 2311 * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO 2312 * and the interface MAC) on the interface. (When PKO first selects a packet from a PKO queue, it 2313 * increments the counts appropriately. When the interface MAC has (largely) completed sending 2314 * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE] 2315 * is set and the most-significant bit of the WORD or packet count for a interface is set, 2316 * PKO will not transfer any packets over the interface. Software can limit the amount of 2317 * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure 2318 * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1. 2319 * For example, to limit the number of packets outstanding in the interface to N, preset PACKET for 2320 * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set). 2321 * 2322 * This CSR is a memory of 32 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2323 * CSR read operations to this address can be performed. The index to this CSR is an INTERFACE. A read of any 2324 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 2325 */ 2326union cvmx_pko_mem_throttle_int { 2327 uint64_t u64; 2328 struct cvmx_pko_mem_throttle_int_s { 2329#ifdef __BIG_ENDIAN_BITFIELD 2330 uint64_t reserved_47_63 : 17; 2331 uint64_t word : 15; /**< On a write, the amount to add to the interface 2332 throttle word count selected by INT. On a read, 2333 returns the current value of the interface throttle 2334 word count selected by PKO_REG_READ_IDX[IDX]. */ 2335 uint64_t reserved_14_31 : 18; 2336 uint64_t packet : 6; /**< On a write, the amount to add to the interface 2337 throttle packet count selected by INT. On a read, 2338 returns the current value of the interface throttle 2339 packet count selected by PKO_REG_READ_IDX[IDX]. */ 2340 uint64_t reserved_5_7 : 3; 2341 uint64_t intr : 5; /**< Selected interface for writes. Undefined on a read. 2342 See PKO_MEM_IPORT_PTRS[INT] for encoding. */ 2343#else 2344 uint64_t intr : 5; 2345 uint64_t reserved_5_7 : 3; 2346 uint64_t packet : 6; 2347 uint64_t reserved_14_31 : 18; 2348 uint64_t word : 15; 2349 uint64_t reserved_47_63 : 17; 2350#endif 2351 } s; 2352 struct cvmx_pko_mem_throttle_int_s cn68xx; 2353 struct cvmx_pko_mem_throttle_int_s cn68xxp1; 2354}; 2355typedef union cvmx_pko_mem_throttle_int cvmx_pko_mem_throttle_int_t; 2356 2357/** 2358 * cvmx_pko_mem_throttle_pipe 2359 * 2360 * Notes: 2361 * Writing PACKET and WORD with 0 resets both counts for PIPE to 0 rather than add 0. 2362 * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the PKO pipe PIPE. 2363 * 2364 * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO 2365 * and the interface MAC) on the pipe. (When PKO first selects a packet from a PKO queue, it 2366 * increments the counts appropriately. When the interface MAC has (largely) completed sending 2367 * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE] 2368 * is set and the most-significant bit of the WORD or packet count for a PKO pipe is set, 2369 * PKO will not transfer any packets over the PKO pipe. Software can limit the amount of 2370 * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure 2371 * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1. 2372 * For example, to limit the number of packets outstanding in the pipe to N, preset PACKET for 2373 * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set). 2374 * 2375 * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 2376 * CSR read operations to this address can be performed. The index to this CSR is a PIPE. A read of any 2377 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 2378 */ 2379union cvmx_pko_mem_throttle_pipe { 2380 uint64_t u64; 2381 struct cvmx_pko_mem_throttle_pipe_s { 2382#ifdef __BIG_ENDIAN_BITFIELD 2383 uint64_t reserved_47_63 : 17; 2384 uint64_t word : 15; /**< On a write, the amount to add to the pipe throttle 2385 word count selected by PIPE. On a read, returns 2386 the current value of the pipe throttle word count 2387 selected by PKO_REG_READ_IDX[IDX]. */ 2388 uint64_t reserved_14_31 : 18; 2389 uint64_t packet : 6; /**< On a write, the amount to add to the pipe throttle 2390 packet count selected by PIPE. On a read, returns 2391 the current value of the pipe throttle packet count 2392 selected by PKO_REG_READ_IDX[IDX]. */ 2393 uint64_t reserved_7_7 : 1; 2394 uint64_t pipe : 7; /**< Selected PKO pipe for writes. Undefined on a read. */ 2395#else 2396 uint64_t pipe : 7; 2397 uint64_t reserved_7_7 : 1; 2398 uint64_t packet : 6; 2399 uint64_t reserved_14_31 : 18; 2400 uint64_t word : 15; 2401 uint64_t reserved_47_63 : 17; 2402#endif 2403 } s; 2404 struct cvmx_pko_mem_throttle_pipe_s cn68xx; 2405 struct cvmx_pko_mem_throttle_pipe_s cn68xxp1; 2406}; 2407typedef union cvmx_pko_mem_throttle_pipe cvmx_pko_mem_throttle_pipe_t; 2408 2409/** 2410 * cvmx_pko_reg_bist_result 2411 * 2412 * Notes: 2413 * Access to the internal BiST results 2414 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 2415 */ 2416union cvmx_pko_reg_bist_result { 2417 uint64_t u64; 2418 struct cvmx_pko_reg_bist_result_s { 2419#ifdef __BIG_ENDIAN_BITFIELD 2420 uint64_t reserved_0_63 : 64; 2421#else 2422 uint64_t reserved_0_63 : 64; 2423#endif 2424 } s; 2425 struct cvmx_pko_reg_bist_result_cn30xx { 2426#ifdef __BIG_ENDIAN_BITFIELD 2427 uint64_t reserved_27_63 : 37; 2428 uint64_t psb2 : 5; /**< BiST result of the PSB memories (0=pass, !0=fail) */ 2429 uint64_t count : 1; /**< BiST result of the COUNT memories (0=pass, !0=fail) */ 2430 uint64_t rif : 1; /**< BiST result of the RIF memories (0=pass, !0=fail) */ 2431 uint64_t wif : 1; /**< BiST result of the WIF memories (0=pass, !0=fail) */ 2432 uint64_t ncb : 1; /**< BiST result of the NCB memories (0=pass, !0=fail) */ 2433 uint64_t out : 1; /**< BiST result of the OUT memories (0=pass, !0=fail) */ 2434 uint64_t crc : 1; /**< BiST result of the CRC memories (0=pass, !0=fail) */ 2435 uint64_t chk : 1; /**< BiST result of the CHK memories (0=pass, !0=fail) */ 2436 uint64_t qsb : 2; /**< BiST result of the QSB memories (0=pass, !0=fail) */ 2437 uint64_t qcb : 2; /**< BiST result of the QCB memories (0=pass, !0=fail) */ 2438 uint64_t pdb : 4; /**< BiST result of the PDB memories (0=pass, !0=fail) */ 2439 uint64_t psb : 7; /**< BiST result of the PSB memories (0=pass, !0=fail) */ 2440#else 2441 uint64_t psb : 7; 2442 uint64_t pdb : 4; 2443 uint64_t qcb : 2; 2444 uint64_t qsb : 2; 2445 uint64_t chk : 1; 2446 uint64_t crc : 1; 2447 uint64_t out : 1; 2448 uint64_t ncb : 1; 2449 uint64_t wif : 1; 2450 uint64_t rif : 1; 2451 uint64_t count : 1; 2452 uint64_t psb2 : 5; 2453 uint64_t reserved_27_63 : 37; 2454#endif 2455 } cn30xx; 2456 struct cvmx_pko_reg_bist_result_cn30xx cn31xx; 2457 struct cvmx_pko_reg_bist_result_cn30xx cn38xx; 2458 struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; 2459 struct cvmx_pko_reg_bist_result_cn50xx { 2460#ifdef __BIG_ENDIAN_BITFIELD 2461 uint64_t reserved_33_63 : 31; 2462 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2463 uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2464 uint64_t out_crc : 1; /**< BiST result of OUT_CRC memories (0=pass, !0=fail) */ 2465 uint64_t out_ctl : 3; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2466 uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2467 uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2468 uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2469 uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2470 uint64_t prt_psb : 6; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2471 uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2472 uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2473 uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2474 uint64_t dat_dat : 4; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2475 uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2476#else 2477 uint64_t dat_ptr : 4; 2478 uint64_t dat_dat : 4; 2479 uint64_t prt_qsb : 3; 2480 uint64_t prt_qcb : 2; 2481 uint64_t ncb_inb : 2; 2482 uint64_t prt_psb : 6; 2483 uint64_t prt_nxt : 1; 2484 uint64_t prt_chk : 3; 2485 uint64_t out_wif : 1; 2486 uint64_t out_sta : 1; 2487 uint64_t out_ctl : 3; 2488 uint64_t out_crc : 1; 2489 uint64_t iob : 1; 2490 uint64_t csr : 1; 2491 uint64_t reserved_33_63 : 31; 2492#endif 2493 } cn50xx; 2494 struct cvmx_pko_reg_bist_result_cn52xx { 2495#ifdef __BIG_ENDIAN_BITFIELD 2496 uint64_t reserved_35_63 : 29; 2497 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2498 uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2499 uint64_t out_dat : 1; /**< BiST result of OUT_DAT memories (0=pass, !0=fail) */ 2500 uint64_t out_ctl : 3; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2501 uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2502 uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2503 uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2504 uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2505 uint64_t prt_psb : 8; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2506 uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2507 uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2508 uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2509 uint64_t prt_ctl : 2; /**< BiST result of PRT_CTL memories (0=pass, !0=fail) */ 2510 uint64_t dat_dat : 2; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2511 uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2512#else 2513 uint64_t dat_ptr : 4; 2514 uint64_t dat_dat : 2; 2515 uint64_t prt_ctl : 2; 2516 uint64_t prt_qsb : 3; 2517 uint64_t prt_qcb : 2; 2518 uint64_t ncb_inb : 2; 2519 uint64_t prt_psb : 8; 2520 uint64_t prt_nxt : 1; 2521 uint64_t prt_chk : 3; 2522 uint64_t out_wif : 1; 2523 uint64_t out_sta : 1; 2524 uint64_t out_ctl : 3; 2525 uint64_t out_dat : 1; 2526 uint64_t iob : 1; 2527 uint64_t csr : 1; 2528 uint64_t reserved_35_63 : 29; 2529#endif 2530 } cn52xx; 2531 struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; 2532 struct cvmx_pko_reg_bist_result_cn52xx cn56xx; 2533 struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; 2534 struct cvmx_pko_reg_bist_result_cn50xx cn58xx; 2535 struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; 2536 struct cvmx_pko_reg_bist_result_cn52xx cn61xx; 2537 struct cvmx_pko_reg_bist_result_cn52xx cn63xx; 2538 struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1; 2539 struct cvmx_pko_reg_bist_result_cn52xx cn66xx; 2540 struct cvmx_pko_reg_bist_result_cn68xx { 2541#ifdef __BIG_ENDIAN_BITFIELD 2542 uint64_t reserved_36_63 : 28; 2543 uint64_t crc : 1; /**< BiST result of CRC memories (0=pass, !0=fail) */ 2544 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2545 uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2546 uint64_t out_dat : 1; /**< BiST result of OUT_DAT memories (0=pass, !0=fail) */ 2547 uint64_t reserved_31_31 : 1; 2548 uint64_t out_ctl : 2; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2549 uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2550 uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2551 uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2552 uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2553 uint64_t prt_psb7 : 1; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2554 uint64_t reserved_21_21 : 1; 2555 uint64_t prt_psb : 6; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2556 uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2557 uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2558 uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2559 uint64_t prt_ctl : 2; /**< BiST result of PRT_CTL memories (0=pass, !0=fail) */ 2560 uint64_t dat_dat : 2; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2561 uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2562#else 2563 uint64_t dat_ptr : 4; 2564 uint64_t dat_dat : 2; 2565 uint64_t prt_ctl : 2; 2566 uint64_t prt_qsb : 3; 2567 uint64_t prt_qcb : 2; 2568 uint64_t ncb_inb : 2; 2569 uint64_t prt_psb : 6; 2570 uint64_t reserved_21_21 : 1; 2571 uint64_t prt_psb7 : 1; 2572 uint64_t prt_nxt : 1; 2573 uint64_t prt_chk : 3; 2574 uint64_t out_wif : 1; 2575 uint64_t out_sta : 1; 2576 uint64_t out_ctl : 2; 2577 uint64_t reserved_31_31 : 1; 2578 uint64_t out_dat : 1; 2579 uint64_t iob : 1; 2580 uint64_t csr : 1; 2581 uint64_t crc : 1; 2582 uint64_t reserved_36_63 : 28; 2583#endif 2584 } cn68xx; 2585 struct cvmx_pko_reg_bist_result_cn68xxp1 { 2586#ifdef __BIG_ENDIAN_BITFIELD 2587 uint64_t reserved_35_63 : 29; 2588 uint64_t csr : 1; /**< BiST result of CSR memories (0=pass, !0=fail) */ 2589 uint64_t iob : 1; /**< BiST result of IOB memories (0=pass, !0=fail) */ 2590 uint64_t out_dat : 1; /**< BiST result of OUT_DAT memories (0=pass, !0=fail) */ 2591 uint64_t reserved_31_31 : 1; 2592 uint64_t out_ctl : 2; /**< BiST result of OUT_CTL memories (0=pass, !0=fail) */ 2593 uint64_t out_sta : 1; /**< BiST result of OUT_STA memories (0=pass, !0=fail) */ 2594 uint64_t out_wif : 1; /**< BiST result of OUT_WIF memories (0=pass, !0=fail) */ 2595 uint64_t prt_chk : 3; /**< BiST result of PRT_CHK memories (0=pass, !0=fail) */ 2596 uint64_t prt_nxt : 1; /**< BiST result of PRT_NXT memories (0=pass, !0=fail) */ 2597 uint64_t prt_psb7 : 1; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2598 uint64_t reserved_21_21 : 1; 2599 uint64_t prt_psb : 6; /**< BiST result of PRT_PSB memories (0=pass, !0=fail) */ 2600 uint64_t ncb_inb : 2; /**< BiST result of NCB_INB memories (0=pass, !0=fail) */ 2601 uint64_t prt_qcb : 2; /**< BiST result of PRT_QCB memories (0=pass, !0=fail) */ 2602 uint64_t prt_qsb : 3; /**< BiST result of PRT_QSB memories (0=pass, !0=fail) */ 2603 uint64_t prt_ctl : 2; /**< BiST result of PRT_CTL memories (0=pass, !0=fail) */ 2604 uint64_t dat_dat : 2; /**< BiST result of DAT_DAT memories (0=pass, !0=fail) */ 2605 uint64_t dat_ptr : 4; /**< BiST result of DAT_PTR memories (0=pass, !0=fail) */ 2606#else 2607 uint64_t dat_ptr : 4; 2608 uint64_t dat_dat : 2; 2609 uint64_t prt_ctl : 2; 2610 uint64_t prt_qsb : 3; 2611 uint64_t prt_qcb : 2; 2612 uint64_t ncb_inb : 2; 2613 uint64_t prt_psb : 6; 2614 uint64_t reserved_21_21 : 1; 2615 uint64_t prt_psb7 : 1; 2616 uint64_t prt_nxt : 1; 2617 uint64_t prt_chk : 3; 2618 uint64_t out_wif : 1; 2619 uint64_t out_sta : 1; 2620 uint64_t out_ctl : 2; 2621 uint64_t reserved_31_31 : 1; 2622 uint64_t out_dat : 1; 2623 uint64_t iob : 1; 2624 uint64_t csr : 1; 2625 uint64_t reserved_35_63 : 29; 2626#endif 2627 } cn68xxp1; 2628 struct cvmx_pko_reg_bist_result_cn52xx cnf71xx; 2629}; 2630typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t; 2631 2632/** 2633 * cvmx_pko_reg_cmd_buf 2634 * 2635 * Notes: 2636 * Sets the command buffer parameters 2637 * The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free 2638 * lists to be used when freeing command buffer segments. 2639 */ 2640union cvmx_pko_reg_cmd_buf { 2641 uint64_t u64; 2642 struct cvmx_pko_reg_cmd_buf_s { 2643#ifdef __BIG_ENDIAN_BITFIELD 2644 uint64_t reserved_23_63 : 41; 2645 uint64_t pool : 3; /**< Free list used to free command buffer segments */ 2646 uint64_t reserved_13_19 : 7; 2647 uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 2648#else 2649 uint64_t size : 13; 2650 uint64_t reserved_13_19 : 7; 2651 uint64_t pool : 3; 2652 uint64_t reserved_23_63 : 41; 2653#endif 2654 } s; 2655 struct cvmx_pko_reg_cmd_buf_s cn30xx; 2656 struct cvmx_pko_reg_cmd_buf_s cn31xx; 2657 struct cvmx_pko_reg_cmd_buf_s cn38xx; 2658 struct cvmx_pko_reg_cmd_buf_s cn38xxp2; 2659 struct cvmx_pko_reg_cmd_buf_s cn50xx; 2660 struct cvmx_pko_reg_cmd_buf_s cn52xx; 2661 struct cvmx_pko_reg_cmd_buf_s cn52xxp1; 2662 struct cvmx_pko_reg_cmd_buf_s cn56xx; 2663 struct cvmx_pko_reg_cmd_buf_s cn56xxp1; 2664 struct cvmx_pko_reg_cmd_buf_s cn58xx; 2665 struct cvmx_pko_reg_cmd_buf_s cn58xxp1; 2666 struct cvmx_pko_reg_cmd_buf_s cn61xx; 2667 struct cvmx_pko_reg_cmd_buf_s cn63xx; 2668 struct cvmx_pko_reg_cmd_buf_s cn63xxp1; 2669 struct cvmx_pko_reg_cmd_buf_s cn66xx; 2670 struct cvmx_pko_reg_cmd_buf_s cn68xx; 2671 struct cvmx_pko_reg_cmd_buf_s cn68xxp1; 2672 struct cvmx_pko_reg_cmd_buf_s cnf71xx; 2673}; 2674typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t; 2675 2676/** 2677 * cvmx_pko_reg_crc_ctl# 2678 * 2679 * Notes: 2680 * Controls datapath reflection when calculating CRC 2681 * 2682 */ 2683union cvmx_pko_reg_crc_ctlx { 2684 uint64_t u64; 2685 struct cvmx_pko_reg_crc_ctlx_s { 2686#ifdef __BIG_ENDIAN_BITFIELD 2687 uint64_t reserved_2_63 : 62; 2688 uint64_t invres : 1; /**< Invert the result */ 2689 uint64_t refin : 1; /**< Reflect the bits in each byte. 2690 Byte order does not change. 2691 - 0: CRC is calculated MSB to LSB 2692 - 1: CRC is calculated MLB to MSB */ 2693#else 2694 uint64_t refin : 1; 2695 uint64_t invres : 1; 2696 uint64_t reserved_2_63 : 62; 2697#endif 2698 } s; 2699 struct cvmx_pko_reg_crc_ctlx_s cn38xx; 2700 struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; 2701 struct cvmx_pko_reg_crc_ctlx_s cn58xx; 2702 struct cvmx_pko_reg_crc_ctlx_s cn58xxp1; 2703}; 2704typedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t; 2705 2706/** 2707 * cvmx_pko_reg_crc_enable 2708 * 2709 * Notes: 2710 * Enables CRC for the GMX ports. 2711 * 2712 */ 2713union cvmx_pko_reg_crc_enable { 2714 uint64_t u64; 2715 struct cvmx_pko_reg_crc_enable_s { 2716#ifdef __BIG_ENDIAN_BITFIELD 2717 uint64_t reserved_32_63 : 32; 2718 uint64_t enable : 32; /**< Mask for ports 31-0 to enable CRC 2719 Mask bit==0 means CRC not enabled 2720 Mask bit==1 means CRC enabled 2721 Note that CRC should be enabled only when using SPI4.2 */ 2722#else 2723 uint64_t enable : 32; 2724 uint64_t reserved_32_63 : 32; 2725#endif 2726 } s; 2727 struct cvmx_pko_reg_crc_enable_s cn38xx; 2728 struct cvmx_pko_reg_crc_enable_s cn38xxp2; 2729 struct cvmx_pko_reg_crc_enable_s cn58xx; 2730 struct cvmx_pko_reg_crc_enable_s cn58xxp1; 2731}; 2732typedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t; 2733 2734/** 2735 * cvmx_pko_reg_crc_iv# 2736 * 2737 * Notes: 2738 * Determines the IV used by the CRC algorithm 2739 * * PKO_CRC_IV 2740 * PKO_CRC_IV controls the initial state of the CRC algorithm. Octane can 2741 * support a wide range of CRC algorithms and as such, the IV must be 2742 * carefully constructed to meet the specific algorithm. The code below 2743 * determines the value to program into Octane based on the algorthim's IV 2744 * and width. In the case of Octane, the width should always be 32. 2745 * 2746 * PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for 2747 * ports 16-31. 2748 * 2749 * @verbatim 2750 * unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w) 2751 * [ 2752 * int i; 2753 * int doit; 2754 * unsigned int current_val = algorithm_iv; 2755 * 2756 * for(i = 0; i < w; i++) [ 2757 * doit = current_val & 0x1; 2758 * 2759 * if(doit) current_val ^= poly; 2760 * assert(!(current_val & 0x1)); 2761 * 2762 * current_val = (current_val >> 1) | (doit << (w-1)); 2763 * ] 2764 * 2765 * return current_val; 2766 * ] 2767 * @endverbatim 2768 */ 2769union cvmx_pko_reg_crc_ivx { 2770 uint64_t u64; 2771 struct cvmx_pko_reg_crc_ivx_s { 2772#ifdef __BIG_ENDIAN_BITFIELD 2773 uint64_t reserved_32_63 : 32; 2774 uint64_t iv : 32; /**< IV used by the CRC algorithm. Default is FCS32. */ 2775#else 2776 uint64_t iv : 32; 2777 uint64_t reserved_32_63 : 32; 2778#endif 2779 } s; 2780 struct cvmx_pko_reg_crc_ivx_s cn38xx; 2781 struct cvmx_pko_reg_crc_ivx_s cn38xxp2; 2782 struct cvmx_pko_reg_crc_ivx_s cn58xx; 2783 struct cvmx_pko_reg_crc_ivx_s cn58xxp1; 2784}; 2785typedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t; 2786 2787/** 2788 * cvmx_pko_reg_debug0 2789 * 2790 * Notes: 2791 * Note that this CSR is present only in chip revisions beginning with pass2. 2792 * 2793 */ 2794union cvmx_pko_reg_debug0 { 2795 uint64_t u64; 2796 struct cvmx_pko_reg_debug0_s { 2797#ifdef __BIG_ENDIAN_BITFIELD 2798 uint64_t asserts : 64; /**< Various assertion checks */ 2799#else 2800 uint64_t asserts : 64; 2801#endif 2802 } s; 2803 struct cvmx_pko_reg_debug0_cn30xx { 2804#ifdef __BIG_ENDIAN_BITFIELD 2805 uint64_t reserved_17_63 : 47; 2806 uint64_t asserts : 17; /**< Various assertion checks */ 2807#else 2808 uint64_t asserts : 17; 2809 uint64_t reserved_17_63 : 47; 2810#endif 2811 } cn30xx; 2812 struct cvmx_pko_reg_debug0_cn30xx cn31xx; 2813 struct cvmx_pko_reg_debug0_cn30xx cn38xx; 2814 struct cvmx_pko_reg_debug0_cn30xx cn38xxp2; 2815 struct cvmx_pko_reg_debug0_s cn50xx; 2816 struct cvmx_pko_reg_debug0_s cn52xx; 2817 struct cvmx_pko_reg_debug0_s cn52xxp1; 2818 struct cvmx_pko_reg_debug0_s cn56xx; 2819 struct cvmx_pko_reg_debug0_s cn56xxp1; 2820 struct cvmx_pko_reg_debug0_s cn58xx; 2821 struct cvmx_pko_reg_debug0_s cn58xxp1; 2822 struct cvmx_pko_reg_debug0_s cn61xx; 2823 struct cvmx_pko_reg_debug0_s cn63xx; 2824 struct cvmx_pko_reg_debug0_s cn63xxp1; 2825 struct cvmx_pko_reg_debug0_s cn66xx; 2826 struct cvmx_pko_reg_debug0_s cn68xx; 2827 struct cvmx_pko_reg_debug0_s cn68xxp1; 2828 struct cvmx_pko_reg_debug0_s cnf71xx; 2829}; 2830typedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t; 2831 2832/** 2833 * cvmx_pko_reg_debug1 2834 */ 2835union cvmx_pko_reg_debug1 { 2836 uint64_t u64; 2837 struct cvmx_pko_reg_debug1_s { 2838#ifdef __BIG_ENDIAN_BITFIELD 2839 uint64_t asserts : 64; /**< Various assertion checks */ 2840#else 2841 uint64_t asserts : 64; 2842#endif 2843 } s; 2844 struct cvmx_pko_reg_debug1_s cn50xx; 2845 struct cvmx_pko_reg_debug1_s cn52xx; 2846 struct cvmx_pko_reg_debug1_s cn52xxp1; 2847 struct cvmx_pko_reg_debug1_s cn56xx; 2848 struct cvmx_pko_reg_debug1_s cn56xxp1; 2849 struct cvmx_pko_reg_debug1_s cn58xx; 2850 struct cvmx_pko_reg_debug1_s cn58xxp1; 2851 struct cvmx_pko_reg_debug1_s cn61xx; 2852 struct cvmx_pko_reg_debug1_s cn63xx; 2853 struct cvmx_pko_reg_debug1_s cn63xxp1; 2854 struct cvmx_pko_reg_debug1_s cn66xx; 2855 struct cvmx_pko_reg_debug1_s cn68xx; 2856 struct cvmx_pko_reg_debug1_s cn68xxp1; 2857 struct cvmx_pko_reg_debug1_s cnf71xx; 2858}; 2859typedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t; 2860 2861/** 2862 * cvmx_pko_reg_debug2 2863 */ 2864union cvmx_pko_reg_debug2 { 2865 uint64_t u64; 2866 struct cvmx_pko_reg_debug2_s { 2867#ifdef __BIG_ENDIAN_BITFIELD 2868 uint64_t asserts : 64; /**< Various assertion checks */ 2869#else 2870 uint64_t asserts : 64; 2871#endif 2872 } s; 2873 struct cvmx_pko_reg_debug2_s cn50xx; 2874 struct cvmx_pko_reg_debug2_s cn52xx; 2875 struct cvmx_pko_reg_debug2_s cn52xxp1; 2876 struct cvmx_pko_reg_debug2_s cn56xx; 2877 struct cvmx_pko_reg_debug2_s cn56xxp1; 2878 struct cvmx_pko_reg_debug2_s cn58xx; 2879 struct cvmx_pko_reg_debug2_s cn58xxp1; 2880 struct cvmx_pko_reg_debug2_s cn61xx; 2881 struct cvmx_pko_reg_debug2_s cn63xx; 2882 struct cvmx_pko_reg_debug2_s cn63xxp1; 2883 struct cvmx_pko_reg_debug2_s cn66xx; 2884 struct cvmx_pko_reg_debug2_s cn68xx; 2885 struct cvmx_pko_reg_debug2_s cn68xxp1; 2886 struct cvmx_pko_reg_debug2_s cnf71xx; 2887}; 2888typedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t; 2889 2890/** 2891 * cvmx_pko_reg_debug3 2892 */ 2893union cvmx_pko_reg_debug3 { 2894 uint64_t u64; 2895 struct cvmx_pko_reg_debug3_s { 2896#ifdef __BIG_ENDIAN_BITFIELD 2897 uint64_t asserts : 64; /**< Various assertion checks */ 2898#else 2899 uint64_t asserts : 64; 2900#endif 2901 } s; 2902 struct cvmx_pko_reg_debug3_s cn50xx; 2903 struct cvmx_pko_reg_debug3_s cn52xx; 2904 struct cvmx_pko_reg_debug3_s cn52xxp1; 2905 struct cvmx_pko_reg_debug3_s cn56xx; 2906 struct cvmx_pko_reg_debug3_s cn56xxp1; 2907 struct cvmx_pko_reg_debug3_s cn58xx; 2908 struct cvmx_pko_reg_debug3_s cn58xxp1; 2909 struct cvmx_pko_reg_debug3_s cn61xx; 2910 struct cvmx_pko_reg_debug3_s cn63xx; 2911 struct cvmx_pko_reg_debug3_s cn63xxp1; 2912 struct cvmx_pko_reg_debug3_s cn66xx; 2913 struct cvmx_pko_reg_debug3_s cn68xx; 2914 struct cvmx_pko_reg_debug3_s cn68xxp1; 2915 struct cvmx_pko_reg_debug3_s cnf71xx; 2916}; 2917typedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t; 2918 2919/** 2920 * cvmx_pko_reg_debug4 2921 */ 2922union cvmx_pko_reg_debug4 { 2923 uint64_t u64; 2924 struct cvmx_pko_reg_debug4_s { 2925#ifdef __BIG_ENDIAN_BITFIELD 2926 uint64_t asserts : 64; /**< Various assertion checks */ 2927#else 2928 uint64_t asserts : 64; 2929#endif 2930 } s; 2931 struct cvmx_pko_reg_debug4_s cn68xx; 2932 struct cvmx_pko_reg_debug4_s cn68xxp1; 2933}; 2934typedef union cvmx_pko_reg_debug4 cvmx_pko_reg_debug4_t; 2935 2936/** 2937 * cvmx_pko_reg_engine_inflight 2938 * 2939 * Notes: 2940 * Sets the maximum number of inflight packets, per engine. Values greater than 4 are illegal. 2941 * Setting an engine's value to 0 effectively stops the engine. 2942 */ 2943union cvmx_pko_reg_engine_inflight { 2944 uint64_t u64; 2945 struct cvmx_pko_reg_engine_inflight_s { 2946#ifdef __BIG_ENDIAN_BITFIELD 2947 uint64_t engine15 : 4; /**< Maximum number of inflight packets for engine15 */ 2948 uint64_t engine14 : 4; /**< Maximum number of inflight packets for engine14 */ 2949 uint64_t engine13 : 4; /**< Maximum number of inflight packets for engine13 */ 2950 uint64_t engine12 : 4; /**< Maximum number of inflight packets for engine12 */ 2951 uint64_t engine11 : 4; /**< Maximum number of inflight packets for engine11 */ 2952 uint64_t engine10 : 4; /**< Maximum number of inflight packets for engine10 */ 2953 uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 2954 uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 2955 uint64_t engine7 : 4; /**< Maximum number of inflight packets for engine7 */ 2956 uint64_t engine6 : 4; /**< Maximum number of inflight packets for engine6 */ 2957 uint64_t engine5 : 4; /**< Maximum number of inflight packets for engine5 */ 2958 uint64_t engine4 : 4; /**< Maximum number of inflight packets for engine4 */ 2959 uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 2960 uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 2961 uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 2962 uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 2963#else 2964 uint64_t engine0 : 4; 2965 uint64_t engine1 : 4; 2966 uint64_t engine2 : 4; 2967 uint64_t engine3 : 4; 2968 uint64_t engine4 : 4; 2969 uint64_t engine5 : 4; 2970 uint64_t engine6 : 4; 2971 uint64_t engine7 : 4; 2972 uint64_t engine8 : 4; 2973 uint64_t engine9 : 4; 2974 uint64_t engine10 : 4; 2975 uint64_t engine11 : 4; 2976 uint64_t engine12 : 4; 2977 uint64_t engine13 : 4; 2978 uint64_t engine14 : 4; 2979 uint64_t engine15 : 4; 2980#endif 2981 } s; 2982 struct cvmx_pko_reg_engine_inflight_cn52xx { 2983#ifdef __BIG_ENDIAN_BITFIELD 2984 uint64_t reserved_40_63 : 24; 2985 uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 2986 uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 2987 uint64_t engine7 : 4; /**< MBZ */ 2988 uint64_t engine6 : 4; /**< MBZ */ 2989 uint64_t engine5 : 4; /**< MBZ */ 2990 uint64_t engine4 : 4; /**< MBZ */ 2991 uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 2992 uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 2993 uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 2994 uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 2995#else 2996 uint64_t engine0 : 4; 2997 uint64_t engine1 : 4; 2998 uint64_t engine2 : 4; 2999 uint64_t engine3 : 4; 3000 uint64_t engine4 : 4; 3001 uint64_t engine5 : 4; 3002 uint64_t engine6 : 4; 3003 uint64_t engine7 : 4; 3004 uint64_t engine8 : 4; 3005 uint64_t engine9 : 4; 3006 uint64_t reserved_40_63 : 24; 3007#endif 3008 } cn52xx; 3009 struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1; 3010 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx; 3011 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1; 3012 struct cvmx_pko_reg_engine_inflight_cn61xx { 3013#ifdef __BIG_ENDIAN_BITFIELD 3014 uint64_t reserved_56_63 : 8; 3015 uint64_t engine13 : 4; /**< Maximum number of inflight packets for engine13 */ 3016 uint64_t engine12 : 4; /**< Maximum number of inflight packets for engine12 */ 3017 uint64_t engine11 : 4; /**< Maximum number of inflight packets for engine11 */ 3018 uint64_t engine10 : 4; /**< Maximum number of inflight packets for engine10 */ 3019 uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 3020 uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 3021 uint64_t engine7 : 4; /**< Maximum number of inflight packets for engine7 */ 3022 uint64_t engine6 : 4; /**< Maximum number of inflight packets for engine6 */ 3023 uint64_t engine5 : 4; /**< Maximum number of inflight packets for engine5 */ 3024 uint64_t engine4 : 4; /**< Maximum number of inflight packets for engine4 */ 3025 uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 3026 uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 3027 uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 3028 uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 3029#else 3030 uint64_t engine0 : 4; 3031 uint64_t engine1 : 4; 3032 uint64_t engine2 : 4; 3033 uint64_t engine3 : 4; 3034 uint64_t engine4 : 4; 3035 uint64_t engine5 : 4; 3036 uint64_t engine6 : 4; 3037 uint64_t engine7 : 4; 3038 uint64_t engine8 : 4; 3039 uint64_t engine9 : 4; 3040 uint64_t engine10 : 4; 3041 uint64_t engine11 : 4; 3042 uint64_t engine12 : 4; 3043 uint64_t engine13 : 4; 3044 uint64_t reserved_56_63 : 8; 3045#endif 3046 } cn61xx; 3047 struct cvmx_pko_reg_engine_inflight_cn63xx { 3048#ifdef __BIG_ENDIAN_BITFIELD 3049 uint64_t reserved_48_63 : 16; 3050 uint64_t engine11 : 4; /**< Maximum number of inflight packets for engine11 */ 3051 uint64_t engine10 : 4; /**< Maximum number of inflight packets for engine10 */ 3052 uint64_t engine9 : 4; /**< Maximum number of inflight packets for engine9 */ 3053 uint64_t engine8 : 4; /**< Maximum number of inflight packets for engine8 */ 3054 uint64_t engine7 : 4; /**< MBZ */ 3055 uint64_t engine6 : 4; /**< MBZ */ 3056 uint64_t engine5 : 4; /**< MBZ */ 3057 uint64_t engine4 : 4; /**< MBZ */ 3058 uint64_t engine3 : 4; /**< Maximum number of inflight packets for engine3 */ 3059 uint64_t engine2 : 4; /**< Maximum number of inflight packets for engine2 */ 3060 uint64_t engine1 : 4; /**< Maximum number of inflight packets for engine1 */ 3061 uint64_t engine0 : 4; /**< Maximum number of inflight packets for engine0 */ 3062#else 3063 uint64_t engine0 : 4; 3064 uint64_t engine1 : 4; 3065 uint64_t engine2 : 4; 3066 uint64_t engine3 : 4; 3067 uint64_t engine4 : 4; 3068 uint64_t engine5 : 4; 3069 uint64_t engine6 : 4; 3070 uint64_t engine7 : 4; 3071 uint64_t engine8 : 4; 3072 uint64_t engine9 : 4; 3073 uint64_t engine10 : 4; 3074 uint64_t engine11 : 4; 3075 uint64_t reserved_48_63 : 16; 3076#endif 3077 } cn63xx; 3078 struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1; 3079 struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx; 3080 struct cvmx_pko_reg_engine_inflight_s cn68xx; 3081 struct cvmx_pko_reg_engine_inflight_s cn68xxp1; 3082 struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx; 3083}; 3084typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t; 3085 3086/** 3087 * cvmx_pko_reg_engine_inflight1 3088 * 3089 * Notes: 3090 * Sets the maximum number of inflight packets, per engine. Values greater than 8 are illegal. 3091 * Setting an engine's value to 0 effectively stops the engine. 3092 */ 3093union cvmx_pko_reg_engine_inflight1 { 3094 uint64_t u64; 3095 struct cvmx_pko_reg_engine_inflight1_s { 3096#ifdef __BIG_ENDIAN_BITFIELD 3097 uint64_t reserved_16_63 : 48; 3098 uint64_t engine19 : 4; /**< Maximum number of inflight packets for engine19 */ 3099 uint64_t engine18 : 4; /**< Maximum number of inflight packets for engine18 */ 3100 uint64_t engine17 : 4; /**< Maximum number of inflight packets for engine17 */ 3101 uint64_t engine16 : 4; /**< Maximum number of inflight packets for engine16 */ 3102#else 3103 uint64_t engine16 : 4; 3104 uint64_t engine17 : 4; 3105 uint64_t engine18 : 4; 3106 uint64_t engine19 : 4; 3107 uint64_t reserved_16_63 : 48; 3108#endif 3109 } s; 3110 struct cvmx_pko_reg_engine_inflight1_s cn68xx; 3111 struct cvmx_pko_reg_engine_inflight1_s cn68xxp1; 3112}; 3113typedef union cvmx_pko_reg_engine_inflight1 cvmx_pko_reg_engine_inflight1_t; 3114 3115/** 3116 * cvmx_pko_reg_engine_storage# 3117 * 3118 * Notes: 3119 * The PKO has 40KB of local storage, consisting of 20, 2KB chunks. Up to 15 contiguous chunks may be mapped per engine. 3120 * The total of all mapped storage must not exceed 40KB. 3121 */ 3122union cvmx_pko_reg_engine_storagex { 3123 uint64_t u64; 3124 struct cvmx_pko_reg_engine_storagex_s { 3125#ifdef __BIG_ENDIAN_BITFIELD 3126 uint64_t engine15 : 4; /**< Number of contiguous 2KB chunks allocated to 3127 engine (X * 16) + 15. 3128 ENGINE15 does not exist and is reserved in 3129 PKO_REG_ENGINE_STORAGE1. */ 3130 uint64_t engine14 : 4; /**< Number of contiguous 2KB chunks allocated to 3131 engine (X * 16) + 14. 3132 ENGINE14 does not exist and is reserved in 3133 PKO_REG_ENGINE_STORAGE1. */ 3134 uint64_t engine13 : 4; /**< Number of contiguous 2KB chunks allocated to 3135 engine (X * 16) + 13. 3136 ENGINE13 does not exist and is reserved in 3137 PKO_REG_ENGINE_STORAGE1. */ 3138 uint64_t engine12 : 4; /**< Number of contiguous 2KB chunks allocated to 3139 engine (X * 16) + 12. 3140 ENGINE12 does not exist and is reserved in 3141 PKO_REG_ENGINE_STORAGE1. */ 3142 uint64_t engine11 : 4; /**< Number of contiguous 2KB chunks allocated to 3143 engine (X * 16) + 11. 3144 ENGINE11 does not exist and is reserved in 3145 PKO_REG_ENGINE_STORAGE1. */ 3146 uint64_t engine10 : 4; /**< Number of contiguous 2KB chunks allocated to 3147 engine (X * 16) + 10. 3148 ENGINE10 does not exist and is reserved in 3149 PKO_REG_ENGINE_STORAGE1. */ 3150 uint64_t engine9 : 4; /**< Number of contiguous 2KB chunks allocated to 3151 engine (X * 16) + 9. 3152 ENGINE9 does not exist and is reserved in 3153 PKO_REG_ENGINE_STORAGE1. */ 3154 uint64_t engine8 : 4; /**< Number of contiguous 2KB chunks allocated to 3155 engine (X * 16) + 8. 3156 ENGINE8 does not exist and is reserved in 3157 PKO_REG_ENGINE_STORAGE1. */ 3158 uint64_t engine7 : 4; /**< Number of contiguous 2KB chunks allocated to 3159 engine (X * 16) + 7. 3160 ENGINE7 does not exist and is reserved in 3161 PKO_REG_ENGINE_STORAGE1. */ 3162 uint64_t engine6 : 4; /**< Number of contiguous 2KB chunks allocated to 3163 engine (X * 16) + 6. 3164 ENGINE6 does not exist and is reserved in 3165 PKO_REG_ENGINE_STORAGE1. */ 3166 uint64_t engine5 : 4; /**< Number of contiguous 2KB chunks allocated to 3167 engine (X * 16) + 5. 3168 ENGINE5 does not exist and is reserved in 3169 PKO_REG_ENGINE_STORAGE1. */ 3170 uint64_t engine4 : 4; /**< Number of contiguous 2KB chunks allocated to 3171 engine (X * 16) + 4. 3172 ENGINE4 does not exist and is reserved in 3173 PKO_REG_ENGINE_STORAGE1. */ 3174 uint64_t engine3 : 4; /**< Number of contiguous 2KB chunks allocated to 3175 engine (X * 16) + 3. */ 3176 uint64_t engine2 : 4; /**< Number of contiguous 2KB chunks allocated to 3177 engine (X * 16) + 2. */ 3178 uint64_t engine1 : 4; /**< Number of contiguous 2KB chunks allocated to 3179 engine (X * 16) + 1. */ 3180 uint64_t engine0 : 4; /**< Number of contiguous 2KB chunks allocated to 3181 engine (X * 16) + 0. */ 3182#else 3183 uint64_t engine0 : 4; 3184 uint64_t engine1 : 4; 3185 uint64_t engine2 : 4; 3186 uint64_t engine3 : 4; 3187 uint64_t engine4 : 4; 3188 uint64_t engine5 : 4; 3189 uint64_t engine6 : 4; 3190 uint64_t engine7 : 4; 3191 uint64_t engine8 : 4; 3192 uint64_t engine9 : 4; 3193 uint64_t engine10 : 4; 3194 uint64_t engine11 : 4; 3195 uint64_t engine12 : 4; 3196 uint64_t engine13 : 4; 3197 uint64_t engine14 : 4; 3198 uint64_t engine15 : 4; 3199#endif 3200 } s; 3201 struct cvmx_pko_reg_engine_storagex_s cn68xx; 3202 struct cvmx_pko_reg_engine_storagex_s cn68xxp1; 3203}; 3204typedef union cvmx_pko_reg_engine_storagex cvmx_pko_reg_engine_storagex_t; 3205 3206/** 3207 * cvmx_pko_reg_engine_thresh 3208 * 3209 * Notes: 3210 * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers. 3211 * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will 3212 * be sent until all of it has been written into the PKO's internal buffer. Note that a packet is 3213 * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8. When enabled and the 3214 * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until 3215 * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer 3216 * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above) 3217 */ 3218union cvmx_pko_reg_engine_thresh { 3219 uint64_t u64; 3220 struct cvmx_pko_reg_engine_thresh_s { 3221#ifdef __BIG_ENDIAN_BITFIELD 3222 uint64_t reserved_20_63 : 44; 3223 uint64_t mask : 20; /**< Mask[n]=0 disables packet send threshold for engine n 3224 Mask[n]=1 enables packet send threshold for engine n $PR NS */ 3225#else 3226 uint64_t mask : 20; 3227 uint64_t reserved_20_63 : 44; 3228#endif 3229 } s; 3230 struct cvmx_pko_reg_engine_thresh_cn52xx { 3231#ifdef __BIG_ENDIAN_BITFIELD 3232 uint64_t reserved_10_63 : 54; 3233 uint64_t mask : 10; /**< Mask[n]=0 disables packet send threshold for eng n 3234 Mask[n]=1 enables packet send threshold for eng n $PR NS 3235 Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */ 3236#else 3237 uint64_t mask : 10; 3238 uint64_t reserved_10_63 : 54; 3239#endif 3240 } cn52xx; 3241 struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1; 3242 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx; 3243 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1; 3244 struct cvmx_pko_reg_engine_thresh_cn61xx { 3245#ifdef __BIG_ENDIAN_BITFIELD 3246 uint64_t reserved_14_63 : 50; 3247 uint64_t mask : 14; /**< Mask[n]=0 disables packet send threshold for engine n 3248 Mask[n]=1 enables packet send threshold for engine n $PR NS */ 3249#else 3250 uint64_t mask : 14; 3251 uint64_t reserved_14_63 : 50; 3252#endif 3253 } cn61xx; 3254 struct cvmx_pko_reg_engine_thresh_cn63xx { 3255#ifdef __BIG_ENDIAN_BITFIELD 3256 uint64_t reserved_12_63 : 52; 3257 uint64_t mask : 12; /**< Mask[n]=0 disables packet send threshold for engine n 3258 Mask[n]=1 enables packet send threshold for engine n $PR NS 3259 Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */ 3260#else 3261 uint64_t mask : 12; 3262 uint64_t reserved_12_63 : 52; 3263#endif 3264 } cn63xx; 3265 struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1; 3266 struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx; 3267 struct cvmx_pko_reg_engine_thresh_s cn68xx; 3268 struct cvmx_pko_reg_engine_thresh_s cn68xxp1; 3269 struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx; 3270}; 3271typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t; 3272 3273/** 3274 * cvmx_pko_reg_error 3275 * 3276 * Notes: 3277 * Note that this CSR is present only in chip revisions beginning with pass2. 3278 * 3279 */ 3280union cvmx_pko_reg_error { 3281 uint64_t u64; 3282 struct cvmx_pko_reg_error_s { 3283#ifdef __BIG_ENDIAN_BITFIELD 3284 uint64_t reserved_4_63 : 60; 3285 uint64_t loopback : 1; /**< A packet was sent to an illegal loopback port */ 3286 uint64_t currzero : 1; /**< A packet data pointer has size=0 */ 3287 uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 3288 uint64_t parity : 1; /**< Read parity error at port data buffer */ 3289#else 3290 uint64_t parity : 1; 3291 uint64_t doorbell : 1; 3292 uint64_t currzero : 1; 3293 uint64_t loopback : 1; 3294 uint64_t reserved_4_63 : 60; 3295#endif 3296 } s; 3297 struct cvmx_pko_reg_error_cn30xx { 3298#ifdef __BIG_ENDIAN_BITFIELD 3299 uint64_t reserved_2_63 : 62; 3300 uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 3301 uint64_t parity : 1; /**< Read parity error at port data buffer */ 3302#else 3303 uint64_t parity : 1; 3304 uint64_t doorbell : 1; 3305 uint64_t reserved_2_63 : 62; 3306#endif 3307 } cn30xx; 3308 struct cvmx_pko_reg_error_cn30xx cn31xx; 3309 struct cvmx_pko_reg_error_cn30xx cn38xx; 3310 struct cvmx_pko_reg_error_cn30xx cn38xxp2; 3311 struct cvmx_pko_reg_error_cn50xx { 3312#ifdef __BIG_ENDIAN_BITFIELD 3313 uint64_t reserved_3_63 : 61; 3314 uint64_t currzero : 1; /**< A packet data pointer has size=0 */ 3315 uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 3316 uint64_t parity : 1; /**< Read parity error at port data buffer */ 3317#else 3318 uint64_t parity : 1; 3319 uint64_t doorbell : 1; 3320 uint64_t currzero : 1; 3321 uint64_t reserved_3_63 : 61; 3322#endif 3323 } cn50xx; 3324 struct cvmx_pko_reg_error_cn50xx cn52xx; 3325 struct cvmx_pko_reg_error_cn50xx cn52xxp1; 3326 struct cvmx_pko_reg_error_cn50xx cn56xx; 3327 struct cvmx_pko_reg_error_cn50xx cn56xxp1; 3328 struct cvmx_pko_reg_error_cn50xx cn58xx; 3329 struct cvmx_pko_reg_error_cn50xx cn58xxp1; 3330 struct cvmx_pko_reg_error_cn50xx cn61xx; 3331 struct cvmx_pko_reg_error_cn50xx cn63xx; 3332 struct cvmx_pko_reg_error_cn50xx cn63xxp1; 3333 struct cvmx_pko_reg_error_cn50xx cn66xx; 3334 struct cvmx_pko_reg_error_s cn68xx; 3335 struct cvmx_pko_reg_error_s cn68xxp1; 3336 struct cvmx_pko_reg_error_cn50xx cnf71xx; 3337}; 3338typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t; 3339 3340/** 3341 * cvmx_pko_reg_flags 3342 * 3343 * Notes: 3344 * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation. When set, ENA_DWB 3345 * enables the use of DontWriteBacks during the buffer freeing operations. When not set, STORE_BE inverts 3346 * bits[2:0] of the STORE0 byte write address. When set, RESET causes a 4-cycle reset pulse to the 3347 * entire box. 3348 */ 3349union cvmx_pko_reg_flags { 3350 uint64_t u64; 3351 struct cvmx_pko_reg_flags_s { 3352#ifdef __BIG_ENDIAN_BITFIELD 3353 uint64_t reserved_9_63 : 55; 3354 uint64_t dis_perf3 : 1; /**< Set to disable inactive queue QOS skipping */ 3355 uint64_t dis_perf2 : 1; /**< Set to disable inactive queue skipping */ 3356 uint64_t dis_perf1 : 1; /**< Set to disable command word prefetching */ 3357 uint64_t dis_perf0 : 1; /**< Set to disable read performance optimizations */ 3358 uint64_t ena_throttle : 1; /**< Set to enable the PKO picker throttle logic 3359 When ENA_THROTTLE=1 and the most-significant 3360 bit of any of the pipe or interface, word or 3361 packet throttle count is set, then PKO will 3362 not output any packets to the interface/pipe. 3363 See PKO_MEM_THROTTLE_PIPE and 3364 PKO_MEM_THROTTLE_INT. */ 3365 uint64_t reset : 1; /**< Reset oneshot pulse */ 3366 uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3367 uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3368 uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3369#else 3370 uint64_t ena_pko : 1; 3371 uint64_t ena_dwb : 1; 3372 uint64_t store_be : 1; 3373 uint64_t reset : 1; 3374 uint64_t ena_throttle : 1; 3375 uint64_t dis_perf0 : 1; 3376 uint64_t dis_perf1 : 1; 3377 uint64_t dis_perf2 : 1; 3378 uint64_t dis_perf3 : 1; 3379 uint64_t reserved_9_63 : 55; 3380#endif 3381 } s; 3382 struct cvmx_pko_reg_flags_cn30xx { 3383#ifdef __BIG_ENDIAN_BITFIELD 3384 uint64_t reserved_4_63 : 60; 3385 uint64_t reset : 1; /**< Reset oneshot pulse */ 3386 uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3387 uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3388 uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3389#else 3390 uint64_t ena_pko : 1; 3391 uint64_t ena_dwb : 1; 3392 uint64_t store_be : 1; 3393 uint64_t reset : 1; 3394 uint64_t reserved_4_63 : 60; 3395#endif 3396 } cn30xx; 3397 struct cvmx_pko_reg_flags_cn30xx cn31xx; 3398 struct cvmx_pko_reg_flags_cn30xx cn38xx; 3399 struct cvmx_pko_reg_flags_cn30xx cn38xxp2; 3400 struct cvmx_pko_reg_flags_cn30xx cn50xx; 3401 struct cvmx_pko_reg_flags_cn30xx cn52xx; 3402 struct cvmx_pko_reg_flags_cn30xx cn52xxp1; 3403 struct cvmx_pko_reg_flags_cn30xx cn56xx; 3404 struct cvmx_pko_reg_flags_cn30xx cn56xxp1; 3405 struct cvmx_pko_reg_flags_cn30xx cn58xx; 3406 struct cvmx_pko_reg_flags_cn30xx cn58xxp1; 3407 struct cvmx_pko_reg_flags_cn61xx { 3408#ifdef __BIG_ENDIAN_BITFIELD 3409 uint64_t reserved_9_63 : 55; 3410 uint64_t dis_perf3 : 1; /**< Set to disable inactive queue QOS skipping */ 3411 uint64_t dis_perf2 : 1; /**< Set to disable inactive queue skipping */ 3412 uint64_t reserved_4_6 : 3; 3413 uint64_t reset : 1; /**< Reset oneshot pulse */ 3414 uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3415 uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3416 uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3417#else 3418 uint64_t ena_pko : 1; 3419 uint64_t ena_dwb : 1; 3420 uint64_t store_be : 1; 3421 uint64_t reset : 1; 3422 uint64_t reserved_4_6 : 3; 3423 uint64_t dis_perf2 : 1; 3424 uint64_t dis_perf3 : 1; 3425 uint64_t reserved_9_63 : 55; 3426#endif 3427 } cn61xx; 3428 struct cvmx_pko_reg_flags_cn30xx cn63xx; 3429 struct cvmx_pko_reg_flags_cn30xx cn63xxp1; 3430 struct cvmx_pko_reg_flags_cn61xx cn66xx; 3431 struct cvmx_pko_reg_flags_s cn68xx; 3432 struct cvmx_pko_reg_flags_cn68xxp1 { 3433#ifdef __BIG_ENDIAN_BITFIELD 3434 uint64_t reserved_7_63 : 57; 3435 uint64_t dis_perf1 : 1; /**< Set to disable command word prefetching */ 3436 uint64_t dis_perf0 : 1; /**< Set to disable read performance optimizations */ 3437 uint64_t ena_throttle : 1; /**< Set to enable the PKO picker throttle logic 3438 When ENA_THROTTLE=1 and the most-significant 3439 bit of any of the pipe or interface, word or 3440 packet throttle count is set, then PKO will 3441 not output any packets to the interface/pipe. 3442 See PKO_MEM_THROTTLE_PIPE and 3443 PKO_MEM_THROTTLE_INT. */ 3444 uint64_t reset : 1; /**< Reset oneshot pulse */ 3445 uint64_t store_be : 1; /**< Force STORE0 byte write address to big endian */ 3446 uint64_t ena_dwb : 1; /**< Set to enable DontWriteBacks */ 3447 uint64_t ena_pko : 1; /**< Set to enable the PKO picker */ 3448#else 3449 uint64_t ena_pko : 1; 3450 uint64_t ena_dwb : 1; 3451 uint64_t store_be : 1; 3452 uint64_t reset : 1; 3453 uint64_t ena_throttle : 1; 3454 uint64_t dis_perf0 : 1; 3455 uint64_t dis_perf1 : 1; 3456 uint64_t reserved_7_63 : 57; 3457#endif 3458 } cn68xxp1; 3459 struct cvmx_pko_reg_flags_cn61xx cnf71xx; 3460}; 3461typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t; 3462 3463/** 3464 * cvmx_pko_reg_gmx_port_mode 3465 * 3466 * Notes: 3467 * The system has a total of 4 + 4 + 4 + 4 + 4 ports and 4 + 4 + 1 + 1 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP + SRIO0 + SRIO1 + SRIO2 + SRIO3). 3468 * This CSR sets the number of GMX0/GMX1 ports and amount of local storage per engine. 3469 * It has no effect on the number of ports or amount of local storage per engine for PCI, LOOP, 3470 * SRIO0, SRIO1, SRIO2, or SRIO3. When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local 3471 * storage. Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and 3472 * increases the local storage per PKO GMX engine by a power of 2. If one of the modes is 5, then only 3473 * one of interfaces GM0 or GM1 is present and the storage per engine of the existing interface is 3474 * doubled. Modes 0 and 1 are illegal and, if selected, are treated as mode 2. 3475 * 3476 * MODE[n] GM[n] PCI LOOP GM[n] PCI LOOP SRIO[n] 3477 * ports ports ports storage/engine storage/engine storage/engine storage/engine 3478 * 0 4 4 4 ( 2.5kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3479 * 1 4 4 4 ( 2.5kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3480 * 2 4 4 4 ( 2.5kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3481 * 3 2 4 4 ( 5.0kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3482 * 4 1 4 4 (10.0kB << (MODE[1-n]==5)) 2.5kB 2.5kB 2.5kB 3483 * 5 0 4 4 ( 0kB ) 2.5kB 2.5kB 2.5kB 3484 * where 0 <= n <= 1 3485 */ 3486union cvmx_pko_reg_gmx_port_mode { 3487 uint64_t u64; 3488 struct cvmx_pko_reg_gmx_port_mode_s { 3489#ifdef __BIG_ENDIAN_BITFIELD 3490 uint64_t reserved_6_63 : 58; 3491 uint64_t mode1 : 3; /**< # of GM1 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */ 3492 uint64_t mode0 : 3; /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */ 3493#else 3494 uint64_t mode0 : 3; 3495 uint64_t mode1 : 3; 3496 uint64_t reserved_6_63 : 58; 3497#endif 3498 } s; 3499 struct cvmx_pko_reg_gmx_port_mode_s cn30xx; 3500 struct cvmx_pko_reg_gmx_port_mode_s cn31xx; 3501 struct cvmx_pko_reg_gmx_port_mode_s cn38xx; 3502 struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2; 3503 struct cvmx_pko_reg_gmx_port_mode_s cn50xx; 3504 struct cvmx_pko_reg_gmx_port_mode_s cn52xx; 3505 struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1; 3506 struct cvmx_pko_reg_gmx_port_mode_s cn56xx; 3507 struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; 3508 struct cvmx_pko_reg_gmx_port_mode_s cn58xx; 3509 struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; 3510 struct cvmx_pko_reg_gmx_port_mode_s cn61xx; 3511 struct cvmx_pko_reg_gmx_port_mode_s cn63xx; 3512 struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1; 3513 struct cvmx_pko_reg_gmx_port_mode_s cn66xx; 3514 struct cvmx_pko_reg_gmx_port_mode_s cnf71xx; 3515}; 3516typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t; 3517 3518/** 3519 * cvmx_pko_reg_int_mask 3520 * 3521 * Notes: 3522 * When a mask bit is set, the corresponding interrupt is enabled. 3523 * 3524 */ 3525union cvmx_pko_reg_int_mask { 3526 uint64_t u64; 3527 struct cvmx_pko_reg_int_mask_s { 3528#ifdef __BIG_ENDIAN_BITFIELD 3529 uint64_t reserved_4_63 : 60; 3530 uint64_t loopback : 1; /**< Bit mask corresponding to PKO_REG_ERROR[3] above */ 3531 uint64_t currzero : 1; /**< Bit mask corresponding to PKO_REG_ERROR[2] above */ 3532 uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */ 3533 uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */ 3534#else 3535 uint64_t parity : 1; 3536 uint64_t doorbell : 1; 3537 uint64_t currzero : 1; 3538 uint64_t loopback : 1; 3539 uint64_t reserved_4_63 : 60; 3540#endif 3541 } s; 3542 struct cvmx_pko_reg_int_mask_cn30xx { 3543#ifdef __BIG_ENDIAN_BITFIELD 3544 uint64_t reserved_2_63 : 62; 3545 uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */ 3546 uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */ 3547#else 3548 uint64_t parity : 1; 3549 uint64_t doorbell : 1; 3550 uint64_t reserved_2_63 : 62; 3551#endif 3552 } cn30xx; 3553 struct cvmx_pko_reg_int_mask_cn30xx cn31xx; 3554 struct cvmx_pko_reg_int_mask_cn30xx cn38xx; 3555 struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; 3556 struct cvmx_pko_reg_int_mask_cn50xx { 3557#ifdef __BIG_ENDIAN_BITFIELD 3558 uint64_t reserved_3_63 : 61; 3559 uint64_t currzero : 1; /**< Bit mask corresponding to PKO_REG_ERROR[2] above */ 3560 uint64_t doorbell : 1; /**< Bit mask corresponding to PKO_REG_ERROR[1] above */ 3561 uint64_t parity : 1; /**< Bit mask corresponding to PKO_REG_ERROR[0] above */ 3562#else 3563 uint64_t parity : 1; 3564 uint64_t doorbell : 1; 3565 uint64_t currzero : 1; 3566 uint64_t reserved_3_63 : 61; 3567#endif 3568 } cn50xx; 3569 struct cvmx_pko_reg_int_mask_cn50xx cn52xx; 3570 struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1; 3571 struct cvmx_pko_reg_int_mask_cn50xx cn56xx; 3572 struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1; 3573 struct cvmx_pko_reg_int_mask_cn50xx cn58xx; 3574 struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1; 3575 struct cvmx_pko_reg_int_mask_cn50xx cn61xx; 3576 struct cvmx_pko_reg_int_mask_cn50xx cn63xx; 3577 struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1; 3578 struct cvmx_pko_reg_int_mask_cn50xx cn66xx; 3579 struct cvmx_pko_reg_int_mask_s cn68xx; 3580 struct cvmx_pko_reg_int_mask_s cn68xxp1; 3581 struct cvmx_pko_reg_int_mask_cn50xx cnf71xx; 3582}; 3583typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t; 3584 3585/** 3586 * cvmx_pko_reg_loopback_bpid 3587 * 3588 * Notes: 3589 * None. 3590 * 3591 */ 3592union cvmx_pko_reg_loopback_bpid { 3593 uint64_t u64; 3594 struct cvmx_pko_reg_loopback_bpid_s { 3595#ifdef __BIG_ENDIAN_BITFIELD 3596 uint64_t reserved_59_63 : 5; 3597 uint64_t bpid7 : 6; /**< Loopback port 7 backpressure-ID */ 3598 uint64_t reserved_52_52 : 1; 3599 uint64_t bpid6 : 6; /**< Loopback port 6 backpressure-ID */ 3600 uint64_t reserved_45_45 : 1; 3601 uint64_t bpid5 : 6; /**< Loopback port 5 backpressure-ID */ 3602 uint64_t reserved_38_38 : 1; 3603 uint64_t bpid4 : 6; /**< Loopback port 4 backpressure-ID */ 3604 uint64_t reserved_31_31 : 1; 3605 uint64_t bpid3 : 6; /**< Loopback port 3 backpressure-ID */ 3606 uint64_t reserved_24_24 : 1; 3607 uint64_t bpid2 : 6; /**< Loopback port 2 backpressure-ID */ 3608 uint64_t reserved_17_17 : 1; 3609 uint64_t bpid1 : 6; /**< Loopback port 1 backpressure-ID */ 3610 uint64_t reserved_10_10 : 1; 3611 uint64_t bpid0 : 6; /**< Loopback port 0 backpressure-ID */ 3612 uint64_t reserved_0_3 : 4; 3613#else 3614 uint64_t reserved_0_3 : 4; 3615 uint64_t bpid0 : 6; 3616 uint64_t reserved_10_10 : 1; 3617 uint64_t bpid1 : 6; 3618 uint64_t reserved_17_17 : 1; 3619 uint64_t bpid2 : 6; 3620 uint64_t reserved_24_24 : 1; 3621 uint64_t bpid3 : 6; 3622 uint64_t reserved_31_31 : 1; 3623 uint64_t bpid4 : 6; 3624 uint64_t reserved_38_38 : 1; 3625 uint64_t bpid5 : 6; 3626 uint64_t reserved_45_45 : 1; 3627 uint64_t bpid6 : 6; 3628 uint64_t reserved_52_52 : 1; 3629 uint64_t bpid7 : 6; 3630 uint64_t reserved_59_63 : 5; 3631#endif 3632 } s; 3633 struct cvmx_pko_reg_loopback_bpid_s cn68xx; 3634 struct cvmx_pko_reg_loopback_bpid_s cn68xxp1; 3635}; 3636typedef union cvmx_pko_reg_loopback_bpid cvmx_pko_reg_loopback_bpid_t; 3637 3638/** 3639 * cvmx_pko_reg_loopback_pkind 3640 * 3641 * Notes: 3642 * None. 3643 * 3644 */ 3645union cvmx_pko_reg_loopback_pkind { 3646 uint64_t u64; 3647 struct cvmx_pko_reg_loopback_pkind_s { 3648#ifdef __BIG_ENDIAN_BITFIELD 3649 uint64_t reserved_59_63 : 5; 3650 uint64_t pkind7 : 6; /**< Loopback port 7 port-kind */ 3651 uint64_t reserved_52_52 : 1; 3652 uint64_t pkind6 : 6; /**< Loopback port 6 port-kind */ 3653 uint64_t reserved_45_45 : 1; 3654 uint64_t pkind5 : 6; /**< Loopback port 5 port-kind */ 3655 uint64_t reserved_38_38 : 1; 3656 uint64_t pkind4 : 6; /**< Loopback port 4 port-kind */ 3657 uint64_t reserved_31_31 : 1; 3658 uint64_t pkind3 : 6; /**< Loopback port 3 port-kind */ 3659 uint64_t reserved_24_24 : 1; 3660 uint64_t pkind2 : 6; /**< Loopback port 2 port-kind */ 3661 uint64_t reserved_17_17 : 1; 3662 uint64_t pkind1 : 6; /**< Loopback port 1 port-kind */ 3663 uint64_t reserved_10_10 : 1; 3664 uint64_t pkind0 : 6; /**< Loopback port 0 port-kind */ 3665 uint64_t num_ports : 4; /**< Number of loopback ports, 0 <= NUM_PORTS <= 8 */ 3666#else 3667 uint64_t num_ports : 4; 3668 uint64_t pkind0 : 6; 3669 uint64_t reserved_10_10 : 1; 3670 uint64_t pkind1 : 6; 3671 uint64_t reserved_17_17 : 1; 3672 uint64_t pkind2 : 6; 3673 uint64_t reserved_24_24 : 1; 3674 uint64_t pkind3 : 6; 3675 uint64_t reserved_31_31 : 1; 3676 uint64_t pkind4 : 6; 3677 uint64_t reserved_38_38 : 1; 3678 uint64_t pkind5 : 6; 3679 uint64_t reserved_45_45 : 1; 3680 uint64_t pkind6 : 6; 3681 uint64_t reserved_52_52 : 1; 3682 uint64_t pkind7 : 6; 3683 uint64_t reserved_59_63 : 5; 3684#endif 3685 } s; 3686 struct cvmx_pko_reg_loopback_pkind_s cn68xx; 3687 struct cvmx_pko_reg_loopback_pkind_s cn68xxp1; 3688}; 3689typedef union cvmx_pko_reg_loopback_pkind cvmx_pko_reg_loopback_pkind_t; 3690 3691/** 3692 * cvmx_pko_reg_min_pkt 3693 * 3694 * Notes: 3695 * This CSR is used with PKO_MEM_IPORT_PTRS[MIN_PKT] to select the minimum packet size. Packets whose 3696 * size in bytes < (SIZEn+1) are zero-padded to (SIZEn+1) bytes. Note that this does not include CRC bytes. 3697 * SIZE0=0 is read-only and is used when no padding is desired. 3698 */ 3699union cvmx_pko_reg_min_pkt { 3700 uint64_t u64; 3701 struct cvmx_pko_reg_min_pkt_s { 3702#ifdef __BIG_ENDIAN_BITFIELD 3703 uint64_t size7 : 8; /**< Minimum packet size-1 in bytes NS */ 3704 uint64_t size6 : 8; /**< Minimum packet size-1 in bytes NS */ 3705 uint64_t size5 : 8; /**< Minimum packet size-1 in bytes NS */ 3706 uint64_t size4 : 8; /**< Minimum packet size-1 in bytes NS */ 3707 uint64_t size3 : 8; /**< Minimum packet size-1 in bytes NS */ 3708 uint64_t size2 : 8; /**< Minimum packet size-1 in bytes NS */ 3709 uint64_t size1 : 8; /**< Minimum packet size-1 in bytes NS */ 3710 uint64_t size0 : 8; /**< Minimum packet size-1 in bytes NS */ 3711#else 3712 uint64_t size0 : 8; 3713 uint64_t size1 : 8; 3714 uint64_t size2 : 8; 3715 uint64_t size3 : 8; 3716 uint64_t size4 : 8; 3717 uint64_t size5 : 8; 3718 uint64_t size6 : 8; 3719 uint64_t size7 : 8; 3720#endif 3721 } s; 3722 struct cvmx_pko_reg_min_pkt_s cn68xx; 3723 struct cvmx_pko_reg_min_pkt_s cn68xxp1; 3724}; 3725typedef union cvmx_pko_reg_min_pkt cvmx_pko_reg_min_pkt_t; 3726 3727/** 3728 * cvmx_pko_reg_preempt 3729 */ 3730union cvmx_pko_reg_preempt { 3731 uint64_t u64; 3732 struct cvmx_pko_reg_preempt_s { 3733#ifdef __BIG_ENDIAN_BITFIELD 3734 uint64_t reserved_16_63 : 48; 3735 uint64_t min_size : 16; /**< Threshhold for packet preemption, measured in bytes. 3736 Only packets which have at least MIN_SIZE bytes 3737 remaining to be read can be preempted. */ 3738#else 3739 uint64_t min_size : 16; 3740 uint64_t reserved_16_63 : 48; 3741#endif 3742 } s; 3743 struct cvmx_pko_reg_preempt_s cn52xx; 3744 struct cvmx_pko_reg_preempt_s cn52xxp1; 3745 struct cvmx_pko_reg_preempt_s cn56xx; 3746 struct cvmx_pko_reg_preempt_s cn56xxp1; 3747 struct cvmx_pko_reg_preempt_s cn61xx; 3748 struct cvmx_pko_reg_preempt_s cn63xx; 3749 struct cvmx_pko_reg_preempt_s cn63xxp1; 3750 struct cvmx_pko_reg_preempt_s cn66xx; 3751 struct cvmx_pko_reg_preempt_s cn68xx; 3752 struct cvmx_pko_reg_preempt_s cn68xxp1; 3753 struct cvmx_pko_reg_preempt_s cnf71xx; 3754}; 3755typedef union cvmx_pko_reg_preempt cvmx_pko_reg_preempt_t; 3756 3757/** 3758 * cvmx_pko_reg_queue_mode 3759 * 3760 * Notes: 3761 * Sets the number of queues and amount of local storage per queue 3762 * The system has a total of 256 queues and (256*8) words of local command storage. This CSR sets the 3763 * number of queues that are used. Increasing the value of MODE by 1 decreases the number of queues 3764 * by a power of 2 and increases the local storage per queue by a power of 2. 3765 * MODEn queues storage/queue 3766 * 0 256 64B ( 8 words) 3767 * 1 128 128B (16 words) 3768 * 2 64 256B (32 words) 3769 */ 3770union cvmx_pko_reg_queue_mode { 3771 uint64_t u64; 3772 struct cvmx_pko_reg_queue_mode_s { 3773#ifdef __BIG_ENDIAN_BITFIELD 3774 uint64_t reserved_2_63 : 62; 3775 uint64_t mode : 2; /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */ 3776#else 3777 uint64_t mode : 2; 3778 uint64_t reserved_2_63 : 62; 3779#endif 3780 } s; 3781 struct cvmx_pko_reg_queue_mode_s cn30xx; 3782 struct cvmx_pko_reg_queue_mode_s cn31xx; 3783 struct cvmx_pko_reg_queue_mode_s cn38xx; 3784 struct cvmx_pko_reg_queue_mode_s cn38xxp2; 3785 struct cvmx_pko_reg_queue_mode_s cn50xx; 3786 struct cvmx_pko_reg_queue_mode_s cn52xx; 3787 struct cvmx_pko_reg_queue_mode_s cn52xxp1; 3788 struct cvmx_pko_reg_queue_mode_s cn56xx; 3789 struct cvmx_pko_reg_queue_mode_s cn56xxp1; 3790 struct cvmx_pko_reg_queue_mode_s cn58xx; 3791 struct cvmx_pko_reg_queue_mode_s cn58xxp1; 3792 struct cvmx_pko_reg_queue_mode_s cn61xx; 3793 struct cvmx_pko_reg_queue_mode_s cn63xx; 3794 struct cvmx_pko_reg_queue_mode_s cn63xxp1; 3795 struct cvmx_pko_reg_queue_mode_s cn66xx; 3796 struct cvmx_pko_reg_queue_mode_s cn68xx; 3797 struct cvmx_pko_reg_queue_mode_s cn68xxp1; 3798 struct cvmx_pko_reg_queue_mode_s cnf71xx; 3799}; 3800typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t; 3801 3802/** 3803 * cvmx_pko_reg_queue_preempt 3804 * 3805 * Notes: 3806 * Per QID, setting both PREEMPTER=1 and PREEMPTEE=1 is illegal and sets only PREEMPTER=1. 3807 * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_REG_QUEUE_PTRS1. When programming queues, the 3808 * programming sequence must first write PKO_REG_QUEUE_PREEMPT, then PKO_REG_QUEUE_PTRS1 and then 3809 * PKO_MEM_QUEUE_PTRS for each queue. Preemption is supported only on queues that are ultimately 3810 * mapped to engines 0-7. It is illegal to set preemptee or preempter for a queue that is ultimately 3811 * mapped to engines 8-11. 3812 * 3813 * Also, PKO_REG_ENGINE_INFLIGHT must be at least 2 for any engine on which preemption is enabled. 3814 * 3815 * See the descriptions of PKO_MEM_QUEUE_PTRS for further explanation of queue programming. 3816 */ 3817union cvmx_pko_reg_queue_preempt { 3818 uint64_t u64; 3819 struct cvmx_pko_reg_queue_preempt_s { 3820#ifdef __BIG_ENDIAN_BITFIELD 3821 uint64_t reserved_2_63 : 62; 3822 uint64_t preemptee : 1; /**< Allow this QID to be preempted. 3823 0=cannot be preempted, 1=can be preempted */ 3824 uint64_t preempter : 1; /**< Preempts the servicing of packet on PID to 3825 allow this QID immediate servicing. 0=do not cause 3826 preemption, 1=cause preemption. Per PID, at most 3827 1 QID can have this bit set. */ 3828#else 3829 uint64_t preempter : 1; 3830 uint64_t preemptee : 1; 3831 uint64_t reserved_2_63 : 62; 3832#endif 3833 } s; 3834 struct cvmx_pko_reg_queue_preempt_s cn52xx; 3835 struct cvmx_pko_reg_queue_preempt_s cn52xxp1; 3836 struct cvmx_pko_reg_queue_preempt_s cn56xx; 3837 struct cvmx_pko_reg_queue_preempt_s cn56xxp1; 3838 struct cvmx_pko_reg_queue_preempt_s cn61xx; 3839 struct cvmx_pko_reg_queue_preempt_s cn63xx; 3840 struct cvmx_pko_reg_queue_preempt_s cn63xxp1; 3841 struct cvmx_pko_reg_queue_preempt_s cn66xx; 3842 struct cvmx_pko_reg_queue_preempt_s cn68xx; 3843 struct cvmx_pko_reg_queue_preempt_s cn68xxp1; 3844 struct cvmx_pko_reg_queue_preempt_s cnf71xx; 3845}; 3846typedef union cvmx_pko_reg_queue_preempt cvmx_pko_reg_queue_preempt_t; 3847 3848/** 3849 * cvmx_pko_reg_queue_ptrs1 3850 * 3851 * Notes: 3852 * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255 3853 * and to allow up mapping of up to 16 queues per port. When programming queues 128-255, the 3854 * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or 3855 * PKO_MEM_QUEUE_QOS for each queue. 3856 * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue 3857 * programming. 3858 */ 3859union cvmx_pko_reg_queue_ptrs1 { 3860 uint64_t u64; 3861 struct cvmx_pko_reg_queue_ptrs1_s { 3862#ifdef __BIG_ENDIAN_BITFIELD 3863 uint64_t reserved_2_63 : 62; 3864 uint64_t idx3 : 1; /**< [3] of Index (distance from head) in the queue array */ 3865 uint64_t qid7 : 1; /**< [7] of Queue ID */ 3866#else 3867 uint64_t qid7 : 1; 3868 uint64_t idx3 : 1; 3869 uint64_t reserved_2_63 : 62; 3870#endif 3871 } s; 3872 struct cvmx_pko_reg_queue_ptrs1_s cn50xx; 3873 struct cvmx_pko_reg_queue_ptrs1_s cn52xx; 3874 struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1; 3875 struct cvmx_pko_reg_queue_ptrs1_s cn56xx; 3876 struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; 3877 struct cvmx_pko_reg_queue_ptrs1_s cn58xx; 3878 struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; 3879 struct cvmx_pko_reg_queue_ptrs1_s cn61xx; 3880 struct cvmx_pko_reg_queue_ptrs1_s cn63xx; 3881 struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1; 3882 struct cvmx_pko_reg_queue_ptrs1_s cn66xx; 3883 struct cvmx_pko_reg_queue_ptrs1_s cnf71xx; 3884}; 3885typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t; 3886 3887/** 3888 * cvmx_pko_reg_read_idx 3889 * 3890 * Notes: 3891 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 3892 * as memories. The names of these CSRs begin with the prefix "PKO_MEM_". 3893 * IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read. 3894 * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 3895 * contents of a CSR memory can be read with consecutive CSR read commands. 3896 */ 3897union cvmx_pko_reg_read_idx { 3898 uint64_t u64; 3899 struct cvmx_pko_reg_read_idx_s { 3900#ifdef __BIG_ENDIAN_BITFIELD 3901 uint64_t reserved_16_63 : 48; 3902 uint64_t inc : 8; /**< Increment to add to current index for next index */ 3903 uint64_t index : 8; /**< Index to use for next memory CSR read */ 3904#else 3905 uint64_t index : 8; 3906 uint64_t inc : 8; 3907 uint64_t reserved_16_63 : 48; 3908#endif 3909 } s; 3910 struct cvmx_pko_reg_read_idx_s cn30xx; 3911 struct cvmx_pko_reg_read_idx_s cn31xx; 3912 struct cvmx_pko_reg_read_idx_s cn38xx; 3913 struct cvmx_pko_reg_read_idx_s cn38xxp2; 3914 struct cvmx_pko_reg_read_idx_s cn50xx; 3915 struct cvmx_pko_reg_read_idx_s cn52xx; 3916 struct cvmx_pko_reg_read_idx_s cn52xxp1; 3917 struct cvmx_pko_reg_read_idx_s cn56xx; 3918 struct cvmx_pko_reg_read_idx_s cn56xxp1; 3919 struct cvmx_pko_reg_read_idx_s cn58xx; 3920 struct cvmx_pko_reg_read_idx_s cn58xxp1; 3921 struct cvmx_pko_reg_read_idx_s cn61xx; 3922 struct cvmx_pko_reg_read_idx_s cn63xx; 3923 struct cvmx_pko_reg_read_idx_s cn63xxp1; 3924 struct cvmx_pko_reg_read_idx_s cn66xx; 3925 struct cvmx_pko_reg_read_idx_s cn68xx; 3926 struct cvmx_pko_reg_read_idx_s cn68xxp1; 3927 struct cvmx_pko_reg_read_idx_s cnf71xx; 3928}; 3929typedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t; 3930 3931/** 3932 * cvmx_pko_reg_throttle 3933 * 3934 * Notes: 3935 * This CSR is used with PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT. INT_MASK corresponds to the 3936 * interfaces listed in the description for PKO_MEM_IPORT_PTRS[INT]. Set INT_MASK[N] to enable the 3937 * updating of PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT counts for packets destined for 3938 * interface N. INT_MASK has no effect on the updates caused by CSR writes to PKO_MEM_THROTTLE_PIPE 3939 * and PKO_MEM_THROTTLE_INT. Note that this does not disable the throttle logic, just the updating of 3940 * the interface counts. 3941 */ 3942union cvmx_pko_reg_throttle { 3943 uint64_t u64; 3944 struct cvmx_pko_reg_throttle_s { 3945#ifdef __BIG_ENDIAN_BITFIELD 3946 uint64_t reserved_32_63 : 32; 3947 uint64_t int_mask : 32; /**< Mask to enable THROTTLE count updates per interface NS */ 3948#else 3949 uint64_t int_mask : 32; 3950 uint64_t reserved_32_63 : 32; 3951#endif 3952 } s; 3953 struct cvmx_pko_reg_throttle_s cn68xx; 3954 struct cvmx_pko_reg_throttle_s cn68xxp1; 3955}; 3956typedef union cvmx_pko_reg_throttle cvmx_pko_reg_throttle_t; 3957 3958/** 3959 * cvmx_pko_reg_timestamp 3960 * 3961 * Notes: 3962 * None. 3963 * 3964 */ 3965union cvmx_pko_reg_timestamp { 3966 uint64_t u64; 3967 struct cvmx_pko_reg_timestamp_s { 3968#ifdef __BIG_ENDIAN_BITFIELD 3969 uint64_t reserved_4_63 : 60; 3970 uint64_t wqe_word : 4; /**< Specifies the 8-byte word in the WQE to which a PTP 3971 timestamp is written. Values 0 and 1 are illegal. */ 3972#else 3973 uint64_t wqe_word : 4; 3974 uint64_t reserved_4_63 : 60; 3975#endif 3976 } s; 3977 struct cvmx_pko_reg_timestamp_s cn61xx; 3978 struct cvmx_pko_reg_timestamp_s cn63xx; 3979 struct cvmx_pko_reg_timestamp_s cn63xxp1; 3980 struct cvmx_pko_reg_timestamp_s cn66xx; 3981 struct cvmx_pko_reg_timestamp_s cn68xx; 3982 struct cvmx_pko_reg_timestamp_s cn68xxp1; 3983 struct cvmx_pko_reg_timestamp_s cnf71xx; 3984}; 3985typedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t; 3986 3987#endif 3988