1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). 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MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Module to support operations on core such as TLB config, etc. 50 * 51 * <hr>$Revision: 70030 $<hr> 52 * 53 */ 54 55 56#ifndef __CVMX_CORE_H__ 57#define __CVMX_CORE_H__ 58 59#ifdef __cplusplus 60extern "C" { 61#endif 62 63/** 64 * The types of performance counters supported per cpu 65 */ 66typedef enum 67{ 68 CVMX_CORE_PERF_NONE = 0, /**< Turn off the performance counter */ 69 CVMX_CORE_PERF_CLK = 1, /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */ 70 CVMX_CORE_PERF_ISSUE = 2, /**< Instructions issued but not retired */ 71 CVMX_CORE_PERF_RET = 3, /**< Instructions retired */ 72 CVMX_CORE_PERF_NISSUE = 4, /**< Cycles no issue */ 73 CVMX_CORE_PERF_SISSUE = 5, /**< Cycles single issue */ 74 CVMX_CORE_PERF_DISSUE = 6, /**< Cycles dual issue */ 75 CVMX_CORE_PERF_IFI = 7, /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */ 76 CVMX_CORE_PERF_BR = 8, /**< Branches retired */ 77 CVMX_CORE_PERF_BRMIS = 9, /**< Branch mispredicts */ 78 CVMX_CORE_PERF_J = 10, /**< Jumps retired */ 79 CVMX_CORE_PERF_JMIS = 11, /**< Jumps mispredicted */ 80 CVMX_CORE_PERF_REPLAY = 12, /**< Mem Replays */ 81 CVMX_CORE_PERF_IUNA = 13, /**< Cycles idle due to unaligned_replays */ 82 CVMX_CORE_PERF_TRAP = 14, /**< trap_6a signal */ 83 CVMX_CORE_PERF_UULOAD = 16, /**< Unexpected unaligned loads (REPUN=1) */ 84 CVMX_CORE_PERF_UUSTORE = 17, /**< Unexpected unaligned store (REPUN=1) */ 85 CVMX_CORE_PERF_ULOAD = 18, /**< Unaligned loads (REPUN=1 or USEUN=1) */ 86 CVMX_CORE_PERF_USTORE = 19, /**< Unaligned store (REPUN=1 or USEUN=1) */ 87 CVMX_CORE_PERF_EC = 20, /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */ 88 CVMX_CORE_PERF_MC = 21, /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */ 89 CVMX_CORE_PERF_CC = 22, /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */ 90 CVMX_CORE_PERF_CSRC = 23, /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */ 91 CVMX_CORE_PERF_CFETCH = 24, /**< Icache committed fetches (demand+prefetch) */ 92 CVMX_CORE_PERF_CPREF = 25, /**< Icache committed prefetches */ 93 CVMX_CORE_PERF_ICA = 26, /**< Icache aliases */ 94 CVMX_CORE_PERF_II = 27, /**< Icache invalidates */ 95 CVMX_CORE_PERF_IP = 28, /**< Icache parity error */ 96 CVMX_CORE_PERF_CIMISS = 29, /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */ 97 CVMX_CORE_PERF_WBUF = 32, /**< Number of write buffer entries created */ 98 CVMX_CORE_PERF_WDAT = 33, /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 99 CVMX_CORE_PERF_WBUFLD = 34, /**< Number of write buffer entries forced out by loads */ 100 CVMX_CORE_PERF_WBUFFL = 35, /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 101 CVMX_CORE_PERF_WBUFTR = 36, /**< Number of stores that found no available write buffer entries */ 102 CVMX_CORE_PERF_BADD = 37, /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 103 CVMX_CORE_PERF_BADDL2 = 38, /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */ 104 CVMX_CORE_PERF_BFILL = 39, /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 105 CVMX_CORE_PERF_DDIDS = 40, /**< Number of Dstream DIDs created */ 106 CVMX_CORE_PERF_IDIDS = 41, /**< Number of Istream DIDs created */ 107 CVMX_CORE_PERF_DIDNA = 42, /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 108 CVMX_CORE_PERF_LDS = 43, /**< Number of load issues */ 109 CVMX_CORE_PERF_LMLDS = 44, /**< Number of local memory load */ 110 CVMX_CORE_PERF_IOLDS = 45, /**< Number of I/O load issues */ 111 CVMX_CORE_PERF_DMLDS = 46, /**< Number of loads that were not prefetches and missed in the cache */ 112 CVMX_CORE_PERF_STS = 48, /**< Number of store issues */ 113 CVMX_CORE_PERF_LMSTS = 49, /**< Number of local memory store issues */ 114 CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */ 115 CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */ 116 CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */ 117 CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */ 118 CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */ 119 CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 120 CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 121 CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */ 122 /* Added in CN63XX */ 123 CVMX_CORE_PERF_ERETMIS = 64, /**< D/eret mispredicts */ 124 CVMX_CORE_PERF_LIKMIS = 65, /**< Branch likely mispredicts */ 125 CVMX_CORE_PERF_HAZTR = 66, /**< Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers */ 126 CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */ 127} cvmx_core_perf_t; 128 129/** 130 * Bit description of the COP0 counter control register 131 */ 132typedef union 133{ 134 uint32_t u32; 135 struct 136 { 137#ifdef __BIG_ENDIAN_BITFIELD 138 uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */ 139 uint32_t w : 1; /**< Set to 1 indicating counters are 64 bit */ 140 uint32_t reserved_11_29 :15; 141 cvmx_core_perf_t event :10; /**< Selects the event to be counted by the corresponding Counter Register */ 142 uint32_t ie : 1; /**< Interrupt Enable */ 143 uint32_t u : 1; /**< Count in user mode */ 144 uint32_t s : 1; /**< Count in supervisor mode */ 145 uint32_t k : 1; /**< Count in kernel mode */ 146 uint32_t ex : 1; /**< Count in exception context */ 147#else 148 uint32_t ex : 1; 149 uint32_t k : 1; 150 uint32_t s : 1; 151 uint32_t u : 1; 152 uint32_t ie : 1; 153 uint32_t event :10; 154 uint32_t reserved_11_29 :15; 155 uint32_t w : 1; 156 uint32_t m : 1; 157#endif 158 } s; 159} cvmx_core_perf_control_t; 160 161typedef enum { 162 CVMX_TLB_PAGEMASK_4K = 0x3 << 11, 163 CVMX_TLB_PAGEMASK_16K = 0xF << 11, 164 CVMX_TLB_PAGEMASK_64K = 0x3F << 11, 165 CVMX_TLB_PAGEMASK_256K = 0xFF << 11, 166 CVMX_TLB_PAGEMASK_1M = 0x3FF << 11, 167 CVMX_TLB_PAGEMASK_4M = 0xFFF << 11, 168 CVMX_TLB_PAGEMASK_16M = 0x3FFF << 11, 169 CVMX_TLB_PAGEMASK_64M = 0xFFFF << 11, 170 CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11, 171} cvmx_tlb_pagemask_t; 172 173 174int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask); 175 176 177int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 178int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 179 180/** 181 * Return number of TLB entries. 182 */ 183int cvmx_core_get_tlb_entries(void); 184#ifdef __cplusplus 185} 186#endif 187 188#endif /* __CVMX_CORE_H__ */ 189