1/*
2 * Copyright 2008-2013 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *     * Redistributions of source code must retain the above copyright
7 *       notice, this list of conditions and the following disclaimer.
8 *     * Redistributions in binary form must reproduce the above copyright
9 *       notice, this list of conditions and the following disclaimer in the
10 *       documentation and/or other materials provided with the distribution.
11 *     * Neither the name of Freescale Semiconductor nor the
12 *       names of its contributors may be used to endorse or promote products
13 *       derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef __FSL_FMAN_DTSEC_MII_ACC_H
34#define __FSL_FMAN_DTSEC_MII_ACC_H
35
36#include "common/general.h"
37
38
39/* MII Management Configuration Register */
40#define MIIMCFG_RESET_MGMT		0x80000000
41#define MIIMCFG_MGNTCLK_MASK		0x00000007
42#define MIIMCFG_MGNTCLK_SHIFT		0
43
44/* MII  Management Command Register */
45#define MIIMCOM_SCAN_CYCLE		0x00000002
46#define MIIMCOM_READ_CYCLE		0x00000001
47
48/* MII  Management Address Register */
49#define MIIMADD_PHY_ADDR_SHIFT		8
50#define MIIMADD_PHY_ADDR_MASK		0x00001f00
51
52#define MIIMADD_REG_ADDR_SHIFT		0
53#define MIIMADD_REG_ADDR_MASK		0x0000001f
54
55/* MII Management Indicator Register */
56#define MIIMIND_BUSY			0x00000001
57
58
59/* PHY Control Register */
60#define PHY_CR_PHY_RESET    0x8000
61#define PHY_CR_LOOPBACK     0x4000
62#define PHY_CR_SPEED0       0x2000
63#define PHY_CR_ANE          0x1000
64#define PHY_CR_RESET_AN     0x0200
65#define PHY_CR_FULLDUPLEX   0x0100
66#define PHY_CR_SPEED1       0x0040
67
68#define PHY_TBICON_SRESET   0x8000
69#define PHY_TBICON_SPEED2   0x0020
70#define PHY_TBICON_CLK_SEL  0x0020
71#define PHY_TBIANA_SGMII    0x4001
72#define PHY_TBIANA_1000X    0x01a0
73/* register map */
74
75/* MII Configuration Control Memory Map Registers */
76struct dtsec_mii_reg {
77	uint32_t reserved1[72];
78	uint32_t miimcfg;	/* MII Mgmt:configuration */
79	uint32_t miimcom;	/* MII Mgmt:command       */
80	uint32_t miimadd;	/* MII Mgmt:address       */
81	uint32_t miimcon;	/* MII Mgmt:control 3     */
82	uint32_t miimstat;	/* MII Mgmt:status        */
83	uint32_t miimind;	/* MII Mgmt:indicators    */
84};
85
86/* dTSEC MII API */
87
88/* functions to access the mii registers for phy configuration.
89 * this functionality may not be available for all dtsecs in the system.
90 * consult the reference manual for details */
91void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs);
92/* frequency is in MHz.
93 * note that dtsec clock is 1/2 of fman clock */
94void fman_dtsec_mii_init(struct dtsec_mii_reg *regs, uint16_t dtsec_freq);
95int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs,
96			uint8_t addr,
97			uint8_t reg,
98			uint16_t data,
99			uint16_t dtsec_freq);
100
101int fman_dtsec_mii_read_reg(struct dtsec_mii_reg *regs,
102			uint8_t addr,
103			uint8_t reg,
104			uint16_t *data,
105			uint16_t dtsec_freq);
106
107#endif /* __FSL_FMAN_DTSEC_MII_ACC_H */
108