1/* 2 * Copyright 2008-2012 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef __FSL_ENET_H 34#define __FSL_ENET_H 35 36/** 37 @Description Ethernet MAC-PHY Interface 38*/ 39 40enum enet_interface { 41 E_ENET_IF_MII = 0x00010000, /**< MII interface */ 42 E_ENET_IF_RMII = 0x00020000, /**< RMII interface */ 43 E_ENET_IF_SMII = 0x00030000, /**< SMII interface */ 44 E_ENET_IF_GMII = 0x00040000, /**< GMII interface */ 45 E_ENET_IF_RGMII = 0x00050000, /**< RGMII interface */ 46 E_ENET_IF_TBI = 0x00060000, /**< TBI interface */ 47 E_ENET_IF_RTBI = 0x00070000, /**< RTBI interface */ 48 E_ENET_IF_SGMII = 0x00080000, /**< SGMII interface */ 49 E_ENET_IF_XGMII = 0x00090000, /**< XGMII interface */ 50 E_ENET_IF_QSGMII = 0x000a0000, /**< QSGMII interface */ 51 E_ENET_IF_XFI = 0x000b0000 /**< XFI interface */ 52}; 53 54/** 55 @Description Ethernet Speed (nominal data rate) 56*/ 57enum enet_speed { 58 E_ENET_SPEED_10 = 10, /**< 10 Mbps */ 59 E_ENET_SPEED_100 = 100, /**< 100 Mbps */ 60 E_ENET_SPEED_1000 = 1000, /**< 1000 Mbps = 1 Gbps */ 61 E_ENET_SPEED_2500 = 2500, /**< 2500 Mbps = 2.5 Gbps */ 62 E_ENET_SPEED_10000 = 10000 /**< 10000 Mbps = 10 Gbps */ 63}; 64 65enum mac_type { 66 E_MAC_DTSEC, 67 E_MAC_TGEC, 68 E_MAC_MEMAC 69}; 70 71/**************************************************************************//** 72 @Description Enum for inter-module interrupts registration 73*//***************************************************************************/ 74enum fman_event_modules { 75 E_FMAN_MOD_PRS, /**< Parser event */ 76 E_FMAN_MOD_KG, /**< Keygen event */ 77 E_FMAN_MOD_PLCR, /**< Policer event */ 78 E_FMAN_MOD_10G_MAC, /**< 10G MAC event */ 79 E_FMAN_MOD_1G_MAC, /**< 1G MAC event */ 80 E_FMAN_MOD_TMR, /**< Timer event */ 81 E_FMAN_MOD_FMAN_CTRL, /**< FMAN Controller Timer event */ 82 E_FMAN_MOD_MACSEC, 83 E_FMAN_MOD_DUMMY_LAST 84}; 85 86/**************************************************************************//** 87 @Description Enum for interrupts types 88*//***************************************************************************/ 89enum fman_intr_type { 90 E_FMAN_INTR_TYPE_ERR, 91 E_FMAN_INTR_TYPE_NORMAL 92}; 93 94/**************************************************************************//** 95 @Description enum for defining MAC types 96*//***************************************************************************/ 97enum fman_mac_type { 98 E_FMAN_MAC_10G = 0, /**< 10G MAC */ 99 E_FMAN_MAC_1G /**< 1G MAC */ 100}; 101 102enum fman_mac_exceptions { 103 E_FMAN_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0, 104 /**< 10GEC MDIO scan event interrupt */ 105 E_FMAN_MAC_EX_10G_MDIO_CMD_CMPL, 106 /**< 10GEC MDIO command completion interrupt */ 107 E_FMAN_MAC_EX_10G_REM_FAULT, 108 /**< 10GEC, mEMAC Remote fault interrupt */ 109 E_FMAN_MAC_EX_10G_LOC_FAULT, 110 /**< 10GEC, mEMAC Local fault interrupt */ 111 E_FMAN_MAC_EX_10G_1TX_ECC_ER, 112 /**< 10GEC, mEMAC Transmit frame ECC error interrupt */ 113 E_FMAN_MAC_EX_10G_TX_FIFO_UNFL, 114 /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */ 115 E_FMAN_MAC_EX_10G_TX_FIFO_OVFL, 116 /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */ 117 E_FMAN_MAC_EX_10G_TX_ER, 118 /**< 10GEC Transmit frame error interrupt */ 119 E_FMAN_MAC_EX_10G_RX_FIFO_OVFL, 120 /**< 10GEC, mEMAC Receive FIFO overflow interrupt */ 121 E_FMAN_MAC_EX_10G_RX_ECC_ER, 122 /**< 10GEC, mEMAC Receive frame ECC error interrupt */ 123 E_FMAN_MAC_EX_10G_RX_JAB_FRM, 124 /**< 10GEC Receive jabber frame interrupt */ 125 E_FMAN_MAC_EX_10G_RX_OVRSZ_FRM, 126 /**< 10GEC Receive oversized frame interrupt */ 127 E_FMAN_MAC_EX_10G_RX_RUNT_FRM, 128 /**< 10GEC Receive runt frame interrupt */ 129 E_FMAN_MAC_EX_10G_RX_FRAG_FRM, 130 /**< 10GEC Receive fragment frame interrupt */ 131 E_FMAN_MAC_EX_10G_RX_LEN_ER, 132 /**< 10GEC Receive payload length error interrupt */ 133 E_FMAN_MAC_EX_10G_RX_CRC_ER, 134 /**< 10GEC Receive CRC error interrupt */ 135 E_FMAN_MAC_EX_10G_RX_ALIGN_ER, 136 /**< 10GEC Receive alignment error interrupt */ 137 E_FMAN_MAC_EX_1G_BAB_RX, 138 /**< dTSEC Babbling receive error */ 139 E_FMAN_MAC_EX_1G_RX_CTL, 140 /**< dTSEC Receive control (pause frame) interrupt */ 141 E_FMAN_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET, 142 /**< dTSEC Graceful transmit stop complete */ 143 E_FMAN_MAC_EX_1G_BAB_TX, 144 /**< dTSEC Babbling transmit error */ 145 E_FMAN_MAC_EX_1G_TX_CTL, 146 /**< dTSEC Transmit control (pause frame) interrupt */ 147 E_FMAN_MAC_EX_1G_TX_ERR, 148 /**< dTSEC Transmit error */ 149 E_FMAN_MAC_EX_1G_LATE_COL, 150 /**< dTSEC Late collision */ 151 E_FMAN_MAC_EX_1G_COL_RET_LMT, 152 /**< dTSEC Collision retry limit */ 153 E_FMAN_MAC_EX_1G_TX_FIFO_UNDRN, 154 /**< dTSEC Transmit FIFO underrun */ 155 E_FMAN_MAC_EX_1G_MAG_PCKT, 156 /**< dTSEC Magic Packet detection */ 157 E_FMAN_MAC_EX_1G_MII_MNG_RD_COMPLET, 158 /**< dTSEC MII management read completion */ 159 E_FMAN_MAC_EX_1G_MII_MNG_WR_COMPLET, 160 /**< dTSEC MII management write completion */ 161 E_FMAN_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET, 162 /**< dTSEC Graceful receive stop complete */ 163 E_FMAN_MAC_EX_1G_TX_DATA_ERR, 164 /**< dTSEC Internal data error on transmit */ 165 E_FMAN_MAC_EX_1G_RX_DATA_ERR, 166 /**< dTSEC Internal data error on receive */ 167 E_FMAN_MAC_EX_1G_1588_TS_RX_ERR, 168 /**< dTSEC Time-Stamp Receive Error */ 169 E_FMAN_MAC_EX_1G_RX_MIB_CNT_OVFL, 170 /**< dTSEC MIB counter overflow */ 171 E_FMAN_MAC_EX_TS_FIFO_ECC_ERR, 172 /**< mEMAC Time-stamp FIFO ECC error interrupt; 173 not supported on T4240/B4860 rev1 chips */ 174}; 175 176#define ENET_IF_SGMII_BASEX 0x80000000 177 /**< SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC 178 and phy or backplane; 179 Note: 1000BaseX auto-negotiation relates only to interface between MAC 180 and phy/backplane, SGMII phy can still synchronize with far-end phy at 181 10Mbps, 100Mbps or 1000Mbps */ 182 183enum enet_mode { 184 E_ENET_MODE_INVALID = 0, 185 /**< Invalid Ethernet mode */ 186 E_ENET_MODE_MII_10 = (E_ENET_IF_MII | E_ENET_SPEED_10), 187 /**< 10 Mbps MII */ 188 E_ENET_MODE_MII_100 = (E_ENET_IF_MII | E_ENET_SPEED_100), 189 /**< 100 Mbps MII */ 190 E_ENET_MODE_RMII_10 = (E_ENET_IF_RMII | E_ENET_SPEED_10), 191 /**< 10 Mbps RMII */ 192 E_ENET_MODE_RMII_100 = (E_ENET_IF_RMII | E_ENET_SPEED_100), 193 /**< 100 Mbps RMII */ 194 E_ENET_MODE_SMII_10 = (E_ENET_IF_SMII | E_ENET_SPEED_10), 195 /**< 10 Mbps SMII */ 196 E_ENET_MODE_SMII_100 = (E_ENET_IF_SMII | E_ENET_SPEED_100), 197 /**< 100 Mbps SMII */ 198 E_ENET_MODE_GMII_1000 = (E_ENET_IF_GMII | E_ENET_SPEED_1000), 199 /**< 1000 Mbps GMII */ 200 E_ENET_MODE_RGMII_10 = (E_ENET_IF_RGMII | E_ENET_SPEED_10), 201 /**< 10 Mbps RGMII */ 202 E_ENET_MODE_RGMII_100 = (E_ENET_IF_RGMII | E_ENET_SPEED_100), 203 /**< 100 Mbps RGMII */ 204 E_ENET_MODE_RGMII_1000 = (E_ENET_IF_RGMII | E_ENET_SPEED_1000), 205 /**< 1000 Mbps RGMII */ 206 E_ENET_MODE_TBI_1000 = (E_ENET_IF_TBI | E_ENET_SPEED_1000), 207 /**< 1000 Mbps TBI */ 208 E_ENET_MODE_RTBI_1000 = (E_ENET_IF_RTBI | E_ENET_SPEED_1000), 209 /**< 1000 Mbps RTBI */ 210 E_ENET_MODE_SGMII_10 = (E_ENET_IF_SGMII | E_ENET_SPEED_10), 211 /**< 10 Mbps SGMII with auto-negotiation between MAC and 212 SGMII phy according to Cisco SGMII specification */ 213 E_ENET_MODE_SGMII_100 = (E_ENET_IF_SGMII | E_ENET_SPEED_100), 214 /**< 100 Mbps SGMII with auto-negotiation between MAC and 215 SGMII phy according to Cisco SGMII specification */ 216 E_ENET_MODE_SGMII_1000 = (E_ENET_IF_SGMII | E_ENET_SPEED_1000), 217 /**< 1000 Mbps SGMII with auto-negotiation between MAC and 218 SGMII phy according to Cisco SGMII specification */ 219 E_ENET_MODE_SGMII_BASEX_10 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII 220 | E_ENET_SPEED_10), 221 /**< 10 Mbps SGMII with 1000BaseX auto-negotiation between 222 MAC and SGMII phy or backplane */ 223 E_ENET_MODE_SGMII_BASEX_100 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII 224 | E_ENET_SPEED_100), 225 /**< 100 Mbps SGMII with 1000BaseX auto-negotiation between 226 MAC and SGMII phy or backplane */ 227 E_ENET_MODE_SGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII 228 | E_ENET_SPEED_1000), 229 /**< 1000 Mbps SGMII with 1000BaseX auto-negotiation between 230 MAC and SGMII phy or backplane */ 231 E_ENET_MODE_QSGMII_1000 = (E_ENET_IF_QSGMII | E_ENET_SPEED_1000), 232 /**< 1000 Mbps QSGMII with auto-negotiation between MAC and 233 QSGMII phy according to Cisco QSGMII specification */ 234 E_ENET_MODE_QSGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_QSGMII 235 | E_ENET_SPEED_1000), 236 /**< 1000 Mbps QSGMII with 1000BaseX auto-negotiation between 237 MAC and QSGMII phy or backplane */ 238 E_ENET_MODE_XGMII_10000 = (E_ENET_IF_XGMII | E_ENET_SPEED_10000), 239 /**< 10000 Mbps XGMII */ 240 E_ENET_MODE_XFI_10000 = (E_ENET_IF_XFI | E_ENET_SPEED_10000) 241 /**< 10000 Mbps XFI */ 242}; 243 244enum fmam_mac_statistics_level { 245 E_FMAN_MAC_NONE_STATISTICS, /**< No statistics */ 246 E_FMAN_MAC_PARTIAL_STATISTICS, /**< Only error counters are available; 247 Optimized for performance */ 248 E_FMAN_MAC_FULL_STATISTICS /**< All counters available; Not 249 optimized for performance */ 250}; 251 252#define _MAKE_ENET_MODE(_interface, _speed) (enum enet_mode)((_interface) \ 253 | (_speed)) 254 255#define _ENET_INTERFACE_FROM_MODE(mode) (enum enet_interface) \ 256 ((mode) & 0x0FFF0000) 257#define _ENET_SPEED_FROM_MODE(mode) (enum enet_speed)((mode) & 0x0000FFFF) 258#define _ENET_ADDR_TO_UINT64(_enet_addr) \ 259 (uint64_t)(((uint64_t)(_enet_addr)[0] << 40) | \ 260 ((uint64_t)(_enet_addr)[1] << 32) | \ 261 ((uint64_t)(_enet_addr)[2] << 24) | \ 262 ((uint64_t)(_enet_addr)[3] << 16) | \ 263 ((uint64_t)(_enet_addr)[4] << 8) | \ 264 ((uint64_t)(_enet_addr)[5])) 265 266#define _MAKE_ENET_ADDR_FROM_UINT64(_addr64, _enet_addr) \ 267 do { \ 268 int i; \ 269 for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) \ 270 (_enet_addr)[i] = (uint8_t)((_addr64) >> ((5-i)*8));\ 271 } while (0) 272 273#endif /* __FSL_ENET_H */ 274