1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8
9/ {
10	/* these are used by bootloader for disabling nodes */
11	aliases {
12		led0 = &led0;
13		led1 = &led1;
14		led2 = &led2;
15		nand = &gpmi;
16		usb0 = &usbh1;
17		usb1 = &usbotg;
18	};
19
20	chosen {
21		stdout-path = &uart2;
22	};
23
24	gpio-keys {
25		compatible = "gpio-keys";
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		user-pb {
30			label = "user_pb";
31			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
32			linux,code = <BTN_0>;
33		};
34
35		user-pb1x {
36			label = "user_pb1x";
37			linux,code = <BTN_1>;
38			interrupt-parent = <&gsc>;
39			interrupts = <0>;
40		};
41
42		key-erased {
43			label = "key-erased";
44			linux,code = <BTN_2>;
45			interrupt-parent = <&gsc>;
46			interrupts = <1>;
47		};
48
49		eeprom-wp {
50			label = "eeprom_wp";
51			linux,code = <BTN_3>;
52			interrupt-parent = <&gsc>;
53			interrupts = <2>;
54		};
55
56		tamper {
57			label = "tamper";
58			linux,code = <BTN_4>;
59			interrupt-parent = <&gsc>;
60			interrupts = <5>;
61		};
62
63		switch-hold {
64			label = "switch_hold";
65			linux,code = <BTN_5>;
66			interrupt-parent = <&gsc>;
67			interrupts = <7>;
68		};
69	};
70
71	leds {
72		compatible = "gpio-leds";
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_gpio_leds>;
75
76		led0: user1 {
77			label = "user1";
78			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
79			default-state = "on";
80			linux,default-trigger = "heartbeat";
81		};
82
83		led1: user2 {
84			label = "user2";
85			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
86			default-state = "off";
87		};
88
89		led2: user3 {
90			label = "user3";
91			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
92			default-state = "off";
93		};
94	};
95
96	memory@10000000 {
97		device_type = "memory";
98		reg = <0x10000000 0x40000000>;
99	};
100
101	pps {
102		compatible = "pps-gpio";
103		pinctrl-names = "default";
104		pinctrl-0 = <&pinctrl_pps>;
105		gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
106	};
107
108	reg_3p3v: regulator-3p3v {
109		compatible = "regulator-fixed";
110		regulator-name = "3P3V";
111		regulator-min-microvolt = <3300000>;
112		regulator-max-microvolt = <3300000>;
113		regulator-always-on;
114	};
115
116	reg_usb_vbus: regulator-5p0v {
117		compatible = "regulator-fixed";
118		regulator-name = "usb_vbus";
119		regulator-min-microvolt = <5000000>;
120		regulator-max-microvolt = <5000000>;
121		regulator-always-on;
122	};
123};
124
125&can1 {
126	pinctrl-names = "default";
127	pinctrl-0 = <&pinctrl_flexcan1>;
128	status = "okay";
129};
130
131&ecspi2 {
132	cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
133	pinctrl-names = "default";
134	pinctrl-0 = <&pinctrl_ecspi2>;
135	status = "okay";
136};
137
138&fec {
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_enet>;
141	phy-mode = "rgmii-id";
142	status = "okay";
143};
144
145&gpmi {
146	pinctrl-names = "default";
147	pinctrl-0 = <&pinctrl_gpmi_nand>;
148	status = "okay";
149};
150
151&i2c1 {
152	clock-frequency = <100000>;
153	pinctrl-names = "default";
154	pinctrl-0 = <&pinctrl_i2c1>;
155	status = "okay";
156
157	gsc: gsc@20 {
158		compatible = "gw,gsc";
159		reg = <0x20>;
160		interrupt-parent = <&gpio1>;
161		interrupts = <4 GPIO_ACTIVE_LOW>;
162		interrupt-controller;
163		#interrupt-cells = <1>;
164		#address-cells = <1>;
165		#size-cells = <0>;
166
167		adc {
168			compatible = "gw,gsc-adc";
169			#address-cells = <1>;
170			#size-cells = <0>;
171
172			channel@0 {
173				gw,mode = <0>;
174				reg = <0x00>;
175				label = "temp";
176			};
177
178			channel@2 {
179				gw,mode = <1>;
180				reg = <0x02>;
181				label = "vdd_vin";
182			};
183
184			channel@5 {
185				gw,mode = <1>;
186				reg = <0x05>;
187				label = "vdd_3p3";
188			};
189
190			channel@8 {
191				gw,mode = <1>;
192				reg = <0x08>;
193				label = "vdd_bat";
194			};
195
196			channel@b {
197				gw,mode = <1>;
198				reg = <0x0b>;
199				label = "vdd_5p0";
200			};
201
202			channel@e {
203				gw,mode = <1>;
204				reg = <0xe>;
205				label = "vdd_arm";
206			};
207
208			channel@11 {
209				gw,mode = <1>;
210				reg = <0x11>;
211				label = "vdd_soc";
212			};
213
214			channel@14 {
215				gw,mode = <1>;
216				reg = <0x14>;
217				label = "vdd_3p0";
218			};
219
220			channel@17 {
221				gw,mode = <1>;
222				reg = <0x17>;
223				label = "vdd_1p5";
224			};
225
226			channel@1d {
227				gw,mode = <1>;
228				reg = <0x1d>;
229				label = "vdd_1p8";
230			};
231
232			channel@20 {
233				gw,mode = <1>;
234				reg = <0x20>;
235				label = "vdd_1p0";
236			};
237
238			channel@23 {
239				gw,mode = <1>;
240				reg = <0x23>;
241				label = "vdd_2p5";
242			};
243		};
244
245		fan-controller@a {
246			compatible = "gw,gsc-fan";
247			#address-cells = <1>;
248			#size-cells = <0>;
249			reg = <0x0a>;
250		};
251	};
252
253	gsc_gpio: gpio@23 {
254		compatible = "nxp,pca9555";
255		reg = <0x23>;
256		gpio-controller;
257		#gpio-cells = <2>;
258		interrupt-parent = <&gsc>;
259		interrupts = <4>;
260	};
261
262	eeprom@50 {
263		compatible = "atmel,24c02";
264		reg = <0x50>;
265		pagesize = <16>;
266	};
267
268	eeprom@51 {
269		compatible = "atmel,24c02";
270		reg = <0x51>;
271		pagesize = <16>;
272	};
273
274	eeprom@52 {
275		compatible = "atmel,24c02";
276		reg = <0x52>;
277		pagesize = <16>;
278	};
279
280	eeprom@53 {
281		compatible = "atmel,24c02";
282		reg = <0x53>;
283		pagesize = <16>;
284	};
285
286	rtc@68 {
287		compatible = "dallas,ds1672";
288		reg = <0x68>;
289	};
290};
291
292&i2c2 {
293	clock-frequency = <100000>;
294	pinctrl-names = "default";
295	pinctrl-0 = <&pinctrl_i2c2>;
296	status = "okay";
297};
298
299&i2c3 {
300	clock-frequency = <100000>;
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_i2c3>;
303	status = "okay";
304
305	accel@19 {
306		pinctrl-names = "default";
307		pinctrl-0 = <&pinctrl_accel>;
308		compatible = "st,lis2de12";
309		reg = <0x19>;
310		st,drdy-int-pin = <1>;
311		interrupt-parent = <&gpio7>;
312		interrupts = <13 0>;
313		interrupt-names = "INT1";
314	};
315};
316
317&pcie {
318	pinctrl-names = "default";
319	pinctrl-0 = <&pinctrl_pcie>;
320	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
321	status = "okay";
322};
323
324&pwm1 {
325	pinctrl-names = "default";
326	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
327	status = "disabled";
328};
329
330&pwm2 {
331	pinctrl-names = "default";
332	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
333	status = "disabled";
334};
335
336&pwm3 {
337	pinctrl-names = "default";
338	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
339	status = "disabled";
340};
341
342&pwm4 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
345	status = "disabled";
346};
347
348&uart1 {
349	pinctrl-names = "default";
350	pinctrl-0 = <&pinctrl_uart1>;
351	rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
352	status = "okay";
353};
354
355&uart2 {
356	pinctrl-names = "default";
357	pinctrl-0 = <&pinctrl_uart2>;
358	status = "okay";
359};
360
361&uart5 {
362	pinctrl-names = "default";
363	pinctrl-0 = <&pinctrl_uart5>;
364	status = "okay";
365};
366
367&usbotg {
368	vbus-supply = <&reg_usb_vbus>;
369	pinctrl-names = "default";
370	pinctrl-0 = <&pinctrl_usbotg>;
371	disable-over-current;
372	dr_mode = "host";
373	status = "okay";
374};
375
376&usbh1 {
377	vbus-supply = <&reg_usb_vbus>;
378	status = "okay";
379};
380
381&usdhc3 {
382	pinctrl-names = "default", "state_100mhz", "state_200mhz";
383	pinctrl-0 = <&pinctrl_usdhc3>;
384	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
385	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
386	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
387	vmmc-supply = <&reg_3p3v>;
388	no-1-8-v; /* firmware will remove if board revision supports */
389	status = "okay";
390};
391
392&wdog1 {
393	status = "disabled";
394};
395
396&wdog2 {
397	pinctrl-names = "default";
398	pinctrl-0 = <&pinctrl_wdog>;
399	fsl,ext-reset-output;
400	status = "okay";
401};
402
403&iomuxc {
404	pinctrl_accel: accelmuxgrp {
405		fsl,pins = <
406			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b1
407		>;
408	};
409
410	pinctrl_enet: enetgrp {
411		fsl,pins = <
412			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
413			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
414			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
415			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
416			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
417			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
418			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
419			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
420			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
421			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
422			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
423			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
424			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
425			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
426			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
427		>;
428	};
429
430	pinctrl_ecspi2: escpi2grp {
431		fsl,pins = <
432			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
433			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
434			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
435			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x100b1
436		>;
437	};
438
439	pinctrl_flexcan1: flexcan1grp {
440		fsl,pins = <
441			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
442			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
443			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0
444		>;
445	};
446
447	pinctrl_gpio_leds: gpioledsgrp {
448		fsl,pins = <
449			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
450			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
451			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
452		>;
453	};
454
455	pinctrl_gpmi_nand: gpminandgrp {
456		fsl,pins = <
457			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
458			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
459			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
460			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
461			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
462			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
463			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
464			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
465			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
466			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
467			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
468			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
469			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
470			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
471			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
472		>;
473	};
474
475	pinctrl_i2c1: i2c1grp {
476		fsl,pins = <
477			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
478			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
479			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x0001b0b0
480		>;
481	};
482
483	pinctrl_i2c2: i2c2grp {
484		fsl,pins = <
485			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
486			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
487		>;
488	};
489
490	pinctrl_i2c3: i2c3grp {
491		fsl,pins = <
492			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
493			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
494		>;
495	};
496
497	pinctrl_pcie: pciegrp {
498		fsl,pins = <
499			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
500			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0
501		>;
502	};
503
504	pinctrl_pps: ppsgrp {
505		fsl,pins = <
506			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x1b0b1
507		>;
508	};
509
510	pinctrl_pwm1: pwm1grp {
511		fsl,pins = <
512			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
513		>;
514	};
515
516	pinctrl_pwm2: pwm2grp {
517		fsl,pins = <
518			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
519		>;
520	};
521
522	pinctrl_pwm3: pwm3grp {
523		fsl,pins = <
524			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
525		>;
526	};
527
528	pinctrl_pwm4: pwm4grp {
529		fsl,pins = <
530			MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
531		>;
532	};
533
534	pinctrl_uart1: uart1grp {
535		fsl,pins = <
536			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
537			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
538			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x4001b0b1
539		>;
540	};
541
542	pinctrl_uart2: uart2grp {
543		fsl,pins = <
544			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
545			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
546			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x4001b0b1
547		>;
548	};
549
550	pinctrl_uart5: uart5grp {
551		fsl,pins = <
552			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
553			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
554		>;
555	};
556
557	pinctrl_usbotg: usbotggrp {
558		fsl,pins = <
559			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x13059
560		>;
561	};
562
563	pinctrl_usdhc3: usdhc3grp {
564		fsl,pins = <
565			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
566			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
567			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
568			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
569			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
570			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
571			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
572			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
573		>;
574	};
575
576	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
577		fsl,pins = <
578			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
579			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
580			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
581			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
582			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
583			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
584			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
585			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
586		>;
587	};
588
589	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
590		fsl,pins = <
591			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
592			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
593			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
594			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
595			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
596			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
597			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
598			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
599		>;
600	};
601
602	pinctrl_wdog: wdoggrp {
603		fsl,pins = <
604			MX6QDL_PAD_SD1_DAT3__WDOG2_B		0x1b0b0
605		>;
606	};
607};
608