1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49#include <dt-bindings/input/linux-event-codes.h> 50 51/ { 52 /* these are used by bootloader for disabling nodes */ 53 aliases { 54 led0 = &led0; 55 led1 = &led1; 56 led2 = &led2; 57 usb0 = &usbh1; 58 usb1 = &usbotg; 59 }; 60 61 chosen { 62 stdout-path = &uart2; 63 }; 64 65 backlight { 66 compatible = "pwm-backlight"; 67 pwms = <&pwm4 0 5000000>; 68 brightness-levels = <0 4 8 16 32 64 128 255>; 69 default-brightness-level = <7>; 70 }; 71 72 gpio-keys { 73 compatible = "gpio-keys"; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 user-pb { 78 label = "user_pb"; 79 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 80 linux,code = <BTN_0>; 81 }; 82 83 user-pb1x { 84 label = "user_pb1x"; 85 linux,code = <BTN_1>; 86 interrupt-parent = <&gsc>; 87 interrupts = <0>; 88 }; 89 90 key-erased { 91 label = "key-erased"; 92 linux,code = <BTN_2>; 93 interrupt-parent = <&gsc>; 94 interrupts = <1>; 95 }; 96 97 eeprom-wp { 98 label = "eeprom_wp"; 99 linux,code = <BTN_3>; 100 interrupt-parent = <&gsc>; 101 interrupts = <2>; 102 }; 103 104 tamper { 105 label = "tamper"; 106 linux,code = <BTN_4>; 107 interrupt-parent = <&gsc>; 108 interrupts = <5>; 109 }; 110 111 switch-hold { 112 label = "switch_hold"; 113 linux,code = <BTN_5>; 114 interrupt-parent = <&gsc>; 115 interrupts = <7>; 116 }; 117 }; 118 119 leds { 120 compatible = "gpio-leds"; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_gpio_leds>; 123 124 led0: user1 { 125 label = "user1"; 126 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 127 default-state = "on"; 128 linux,default-trigger = "heartbeat"; 129 }; 130 131 led1: user2 { 132 label = "user2"; 133 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 134 default-state = "off"; 135 }; 136 137 led2: user3 { 138 label = "user3"; 139 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 140 default-state = "off"; 141 }; 142 }; 143 144 memory@10000000 { 145 device_type = "memory"; 146 reg = <0x10000000 0x40000000>; 147 }; 148 149 pps { 150 compatible = "pps-gpio"; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_pps>; 153 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 154 }; 155 156 reg_1p0v: regulator-1p0v { 157 compatible = "regulator-fixed"; 158 regulator-name = "1P0V"; 159 regulator-min-microvolt = <1000000>; 160 regulator-max-microvolt = <1000000>; 161 regulator-always-on; 162 }; 163 164 reg_3p3v: regulator-3p3v { 165 compatible = "regulator-fixed"; 166 regulator-name = "3P3V"; 167 regulator-min-microvolt = <3300000>; 168 regulator-max-microvolt = <3300000>; 169 regulator-always-on; 170 }; 171 172 reg_usb_h1_vbus: regulator-usb-h1-vbus { 173 compatible = "regulator-fixed"; 174 regulator-name = "usb_h1_vbus"; 175 regulator-min-microvolt = <5000000>; 176 regulator-max-microvolt = <5000000>; 177 regulator-always-on; 178 }; 179 180 reg_usb_otg_vbus: regulator-usb-otg-vbus { 181 compatible = "regulator-fixed"; 182 regulator-name = "usb_otg_vbus"; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 186 enable-active-high; 187 }; 188}; 189 190&clks { 191 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 192 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 193 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 194 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 195}; 196 197&fec { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_enet>; 200 phy-mode = "rgmii-id"; 201 status = "okay"; 202 203 fixed-link { 204 speed = <1000>; 205 full-duplex; 206 }; 207 208 mdio { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 switch@0 { 213 compatible = "marvell,mv88e6085"; 214 reg = <0>; 215 216 ports { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 220 port@0 { 221 reg = <0>; 222 label = "lan4"; 223 }; 224 225 port@1 { 226 reg = <1>; 227 label = "lan3"; 228 }; 229 230 port@2 { 231 reg = <2>; 232 label = "lan2"; 233 }; 234 235 port@3 { 236 reg = <3>; 237 label = "lan1"; 238 }; 239 240 port@5 { 241 reg = <5>; 242 label = "cpu"; 243 ethernet = <&fec>; 244 }; 245 }; 246 }; 247 }; 248}; 249 250&i2c1 { 251 clock-frequency = <100000>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_i2c1>; 254 status = "okay"; 255 256 gsc: gsc@20 { 257 compatible = "gw,gsc"; 258 reg = <0x20>; 259 interrupt-parent = <&gpio1>; 260 interrupts = <4 GPIO_ACTIVE_LOW>; 261 interrupt-controller; 262 #interrupt-cells = <1>; 263 #size-cells = <0>; 264 265 adc { 266 compatible = "gw,gsc-adc"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 270 channel@0 { 271 gw,mode = <0>; 272 reg = <0x00>; 273 label = "temp"; 274 }; 275 276 channel@2 { 277 gw,mode = <1>; 278 reg = <0x02>; 279 label = "vdd_vin"; 280 }; 281 282 channel@5 { 283 gw,mode = <1>; 284 reg = <0x05>; 285 label = "vdd_3p3"; 286 }; 287 288 channel@8 { 289 gw,mode = <1>; 290 reg = <0x08>; 291 label = "vdd_bat"; 292 }; 293 294 channel@b { 295 gw,mode = <1>; 296 reg = <0x0b>; 297 label = "vdd_5p0"; 298 }; 299 300 channel@e { 301 gw,mode = <1>; 302 reg = <0xe>; 303 label = "vdd_arm"; 304 }; 305 306 channel@11 { 307 gw,mode = <1>; 308 reg = <0x11>; 309 label = "vdd_soc"; 310 }; 311 312 channel@14 { 313 gw,mode = <1>; 314 reg = <0x14>; 315 label = "vdd_3p0"; 316 }; 317 318 channel@17 { 319 gw,mode = <1>; 320 reg = <0x17>; 321 label = "vdd_1p5"; 322 }; 323 324 channel@1d { 325 gw,mode = <1>; 326 reg = <0x1d>; 327 label = "vdd_1p8"; 328 }; 329 330 channel@20 { 331 gw,mode = <1>; 332 reg = <0x20>; 333 label = "vdd_an1"; 334 }; 335 336 channel@23 { 337 gw,mode = <1>; 338 reg = <0x23>; 339 label = "vdd_2p5"; 340 }; 341 }; 342 }; 343 344 gsc_gpio: gpio@23 { 345 compatible = "nxp,pca9555"; 346 reg = <0x23>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-parent = <&gsc>; 350 interrupts = <4>; 351 }; 352 353 eeprom1: eeprom@50 { 354 compatible = "atmel,24c02"; 355 reg = <0x50>; 356 pagesize = <16>; 357 }; 358 359 eeprom2: eeprom@51 { 360 compatible = "atmel,24c02"; 361 reg = <0x51>; 362 pagesize = <16>; 363 }; 364 365 eeprom3: eeprom@52 { 366 compatible = "atmel,24c02"; 367 reg = <0x52>; 368 pagesize = <16>; 369 }; 370 371 eeprom4: eeprom@53 { 372 compatible = "atmel,24c02"; 373 reg = <0x53>; 374 pagesize = <16>; 375 }; 376 377 dts1672: rtc@68 { 378 compatible = "dallas,ds1672"; 379 reg = <0x68>; 380 }; 381}; 382 383&i2c2 { 384 clock-frequency = <100000>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_i2c2>; 387 status = "okay"; 388 389 magn@1c { 390 compatible = "st,lsm9ds1-magn"; 391 reg = <0x1c>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_mag>; 394 interrupt-parent = <&gpio5>; 395 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 396 }; 397 398 ltc3676: pmic@3c { 399 compatible = "lltc,ltc3676"; 400 reg = <0x3c>; 401 interrupt-parent = <&gpio1>; 402 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 403 404 regulators { 405 /* VDD_SOC (1+R1/R2 = 1.635) */ 406 reg_vdd_soc: sw1 { 407 regulator-name = "vddsoc"; 408 regulator-min-microvolt = <674400>; 409 regulator-max-microvolt = <1308000>; 410 lltc,fb-voltage-divider = <127000 200000>; 411 regulator-ramp-delay = <7000>; 412 regulator-boot-on; 413 regulator-always-on; 414 }; 415 416 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ 417 reg_1p8v: sw2 { 418 regulator-name = "vdd1p8"; 419 regulator-min-microvolt = <1033310>; 420 regulator-max-microvolt = <2004000>; 421 lltc,fb-voltage-divider = <301000 200000>; 422 regulator-ramp-delay = <7000>; 423 regulator-boot-on; 424 regulator-always-on; 425 }; 426 427 /* VDD_ARM (1+R1/R2 = 1.635) */ 428 reg_vdd_arm: sw3 { 429 regulator-name = "vddarm"; 430 regulator-min-microvolt = <674400>; 431 regulator-max-microvolt = <1308000>; 432 lltc,fb-voltage-divider = <127000 200000>; 433 regulator-ramp-delay = <7000>; 434 regulator-boot-on; 435 regulator-always-on; 436 }; 437 438 /* VDD_DDR (1+R1/R2 = 2.105) */ 439 reg_vdd_ddr: sw4 { 440 regulator-name = "vddddr"; 441 regulator-min-microvolt = <868310>; 442 regulator-max-microvolt = <1684000>; 443 lltc,fb-voltage-divider = <221000 200000>; 444 regulator-ramp-delay = <7000>; 445 regulator-boot-on; 446 regulator-always-on; 447 }; 448 449 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 450 reg_2p5v: ldo2 { 451 regulator-name = "vdd2p5"; 452 regulator-min-microvolt = <2490375>; 453 regulator-max-microvolt = <2490375>; 454 lltc,fb-voltage-divider = <487000 200000>; 455 regulator-boot-on; 456 regulator-always-on; 457 }; 458 459 /* VDD_HIGH (1+R1/R2 = 4.17) */ 460 reg_3p0v: ldo4 { 461 regulator-name = "vdd3p0"; 462 regulator-min-microvolt = <3023250>; 463 regulator-max-microvolt = <3023250>; 464 lltc,fb-voltage-divider = <634000 200000>; 465 regulator-boot-on; 466 regulator-always-on; 467 }; 468 }; 469 }; 470 471 imu@6a { 472 compatible = "st,lsm9ds1-imu"; 473 reg = <0x6a>; 474 st,drdy-int-pin = <1>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_imu>; 477 interrupt-parent = <&gpio4>; 478 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 479 }; 480}; 481 482&i2c3 { 483 clock-frequency = <100000>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&pinctrl_i2c3>; 486 status = "okay"; 487 488 egalax_ts: touchscreen@4 { 489 compatible = "eeti,egalax_ts"; 490 reg = <0x04>; 491 interrupt-parent = <&gpio1>; 492 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 493 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 494 }; 495}; 496 497&ldb { 498 status = "okay"; 499 500 lvds-channel@0 { 501 fsl,data-mapping = "spwg"; 502 fsl,data-width = <18>; 503 status = "okay"; 504 505 display-timings { 506 native-mode = <&timing0>; 507 timing0: hsd100pxn1 { 508 clock-frequency = <65000000>; 509 hactive = <1024>; 510 vactive = <768>; 511 hback-porch = <220>; 512 hfront-porch = <40>; 513 vback-porch = <21>; 514 vfront-porch = <7>; 515 hsync-len = <60>; 516 vsync-len = <10>; 517 }; 518 }; 519 }; 520}; 521 522&pcie { 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pinctrl_pcie>; 525 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 526 status = "okay"; 527}; 528 529&pwm2 { 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 532 status = "disabled"; 533}; 534 535&pwm3 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 538 status = "disabled"; 539}; 540 541&pwm4 { 542 #pwm-cells = <2>; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_pwm4>; 545 status = "okay"; 546}; 547 548&uart1 { 549 pinctrl-names = "default"; 550 pinctrl-0 = <&pinctrl_uart1>; 551 status = "okay"; 552}; 553 554&uart2 { 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_uart2>; 557 status = "okay"; 558}; 559 560&uart3 { 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_uart3>; 563 uart-has-rtscts; 564 status = "okay"; 565}; 566 567&uart4 { 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pinctrl_uart4>; 570 uart-has-rtscts; 571 status = "okay"; 572}; 573 574&uart5 { 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pinctrl_uart5>; 577 status = "okay"; 578}; 579 580&usbotg { 581 vbus-supply = <®_usb_otg_vbus>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&pinctrl_usbotg>; 584 disable-over-current; 585 status = "okay"; 586}; 587 588&usbh1 { 589 vbus-supply = <®_usb_h1_vbus>; 590 status = "okay"; 591}; 592 593&usdhc3 { 594 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 595 pinctrl-0 = <&pinctrl_usdhc3>; 596 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 597 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 598 non-removable; 599 vmmc-supply = <®_3p3v>; 600 keep-power-in-suspend; 601 status = "okay"; 602}; 603 604&wdog1 { 605 pinctrl-names = "default"; 606 pinctrl-0 = <&pinctrl_wdog>; 607 fsl,ext-reset-output; 608}; 609 610&iomuxc { 611 pinctrl_enet: enetgrp { 612 fsl,pins = < 613 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 614 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 615 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 616 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 617 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 618 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 619 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 620 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 621 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 622 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 623 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 624 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 625 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 626 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 627 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 628 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 629 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 630 >; 631 }; 632 633 pinctrl_gpio_leds: gpioledsgrp { 634 fsl,pins = < 635 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 636 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 637 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 638 >; 639 }; 640 641 pinctrl_i2c1: i2c1grp { 642 fsl,pins = < 643 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 644 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 645 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 646 >; 647 }; 648 649 pinctrl_i2c2: i2c2grp { 650 fsl,pins = < 651 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 652 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 653 >; 654 }; 655 656 pinctrl_i2c3: i2c3grp { 657 fsl,pins = < 658 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 659 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 660 >; 661 }; 662 663 pinctrl_imu: imugrp { 664 fsl,pins = < 665 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 666 >; 667 }; 668 669 pinctrl_mag: maggrp { 670 fsl,pins = < 671 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 672 >; 673 }; 674 675 pinctrl_pcie: pciegrp { 676 fsl,pins = < 677 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 678 >; 679 }; 680 681 pinctrl_pmic: pmicgrp { 682 fsl,pins = < 683 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ 684 >; 685 }; 686 687 pinctrl_pps: ppsgrp { 688 fsl,pins = < 689 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 690 >; 691 }; 692 693 pinctrl_pwm2: pwm2grp { 694 fsl,pins = < 695 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 696 >; 697 }; 698 699 pinctrl_pwm3: pwm3grp { 700 fsl,pins = < 701 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 702 >; 703 }; 704 705 pinctrl_pwm4: pwm4grp { 706 fsl,pins = < 707 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 708 >; 709 }; 710 711 pinctrl_uart1: uart1grp { 712 fsl,pins = < 713 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 714 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 715 >; 716 }; 717 718 pinctrl_uart2: uart2grp { 719 fsl,pins = < 720 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 721 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 722 >; 723 }; 724 725 pinctrl_uart3: uart3grp { 726 fsl,pins = < 727 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 728 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 729 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 730 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 731 >; 732 }; 733 734 pinctrl_uart4: uart4grp { 735 fsl,pins = < 736 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 737 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 738 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 739 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 740 >; 741 }; 742 743 pinctrl_uart5: uart5grp { 744 fsl,pins = < 745 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 746 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 747 >; 748 }; 749 750 pinctrl_usbotg: usbotggrp { 751 fsl,pins = < 752 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 753 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 754 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 755 >; 756 }; 757 758 pinctrl_usdhc3: usdhc3grp { 759 fsl,pins = < 760 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 761 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 762 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 763 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 764 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 765 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 766 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 767 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 768 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 769 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 770 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 771 >; 772 }; 773 774 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 775 fsl,pins = < 776 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 777 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 778 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 779 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 780 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 781 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 782 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 783 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 784 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 785 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 786 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 787 >; 788 }; 789 790 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 791 fsl,pins = < 792 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 793 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 794 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 795 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 796 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 797 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 798 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 799 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 800 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 801 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 802 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 803 >; 804 }; 805 806 pinctrl_wdog: wdoggrp { 807 fsl,pins = < 808 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 809 >; 810 }; 811}; 812