1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17/* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25#ifndef __ar9300templateAP121_h__ 26#define __ar9300templateAP121_h__ 27 28/* Ensure that AH_BYTE_ORDER is defined */ 29#ifndef AH_BYTE_ORDER 30#error AH_BYTE_ORDER needs to be defined! 31#endif 32 33static ar9300_eeprom_t ar9300_template_ap121= 34{ 35 36 2, // eeprom_version; 37 38 ar9300_eeprom_template_ap121, // template_version; 39 40 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; 41 42 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 43 44 {"ap121-010-00000"}, 45// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 46 47 //static OSPREY_BASE_EEP_HEADER base_eep_header= 48 49 { 50 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 51 0x11, // txrx_mask; //4 bits tx and 4 bits rx 52 {AR9300_OPFLAGS_11G , 0}, // op_cap_flags; 53 0, // rf_silent; 54 0, // blue_tooth_options; 55 0, // device_cap; 56 4, // device_type; // takes lower byte in eeprom location 57 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 58 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 59 0x0d, //feature_enable; //bit0 - enable tx temp comp 60 //bit1 - enable tx volt comp 61 //bit2 - enable fastClock - default to 1 62 //bit3 - enable doubling - default to 1 63 //bit4 - enable internal regulator - default to 0 64 //bit5 - enable paprd -- default to 0 65 0, //misc_configuration: bit0 - turn down drivestrength 66 6, // eeprom_write_enable_gpio 67 0, // wlan_disable_gpio 68 8, // wlan_led_gpio 69 0xff, // rx_band_select_gpio 70 0x10, // txrxgain 71 0, // swreg 72 }, 73 74 75 //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 76 { 77 78 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 79 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 80 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 81 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 82 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 83 25, // temp_slope; 84 0, // voltSlope; 85 {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 86 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 87 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 88 0, // quick drop 89 0, // xpa_bias_lvl; // 1 90 0x0e, // tx_frame_to_data_start; // 1 91 0x0e, // tx_frame_to_pa_on; // 1 92 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 93 0, // antenna_gain; // 1 94 0x2c, // switchSettling; // 1 95 -30, // adcDesiredSize; // 1 96 0, // txEndToXpaOff; // 1 97 0x2, // txEndToRxOn; // 1 98 0xe, // tx_frame_to_xpa_on; // 1 99 28, // thresh62; // 1 100 0x80c0e0, // paprd_rate_mask_ht20 // 4 101 0x1ffffff, // paprd_rate_mask_ht40 102 0, // switchcomspdt; // 2 103 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 104 0, // rf_gain_cap 105 0, // tx_gain_cap 106 {0,0,0,0,0} //futureModal[5]; 107 }, 108 109 { 110 6, // ant_div_control 111 {0,0}, // base_ext1 112 0, // misc_enable 113 {0,0,0,0,0,0,0,0}, // temp slop extension 114 0, // quick drop low 115 0, // quick drop high 116 }, 117 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 118 { 119 FREQ2FBIN(2412, 1), 120 FREQ2FBIN(2437, 1), 121 FREQ2FBIN(2462, 1) 122 }, 123 124 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 125 126 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 127 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 128 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 129 }, 130 131 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 132 133 { 134 FREQ2FBIN(2412, 1), 135 FREQ2FBIN(2472, 1) 136 }, 137 138 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 139 { 140 FREQ2FBIN(2412, 1), 141 FREQ2FBIN(2437, 1), 142 FREQ2FBIN(2472, 1) 143 }, 144 145 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 146 { 147 FREQ2FBIN(2412, 1), 148 FREQ2FBIN(2437, 1), 149 FREQ2FBIN(2472, 1) 150 }, 151 152 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 153 { 154 FREQ2FBIN(2412, 1), 155 FREQ2FBIN(2437, 1), 156 FREQ2FBIN(2472, 1) 157 }, 158 159 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 160 { 161 //1L-5L,5S,11L,11S 162 {{34,34,34,34}}, 163 {{34,34,34,34}} 164 }, 165 166 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 167 { 168 //6-24,36,48,54 169 {{34,34,32,32}}, 170 {{34,34,32,32}}, 171 {{34,34,32,32}}, 172 }, 173 174 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 175 { 176 //0_8_16,1-3_9-11_17-19, 177 // 4,5,6,7,12,13,14,15,20,21,22,23 178 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, 179 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, 180 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}}, 181 }, 182 183 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 184 { 185 //0_8_16,1-3_9-11_17-19, 186 // 4,5,6,7,12,13,14,15,20,21,22,23 187 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, 188 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, 189 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}}, 190 }, 191 192//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 193 194 { 195 196 0x11, 197 0x12, 198 0x15, 199 0x17, 200 0x41, 201 0x42, 202 0x45, 203 0x47, 204 0x31, 205 0x32, 206 0x35, 207 0x37 208 209 }, 210 211//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 212 213 { 214 {FREQ2FBIN(2412, 1), 215 FREQ2FBIN(2417, 1), 216 FREQ2FBIN(2457, 1), 217 FREQ2FBIN(2462, 1)}, 218 219 {FREQ2FBIN(2412, 1), 220 FREQ2FBIN(2417, 1), 221 FREQ2FBIN(2462, 1), 222 0xFF}, 223 224 {FREQ2FBIN(2412, 1), 225 FREQ2FBIN(2417, 1), 226 FREQ2FBIN(2462, 1), 227 0xFF}, 228 229 {FREQ2FBIN(2422, 1), 230 FREQ2FBIN(2427, 1), 231 FREQ2FBIN(2447, 1), 232 FREQ2FBIN(2452, 1)}, 233 234 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 235 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 236 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 237 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 238 239 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 240 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 241 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 242 0}, 243 244 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 245 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 246 FREQ2FBIN(2472, 1), 247 0}, 248 249 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 250 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 251 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 252 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 253 254 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 255 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 256 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 257 0}, 258 259 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 260 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 261 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 262 0}, 263 264 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 265 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 266 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 267 0}, 268 269 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 270 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 271 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 272 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 273 }, 274 275 276//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 277 278#if AH_BYTE_ORDER == AH_BIG_ENDIAN 279 { 280 281 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 282 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 283 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 284 285 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 286 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 287 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 288 289 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 290 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 291 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 292 293 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 294 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 295 296 }, 297#else 298 { 299 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 300 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 301 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 302 303 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 304 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 305 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 306 307 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 308 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 309 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 310 311 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 312 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 313 }, 314#endif 315 316//static OSPREY_MODAL_EEP_HEADER modal_header_5g= 317 318 { 319 320 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 321 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 322 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 323 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 324 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 325 45, // temp_slope; 326 0, // voltSlope; 327 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 328 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 329 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 330 0, // quick drop 331 0, // xpa_bias_lvl; // 1 332 0x0e, // tx_frame_to_data_start; // 1 333 0x0e, // tx_frame_to_pa_on; // 1 334 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 335 0, // antenna_gain; // 1 336 0x2d, // switchSettling; // 1 337 -30, // adcDesiredSize; // 1 338 0, // txEndToXpaOff; // 1 339 0x2, // txEndToRxOn; // 1 340 0xe, // tx_frame_to_xpa_on; // 1 341 28, // thresh62; // 1 342 0xf0e0e0, // paprd_rate_mask_ht20 // 4 343 0xf0e0e0, // paprd_rate_mask_ht40 // 4 344 0, // switchcomspdt; // 2 345 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 346 0, // rf_gain_cap 347 0, // tx_gain_cap 348 {0,0,0,0,0} //futureModal[5]; 349 }, 350 351 { // base_ext2 352 40, // temp_slope_low 353 50, // temp_slope_high 354 {0,0,0}, 355 {0,0,0}, 356 {0,0,0}, 357 {0,0,0} 358 }, 359 360//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 361 { 362 //pPiers[0] = 363 FREQ2FBIN(5180, 0), 364 //pPiers[1] = 365 FREQ2FBIN(5220, 0), 366 //pPiers[2] = 367 FREQ2FBIN(5320, 0), 368 //pPiers[3] = 369 FREQ2FBIN(5400, 0), 370 //pPiers[4] = 371 FREQ2FBIN(5500, 0), 372 //pPiers[5] = 373 FREQ2FBIN(5600, 0), 374 //pPiers[6] = 375 FREQ2FBIN(5700, 0), 376 //pPiers[7] = 377 FREQ2FBIN(5785, 0), 378 }, 379 380//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 381 382 { 383 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 384 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 385 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 386 387 }, 388 389//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 390 391 { 392 FREQ2FBIN(5180, 0), 393 FREQ2FBIN(5240, 0), 394 FREQ2FBIN(5320, 0), 395 FREQ2FBIN(5400, 0), 396 FREQ2FBIN(5500, 0), 397 FREQ2FBIN(5600, 0), 398 FREQ2FBIN(5700, 0), 399 FREQ2FBIN(5825, 0) 400 }, 401 402//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 403 404 { 405 FREQ2FBIN(5180, 0), 406 FREQ2FBIN(5240, 0), 407 FREQ2FBIN(5320, 0), 408 FREQ2FBIN(5400, 0), 409 FREQ2FBIN(5500, 0), 410 FREQ2FBIN(5700, 0), 411 FREQ2FBIN(5745, 0), 412 FREQ2FBIN(5825, 0) 413 }, 414 415//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 416 417 { 418 FREQ2FBIN(5180, 0), 419 FREQ2FBIN(5240, 0), 420 FREQ2FBIN(5320, 0), 421 FREQ2FBIN(5400, 0), 422 FREQ2FBIN(5500, 0), 423 FREQ2FBIN(5700, 0), 424 FREQ2FBIN(5745, 0), 425 FREQ2FBIN(5825, 0) 426 }, 427 428 429//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 430 431 432 { 433 //6-24,36,48,54 434 {{30,30,28,24}}, 435 {{30,30,28,24}}, 436 {{30,30,28,24}}, 437 {{30,30,28,24}}, 438 {{30,30,28,24}}, 439 {{30,30,28,24}}, 440 {{30,30,28,24}}, 441 {{30,30,28,24}}, 442 }, 443 444//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 445 446 { 447 //0_8_16,1-3_9-11_17-19, 448 // 4,5,6,7,12,13,14,15,20,21,22,23 449 {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, 450 {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}}, 451 {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, 452 {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}}, 453 {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, 454 {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}}, 455 {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, 456 {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}}, 457 }, 458 459//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 460 { 461 //0_8_16,1-3_9-11_17-19, 462 // 4,5,6,7,12,13,14,15,20,21,22,23 463 {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, 464 {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}}, 465 {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, 466 {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}}, 467 {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, 468 {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}}, 469 {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, 470 {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}}, 471 }, 472 473//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 474 475 { 476 //pCtlIndex[0] = 477 0x10, 478 //pCtlIndex[1] = 479 0x16, 480 //pCtlIndex[2] = 481 0x18, 482 //pCtlIndex[3] = 483 0x40, 484 //pCtlIndex[4] = 485 0x46, 486 //pCtlIndex[5] = 487 0x48, 488 //pCtlIndex[6] = 489 0x30, 490 //pCtlIndex[7] = 491 0x36, 492 //pCtlIndex[8] = 493 0x38 494 }, 495 496// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 497 498 { 499 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 500 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 501 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 502 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 503 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 504 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 505 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 506 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 507 508 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 509 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 510 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 511 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 512 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 513 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 514 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 515 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 516 517 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 518 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 519 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 520 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 521 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 522 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 523 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 524 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 525 526 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 527 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 528 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 529 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 530 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 531 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 532 /* Data[3].ctl_edges[6].bChannel*/0xFF, 533 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 534 535 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 536 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 537 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 538 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 539 /* Data[4].ctl_edges[4].bChannel*/0xFF, 540 /* Data[4].ctl_edges[5].bChannel*/0xFF, 541 /* Data[4].ctl_edges[6].bChannel*/0xFF, 542 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 543 544 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 545 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 546 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 547 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 548 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 549 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 550 /* Data[5].ctl_edges[6].bChannel*/0xFF, 551 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 552 553 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 554 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 555 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 556 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 557 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 558 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 559 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 560 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 561 562 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 563 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 564 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 565 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 566 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 567 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 568 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 569 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 570 571 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 572 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 573 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 574 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 575 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 576 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 577 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 578 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 579 }, 580 581//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 582 583#if AH_BYTE_ORDER == AH_BIG_ENDIAN 584 { 585 {{{1, 60}, 586 {1, 60}, 587 {1, 60}, 588 {1, 60}, 589 {1, 60}, 590 {1, 60}, 591 {1, 60}, 592 {0, 60}}}, 593 594 {{{1, 60}, 595 {1, 60}, 596 {1, 60}, 597 {1, 60}, 598 {1, 60}, 599 {1, 60}, 600 {1, 60}, 601 {0, 60}}}, 602 603 {{{0, 60}, 604 {1, 60}, 605 {0, 60}, 606 {1, 60}, 607 {1, 60}, 608 {1, 60}, 609 {1, 60}, 610 {1, 60}}}, 611 612 {{{0, 60}, 613 {1, 60}, 614 {1, 60}, 615 {0, 60}, 616 {1, 60}, 617 {0, 60}, 618 {0, 60}, 619 {0, 60}}}, 620 621 {{{1, 60}, 622 {1, 60}, 623 {1, 60}, 624 {0, 60}, 625 {0, 60}, 626 {0, 60}, 627 {0, 60}, 628 {0, 60}}}, 629 630 {{{1, 60}, 631 {1, 60}, 632 {1, 60}, 633 {1, 60}, 634 {1, 60}, 635 {0, 60}, 636 {0, 60}, 637 {0, 60}}}, 638 639 {{{1, 60}, 640 {1, 60}, 641 {1, 60}, 642 {1, 60}, 643 {1, 60}, 644 {1, 60}, 645 {1, 60}, 646 {1, 60}}}, 647 648 {{{1, 60}, 649 {1, 60}, 650 {0, 60}, 651 {1, 60}, 652 {1, 60}, 653 {1, 60}, 654 {1, 60}, 655 {0, 60}}}, 656 657 {{{1, 60}, 658 {0, 60}, 659 {1, 60}, 660 {1, 60}, 661 {1, 60}, 662 {1, 60}, 663 {0, 60}, 664 {1, 60}}}, 665 } 666#else 667 { 668 {{{60, 1}, 669 {60, 1}, 670 {60, 1}, 671 {60, 1}, 672 {60, 1}, 673 {60, 1}, 674 {60, 1}, 675 {60, 0}}}, 676 677 {{{60, 1}, 678 {60, 1}, 679 {60, 1}, 680 {60, 1}, 681 {60, 1}, 682 {60, 1}, 683 {60, 1}, 684 {60, 0}}}, 685 686 {{{60, 0}, 687 {60, 1}, 688 {60, 0}, 689 {60, 1}, 690 {60, 1}, 691 {60, 1}, 692 {60, 1}, 693 {60, 1}}}, 694 695 {{{60, 0}, 696 {60, 1}, 697 {60, 1}, 698 {60, 0}, 699 {60, 1}, 700 {60, 0}, 701 {60, 0}, 702 {60, 0}}}, 703 704 {{{60, 1}, 705 {60, 1}, 706 {60, 1}, 707 {60, 0}, 708 {60, 0}, 709 {60, 0}, 710 {60, 0}, 711 {60, 0}}}, 712 713 {{{60, 1}, 714 {60, 1}, 715 {60, 1}, 716 {60, 1}, 717 {60, 1}, 718 {60, 0}, 719 {60, 0}, 720 {60, 0}}}, 721 722 {{{60, 1}, 723 {60, 1}, 724 {60, 1}, 725 {60, 1}, 726 {60, 1}, 727 {60, 1}, 728 {60, 1}, 729 {60, 1}}}, 730 731 {{{60, 1}, 732 {60, 1}, 733 {60, 0}, 734 {60, 1}, 735 {60, 1}, 736 {60, 1}, 737 {60, 1}, 738 {60, 0}}}, 739 740 {{{60, 1}, 741 {60, 0}, 742 {60, 1}, 743 {60, 1}, 744 {60, 1}, 745 {60, 1}, 746 {60, 0}, 747 {60, 1}}}, 748 } 749#endif 750}; 751 752#endif 753 754