1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include <sys/param.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/mutex.h> 36#include <sys/rman.h> 37#include <machine/bus.h> 38 39#include <dev/ofw/ofw_bus.h> 40#include <dev/ofw/ofw_bus_subr.h> 41 42#include <dev/iicbus/iiconf.h> 43#include <dev/iicbus/iicbus.h> 44 45#include <dev/extres/clk/clk.h> 46 47#include "iicbus_if.h" 48 49#define RK_I2C_CON 0x00 50#define RK_I2C_CON_EN (1 << 0) 51#define RK_I2C_CON_MODE_SHIFT 1 52#define RK_I2C_CON_MODE_TX 0 53#define RK_I2C_CON_MODE_RRX 1 54#define RK_I2C_CON_MODE_RX 2 55#define RK_I2C_CON_MODE_RTX 3 56#define RK_I2C_CON_MODE_MASK 0x6 57#define RK_I2C_CON_START (1 << 3) 58#define RK_I2C_CON_STOP (1 << 4) 59#define RK_I2C_CON_LASTACK (1 << 5) 60#define RK_I2C_CON_NAKSTOP (1 << 6) 61#define RK_I2C_CON_CTRL_MASK 0xFF 62 63#define RK_I2C_CLKDIV 0x04 64#define RK_I2C_CLKDIVL_MASK 0xFFFF 65#define RK_I2C_CLKDIVL_SHIFT 0 66#define RK_I2C_CLKDIVH_MASK 0xFFFF0000 67#define RK_I2C_CLKDIVH_SHIFT 16 68#define RK_I2C_CLKDIV_MUL 8 69 70#define RK_I2C_MRXADDR 0x08 71#define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF 72#define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x)) 73 74#define RK_I2C_MRXRADDR 0x0C 75#define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF 76#define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x)) 77 78#define RK_I2C_MTXCNT 0x10 79#define RK_I2C_MTXCNT_MASK 0x3F 80 81#define RK_I2C_MRXCNT 0x14 82#define RK_I2C_MRXCNT_MASK 0x3F 83 84#define RK_I2C_IEN 0x18 85#define RK_I2C_IEN_BTFIEN (1 << 0) 86#define RK_I2C_IEN_BRFIEN (1 << 1) 87#define RK_I2C_IEN_MBTFIEN (1 << 2) 88#define RK_I2C_IEN_MBRFIEN (1 << 3) 89#define RK_I2C_IEN_STARTIEN (1 << 4) 90#define RK_I2C_IEN_STOPIEN (1 << 5) 91#define RK_I2C_IEN_NAKRCVIEN (1 << 6) 92#define RK_I2C_IEN_ALL (RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \ 93 RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN) 94 95#define RK_I2C_IPD 0x1C 96#define RK_I2C_IPD_BTFIPD (1 << 0) 97#define RK_I2C_IPD_BRFIPD (1 << 1) 98#define RK_I2C_IPD_MBTFIPD (1 << 2) 99#define RK_I2C_IPD_MBRFIPD (1 << 3) 100#define RK_I2C_IPD_STARTIPD (1 << 4) 101#define RK_I2C_IPD_STOPIPD (1 << 5) 102#define RK_I2C_IPD_NAKRCVIPD (1 << 6) 103#define RK_I2C_IPD_ALL (RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \ 104 RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD) 105 106#define RK_I2C_FNCT 0x20 107#define RK_I2C_FNCT_MASK 0x3F 108 109#define RK_I2C_TXDATA_BASE 0x100 110 111#define RK_I2C_RXDATA_BASE 0x200 112 113enum rk_i2c_state { 114 STATE_IDLE = 0, 115 STATE_START, 116 STATE_READ, 117 STATE_WRITE, 118 STATE_STOP 119}; 120 121struct rk_i2c_softc { 122 device_t dev; 123 struct resource *res[2]; 124 struct mtx mtx; 125 clk_t sclk; 126 clk_t pclk; 127 int busy; 128 void * intrhand; 129 uint32_t intr; 130 uint32_t ipd; 131 struct iic_msg *msg; 132 size_t cnt; 133 int msg_len; 134 bool transfer_done; 135 bool nak_recv; 136 bool tx_slave_addr; 137 uint8_t mode; 138 uint8_t state; 139 140 device_t iicbus; 141}; 142 143static struct ofw_compat_data compat_data[] = { 144 {"rockchip,rk3288-i2c", 1}, 145 {"rockchip,rk3328-i2c", 1}, 146 {"rockchip,rk3399-i2c", 1}, 147 {NULL, 0} 148}; 149 150static struct resource_spec rk_i2c_spec[] = { 151 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 152 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 153 { -1, 0 } 154}; 155 156static int rk_i2c_probe(device_t dev); 157static int rk_i2c_attach(device_t dev); 158static int rk_i2c_detach(device_t dev); 159 160#define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx) 161#define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 162#define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 163#define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 164#define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 165 166static uint32_t 167rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint32_t speed) 168{ 169 uint64_t sclk_freq; 170 uint32_t clkdiv; 171 int err; 172 173 err = clk_get_freq(sc->sclk, &sclk_freq); 174 if (err != 0) 175 return (err); 176 177 clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1; 178 clkdiv &= RK_I2C_CLKDIVL_MASK; 179 180 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv; 181 182 return (clkdiv); 183} 184 185static int 186rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 187{ 188 struct rk_i2c_softc *sc; 189 uint32_t clkdiv; 190 u_int busfreq; 191 192 sc = device_get_softc(dev); 193 194 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 195 196 clkdiv = rk_i2c_get_clkdiv(sc, busfreq); 197 198 RK_I2C_LOCK(sc); 199 200 /* Set the clock divider */ 201 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv); 202 203 /* Disable the module */ 204 RK_I2C_WRITE(sc, RK_I2C_CON, 0); 205 206 RK_I2C_UNLOCK(sc); 207 208 return (0); 209} 210 211static uint8_t 212rk_i2c_fill_tx(struct rk_i2c_softc *sc) 213{ 214 uint32_t buf32; 215 uint8_t buf; 216 int i, j, len; 217 218 if (sc->msg == NULL || sc->msg->len == sc->cnt) 219 return (0); 220 221 len = sc->msg->len - sc->cnt; 222 if (len > 8) 223 len = 8; 224 225 for (i = 0; i < len; i++) { 226 buf32 = 0; 227 for (j = 0; j < 4 ; j++) { 228 if (sc->cnt == sc->msg->len) 229 break; 230 231 /* Fill the addr if needed */ 232 if (sc->cnt == 0 && sc->tx_slave_addr) { 233 buf = sc->msg->slave; 234 sc->tx_slave_addr = false; 235 } else { 236 buf = sc->msg->buf[sc->cnt]; 237 sc->cnt++; 238 } 239 buf32 |= buf << (j * 8); 240 } 241 RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + 4 * i, buf32); 242 243 if (sc->cnt == sc->msg->len) 244 break; 245 } 246 247 return (uint8_t)len; 248} 249 250static void 251rk_i2c_drain_rx(struct rk_i2c_softc *sc) 252{ 253 uint32_t buf32 = 0; 254 uint8_t buf8; 255 int len; 256 int i; 257 258 if (sc->msg == NULL) { 259 device_printf(sc->dev, "No current iic msg\n"); 260 return; 261 } 262 263 len = sc->msg->len - sc->cnt; 264 if (len > 32) 265 len = 32; 266 267 for (i = 0; i < len; i++) { 268 if (i % 4 == 0) 269 buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + (i / 4) * 4); 270 271 buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF; 272 sc->msg->buf[sc->cnt++] = buf8; 273 } 274} 275 276static void 277rk_i2c_send_stop(struct rk_i2c_softc *sc) 278{ 279 uint32_t reg; 280 281 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN); 282 283 sc->state = STATE_STOP; 284 285 reg = RK_I2C_READ(sc, RK_I2C_CON); 286 reg |= RK_I2C_CON_STOP; 287 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 288} 289 290static void 291rk_i2c_intr_locked(struct rk_i2c_softc *sc) 292{ 293 uint32_t reg; 294 295 sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD); 296 297 /* Something to handle? */ 298 if ((sc->ipd & RK_I2C_IPD_ALL) == 0) 299 return; 300 301 RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd); 302 sc->ipd &= RK_I2C_IPD_ALL; 303 304 if (sc->ipd & RK_I2C_IPD_NAKRCVIPD) { 305 /* NACK received */ 306 sc->ipd &= ~RK_I2C_IPD_NAKRCVIPD; 307 sc->nak_recv = 1; 308 /* XXXX last byte !!!, signal error !!! */ 309 sc->transfer_done = 1; 310 sc->state = STATE_IDLE; 311 goto err; 312 } 313 314 switch (sc->state) { 315 case STATE_START: 316 /* Disable start bit */ 317 reg = RK_I2C_READ(sc, RK_I2C_CON); 318 reg &= ~RK_I2C_CON_START; 319 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 320 321 if (sc->mode == RK_I2C_CON_MODE_RRX || 322 sc->mode == RK_I2C_CON_MODE_RX) { 323 sc->state = STATE_READ; 324 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN | 325 RK_I2C_IEN_NAKRCVIEN); 326 327 reg = RK_I2C_READ(sc, RK_I2C_CON); 328 reg |= RK_I2C_CON_LASTACK; 329 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 330 331 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len); 332 } else { 333 sc->state = STATE_WRITE; 334 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN | 335 RK_I2C_IEN_NAKRCVIEN); 336 337 sc->msg->len += 1; 338 rk_i2c_fill_tx(sc); 339 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, sc->msg->len); 340 } 341 break; 342 case STATE_READ: 343 rk_i2c_drain_rx(sc); 344 345 if (sc->cnt == sc->msg->len) 346 rk_i2c_send_stop(sc); 347 348 break; 349 case STATE_WRITE: 350 if (sc->cnt == sc->msg->len && 351 !(sc->msg->flags & IIC_M_NOSTOP)) { 352 rk_i2c_send_stop(sc); 353 break; 354 } 355 /* passthru */ 356 case STATE_STOP: 357 /* Disable stop bit */ 358 reg = RK_I2C_READ(sc, RK_I2C_CON); 359 reg &= ~RK_I2C_CON_STOP; 360 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 361 362 sc->transfer_done = 1; 363 sc->state = STATE_IDLE; 364 break; 365 case STATE_IDLE: 366 break; 367 } 368 369err: 370 wakeup(sc); 371} 372 373static void 374rk_i2c_intr(void *arg) 375{ 376 struct rk_i2c_softc *sc; 377 378 sc = (struct rk_i2c_softc *)arg; 379 380 RK_I2C_LOCK(sc); 381 rk_i2c_intr_locked(sc); 382 RK_I2C_UNLOCK(sc); 383} 384 385static void 386rk_i2c_start_xfer(struct rk_i2c_softc *sc, struct iic_msg *msg, boolean_t last) 387{ 388 uint32_t reg; 389 uint8_t len; 390 391 sc->transfer_done = false; 392 sc->nak_recv = false; 393 sc->tx_slave_addr = false; 394 sc->cnt = 0; 395 sc->state = STATE_IDLE; 396 sc->msg = msg; 397 sc->msg_len = sc->msg->len; 398 399 reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK; 400 if (!(sc->msg->flags & IIC_M_NOSTART)) { 401 /* Stadard message */ 402 if (sc->mode == RK_I2C_CON_MODE_TX) { 403 sc->msg_len++; /* Take slave address in account. */ 404 sc->tx_slave_addr = true; 405 } 406 sc->state = STATE_START; 407 reg |= RK_I2C_CON_START; 408 409 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN); 410 } else { 411 /* Continuation message */ 412 if (sc->mode == RK_I2C_CON_MODE_RX) { 413 sc->state = STATE_READ; 414 if (last) 415 reg |= RK_I2C_CON_LASTACK; 416 417 RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len); 418 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN | 419 RK_I2C_IEN_NAKRCVIEN); 420 } else { 421 sc->state = STATE_WRITE; 422 len = rk_i2c_fill_tx(sc); 423 424 RK_I2C_WRITE(sc, RK_I2C_MTXCNT, len); 425 426 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN | 427 RK_I2C_IEN_NAKRCVIEN); 428 } 429 } 430 reg |= sc->mode << RK_I2C_CON_MODE_SHIFT; 431 reg |= RK_I2C_CON_EN; 432 RK_I2C_WRITE(sc, RK_I2C_CON, reg); 433} 434 435static int 436rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 437{ 438 struct rk_i2c_softc *sc; 439 uint32_t reg; 440 bool last_msg; 441 int i, j, timeout, err; 442 443 sc = device_get_softc(dev); 444 445 RK_I2C_LOCK(sc); 446 447 while (sc->busy) 448 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); 449 sc->busy = 1; 450 451 /* Disable the module and interrupts */ 452 RK_I2C_WRITE(sc, RK_I2C_CON, 0); 453 RK_I2C_WRITE(sc, RK_I2C_IEN, 0); 454 455 /* Clean stale interrupts */ 456 RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL); 457 458 err = 0; 459 for (i = 0; i < nmsgs; i++) { 460 /* Validate parameters. */ 461 if (msgs == NULL || msgs[i].buf == NULL || 462 msgs[i].len == 0) { 463 err = EINVAL; 464 break; 465 } 466 /* 467 * If next message have NOSTART flag, then they both 468 * should be same type (read/write) and same address. 469 */ 470 if (i < nmsgs - 1) { 471 if ((msgs[i + 1].flags & IIC_M_NOSTART) && 472 ((msgs[i].flags & IIC_M_RD) != 473 (msgs[i + 1].flags & IIC_M_RD) || 474 (msgs[i].slave != msgs[i + 1].slave))) { 475 err = EINVAL; 476 break; 477 } 478 } 479 /* 480 * Detect simple register read case. 481 * The first message should be IIC_M_WR | IIC_M_NOSTOP, 482 * next pure IIC_M_RD (no other flags allowed). Both 483 * messages should have same slave address. 484 */ 485 486 if (nmsgs - i >= 2 && msgs[i].len < 4 && 487 msgs[i].flags == (IIC_M_WR | IIC_M_NOSTOP) && 488 msgs[i + 1].flags == IIC_M_RD && 489 (msgs[i].slave & ~LSB) == (msgs[i + 1].slave & ~LSB)) { 490 sc->mode = RK_I2C_CON_MODE_RRX; 491 492 /* Write slave address */ 493 reg = msgs[i].slave & ~LSB; 494 reg |= RK_I2C_MRXADDR_VALID(0); 495 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg); 496 497 /* Write slave register address */ 498 reg = 0; 499 for (j = 0; j < msgs[i].len ; j++) { 500 reg |= (msgs[i].buf[j] & 0xff) << (j * 8); 501 reg |= RK_I2C_MRXADDR_VALID(j); 502 } 503 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg); 504 505 i++; 506 } else { 507 if (msgs[i].flags & IIC_M_RD) { 508 if (msgs[i].flags & IIC_M_NOSTART) { 509 sc->mode = RK_I2C_CON_MODE_RX; 510 } else { 511 sc->mode = RK_I2C_CON_MODE_RRX; 512 reg = msgs[i].slave & LSB; 513 reg |= RK_I2C_MRXADDR_VALID(0); 514 RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg); 515 RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, 0); 516 } 517 } else { 518 sc->mode = RK_I2C_CON_MODE_TX; 519 } 520 } 521 /* last message ? */ 522 last_msg = (i > nmsgs - 1) || 523 !(msgs[i + 1].flags & IIC_M_NOSTART); 524 rk_i2c_start_xfer(sc, msgs + i, last_msg); 525 526 if (cold) { 527 for(timeout = 10000; timeout > 0; timeout--) { 528 rk_i2c_intr_locked(sc); 529 if (sc->transfer_done != 0) 530 break; 531 DELAY(1000); 532 } 533 if (timeout <= 0) 534 err = ETIMEDOUT; 535 } else { 536 while (err == 0 && sc->transfer_done != 1) { 537 err = msleep(sc, &sc->mtx, PZERO, "rk_i2c", 538 10 * hz); 539 } 540 } 541 } 542 543 /* Disable the module and interrupts */ 544 RK_I2C_WRITE(sc, RK_I2C_CON, 0); 545 RK_I2C_WRITE(sc, RK_I2C_IEN, 0); 546 547 sc->busy = 0; 548 549 RK_I2C_UNLOCK(sc); 550 return (err); 551} 552 553static int 554rk_i2c_probe(device_t dev) 555{ 556 557 if (!ofw_bus_status_okay(dev)) 558 return (ENXIO); 559 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 560 return (ENXIO); 561 562 device_set_desc(dev, "RockChip I2C"); 563 return (BUS_PROBE_DEFAULT); 564} 565 566static int 567rk_i2c_attach(device_t dev) 568{ 569 struct rk_i2c_softc *sc; 570 int error; 571 572 sc = device_get_softc(dev); 573 sc->dev = dev; 574 575 mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF); 576 577 if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) { 578 device_printf(dev, "cannot allocate resources for device\n"); 579 error = ENXIO; 580 goto fail; 581 } 582 583 if (bus_setup_intr(dev, sc->res[1], 584 INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc, 585 &sc->intrhand)) { 586 bus_release_resources(dev, rk_i2c_spec, sc->res); 587 device_printf(dev, "cannot setup interrupt handler\n"); 588 return (ENXIO); 589 } 590 591 clk_set_assigned(dev, ofw_bus_get_node(dev)); 592 593 /* Activate the module clocks. */ 594 error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk); 595 if (error != 0) { 596 device_printf(dev, "cannot get i2c clock\n"); 597 goto fail; 598 } 599 error = clk_enable(sc->sclk); 600 if (error != 0) { 601 device_printf(dev, "cannot enable i2c clock\n"); 602 goto fail; 603 } 604 /* pclk clock is optional. */ 605 error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk); 606 if (error != 0 && error != ENOENT) { 607 device_printf(dev, "cannot get pclk clock\n"); 608 goto fail; 609 } 610 if (sc->pclk != NULL) { 611 error = clk_enable(sc->pclk); 612 if (error != 0) { 613 device_printf(dev, "cannot enable pclk clock\n"); 614 goto fail; 615 } 616 } 617 618 sc->iicbus = device_add_child(dev, "iicbus", -1); 619 if (sc->iicbus == NULL) { 620 device_printf(dev, "cannot add iicbus child device\n"); 621 error = ENXIO; 622 goto fail; 623 } 624 625 bus_generic_attach(dev); 626 627 return (0); 628 629fail: 630 if (rk_i2c_detach(dev) != 0) 631 device_printf(dev, "Failed to detach\n"); 632 return (error); 633} 634 635static int 636rk_i2c_detach(device_t dev) 637{ 638 struct rk_i2c_softc *sc; 639 int error; 640 641 sc = device_get_softc(dev); 642 643 if ((error = bus_generic_detach(dev)) != 0) 644 return (error); 645 646 if (sc->iicbus != NULL) 647 if ((error = device_delete_child(dev, sc->iicbus)) != 0) 648 return (error); 649 650 if (sc->sclk != NULL) 651 clk_release(sc->sclk); 652 if (sc->pclk != NULL) 653 clk_release(sc->pclk); 654 655 if (sc->intrhand != NULL) 656 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); 657 658 bus_release_resources(dev, rk_i2c_spec, sc->res); 659 660 mtx_destroy(&sc->mtx); 661 662 return (0); 663} 664 665static phandle_t 666rk_i2c_get_node(device_t bus, device_t dev) 667{ 668 669 return ofw_bus_get_node(bus); 670} 671 672static device_method_t rk_i2c_methods[] = { 673 DEVMETHOD(device_probe, rk_i2c_probe), 674 DEVMETHOD(device_attach, rk_i2c_attach), 675 DEVMETHOD(device_detach, rk_i2c_detach), 676 677 /* OFW methods */ 678 DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node), 679 680 DEVMETHOD(iicbus_callback, iicbus_null_callback), 681 DEVMETHOD(iicbus_reset, rk_i2c_reset), 682 DEVMETHOD(iicbus_transfer, rk_i2c_transfer), 683 684 DEVMETHOD_END 685}; 686 687static driver_t rk_i2c_driver = { 688 "rk_i2c", 689 rk_i2c_methods, 690 sizeof(struct rk_i2c_softc), 691}; 692 693static devclass_t rk_i2c_devclass; 694 695EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, rk_i2c_devclass, 0, 0, 696 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 697EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver, ofw_iicbus_devclass, 698 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 699MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1); 700MODULE_VERSION(rk_i2c, 1); 701