1#ifndef _RK3399_DT_H_ 2#define _RK3399_DT_H_ 3 4#define PLL_APLLL 1 5#define PLL_APLLB 2 6#define PLL_DPLL 3 7#define PLL_CPLL 4 8#define PLL_GPLL 5 9#define PLL_NPLL 6 10#define PLL_VPLL 7 11#define ARMCLKL 8 12#define ARMCLKB 9 13#define SCLK_I2C1 65 14#define SCLK_I2C2 66 15#define SCLK_I2C3 67 16#define SCLK_I2C5 68 17#define SCLK_I2C6 69 18#define SCLK_I2C7 70 19#define SCLK_SPI0 71 20#define SCLK_SPI1 72 21#define SCLK_SPI2 73 22#define SCLK_SPI4 74 23#define SCLK_SPI5 75 24#define SCLK_SDMMC 76 25#define SCLK_SDIO 77 26#define SCLK_EMMC 78 27#define SCLK_TSADC 79 28#define SCLK_SARADC 80 29#define SCLK_UART0 81 30#define SCLK_UART1 82 31#define SCLK_UART2 83 32#define SCLK_UART3 84 33#define SCLK_SPDIF_8CH 85 34#define SCLK_I2S0_8CH 86 35#define SCLK_I2S1_8CH 87 36#define SCLK_I2S2_8CH 88 37#define SCLK_I2S_8CH_OUT 89 38#define SCLK_TIMER00 90 39#define SCLK_TIMER01 91 40#define SCLK_TIMER02 92 41#define SCLK_TIMER03 93 42#define SCLK_TIMER04 94 43#define SCLK_TIMER05 95 44#define SCLK_TIMER06 96 45#define SCLK_TIMER07 97 46#define SCLK_TIMER08 98 47#define SCLK_TIMER09 99 48#define SCLK_TIMER10 100 49#define SCLK_TIMER11 101 50#define SCLK_MACREF 102 51#define SCLK_MAC_RX 103 52#define SCLK_MAC_TX 104 53#define SCLK_MAC 105 54#define SCLK_MACREF_OUT 106 55#define SCLK_VOP0_PWM 107 56#define SCLK_VOP1_PWM 108 57#define SCLK_RGA_CORE 109 58#define SCLK_ISP0 110 59#define SCLK_ISP1 111 60#define SCLK_HDMI_CEC 112 61#define SCLK_HDMI_SFR 113 62#define SCLK_DP_CORE 114 63#define SCLK_PVTM_CORE_L 115 64#define SCLK_PVTM_CORE_B 116 65#define SCLK_PVTM_GPU 117 66#define SCLK_PVTM_DDR 118 67#define SCLK_MIPIDPHY_REF 119 68#define SCLK_MIPIDPHY_CFG 120 69#define SCLK_HSICPHY 121 70#define SCLK_USBPHY480M 122 71#define SCLK_USB2PHY0_REF 123 72#define SCLK_USB2PHY1_REF 124 73#define SCLK_UPHY0_TCPDPHY_REF 125 74#define SCLK_UPHY0_TCPDCORE 126 75#define SCLK_UPHY1_TCPDPHY_REF 127 76#define SCLK_UPHY1_TCPDCORE 128 77#define SCLK_USB3OTG0_REF 129 78#define SCLK_USB3OTG1_REF 130 79#define SCLK_USB3OTG0_SUSPEND 131 80#define SCLK_USB3OTG1_SUSPEND 132 81#define SCLK_CRYPTO0 133 82#define SCLK_CRYPTO1 134 83#define SCLK_CCI_TRACE 135 84#define SCLK_CS 136 85#define SCLK_CIF_OUT 137 86#define SCLK_PCIEPHY_REF 138 87#define SCLK_PCIE_CORE 139 88#define SCLK_M0_PERILP 140 89#define SCLK_M0_PERILP_DEC 141 90#define SCLK_CM0S 142 91#define SCLK_DBG_NOC 143 92#define SCLK_DBG_PD_CORE_B 144 93#define SCLK_DBG_PD_CORE_L 145 94#define SCLK_DFIMON0_TIMER 146 95#define SCLK_DFIMON1_TIMER 147 96#define SCLK_INTMEM0 148 97#define SCLK_INTMEM1 149 98#define SCLK_INTMEM2 150 99#define SCLK_INTMEM3 151 100#define SCLK_INTMEM4 152 101#define SCLK_INTMEM5 153 102#define SCLK_SDMMC_DRV 154 103#define SCLK_SDMMC_SAMPLE 155 104#define SCLK_SDIO_DRV 156 105#define SCLK_SDIO_SAMPLE 157 106#define SCLK_VDU_CORE 158 107#define SCLK_VDU_CA 159 108#define SCLK_PCIE_PM 160 109#define SCLK_SPDIF_REC_DPTX 161 110#define SCLK_DPHY_PLL 162 111#define SCLK_DPHY_TX0_CFG 163 112#define SCLK_DPHY_TX1RX1_CFG 164 113#define SCLK_DPHY_RX0_CFG 165 114#define SCLK_RMII_SRC 166 115#define SCLK_PCIEPHY_REF100M 167 116#define SCLK_DDRC 168 117#define SCLK_TESTCLKOUT1 169 118#define SCLK_TESTCLKOUT2 170 119#define DCLK_VOP0 180 120#define DCLK_VOP1 181 121#define DCLK_VOP0_DIV 182 122#define DCLK_VOP1_DIV 183 123#define DCLK_M0_PERILP 184 124#define DCLK_VOP0_FRAC 185 125#define DCLK_VOP1_FRAC 186 126#define FCLK_CM0S 190 127#define ACLK_PERIHP 192 128#define ACLK_PERIHP_NOC 193 129#define ACLK_PERILP0 194 130#define ACLK_PERILP0_NOC 195 131#define ACLK_PERF_PCIE 196 132#define ACLK_PCIE 197 133#define ACLK_INTMEM 198 134#define ACLK_TZMA 199 135#define ACLK_DCF 200 136#define ACLK_CCI 201 137#define ACLK_CCI_NOC0 202 138#define ACLK_CCI_NOC1 203 139#define ACLK_CCI_GRF 204 140#define ACLK_CENTER 205 141#define ACLK_CENTER_MAIN_NOC 206 142#define ACLK_CENTER_PERI_NOC 207 143#define ACLK_GPU 208 144#define ACLK_PERF_GPU 209 145#define ACLK_GPU_GRF 210 146#define ACLK_DMAC0_PERILP 211 147#define ACLK_DMAC1_PERILP 212 148#define ACLK_GMAC 213 149#define ACLK_GMAC_NOC 214 150#define ACLK_PERF_GMAC 215 151#define ACLK_VOP0_NOC 216 152#define ACLK_VOP0 217 153#define ACLK_VOP1_NOC 218 154#define ACLK_VOP1 219 155#define ACLK_RGA 220 156#define ACLK_RGA_NOC 221 157#define ACLK_HDCP 222 158#define ACLK_HDCP_NOC 223 159#define ACLK_HDCP22 224 160#define ACLK_IEP 225 161#define ACLK_IEP_NOC 226 162#define ACLK_VIO 227 163#define ACLK_VIO_NOC 228 164#define ACLK_ISP0 229 165#define ACLK_ISP1 230 166#define ACLK_ISP0_NOC 231 167#define ACLK_ISP1_NOC 232 168#define ACLK_ISP0_WRAPPER 233 169#define ACLK_ISP1_WRAPPER 234 170#define ACLK_VCODEC 235 171#define ACLK_VCODEC_NOC 236 172#define ACLK_VDU 237 173#define ACLK_VDU_NOC 238 174#define ACLK_PERI 239 175#define ACLK_EMMC 240 176#define ACLK_EMMC_CORE 241 177#define ACLK_EMMC_NOC 242 178#define ACLK_EMMC_GRF 243 179#define ACLK_USB3 244 180#define ACLK_USB3_NOC 245 181#define ACLK_USB3OTG0 246 182#define ACLK_USB3OTG1 247 183#define ACLK_USB3_RKSOC_AXI_PERF 248 184#define ACLK_USB3_GRF 249 185#define ACLK_GIC 250 186#define ACLK_GIC_NOC 251 187#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 188#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 189#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 190#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 191#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 192#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 193#define ACLK_ADB400M_PD_CORE_L 258 194#define ACLK_ADB400M_PD_CORE_B 259 195#define ACLK_PERF_CORE_L 260 196#define ACLK_PERF_CORE_B 261 197#define ACLK_GIC_PRE 262 198#define ACLK_VOP0_PRE 263 199#define ACLK_VOP1_PRE 264 200#define PCLK_PERIHP 320 201#define PCLK_PERIHP_NOC 321 202#define PCLK_PERILP0 322 203#define PCLK_PERILP1 323 204#define PCLK_PERILP1_NOC 324 205#define PCLK_PERILP_SGRF 325 206#define PCLK_PERIHP_GRF 326 207#define PCLK_PCIE 327 208#define PCLK_SGRF 328 209#define PCLK_INTR_ARB 329 210#define PCLK_CENTER_MAIN_NOC 330 211#define PCLK_CIC 331 212#define PCLK_COREDBG_B 332 213#define PCLK_COREDBG_L 333 214#define PCLK_DBG_CXCS_PD_CORE_B 334 215#define PCLK_DCF 335 216#define PCLK_GPIO2 336 217#define PCLK_GPIO3 337 218#define PCLK_GPIO4 338 219#define PCLK_GRF 339 220#define PCLK_HSICPHY 340 221#define PCLK_I2C1 341 222#define PCLK_I2C2 342 223#define PCLK_I2C3 343 224#define PCLK_I2C5 344 225#define PCLK_I2C6 345 226#define PCLK_I2C7 346 227#define PCLK_SPI0 347 228#define PCLK_SPI1 348 229#define PCLK_SPI2 349 230#define PCLK_SPI4 350 231#define PCLK_SPI5 351 232#define PCLK_UART0 352 233#define PCLK_UART1 353 234#define PCLK_UART2 354 235#define PCLK_UART3 355 236#define PCLK_TSADC 356 237#define PCLK_SARADC 357 238#define PCLK_GMAC 358 239#define PCLK_GMAC_NOC 359 240#define PCLK_TIMER0 360 241#define PCLK_TIMER1 361 242#define PCLK_EDP 362 243#define PCLK_EDP_NOC 363 244#define PCLK_EDP_CTRL 364 245#define PCLK_VIO 365 246#define PCLK_VIO_NOC 366 247#define PCLK_VIO_GRF 367 248#define PCLK_MIPI_DSI0 368 249#define PCLK_MIPI_DSI1 369 250#define PCLK_HDCP 370 251#define PCLK_HDCP_NOC 371 252#define PCLK_HDMI_CTRL 372 253#define PCLK_DP_CTRL 373 254#define PCLK_HDCP22 374 255#define PCLK_GASKET 375 256#define PCLK_DDR 376 257#define PCLK_DDR_MON 377 258#define PCLK_DDR_SGRF 378 259#define PCLK_ISP1_WRAPPER 379 260#define PCLK_WDT 380 261#define PCLK_EFUSE1024NS 381 262#define PCLK_EFUSE1024S 382 263#define PCLK_PMU_INTR_ARB 383 264#define PCLK_MAILBOX0 384 265#define PCLK_USBPHY_MUX_G 385 266#define PCLK_UPHY0_TCPHY_G 386 267#define PCLK_UPHY0_TCPD_G 387 268#define PCLK_UPHY1_TCPHY_G 388 269#define PCLK_UPHY1_TCPD_G 389 270#define PCLK_ALIVE 390 271#define HCLK_PERIHP 448 272#define HCLK_PERILP0 449 273#define HCLK_PERILP1 450 274#define HCLK_PERILP0_NOC 451 275#define HCLK_PERILP1_NOC 452 276#define HCLK_M0_PERILP 453 277#define HCLK_M0_PERILP_NOC 454 278#define HCLK_AHB1TOM 455 279#define HCLK_HOST0 456 280#define HCLK_HOST0_ARB 457 281#define HCLK_HOST1 458 282#define HCLK_HOST1_ARB 459 283#define HCLK_HSIC 460 284#define HCLK_SD 461 285#define HCLK_SDMMC 462 286#define HCLK_SDMMC_NOC 463 287#define HCLK_M_CRYPTO0 464 288#define HCLK_M_CRYPTO1 465 289#define HCLK_S_CRYPTO0 466 290#define HCLK_S_CRYPTO1 467 291#define HCLK_I2S0_8CH 468 292#define HCLK_I2S1_8CH 469 293#define HCLK_I2S2_8CH 470 294#define HCLK_SPDIF 471 295#define HCLK_VOP0_NOC 472 296#define HCLK_VOP0 473 297#define HCLK_VOP1_NOC 474 298#define HCLK_VOP1 475 299#define HCLK_ROM 476 300#define HCLK_IEP 477 301#define HCLK_IEP_NOC 478 302#define HCLK_ISP0 479 303#define HCLK_ISP1 480 304#define HCLK_ISP0_NOC 481 305#define HCLK_ISP1_NOC 482 306#define HCLK_ISP0_WRAPPER 483 307#define HCLK_ISP1_WRAPPER 484 308#define HCLK_RGA 485 309#define HCLK_RGA_NOC 486 310#define HCLK_HDCP 487 311#define HCLK_HDCP_NOC 488 312#define HCLK_HDCP22 489 313#define HCLK_VCODEC 490 314#define HCLK_VCODEC_NOC 491 315#define HCLK_VDU 492 316#define HCLK_VDU_NOC 493 317#define HCLK_SDIO 494 318#define HCLK_SDIO_NOC 495 319#define HCLK_SDIOAUDIO_NOC 496 320#endif 321